SA5225D [NXP]
Fiber optic postamplifier; 光纤后置放大器
| 型号： | SA5225D |
| 厂家： | 
NXP |
| 描述： | Fiber optic postamplifier |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
SA5225
Fiber optic postamplifier
Product specification
1998 Oct 07
Replaces datasheet NE/SA5225 of 1997 Jun 05
IC19 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
DESCRIPTION
PIN DESCRIPTION
The SA5225 is a high-gain limiting amplifier that is designed to
process signals from fiber optic preamplifiers. Capable of operating
at 125Mb/s, the chip has input signal level-detection with a
user-adjustable threshold. The DATA and LEVEL-DETECT outputs
are differential for optimum noise margin and ease of use. Also
available is the SA5224 which is optimized for FDDI applications.
D Package
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CAZN
CAZP
SET
V
REF
GND
A
V
CCE
D
D
OUT
IN
FEATURES
D
D
OUT
IN
• Wideband operation: 1.0kHz to 120MHz typical
V
GND
E
ST
CCA
CF
• Applicable in 155Mb/s OC3/SONET receivers
• Operation with single +5V or –5.2V supply
• Differential 10k ECL outputs
JAM
ST
SD00374
Figure 1. Pin Configuration
• Programmable input signal level-detection
• Fully differential for excellent PSRR to 1GHz
APPLICATIONS
• Data communication in noisy industrial environments
• LANs
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
–40 to +85°C
16-Pin Plastic Small Outline (SO) Package
SA5225D
SOT109-1
BLOCK DIAGRAM
V
C
C
V
CCA
(6)
AZP
(2)
AZN
(1)
CCE
(16)
(13)
(12)
D
D
(4)
(5)
D
OUT
OUT
IN
ECL
BUFFER
LIMITING
AMPLIFIER
D
IN
JAM
BUFFER
(8) JAM
(15)
(16)
V
V
REFERENCE
REF
ST
ST
(9)
LEVEL
DETECTOR
SD
BUFFER
(10)
SET
(3)
(7)
(11)
GND
C
F
GND
E
SD00375
A
Figure 2. Block Diagram
2
1998 Oct 07
853-1595 20141
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
PIN DESCRIPTIONS
PIN NO.
NAME
FUNCTION
1
C
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
limiting amplifier.
will cancel the offset voltage of the
AZN
AZP
AZP
2
3
C
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
limiting amplifier.
will cancel the offset voltage of the
AZN
GND
Analog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL
operation. Must be at same potential as GND (Pin 11).
A
E
4
5
6
D
D
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D (Pin 5).
IN
IN
IN
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D (Pin 4).
IN
V
CCA
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as V
(Pin 14).
CCE
7
8
C
Filter capacitor for level detector. Capacitor should be connected between this pin and V
.
F
CCA
JAM
This ECL-compatible input controls the output buffers D
and D
(Pins 12 and 13). When an ECL LOW signal
OUT
OUT
is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the D
and D
pins
OUT
OUT
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).
9
ST
ST
Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable
threshold level.
10
11
ECL compliment of ST (Pin 9).
GND
Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL
E
operation. Must be at the same potential as GND (Pin 3).
A
12
13
14
D
D
V
ECL-compatible output. Nominal level is V
–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH
OUT
CCE
condition. Complimentary to D
(Pin 13).
OUT
ECL-compatible output. Nominal level is V
condition. Complimentary to D
–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW
OUT
CCE
CCE
(Pin 12).
OUT
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as V (Pin 6).
CCA
15
16
V
V
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
Input threshold level setting circuit. This input can come from a voltage divider between V
REF
and GND .
SET
REF
A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V
CC
Power supply (V - GND)
6
V
CC
T
Operating ambient
Operating junction
Storage
–40 to +85
–55 to +150
–65 to +150
°C
°C
°C
A
T
J
T
STG
1
Power dissipation, T = 25°C (still air)
A
P
D
1100
mW
16-pin Plastic SO
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
: 16-pin SO: θ = 110°C/W
θ
JA
JA
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
RATING
UNITS
V
V
CC
Supply voltage
4.5 to 5.5
–40 to +85
–40 to +110
T
A
Ambient temperature ranges
Junction temperature ranges
°C
T
J
°C
3
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
DC ELECTRICAL CHARACTERISTICS
Min and Max limits apply over operating temperature at V = 5V ±10%, unless otherwise specified.
CC
Typical data apply at T = 25°C and V = +5V.
A
CC
SA5225
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Max
Min
Typ
Input signal voltage
single-ended
0.002
0.004
1.5
3.0
V
IN
V
P-P
differential
2
V
Input offset voltage
50
60
µV
µV
OS
2
V
Input RMS noise
N
Input level-detect programmability single-en-
ded
V
V
IN
= 200kHz square wave
2
2
12
mV
P-P
TH
3
V
HYS
Level-detect hysteresis
3
4
dB
mA
µA
I
V
CCA
+ V supply current
CCE
No ECL loading
Pin 8 = 0V
27
35
10
CC
I
JAM input current
–10
INL
1
V
Minimum input for JAM = high
–1.165
V
IH
DC
DC
DC
DC
1
V
Maximum input for JAM = low
Status pins
–1.490
–0.81
–1.63
V
V
V
IL
4
V
V
–1.0
OH
4
Status pins
–1.95
OL
NOTES:
1. These ECL specifications are referenced to the V
2. Guaranteed by design.
rail and apply for T = 0°C to 85°C.
A
CCE
3. Also see the SA5224 which has 5dB ±1dB hysteresis for FDDI compatibility.
4. Valid for Status pins only (#9, 10).
Table 1.
10K ECL Voltage Levels (referenced to V ) (Pins 12 & 13 only)
CCE
PARAMETER
–30°C
–0.890
–1.060
–1.650
–1.890
0°C
25°C
75°C
85°C
UNIT
V
V
V
V
–0.840
–1.020
–1.630
–1.950
–0.810
–0.980
–1.630
–1.950
–0.735
–0.920
–1.600
–1.950
–0.700
–0.890
–1.615
–1.920
V
DC
V
DC
V
DC
V
DC
OHMAX
OHMIN
OLMAX
OLMIN
AC ELECTRICAL CHARACTERISTICS
Min and Max limits apply for 4.5 ≤ V ≤ 5.5V.
CC
Typical data apply at T = 25°C and V = +5V.
A
CC
SA5225
SYMBOL
PARAMETER
TEST CONDITIONS
= 0.1µF
UNIT
Min
0.5
90
Typ
1.0
Max
1.5
BW
BW
Lower –3dB bandwidth
Upper –3dB bandwidth
Input resistance
C
kHz
MHz
kΩ
1
AZ
120
4.5
150
7.6
2
R
C
Pin 4 or 5
Pin 4 or 5
2.9
IN
IN
Input capacitance
2.5
pF
R = 50Ω
L
1
ECL output
risetime,
falltime
To V
– 2V
t , t
r
1.2
2.2
ns
CCE
f
20–80%
t
Pulsewidth distortion
0.3
ns
P-P
PWD
R
Auto zero output resistance
Level-detect filter resistance
Level-detect time constant
Pin 1 or 2
Pin 7
155
14
250
24
423
41
kΩ
kΩ
µs
AZ
R
F
t
LD
C = 0
F
0.5
1.0
2.0
NOTE:
1. Both outputs should be terminated identically to minimize differential feedback to the device inputs on a PC board or substrate.
4
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
INPUT SIGNAL LEVEL-DETECTION
The SA5225 allows for user programmable input signal
level-detection and can automatically disable the switching of its
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.
CLOCK
RECOVERY
&
NE5212
NE5224
RETIMING
SD00376
Figure 3. Typical Fiber Optic Receiving System
Figure 6 shows a simplified block diagram of the SA5225
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1µs time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
INPUT BIASING
The DATA INPUT pins (4 and 5) are DC biased at approximately
2.9V by an internal reference generator. The SA5225 can be DC
coupled, but the driving source must operate within the allowable
V
CCA
(the internal driving impedance is nominally 24k). The
1.4V to 4.4V input signal range (for V = 5V). If AC coupling is
CC
resultant signal is then compared to a programmable level, V
,
SET
used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001µF coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to
7.6k) must be included for an accurate calculation.
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.
HYST
V
V
TL
(OFF)
TH
(ON)
SD00377
AUTO-ZERO CIRCUIT
Figure 4.
Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
The circuit is designed to operate accurately over a differential
2-12mV square-wave input level detect range. This level,
P-P
V /100, is the average of V and V .
SET TH TL
Nominal hysteresis of 3dB is provided by the complimentary ECL
(C ) connected between Pins 1 and 2. The formula for the lower
–3dB frequency is:
AZ
VSET
VSET
VTL
+
VTH
+
121
85
output comparator yielding
example, with V
and
. For
150
f*3dB
+
= 1.2V, a 14.05mV
square-wave differential
P-P
2p @ RAZ @ CAZ
SET
input will drive the ST pin high, and an input level below 9.95mV
will drive the ST pin low.
P-P
where R is the internal driving impedance which can vary from
AZ
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5225.
Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (D = LOW, D = HIGH), the
OUT
OUT
ST and JAM pins can be connected together to automatically
disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST will be in a high ECL state for input signals below
threshold.
C
AZ
R
R
AZ
250kΩ
AZ
250kΩ
V
BIAS
A4
R
R
IN
4.5kΩ
IN
4.5kΩ
C1
D
D
OUT
–
ECL 10K
D
D
DATA IN
IN
A1
+
A3
A6
DATA OUT
INB
OUTB
C2
SD00668
Figure 5. SA5225 Sample Application: Forward Gain Path Including Auto-Zero
5
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
V
CCA
C
F
LOW-PASS
FILTER
DATA IN
50X
2.64V
+
–
ST
ST
V
REF
ECL 10K
R
1
2
LEVEL-
DETECT
FLAGS
.25X
R
SD00669
Figure 6. SA5225 Sample Application: Input Signal Level-Detect System
1
2
3
4
5
6
7
8
C
C
V
V
16
15
14
13
12
11
10
9
AZN
AZP
SET
C
AZ
0.1µF
R
R
2
1
REF
5V
GND
V
D
A
CCE
0.1µF
C
IN1
R
3
D
IN
OUT
0.1µF
50Ω
DATA IN
DATA OUT
C
IN2
R
4
3V
D
D
IN
OUT
0.1µF
50Ω
5V
V
GND
E
CCA
0.1µF
0.1µF
R
5
ST
C
F
50Ω
LEVEL-DETECT
STATUS
JAM
ST
SD00380
Figure 7. SA5225 Sample Application with V = 5.0V
CC
NOTE: A 50Ω resistor is required from Pin 9 to 3V only if the ST pin is required to meet 10k ECL specifications.
All die are 100% functional with various parametrics tested at the
wafer level, at room temperature only (25°C), and are guaranteed to
be 100% functional as a result of electrical testing to the point of
wafer sawing only. Although the most modern processes are
utilized for wafer sawing and die pick and place into waffle pack
carriers, it is impossible to guarantee 100% functionality through this
process. There is no post waffle pack testing performed on
individual die.
Die Sales Disclaimer
Due to the limitations in testing high frequency and other parameters
at the die level, and the fact that die electrical characteristics may
shift after packaging, die electrical parameters are not specified and
die are not guaranteed to meet electrical characteristics (including
temperature range) as noted in this data sheet which is intended
only to specify electrical characteristics for a packaged device.
6
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
Since Philips Semiconductors has no control of third party
procedures in the handling or packaging of die, Philips
Semiconductors assumes no liability for device functionality or
performance of the die or systems on any die sales.
Although Philips Semiconductors typically realizes a yield of 85%
after assembling die into their respective packages, with care
customers should achieve a similar yield. However, for the reasons
stated above, Philips Semiconductors cannot guarantee this or any
other yield on any die sales.
CAZN
V
SET
CAZP
V
REF
1
2
16
15
3
4
5
GNDA
V
CCE
14
DIN
DOUT
13
12
DIN
DOUT
6
11
V
GND
E
CCA
7
8
9
10
ST
CF
JAM
ST
ECN No.: 01671
1991 Jul 8
SD00493
Figure 8. SA5225 Bonding Diagram
7
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
8
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
NOTES
9
1998 Oct 07
Philips Semiconductors
Product specification
Fiber optic postamplifier
SA5225
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-98
Document order number:
9397 750 04629
Philips
Semiconductors
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