SAA7105H/V1_技术文档

SAA7102; SAA7103

Digital video encoder

Rev. 04 — 18 January 2006

Product data sheet

1. General description

The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800 × 600

resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and

interlacer ensures properly sized and ﬂicker-free TV display as CVBS or S-video output.

Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals

together with a TTL composite sync to feed SCART connectors.

When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the

RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor

at maximum 800 × 600 resolution/60 Hz (PIXCLK < 45 MHz).

The device includes a sync/clock generator and on-chip DACs.

2. Features

■ Digital PAL/NTSC encoder with integrated high quality scaler and anti-ﬂicker ﬁlter for

TV output from a PC

■ 27 MHz crystal-stable subcarrier generation

■ Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip

or from external source

■ Up to 800 × 600 graphics data at 60 Hz or 50 Hz with programmable underscan range.

■ Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,

C_B), VBS (GREEN, CVBS) and C (RED, C_R) (signals in parenthesis are optional); all at

10-bit resolution

■ Non-Interlaced (NI) C_B-Y-C_Ror RGB input at maximum 4 : 4 : 4 sampling

■ Downscaling from 1 : 1 to 1 : 2 and up to 20 % upscaling

■ Optional interlaced C_B-Y-C_Rinput of Digital Versatile Disc (DVD) signals

■ Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with

maximum 45 MHz)

■ 3 × 256 bytes RGB Look-Up Table (LUT)

■ Support for hardware cursor

■ Programmable border color of underscan area

■ On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)

■ Fast I²C-bus control port (400 kHz)

■ Encoder can be master or slave

■ Programmable horizontal and vertical input synchronization phase

■ Programmable horizontal sync output phase

■ Internal Color Bar Generator (CBG)

■ Optional support of various Vertical Blanking Interval (VBI) data insertion

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

■ Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this

applies to the SAA7102 only

■ Power-save modes

■ Joint Test Action Group (JTAG) Boundary Scan Test (BST)

■ Monolithic CMOS 3.3 V device, 5 V tolerant I/Os

■ QFP44 and LBGA156 packages

■ Same footprint as SAA7108E; SAA7109E

3. Quick reference data

Table 1:

Quick reference data

Symbol

V_DDA

V_DDD

I_DDA

Parameter

Conditions

Min

3.15

3.0

1

Typ

3.3

110

70

Max

3.45

3.6

Unit

V

analog supply voltage

digital supply voltage

analog supply current

digital supply current

input signal voltage levels

V

140

90

mA

I_DDD

1

V_i

TTL compatible

V_o(p-p)

analog CVBS output signal

voltage for a 100/100 color bar

at 75/2 Ω load

-

1.23

-

V

(peak-to-peak value)

R_L

load resistance

-

37.5

-

Ω

ILE_lf(DAC)

low frequency integral linearity

error of DACs

3

LSB

DLE_lf(DAC)low frequency differential

linearity error of DACs

-

1

LSB

T_amb

ambient temperature

0

70

°C

4. Ordering information

Table 2:

Ordering information

Type number Package

Name

Description

Version

SAA7102E

SAA7103E

SAA7102H

SAA7103H

LBGA156

plastic low proﬁle ball grid array package; 156 balls;

body 15 × 15 × 1.05 mm

SOT700-1

QFP44

plastic quad ﬂat package; 44 leads (lead length

1.3 mm); body 10 × 10 × 1.75 mm

SOT307-2

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

2 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

6. Pinning information

6.1 Pinning

ball A1

index area

1

2 3 4 5 6 7 8 9 10 11 12 13 14

A

B

C

D

E

F

G

H

J

SAA7102E

SAA7103E

K

L

M

N

P

001aad559

Transparent top view

Fig 2. Pin conﬁguration (LBGA156)

1

2

33

V

PD8

PD9

SSA1

32

31

30

29

28

27

26

25

24

23

DUMP

3

PD10

PD11

RESET

TMS

RSET

4

BLUE_CB_CVBS

5

V

DDA1

SAA7102H

SAA7103H

6

GREEN_VBS_CVBS

RED_CR_C

7

TDO

8

TCK

HSM_CSYNC

VSM

9

V

SSD1

10

11

V

TTXRQ_XCLKO2

TTX_SRES

DDD1

SCL

001aad558

Fig 3. Pin conﬁguration (QFP44)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

4 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 3:

A2

Pin allocation table SAA7102E; SAA7103E

Symbol

PD7

A3

A5

A7

A9

B1

B3

B5

B7

B9

C2

C4

C6

C8

D1

D3

D5

D7

D9

E2

E4

F2

F4

G2

G4

H2

Symbol

PD4

A4

TRST

XTALI

A6

XTALO

V_SSA1

DUMP

RSET

A8

A10

B2

V_DDA1

PD9

PD8

PD5

B4

PD6

TDI

B6

V_DDA2

DUMP

V_DDA1

B8

V_SSA1

C1

C3

C5

C7

C9

D2

D4

D6

D8

E1

PD11

PD10

TTX_SRES

V_SSD2

TTXRQ_XCLKO2

BLUE_CB_CVBS

RED_CR_C

TDO

GREEN_VBS_CVBS

V_DDA1

RESET

V_DDD2

TMS

V_SSD2

V_DDA2

VSM

HSM_CSYNC

TCK

V_DDA1

SCL

E3

HSVGC

VSVGC

PD3

V_SSD1

F1

PIXCLKI

V_DDD1

F3

G1

G3

H1

H3

FSVGC

CBO

SDA

PIXCLKO

PD1

PD2

PD0

6.2 Pin description

Table 4:

Symbol

Pin description

Type^[1]Description

LBGA156 QFP44

PD8

B2

B1

C2

C1

D2

D3

D1

E1

E4

1

2

3

4

5

6

7

8

9

I

see Table 28 to Table 33 for pin assignment

PD9

I

see Table 28 to Table 33 for pin assignment

reset input; active LOW

test mode select input for BST ^[2]

test data output for BST ^[2]

PD10

PD11

RESET

TMS

I

TDO

O

I

TCK

test clock input for BST^[2]

V_SSD1

S

digital ground 1 (peripheral cells)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

5 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 4:

Symbol

Pin description …continued

Type^[1]Description

LBGA156 QFP44

V_DDD1

SCL

F4

10

S

digital supply voltage 1 (3.3 V for peripheral

cells)

serial clock input (I²C-bus) with inactive

output path

E2

11

I(/O)

SDA

G2

G1

12

13

I/O

serial data input/output (I²C-bus)

FSVGC

frame synchronization output to Video

Graphics Controller (VGC) (optional input)^[3]

VSVGC

F1

14

I/O

vertical synchronization output to VGC

(optional input)^[3]

PIXCLKI

PD3

F2

F3

15

16

I

pixel clock input (looped through)

MSB − 4 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

PD2

PD1

PD0

H1

H2

H3

17

18

19

I

MSB − 5 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

MSB − 6 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

MSB − 7 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

PIXCLKO

CBO

G4

G3

20

21

O

pixel clock output to VGC

composite blanking output to VGC; active

LOW^[3]

HSVGC

E3

22

I/O

horizontal synchronization output to VGC

(optional input)^[3]

TTX_SRES

C3

C4

23

24

I

teletext input or sync reset input

TTXRQ_XCLKO2

O

teletext request output or 13.5 MHz clock

output of the crystal oscillator^[3]

VSM

D7

D8

25

26

O

vertical synchronization output to monitor

(non-interlaced auxiliary RGB)

HSM_CSYNC

horizontal synchronization output to monitor

(non-interlaced auxiliary RGB) or composite

sync for RGB-SCART

RED_CR_C

C8

27

28

O

analog output of RED or C_Ror C signal

GREEN_VBS_CVBS C7

analog output of GREEN or VBS or CVBS

signal

V_DDA1

A10, B9, 29

C9, D9

S

analog supply voltage 1 (3.3 V for DACs)

BLUE_CB_CVBS

RSET

C6

A9

30

31

O

analog output of BLUE or C_Bor CVBS signal

DAC reference pin; connected via 1 kΩ

resistor to analog ground (do not use

capacitor in parallel with 1 kΩ resistor)

DUMP

A7, B7

32

O

DAC reference pin; connected via 12 Ω

resistor to analog ground

V_SSA1

XTALO

XTALI

A8, B8

A6

33

34

35

S

O

I

analog ground 1

crystal oscillator output

crystal oscillator input

A5

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

6 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 4:

Symbol

Pin description …continued

Type^[1]Description

LBGA156 QFP44

V_DDA2

B6, D6

36

S

analog supply voltage 2 (3.3 V for DACs and

oscillator)

TRST

TDI

A4

37

38

39

40

41

I

test reset input for BST; active LOW^{[2] [4] [5]}

test data input for BST ^[2]

B5

I

V_SSD2

V_DDD2

PD4

C5, D5

D4

S

I

digital ground 2

digital supply voltage 2 (3.3 V for core)

A3

MSB − 3 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

PD5

PD6

PD7

B3

B4

A2

42

43

44

I

MSB − 2 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

MSB − 1 with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

MSB with C_B-Y-C_R4 : 2 : 2;

see Table 28 to Table 33 for pin assignment

[1] Pin type: I = input, O = output, S = supply.

[2] In accordance with the “IEEE1149.1” standard the pins TDI, TMS, TCK and TRST are input pins with an

internal pull-up resistor and TDO is a 3-state output pin.

[3] Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.

[4] For board design without boundary scan implementation connect TRST to ground.

[5] This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port

(TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

7. Functional description

The digital video encoder encodes digital luminance and color difference signals

(C_B-Y-C_R) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or

C_R-Y-C_Bsignals. NTSC M, PAL B/G and sub-standards are supported.

The SAA7102; SAA7103 can be directly connected to a PC video graphics controller with

a maximum resolution of 800 × 600 at a 50 Hz or 60 Hz frame rate. A programmable

scaler scales the computer graphics picture so that it will ﬁt into a standard TV screen with

an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with

an adjustable anti-ﬂicker ﬁlter for a ﬂicker-free display at a very high sharpness.

Besides the most common 16-bit 4 : 2 : 2 C_B-Y-C_Rinput format (using 8 pins with double

edge clocking), other C_B-Y-C_Rand RGB formats are also supported; see

Table 28 to Table 33.

A complete 3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a

separate gamma corrector, is located in the RGB domain; it can be loaded either through

the video input port Pixel Data (PD) or via the I²C-bus.

The SAA7102; SAA7103 supports a 32-bit × 32-bit × 2-bit hardware cursor, the pattern of

which can also be loaded through the video input port or via the I²C-bus.

It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the

anti-ﬂicker ﬁlter, and in most cases the scaler, will simply be bypassed.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

7 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Besides the applications for video output, the SAA7102; SAA7103 can also be used for

generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed

to the DACs. This may be of interest for example, when the graphics controller provides a

second graphics window at its video output port.

The basic encoder function consists of subcarrier generation, color modulation and

insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz

(independent of the actual pixel clock used at the input side), corresponding to an internal

4 : 2 : 2 bandwidth in the luminance/color difference domain. Luminance and

chrominance signals are ﬁltered in accordance with the standard requirements of

“RS-170-A” and “ITU-R BT.470-3”.

For ease of analog post ﬁltering the signals are twice oversampled to 27 MHz before

digital-to-analog conversion.

The total ﬁlter transfer characteristics (scaler and anti-ﬂicker ﬁlter are not taken into

account) are illustrated in Figure 6 to Figure 11. All three DACs are realized with full 10-bit

resolution. The C_R-Y-C_Bto RGB dematrix can be bypassed (optionally) in order to provide

the upsampled C_R-Y-C_Binput signals.

The 8-bit multiplexed C_B-Y-C_Rformats are “ITU-R BT.656” (D1 format) compatible, but the

SAV and EAV codes can be decoded optionally, when the device is operated in Slave

mode. For assignment of the input data to the rising or falling clock edge see

Table 28 to Table 34.

In order to display interlaced RGB signals through a euro-connector TV set, a separate

digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced

up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing

of a TV set.

The SAA7102; SAA7103 synthesizes all necessary internal signals, color subcarrier

frequency and synchronization signals from that clock.

Wide screen signalling data can be loaded via the I²C-bus and is inserted into line 23 for

standards using a 50 Hz ﬁeld rate.

VPS data for program dependent automatic start and stop of such featured VCRs is

loadable via the I²C-bus.

The IC also contains closed caption and extended data services encoding (line 21), and

supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate

(see Figure 15). It is also possible to load data for the copy generation management

system into line 20 of every ﬁeld (525/60 line counting).

A number of possibilities are provided for setting different video parameters such as:

• Black and blanking level control

• Color subcarrier frequency

• Variable burst amplitude etc.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

8 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

7.1 Reset conditions

To activate the reset a pulse at least of 2 crystal clocks duration is required.

During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC,

CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set

to 3-state. A reset also forces the I²C-bus interface to abort any running bus transfer and

sets it into receive condition.

After reset, the state of the I/Os and other functions is deﬁned by the strapping pins until

an I²C-bus access redeﬁnes the corresponding registers; see Table 5.

Table 5:

Strapping pins

Tied

Preset

FSVGC

LOW

NTSC M encoding, PIXCLK ﬁts to 640 × 480 graphics input

PAL B/G encoding, PIXCLK ﬁts to 640 × 480 graphics input

4 : 2 : 2 Y-C_B-C_Rgraphics input (format 0)

4 : 4 : 4 RGB graphics input (format 3)

input demultiplex phase: LSB = LOW

input demultiplex phase: LSB = HIGH

input demultiplex phase: MSB = LOW

input demultiplex phase: MSB = HIGH

HIGH

VSVGC

CBO

LOW

HIGH

LOW

HIGH

HSVGC

LOW

HIGH

TTXRQ_XCLKO2 LOW

slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar is

active)

HIGH

master (FSVGC, VSVGC and HSVGC are outputs)

7.2 Input formatter

The input formatter converts all accepted PD input data formats, either RGB or Y-C_B-C_R,

to a common internal RGB or Y-C_B-C_Rdata stream.

When double-edge clocking is used, the data is internally split into portions PPD1 and

PPD2. The clock edge assignment must be set according to the I²C-bus control bits

EDGE1 and EDGE2 for correct operation.

If Y-C_B-C_Ris being applied as a 27 MB/s data stream, the output of the input formatter can

be used directly to feed the video encoder block.

7.3 RGB LUT

The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus

it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the

event that the indexed color data is applied, the RAMs are addressed in parallel.

The LUTs can either be loaded by an I²C-bus write access or can be part of the pixel data

input through the PD port. In the latter case, 256 bytes × 3 bytes for the R, G and B LUT

are expected at the beginning of the input video line, two lines before the line that has

been deﬁned as ﬁrst active line, until the middle of the line immediately preceding the ﬁrst

active line. The ﬁrst 3 bytes represent the ﬁrst RGB LUT data, and so on.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

9 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

7.4 Cursor insertion

A 32 dots × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be

uploaded by an I²C-bus write access to speciﬁc registers or in the pixel data input through

the PD port. In the latter case, the 256 bytes deﬁning the cursor bit map (2 bits per pixel)

are expected immediately following the last RGB LUT data in the line preceding the ﬁrst

active line.

The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these

bits depends on the CMODE I²C-bus register as described in Table 8. Transparent means

that the input pixels are passed through, the ‘cursor colors’ can be programmed in

separate registers.

The bit map is stored with 4 pixels per byte, aligned to the least signiﬁcant bit. So the ﬁrst

pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The ﬁrst index is the

column, followed by the row; index 0,0 is the upper left corner.

Table 6:

7

Layout of a byte in the cursor bit map

6

5

4

3

2

1

0

pixel n + 3

pixel n + 2

pixel n + 1

pixel n

D1

D0

D1

D0

D1

D0

D1

D0

For each direction, there are 2 registers controlling the position of the cursor, one controls

the position of the ‘hot spot’, the other register controls the insertion position. The hot spot

is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position

registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner.

While it is not possible to move the hot spot beyond the left respectively upper screen

border this is perfectly legal for the right respectively lower border. It should be noted that

the cursor position is described relative to the input resolution.

Table 7:

Cursor bit map

7

Byte

0

6

5

4

3

2

1

0

row 0 column 3

row 0 column 7

row 0 column 11

...

row 0 column 2

row 0 column 6

row 0 column 10

...

row 0 column 1

row 0 column 5

row 0 column 9

...

row 0 column 0

row 0 column 4

row 0 column 8

...

1

2

...

6

row 0 column 27

row 0 column 31

...

row 0 column 26

row 0 column 30

...

row 0 column 25

row 0 column 29

...

row 0 column 24

row 0 column 28

...

7

...

254

255

row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24

row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28

SAA7102_SAA7103_4

Product data sheet

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 8:

Cursor modes

Cursor pattern

Cursor mode

CMODE = 0

CMODE = 1

00

01

10

11

second cursor color

ﬁrst cursor color

transparent

second cursor color

ﬁrst cursor color

transparent

inverted input

auxiliary cursor color

7.5 RGB Y-C_B-C_Rmatrix

RGB input signals to be encoded to PAL or NTSC are converted to the Y-C_B-C_Rcolor

space in this block. The color difference signals are fed through low-pass ﬁlters and

formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing.

The matrix and formatting blocks can be bypassed for Y-C_B-C_Rgraphics input.

When the auxiliary VGA mode is selected, the output of the cursor insertion block is

immediately directed to the triple DAC.

7.6 Horizontal scaler

The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines

compensate the color phase offset automatically.

The scaler starts processing after a programmable horizontal offset and continues with a

number of input pixels. Each input pixel is a programmable fraction of the current output

pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1.

If the SAA7102; SAA7103 input data is in accordance with “ITU-R BT.656”, the scaler

enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1.

With higher values, upscaling will occur.

The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800

input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.

7.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the

vertical scaler.

Besides the entire input frame, it receives the ﬁrst and last lines of the border to allow

anti-ﬂicker ﬁltering.

The circuit generates the interlaced output ﬁelds by scaling down the input frames with

different offsets for odd and even ﬁelds. Increasing the YSKIP setting reduces the

anti-ﬂicker function. A YSKIP value of 4095 switches it off; see Table 91.

The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions

of the offset registers are not sufﬁcient, so the weighting factors for the ﬁrst lines can also

be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

11 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Due to the re-interlacing, the circuit can perform upscaling. The maximum factor depends

on the setting of the anti-ﬂicker function and can be derived from the formulae given in

Section 7.17.

7.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock

domain. The write clock is PIXCLK and the read clock is XTAL. An underﬂow or overﬂow

condition can be detected via the I²C-bus read access.

In order to avoid underﬂows and overﬂows, it is essential that the frequency of the

synthesized PIXCLK matches to the input graphics resolution and the desired scaling

factor. It is suggested to refer to Table 9 to Table 26 for some representative combinations.

7.9 Border generator

When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on

a TV screen, it is desired in many cases not to lose picture information due to the inherent

overscanning of a TV set. The desired amount of underscan area, which is achieved

through appropriate scaling in the vertical and horizontal direction, can be ﬁlled in the

border generator with an arbitrary true color tint.

7.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz crystal oscillator, which can operate

with either a fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and

the I²C-bus control block. It also usually supplies the triple DAC, with the exception of the

auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK).

The DTO can be programmed to synthesize all relevant pixel clock frequencies between

circa 18 MHz and 44 MHz.

7.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking

ﬁlter for all relevant synthesized pixel clock frequencies.

7.12 Encoder

7.12.1 Video path

The encoder generates luminance and color subcarrier output signals from the Y,

C_Band C_Rbaseband signals, which are suitable for use as CVBS or separate Yand C

signals.

Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer

graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656

style signal.

Luminance is modiﬁed in gain and in offset (the offset is programmable in a certain range

to enable different black level set-ups). A blanking level can be set after insertion of a ﬁxed

synchronization pulse tip level, in accordance with standard composite synchronization

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

schemes. Other manipulations used for the Macrovision anti-taping process, such as

additional insertion of AGC super-white pulses (programmable in height), are supported

by the SAA7102 only.

To enable easy analog post ﬁltering, luminance is interpolated from a 13.5 MHz data rate

to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer

characteristics of the luminance interpolation ﬁlter are illustrated in Figure 8 and Figure 9.

Appropriate transients at start/end of active video and for synchronization pulses are

ensured.

Chrominance is modiﬁed in gain (programmable separately for C_Band C_R), and a

standard dependent burst is inserted, before baseband color signals are interpolated from

a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be

bypassed, thus providing a higher color bandwidth, which can be used for the Yand C

output. The transfer characteristics of the chrominance interpolation ﬁlter are illustrated in

Figure 6 and Figure 7.

The amplitude (beginning and ending) of the inserted burst, is programmable in a certain

range that is suitable for standard signals and for special effects. After the succeeding

quadrature modulator, color is provided on the subcarrier in 10-bit resolution.

The numeric ratio between the Yand C outputs is in accordance with the standards.

7.12.2 Teletext insertion and encoding (not simultaneously with real-time control)

Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock.

At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided

after a programmable delay at input pin TTX_SRES.

Phase variant interpolation is achieved on this bitstream in the internal teletext encoder,

providing sufﬁcient small phase jitter on the output text lines.

TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source,

indicating the insertion period of bitstream at lines which can be selected independently

for both ﬁelds. The internal insertion window for text is set to 360 (PAL WST),

296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol

and timing are illustrated in Figure 15.

Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.

7.12.3 Video Programming System (VPS) encoding

Five bytes of VPS information can be loaded via the I²C-bus and will be encoded in the

appropriate format into line 16.

7.12.4 Closed caption encoder

Using this circuit, data in accordance with the speciﬁcation of closed caption or extended

data service, delivered by the control interface, can be encoded (line 21). Two dedicated

pairs of bytes (two bytes per ﬁeld), each pair preceded by run-in clocks and framing code,

are possible.

The actual line number in which data is to be encoded, can be modiﬁed in a certain range.

The data clock frequency is in accordance with the deﬁnition for NTSC M standard

32 times horizontal line frequency.

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Philips Semiconductors

Digital video encoder

Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the

DACs corresponds to approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz ﬁeld frequencies at 32 times the

horizontal line frequency.

7.12.5 Anti-taping (SAA7102 only)

For more information contact your nearest Philips Semiconductors sales ofﬁce.

7.13 RGB processor

This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be

fed to a SCART plug.

Before Y, C_Band C_Rsignals are de-matrixed, individual gain adjustment for Y and color

difference signals and 2 times oversampling for luminance and 4 times oversampling for

color difference signals is performed. The transfer curves of luminance and color

difference components of RGB are illustrated in Figure 10 and Figure 11.

7.14 Triple DAC

Both Yand C signals are converted from digital-to-analog in a 10-bit resolution at the

output of the video encoder. Yand C signals are also combined into a 10-bit CVBS signal.

The CVBS output signal occurs with the same processing delay as the Y, C and optional

RGB or C_R-Y-C_Boutputs. Absolute amplitude at the input of the DAC for CVBS is reduced

by ¹⁵

⁄₁₆with respect to Yand C DACs to make maximum use of the conversion ranges.

RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing

a 10-bit resolution.

The reference currents of all three DACs can be adjusted individually in order to adapt for

different output signals. In addition, all reference currents can be adjusted commonly to

compensate for small tolerances of the on-chip band gap reference voltage.

Alternatively, all currents can be switched off to reduce power dissipation.

All three outputs can be used to sense for an external load (usually 75 Ω) during a

pre-deﬁned output. A ﬂag in the I²C-bus status byte reﬂects whether a load is applied or

not.

If the SAA7102; SAA7103 is required to drive a second (auxiliary) VGA monitor, the DACs

receive the signal directly from the cursor insertion block. In this event, the DACs are

clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video

encoder.

7.15 Timing generator

The synchronization of the SAA7102; SAA7103 is able to operate in two modes; Slave

mode and Master mode.

In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync),

VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can

be programmed. The frame sync signal is only necessary when the input signal is

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

interlaced, in other cases it may be omitted. If the frame sync signal is present, it is

possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS

bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the

pins to output mode.

Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data

stream via PD7 to PD0.

Only vertical frequencies of 50 Hz and 60 Hz are allowed with the SAA7102; SAA7103. In

Slave mode, it is not possible to lock the encoders color carrier to the line frequency with

the PHRES bits.

In the (more common) Master mode, the time base of the circuit is continuously

free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC,

a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these

signals are deﬁned in the PIXCLK domain. The duration of HSVGC and VSVGC are ﬁxed,

they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and

the polarities can be programmed.

The input line length can be programmed. The ﬁeld length is always derived from the ﬁeld

length of the encoder and the pixel clock frequency that is being used.

CBO acts as a data request signal. The circuit accepts input data at a programmable

number of clocks after CBO goes active. This signal is programmable and it is possible to

adjust the following (see Figure 13 and Figure 14):

• The horizontal offset

• The length of the active part of the line

• The distance from active start to ﬁrst expected data

• The vertical offset separately for odd and even ﬁelds

• The number of lines per input ﬁeld

In most cases, the vertical offsets for odd and even ﬁelds are equal. If they are not, then

the even ﬁeld will start later. The SAA7102; SAA7103 will also request the ﬁrst input lines

in the even ﬁeld, the total number of requested lines will increase by the difference of the

offsets.

As stated above, the circuit can be programmed to accept the look-up and cursor data in

the ﬁrst 2 lines of each ﬁeld. The timing generator provides normal data request pulses for

these lines; the duration is the same as for regular lines. The additional request pulses will

be suppressed with LUTL set to logic 0; see Table 101. The other vertical timings do not

change in this case, so the ﬁrst active line can be number 2, counted from 0.

7.16 I²C-bus interface

The I²C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses

and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an

auto-increment function. All registers are write and read, except two read only status

bytes.

The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and

control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is

assigned to one address. Thus a write access needs the LUT address and three data

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SAA7102; SAA7103

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Digital video encoder

bytes following subaddress FFh. For further write access auto-incrementing of the LUT

address is performed. The cursor bit map access is similar to the LUT access but contains

only a single byte per address.

The I²C-bus slave address is deﬁned as 88h.

7.17 Programming the SAA7102; SAA7103

In order to program the SAA7102; SAA7103 it is ﬁrst necessary to determine the input

and output ﬁeld timings. The timings are controlled by decoding binary counters that index

the position in the current line and ﬁeld respectively. In both cases, 0 means the start of

the sync pulse.

At 60 Hz, the ﬁrst visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the

index is 284, 702 pixels can be visible. Some variables are deﬁned below:

• InPix: the number of active pixels per input line

• InPpl: the length of the entire input line in pixel clocks

• InLin: the number of active lines per input ﬁeld/frame

• TPclk: the pixel clock period

• OutPix: the number of active pixels per output line

• OutLin: the number of active lines per output ﬁeld

• TXclk: the encoder clock period (37.037 ns)

The output lines should be centred on the screen. It should be noted that the encoder has

2 clocks per pixel; see Table 62.

ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz);

ADWHE = ADWHS + OutPix × 2 (all frequencies)

For vertical, the procedure is the same. At 60 Hz, the ﬁrst line with video information is

number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 70

to Table 72.

240 – OutLin

---------------------------------

2

287 – OutLin

---------------------------------

2

FAL = 19 +

(60 Hz); FAL = 23 +

(50 Hz);

LAL = FAL + OutLin (all frequencies).

Most TV sets use overscan, and not all pixels respectively lines are visible. There is no

standard for the factor, it is highly recommended to make the number of output pixels and

lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output

pixels per line.

The total number of pixel clocks per line and the input horizontal offset need to be chosen

next. The only constraint is that the horizontal blanking has at least 10 clock pulses.

The required pixel clock frequency can be determined in the following way: Due to the

limited internal FIFO size, the input path has to provide all pixels in the same time frame

as the encoders vertical active time. The scaler also has to process the ﬁrst and last

border lines for the anti-ﬂicker function. Thus:

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Digital video encoder

262.5 × 1716 × TXclk

TPclk =

PCL =

(60 Hz)

-----------------------------------------------------------------------------------------

InLin + 2

OutLin

⎛

⎞

InPpl × integer

× 262.5

-----------------------

⎝

⎠

312.5 × 1728 × TXclk

(50 Hz) and for the pixel clock generator

-----------------------------------------------------------------------------------------

InLin + 2

⎛

⎝

⎞

InPpl × integer

× 312.5

-----------------------

OutLin

⎠

TXclk

× 2²¹(all frequencies); see Table 74.

--------------

TPclk

The input vertical offset can be taken from the assumption that the scaler should just have

ﬁnished writing the ﬁrst line when the encoder starts reading it:

FAL × 1716 × TXclk

--------------------------------------------------

InPpl × TPclk

FAL × 1728 × TXclk

--------------------------------------------------

InPpl × TPclk

YOFS =

– 2 (60 Hz) YOFS =

– 2 (50 Hz)

In most cases the vertical offsets will be the same for odd and even ﬁelds. The results

should be rounded down.

Once the timings are known the scaler can be programmed.

XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulﬁlled.

Values given by the VESA display timings are preferred.

HLEN = InPpl − 1

InPix

2

XPIX =

XINC =

-------------

OutPix

------------------

InPix

× 4096

XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.

YPIX = InLin

YSKIP deﬁnes the anti-ﬂicker function. 0 means maximum ﬂicker reduction but minimum

vertical bandwidth, 4095 gives no ﬂicker reduction and maximum bandwidth.

OutLin

-----------------------

InLin + 2

YSKIP

----------------

4095

⎛

⎞

YINC =

× 1 +

× 4096

⎝

⎠

YINC

2

YIWGTO =

YIWGTE =

+ 2048

-------------

YINC – YSKIP

-------------------------------------

2

When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not

be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added

and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE

positive.

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SAA7102; SAA7103

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Digital video encoder

Due to the limited amount of memory it is not possible to get valid vertical scaler settings

only from the formulae above. In some cases it is necessary to adjust the vertical offsets

or the scaler increment to get valid settings. Table 9 to Table 26 show veriﬁed settings.

They are organized in the following way: The tables are separate for the standard to be

encoded, the input resolution and three different anti-ﬂicker ﬁlter settings. Each table

contains 5 vertical sizes with 5 different offsets. They are intended to be selected

according to the current TV set. The corresponding horizontal resolutions of 640 pixels

give proper aspect ratios. They can be adjusted according to the formulae above. The

next line gives a minimum size intended to ﬁt on the screen under all circumstances. The

corresponding horizontal resolution is 620 pixels. Overscan is only possible with an input

resolution of 800 × 600 pixels. Where possible, the corresponding settings are given on

the last lines of the tables.

7.18 Input levels and formats

The SAA7102; SAA7103 accepts digital Y, C_B, C_Ror RGB data with levels (digital codes)

in accordance with “ITU-R BT.601”; see Table 27.

For C and CVBS outputs, deviating amplitudes of the color difference signals can be

compensated for by independent gain control setting, while gain for luminance is set to

predeﬁned values, distinguishable for 7.5 IRE set-up or without set-up.

The RGB, respectively C_R-Y-C_Bpath features an individual gain setting for luminance

(GY) and color difference signals (GCD). Reference levels are measured with a color bar,

100 % white, 100 % amplitude and 100 % saturation.

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 9:

TV line

Y scaler programming at NTSC, input frame size: 640 × 400, full anti-ﬂicker ﬁlter

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099 2163

1836201 2181

1817578 2202

1802680 2222

1784057 2245

0

52

56

60

63

67

50

54

57

61

65

47

51

55

58

62

45

49

53

56

60

43

46

50

54

57

52

56

60

63

67

50

54

57

61

65

47

51

55

58

62

45

49

53

56

60

43

46

50

54

57

3128

3138

3148

3158

3168

1080

1090

1100

1110

1120

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Overscan (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

1925590 2079

70

3087

1039

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SAA7102; SAA7103

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Digital video encoder

Table 10: Y scaler programming at NTSC, input frame size: 640 × 400, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099 3123

1836201 3135

1817578 3145

1802680 3155

1784057 3165

1820

1790

1750

1720

1680

52

56

60

64

67

50

54

58

61

65

48

51

55

59

63

45

49

53

56

60

43

47

50

54

58

52

56

60

64

67

50

54

58

61

65

48

51

55

59

63

45

49

53

56

60

43

47

50

54

58

3668

3683

3698

3714

3729

596

611

626

642

657

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

1925590 3087

1980

70

3589

551

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 11: Y scaler programming at NTSC, input frame size: 640 × 400, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

1851099 4094

1836201 4090

1836201 4088

1817578 4093

1802680 4092

1784057 4090

3655

3580

3510

3445

3370

52

56

60

64

68

50

54

58

61

65

48

52

55

59

63

46

49

53

57

60

43

47

50

54

58

52

56

60

64

68

50

54

58

61

65

48

52

55

59

63

46

49

53

57

60

43

47

50

54

58

4092

4091

4092

4091

216

253

288

322

358

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

1925590 4087

3950

70

4089

66

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Digital video encoder

Table 12: Y scaler programming at NTSC, input frame size: 640 × 480, full anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829 1804

2201206 1819

2178859 1836

2160236 1853

2141613 1870

0

63

67

72

77

81

60

65

69

73

78

57

61

66

70

75

54

59

63

68

72

52

56

61

65

69

63

67

72

77

81

60

65

69

73

78

57

61

66

70

75

54

59

63

68

72

52

56

61

65

69

2948

2957

2965

2974

2982

900

909

917

926

934

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

2309218 1734

84

2941

866

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Digital video encoder

Table 13: Y scaler programming at NTSC, input frame size: 640 × 480, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829 2704

2201206 2730

2178859 2756

2160236 2781

2141613 2807

2048

63

67

72

77

81

60

65

69

74

78

57

62

66

71

75

55

59

63

68

72

52

57

61

65

70

63

67

72

77

81

60

65

69

74

78

57

62

66

71

75

55

59

63

68

72

52

57

61

65

70

3399

3412

3424

3437

3450

327

340

352

365

378

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

2309218 2602

2048

84

3348

276

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Digital video encoder

Table 14: Y scaler programming at NTSC, input frame size: 640 × 480, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

2219829 3607

2201206 3639

2178859 3675

2160236 3709

2141613 3741

4095

63

68

72

77

81

60

65

69

74

78

57

62

66

71

75

55

59

64

68

73

52

57

61

65

70

64

69

73

78

82

61

66

70

75

79

58

63

67

72

76

56

60

65

69

74

53

58

62

66

71

3849

3866

3883

3900

3917

3362

3413

3464

3515

3566

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241

Small size (horizontal size: 620 pixels)

204 37 241

0

2309218 3471

4095

85

86

3781

3158

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

24 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 15: Y scaler programming at NTSC, input frame size: 800 × 600, full anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726 1443

3518354 1457

3484982 1470

3451610 1484

3423006 1497

0

79

84

90

96

102

75

81

86

92

98

72

77

82

88

94

68

73

79

85

90

65

71

76

81

87

79

84

90

96

102

75

81

86

92

98

72

77

82

88

94

68

73

79

85

90

65

71

76

81

87

2769

2776

2782

2789

2796

721

728

734

741

748

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241 18 259

Small size (horizontal size: 620 pixels)

204 37 241

0

3122659 1642

3689981 1389

0

42

2867

2742

819

694

0

106

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

25 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 16: Y scaler programming at NTSC, input frame size: 800 × 600, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726 2165

3518354 2185

3484982 2205

3451610 2226

3423006 2246

2048

79

85

91

96

102

75

81

87

92

98

72

77

83

89

94

68

74

80

85

90

65

71

76

81

87

79

85

91

96

102

75

81

87

92

98

72

77

83

89

94

68

74

80

85

90

65

71

76

81

87

3129

3140

3150

3160

3170

57

68

78

88

98

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241 18 259

Small size (horizontal size: 620 pixels)

204 37 241

0

3122659 2461

3689981 2083

2048

42

3277

3089

205

17

0

106

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

26 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 17: Y scaler programming at NTSC, input frame size: 800 × 600, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

212

214

216

218

220

−4

−2

0

29

31

33

35

37

28

30

32

34

36

27

29

31

33

35

26

28

30

32

34

25

27

29

31

33

241

243

245

247

249

242

244

246

248

250

243

245

247

249

251

244

246

248

250

252

245

247

249

251

253

3551726 2887

3518354 2912

3484982 2941

3451610 2969

3423006 2994

4095

79

85

91

96

102

76

81

87

92

98

72

78

83

89

94

69

74

80

85

90

65

71

76

82

87

80

86

92

97

103

77

82

88

93

99

73

79

84

90

95

70

75

81

86

91

66

72

77

83

88

3490

3504

3517

3531

3544

2282

2323

2364

2405

2446

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 710 pixels)

241 18 259

Small size (horizontal size: 620 pixels)

204 37 241

0

3122659 3282

3689981 2778

4095

42

43

3687

3436

2875

2119

0

106

107

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

27 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 18: Y scaler programming at PAL, input frame size: 640 × 400, full anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1528590 2600

1528590 2602

1516163 2621

1516163 2623

1506842 2641

1494414 2661

1481987 2684

0

52

55

59

62

65

50

53

57

60

63

49

52

55

58

61

47

50

53

56

59

45

48

51

54

57

52

55

59

62

65

50

53

57

60

63

49

52

55

58

61

47

50

53

56

59

45

48

51

54

57

3347

3357

3367

3377

3387

1299

1309

1319

1329

1339

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1559659 2549

63

3321

1273

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

28 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 19: Y scaler programming at PAL, input frame size: 640 × 400, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1528590 3346

1516163 3360

1506842 3362

1494414 3378

1481987 3384

1170

1150

1120

1100

1070

53

56

59

62

65

51

54

57

60

63

49

52

55

58

61

47

50

53

56

59

45

48

51

54

57

53

56

59

62

65

51

54

57

60

63

49

52

55

58

61

47

50

53

56

59

45

48

51

54

57

3996

4012

4070

4042

4057

924

940

998

970

985

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1559659 3322

1240

63

3707

1039

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

29 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 20: Y scaler programming at PAL, input frame size: 640 × 400, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

42

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

301

293

295

297

299

301

294

296

298

300

302

1528590 4095

1516163 4095

1506842 4093

1506842 4091

1494414 4094

1494414 4093

1481987 4092

2350

2300

2250

2200

2150

53

56

59

62

65

51

54

57

60

63

49

52

55

58

63

47

50

53

56

59

45

48

51

54

57

53

56

59

62

65

51

54

57

60

63

49

52

55

58

63

47

50

53

56

59

45

48

51

54

57

4092

4091

869

894

919

944

968

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1559659 4087

2470

63

4089

806

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

30 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 21: Y scaler programming at PAL, input frame size: 640 × 480, full anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066 2168

1820638 2185

1805104 2202

1805104 2204

1805104 2202

1792676 2219

1777142 2238

0

63

67

71

74

78

61

65

69

72

76

58

62

66

70

73

56

60

64

67

71

54

58

61

65

69

63

67

71

74

78

61

65

69

72

76

58

62

66

70

73

56

60

64

67

71

54

58

61

65

69

3131

3139

3148

3156

3165

1083

1091

1100

1108

1117

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1870348 2125

76

3110

1062

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

31 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 22: Y scaler programming at PAL, input frame size: 640 × 480, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066 3254

1820638 3277

1805104 3305

1792676 3328

1777142 3354

2048

63

67

71

75

79

61

65

69

72

76

59

63

66

70

74

57

60

64

68

71

54

58

61

65

69

63

67

71

75

79

61

65

69

72

76

59

63

66

70

74

57

60

64

68

71

54

58

61

65

69

3673

3686

3698

3711

3724

601

614

626

639

652

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1870348 3108

1890

76

3600

607

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

32 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 23: Y scaler programming at PAL, input frame size: 640 × 480, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

1833066 4093

1820638 4090

1805104 4092

1792676 4088

1777142 4095

3630

3570

3510

3450

3400

64

67

71

75

79

61

65

69

73

76

59

63

66

70

74

57

60

64

68

71

54

58

62

65

69

64

67

71

75

79

61

65

69

73

76

59

63

66

70

74

57

60

64

68

71

54

58

62

65

69

4091

4095

228

258

288

318

345

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288

Small size (horizontal size: 620 pixels)

250 41 291

0

1870348 4088

3780

76

4090

152

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

33 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 24: Y scaler programming at PAL, input frame size: 800 × 600, full anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917 1736

2911033 1749

2887172 1763

2863311 1778

2843427 1790

0

79

84

89

93

98

77

81

86

91

95

73

78

83

87

92

71

75

80

85

89

68

72

77

82

86

79

84

89

93

98

77

81

86

91

95

73

78

83

87

92

71

75

80

85

89

68

72

77

82

86

2915

2922

2929

2935

2942

867

874

881

887

894

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288 22 310

Small size (horizontal size: 620 pixels)

250 41 291

0

2596864 1960

2990569 1701

0

43

95

43

95

3027

2898

979

850

0

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

34 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 25: Y scaler programming at PAL, input frame size: 800 × 600, half anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917 2604

2911033 2625

2887172 2645

2863311 2666

2843427 2686

2048

80

84

89

94

98

77

82

86

91

96

74

79

83

88

92

71

75

80

85

89

68

73

77

82

86

80

84

89

94

98

77

82

86

91

96

74

79

83

88

92

71

75

80

85

89

68

73

77

82

86

3349

3359

3369

3379

3390

277

287

297

307

318

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288 22 310

Small size (horizontal size: 620 pixels)

250 41 291

0

2596864 2940

2990569 2553

2048

43

96

43

96

3517

3323

445

251

0

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 26: Y scaler programming at PAL, input frame size: 800 × 600, no anti-ﬂicker ﬁlter

TV line

Offset

FAL

LAL

PCL

YINC

YSKIP

YOFSO

YOFSE

YIWGTO YIWGTE

Regular size (horizontal TV size: 640 pixels, offset 10 pixels)

255

257

259

261

263

−4

−2

0

35

37

39

41

43

34

36

38

40

42

33

35

37

39

41

32

34

36

38

40

31

33

35

37

39

290

292

294

296

298

291

293

295

297

299

292

294

296

298

300

293

295

297

299

301

294

296

298

300

302

2930917 3473

2911033 3500

2887172 3527

2863311 3555

2843427 3582

4095

80

84

89

94

99

77

82

87

91

96

74

79

83

88

93

71

76

80

85

89

68

73

78

82

87

81

85

90

95

100

78

83

88

92

97

75

80

84

89

94

72

77

81

86

90

69

74

79

83

88

3783

3796

3810

3823

3837

3161

3202

3242

3284

3324

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

−4

−2

0

2

4

Full size (horizontal size: 702 pixels)

288 22 310

Small size (horizontal size: 620 pixels)

250 41 291

0

2596864 3923

2990569 3405

4095

44

96

45

97

4007

3748

3836

3059

0

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 27: “ITU-R BT.601” signal component levels

Color

Signals^[1]

Y

C_B

C_R

R

G

B

White

Yellow

Cyan

235

210

170

145

106

81

128

16

128

146

16

235

16

235

16

235

16

166

54

235

16

Green

Magenta

Red

34

16

202

90

222

240

110

128

235

16

235

16

Blue

41

240

128

16

235

16

Black

16

[1] Transformation:

R = Y + 1.3707 × (C_R− 128)

G = Y − 0.3365 × (C_B− 128) − 0.6982 × (C_R− 128)

B = Y + 1.7324 × (C_B− 128).

Table 28: Pin assignment for input format 0

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/C_B-Y-C_R

Falling clock edge

G3/Y3

Rising clock edge

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

R2/C_R2

R1/C_R1

R0/C_R0

G7/Y7

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2/Y2

G1/Y1

G0/Y0

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

B2/C_B2

B1/C_B1

B0/C_B0

G6/Y6

G5/Y5

G4/Y4

Table 29: Pin assignment for input format 1

5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB

Falling clock edge

Rising clock edge

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2

G1

G0

B4

B3

B2

B1

B0

X

R4

R3

R2

R1

R0

G4

G3

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Digital video encoder

Table 30: Pin assignment for input format 2

5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB

Falling clock edge

Rising clock edge

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2

G1

G0

B4

B3

B2

B1

B0

R4

R3

R2

R1

R0

G5

G4

G3

Table 31: Pin assignment for input format 3

8 + 8 + 8-bit 4 : 2 : 2 non-interlaced C_B-Y-C_R

Falling clock

edge n

Rising clock

edge n

Falling clock

edge n + 1

Rising clock

edge n + 1

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

C_B7(0)

C_B6(0)

C_B5(0)

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y7(0)

Y6(0)

Y5(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

C_R7(0)

C_R6(0)

C_R5(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

Y7(1)

Y6(1)

Y5(1)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

Table 32: Pin assignment for input format 4

8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656, 27 MHz clock)

Rising clock

edge n

Rising clock

edge n + 1

Rising clock

edge n + 2

Rising clock

edge n + 3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

C_B7(0)

C_B6(0)

C_B5(0)

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y7(0)

Y6(0)

Y5(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

C_R7(0)

C_R6(0)

C_R5(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

Y7(1)

Y6(1)

Y5(1)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

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Philips Semiconductors

Digital video encoder

Table 33: Pin assignment for input format 5^[1]

8-bit non-interlaced index color

Falling clock edge

Rising clock edge

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

X

INDEX7

INDEX6

INDEX5

INDEX4

INDEX3

INDEX2

INDEX1

INDEX0

[1] X = don’t care.

Table 34: Pin assignment for input format 6

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/C_B-Y-C_R

Falling clock edge

G4/Y4

Rising clock edge

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

G7/Y7

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G3/Y3

G2/Y2

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

G0/Y0

G6/Y6

G5/Y5

R2/C_R2

R1/C_R1

R0/C_R0

G1/Y1

B2/C_B2

B1/C_B1

B0/C_B0

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Philips Semiconductors

Digital video encoder

8.2 I²C-bus format

S

1000 1000

A

SUBADDRESS

A

DATA 0

A

............

DATA n

A

P

001aad411

a. to control registers

1000 1000

A

FEh

A

RAM ADDRESS

A

DATA 0

A

............

DATA n

A

P

001aad413

b. to cursor bit map (subaddress FEh)

1000 1000

A

FFh

A

RAM ADDRESS

A

DATA 0R

A

DATA 0G

A

DATA 0B

A

............

P

001aad414

c. to color look-up table (subaddress FFh)

See Table 36 for explanations.

Fig 4. I²C-bus write access

S

1000 1000

A

SUBADDRESS

A

Sr 1000 1001

A

DATA 0

Am ............ DATA n Am

P

001aad415

a. to control registers

FEh

S

1000 1000

A

RAM ADDRESS

A

Sr 1000 1001

A

DATA 0 Am .......... DATA n Am

P

or

FFh

001aad416

b. to cursor bit map or color LUT

See Table 36 for explanations.

Fig 5. I²C-bus read access

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 36: Explanations of Figure 4 and Figure 5

Code

Description

S

START condition

repeated START condition

slave address

Sr

1000 100X^[1]

A

acknowledge generated by the slave

acknowledge generated by the master

subaddress byte

Am

SUBADDRESS^[2]

DATA

data byte

--------

continued data bytes and acknowledges

STOP condition

P

RAM ADDRESS

start address for RAM access

[1] X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

[2] If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

8.3 Slave receiver

Table 37: Common DAC adjust ﬁne register, subaddress 16h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 4 -

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

3 to 0 DACF[3:0] R/W

DAC ﬁne output voltage adjustment, 1 % steps for all DACs

0111 7 %

0110 6 %

0101 5 %

0100 4 %

0011 3 %

0010 2 %

0001 1 %

0000* 0 %

1000 0 %

1001 −1 %

1010 −2 %

1011 −3 %

1100 −4 %

1101 −5 %

1110 −6 %

1111 −7 %

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 38: RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description

Subaddress Bit

Symbol

Description

17h to 19h

7 to 5 -

must be programmed with logic 0 to ensure compatibility to

future enhancements

17h

4 to 0 RDACC[4:0] output level coarse adjustment for RED DAC; default after

reset is 1Bh for output of C signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

18h

19h

4 to 0 GDACC[4:0] output level coarse adjustment for GREEN DAC; default after

reset is 1Bh for output of VBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

4 to 0 BDACC[4:0] output level coarse adjustment for BLUE DAC; default after

reset is 1Fh for output of CVBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

Table 39: MSM threshold, subaddress 1Ah, bit description

Bit Symbol Description

7 to 0 MSMT[7:0] monitor sense mode threshold for DAC output voltage, should be set to 70h

Table 40: Monitor sense mode register, subaddress 1Bh, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

MSM

R/W

monitor sense mode

0*

1

off; RCOMP, GCOMP and BCOMP bits are not valid

on

6 to 3

2

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

RCOMP R

GCOMP R

check comparator at DAC on pin RED_CR_C

active, output is loaded

0

1

inactive, output is not loaded

1

0

check comparator at DAC on pin GREEN_VBS_CVBS

active, output is loaded

0

1

inactive, output is not loaded

BCOMP

R

check comparator at DAC on pin BLUE_CB_CVBS

active, output is loaded

0

1

inactive, output is not loaded

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 41: Wide screen signal registers, subaddresses 26h and 27h, bit description

Legend: * = default value after reset.

Subaddress Bit

Symbol

Access Value Description

27h

7

6

WSSON

R/W

0*

1

wide screen signalling output is disabled

wide screen signalling output is enabled

-

0

must be programmed with logic 0 to ensure

compatibility to future enhancements

5 to 3 WSS[13:11] R/W

2 to 0 WSS[10:8] R/W

-

wide screen signalling bits, reserved

wide screen signalling bits, subtitles

26h

7 to 4 WSS[7:4]

R/W

wide screen signalling bits, enhanced

services

3 to 0 WSS[3:0]

R/W

-

wide screen signalling bits, aspect ratio

Table 42: Real-time control and burst start register, subaddress 28h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 and 6 -

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0

BS[5:0] R/W

starting point of burst in clock cycles

21h* PAL: BS = 33; strapping pin FSVGC tied to HIGH

19h* NTSC: BS = 25; strapping pin FSVGC tied to LOW

Table 43: Sync reset enable and burst end register, subaddress 29h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

SRES

R/W

0*

1

pin TTX_SRES accepts a teletext bit stream (TTX)

pin TTX_SRES accepts a sync reset input (SRES); a HIGH

impulse resets synchronization of the encoder (ﬁrst ﬁeld, ﬁrst

line)

6

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0

BE[5:0] R/W

ending point of burst in clock cycles

1Dh* PAL: BE = 29; strapping pin FSVGC tied to HIGH

1Dh* NTSC: BE = 29; strapping pin FSVGC tied to LOW

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 44: Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit

description

Legend: * = default value after reset.

Subaddress Bit

Symbol

Access Value Description

2Ch

7

CGEN

R/W

copy generation data output

0*

1

disabled

enabled

6 to 4 -

R/W

0

must be programmed with logic 0 to ensure

compatibility to future enhancements

3 to 0 CG[19:16] R/W

7 to 0 CG[15:8]

-

LSBs of the respective bytes are encoded

immediately after run-in, the MSBs of the

respective bytes have to carry the CRCC bits,

in accordance with the deﬁnition of copy

generation management system encoding

format.

2Bh

2Ah

7 to 0 CG[7:0]

Table 45: Output port control register, subaddress 2Dh, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

R/W pin GREEN_VBS_CVBS provides a

7

VBSEN

0

component GREEN signal (CVBSEN1 = 0) or CVBS signal

(CVBSEN1 = 1)

1*

luminance (VBS) signal

6

5

4

CVBSEN1 R/W

CVBSEN0 R/W

pin GREEN_VBS_CVBS provides a

component GREEN (G) or luminance (VBS) signal

CVBS signal

0*

1

pin BLUE_CB_CVBS provides a

component BLUE (B) or color difference BLUE (C_B) signal

CVBS signal

0

1*

CEN

R/W

pin RED_CR_C provides a

0

component RED (R) or color difference RED (C_R) signal

1*

chrominance signal (C) as modulated subcarrier for

S-video

3

2

ENCOFF R/W

encoder

active

0*

1

bypass, DACs are provided with RGB signal after cursor

insertion block

CLK2EN

R/W

pin TTXRQ_XCLKO2 provides

0

teletext request signal (TTXRQ)

1*

0

buffered crystal clock divided by two (13.5 MHz)

1 and 0 -

must be programmed with logic 0 to ensure compatibility to

future enhancements

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 46: Gain luminance for RGB register, subaddress 38h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 to 5

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

4 to 0

GY[4:0] R/W

-

Gain luminance of RGB (C_R, Yand C_B) output, ranging from

(1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂). Suggested nominal value = 0,

depending on external application.

Table 47: Gain color difference for RGB register, subaddress 39h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 to 5

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

4 to 0

GCD[4:0] R/W

-

Gain color difference of RGB (C_R, Yand C_B) output, ranging

from (1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂). Suggested nominal value = 0,

depending on external application.

Table 48: Input port control 1 register, subaddress 3Ah, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

CBENB R/W

0

1

0

data from input ports is encoded

color bar with ﬁxed colors is encoded

6 and 5 -

R/W

must be programmed with logic 0 to ensure compatibility to

future enhancements

4

3

2

SYMP

horizontal and vertical trigger

taken from FSVGC or both VSVGC and HSVGC

decoded out of ‘ITU-R BT.656’ compatible data at PD port

Y-C_B-C_Rto RGB dematrix

0*

1

DEMOFF R/W

CSYNC R/W

0*

1

active

bypassed

pin HSM_CSYNC provides

0

1

horizontal sync for non-interlaced VGA components output

(at PIXCLK)

composite sync for interlaced components output (at XTAL

clock)

1

0

Y2C

R/W

input luminance data

0

twos complement from PD input port

straight binary from PD input port

input color difference data

1*

UV2C

0

twos complement from PD input port

straight binary from PD input port

1*

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 49: VPS enable, input control 2, subaddress 54h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

VPSEN R/W

video programming system data insertion

is disabled

0*

1

in line 16 is enabled

6 to 2

1

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

EDGE2 R/W

internal PPD2 data is sampled with

rising clock edges

0

1*

falling clock edges; see Table 28 to Table 34

internal PPD1 data is sampled with

rising clock edges

0

EDGE1 R/W

0*

1

falling clock edges; see Table 28 to Table 34

Table 50: VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit

description^[1]

Subaddress Bit

Symbol

Access Value Description

55h

56h

7 to 0 VPS5[7:0] R/W

7 to 0 VPS11[7:0] R/W

-

ﬁfth byte of video programming system data

eleventh byte of video programming system

data

57h

58h

59h

7 to 0 VPS12[7:0] R/W

7 to 0 VPS13[7:0] R/W

7 to 0 VPS14[7:0] R/W

-

twelfth byte of video programming system

data

thirteenth byte of video programming system

data

fourteenth byte of video programming system

data

[1] In line 16; LSB ﬁrst; all other bytes are not relevant for VPS.

Table 51: Chrominance phase register, subaddress 5Ah, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0

CHPS[7:0] R/W

00h* phase of encoded color subcarrier (including burst) relative

to horizontal sync; can be adjusted in steps of

360/256 degrees

6Bh

16h

25h

46h

PAL B/G and data from input ports in Master mode

PAL B/G and data from look-up table

NTSC M and data from input ports in Master mode

NTSC M and data from look-up table

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 52: Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description

Subaddress Bit

Symbol

Conditions

Remarks

5Bh

5Dh

7 to 0

GAINU[8:0] ^[1]

white-to-black = 92.5 IRE

GAINU = 0

GAINU = −2.17 × nominal to +2.16 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

GAINU = −2.05 × nominal to +2.04 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

7

GAINU = 118 (76h)

white-to-black = 100 IRE

GAINU = 0

GAINU = 125 (7Dh)

6

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

5 to 0

BLCKL[5:0]^[2]

white-to-sync = 140 IRE ^[3]recommended value: BLCKL = 58 (3Ah)

BLCKL = 0 ^[3]

output black level = 29 IRE

BLCKL = 63 (3Fh) ^[3]

output black level = 49 IRE

white-to-sync = 143 IRE ^[4]recommended value: BLCKL = 51 (33h)

BLCKL = 0 ^[4]

BLCKL = 63 (3Fh) ^[4]

output black level = 27 IRE

output black level = 47 IRE

[1] Variable gain for C_Bsignal; input representation in accordance with ‘ITU-R BT.601’.

[2] Variable black level; input representation in accordance with ‘ITU-R BT.601’.

[3] Output black level/IRE = BLCKL × 2/6.29 + 28.9.

[4] Output black level/IRE = BLCKL × 2/6.18 + 26.5.

Table 53: Gain V and gain V MSB, blanking level registers, subaddresses 5Ch and 5Eh, bit description

Subaddress Bit

Symbol

Conditions

Remarks

5Ch

5Eh

7 to 0

GAINV[8:0]^[1]

white-to-black = 92.5 IRE

GAINV = 0

GAINV = −1.55 × nominal to +1.55 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

GAINV = −1.46 × nominal to +1.46 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

7

GAINV = 165 (A5h)

white-to-black = 100 IRE

GAINV = 0

GAINV = 175 (AFh)

6

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

5 to 0

BLNNL[5:0]^[2]

white-to-sync = 140 IRE ^[3]recommended value: BLNNL = 46 (2Eh)

BLNNL = 0^[3]

output blanking level = 25 IRE

BLNNL = 63 (3Fh)^[3]

output blanking level = 45 IRE

white-to-sync = 143 IRE ^[4]recommended value: BLNNL = 53 (35h)

BLNNL = 0^[4]

BLNNL = 63 (3Fh)^[4]

output blanking level = 26 IRE

output blanking level = 46 IRE

[1] Variable gain for C_Rsignal; input representation in accordance with ‘ITU-R BT.601’.

[2] Variable blanking level.

[3] Output black level/IRE = BLNNL × 2/6.29 + 25.4.

[4] Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35h.

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 54: CCR and blanking level VBI register, subaddress 5Fh, bit description

Bit Symbol Access Value Description

7 and 6 CCRS[1:0] R/W

select cross-color reduction ﬁlter in luminance; for overall

transfer characteristic of luminance see Figure 8

00

01

10

11

-

no cross-color reduction

cross-color reduction #1 active

cross-color reduction #2 active

cross-color reduction #3 active

5 to 0

BLNVB[5:0] R/W

variable blanking level during vertical blanking interval is

typically identical to value of BLNNL

Table 55: Standard control register, subaddress 61h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

DOWND

R/W

digital core

0*

1

in normal operational mode

in Sleep mode and is reactivated with an I²C-bus address

DACs

6

DOWNA

0*

1

in normal operational mode

in Power-down mode

5

4

-

R/W

0

must be programmed with logic 0 to ensure compatibility

to future enhancements

YGS

luminance gain for white − black

100 IRE

0

1

0

92.5 IRE including 7.5 IRE set-up of black

3

2

-

R/W

must be programmed with logic 0 to ensure compatibility

to future enhancements

SCBW

bandwidth for chrominance encoding (for overall transfer

characteristic of chrominance in baseband representation

see Figure 6 and Figure 7)

0

enlarged

1*

standard

1

0

PAL

R/W

encoding

0

1

NTSC (non-alternating V component)

PAL (alternating V component)

FISE

total pixel clocks per line

0

1

864

858

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 56: Burst amplitude register, subaddress 62h, bit description

Legend: * = default value after reset, ^ = recommended value.

Bit

Symbol Access Value Description

7

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

6 to 0 BSTA[6:0] R/W

amplitude of color burst; input representation in accordance

with ‘ITU-R BT.601’

3Fh

white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding;

(63)^ BSTA = 0 to 2.02 × nominal

2Dh white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding;

(45)^ BSTA = 0 to 2.82 × nominal

43h

white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding;

(67)^ BSTA = 0 to 1.90 × nominal

2Fh white-to-black = 100 IRE; burst = 43 IRE; PAL encoding;

(47)*^ BSTA = 0 to 3.02 × nominal

Table 57: Subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description

Subaddress Bit Symbol Access Value Description

66h

65h

64h

63h

7 to 0 FSC[31:24] R/W

7 to 0 FSC[23:16] R/W

7 to 0 FSC[15:08] R/W

7 to 0 FSC[07:00] R/W

-

f_fsc= subcarrier frequency (in multiples of line

frequency); f_llc= clock frequency (in multiples

of line frequency); FSC[31:24] = most

signiﬁcant byte; FSC[07:00] = least signiﬁcant

byte^[1]

f

32

⎠

fsc

⎛

⎝

⎞

[1] FSC = round

× 2

---------

f

llc

Examples:

a) NTSC M: f_fsc= 227.5, f_llc= 1716 → FSC = 569408543 (21F0 7C1Fh).

b) PAL B/G: f_fsc= 283.7516, f_llc= 1728 → FSC = 705268427 (2A09 8ACBh).

Table 58: Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit

description^[1]

Subaddress Bit

Symbol

Access Value Description

67h

68h

69h

6Ah

7 to 0 L21O[07:00] R/W

7 to 0 L21O[17:10] R/W

7 to 0 L21E[07:00] R/W

7 to 0 L21E[17:10] R/W

-

ﬁrst byte of captioning data, odd ﬁeld

second byte of captioning data, odd ﬁeld

ﬁrst byte of extended data, even ﬁeld

second byte of extended data, even ﬁeld

[1] LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the

respective bytes have to carry the parity bit, in accordance with the deﬁnition of line 21 encoding format.

Table 59: Trigger control registers, subaddresses 6Ch and 6Dh, bit description

Legend: * = default value after reset.

Subaddress Bit

Symbol

Access Value Description

6Ch

6Dh

7 to 0 HTRIG[7:0] R/W

7 to 5 HTRIG[10:8] R/W

4 to 0 VTRIG[4:0] R/W

00h* sets the horizontal trigger phase related to

chip-internal horizontal input ^[1]

0h*

00h* sets the vertical trigger phase related to

chip-internal vertical input^[2]

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of

all internally generated timing signals.

[2] Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;

variation range of VTRIG = 0 to 31 (1Fh).

Table 60: Multi control register, subaddress 6Eh, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

-

R/W

0

must be programmed with logic 0 to ensure compatibility

to future enhancements

6

BLCKON

R/W

0*

1

encoder in normal operation mode

output signal is forced to blanking level

5 and 4 PHRES[1:0] R/W

selects the phase reset mode of the color subcarrier

generator

00

01

10

11

no subcarrier reset

subcarrier reset every two lines

subcarrier reset every eight ﬁelds

subcarrier reset every four ﬁelds

3 and 2 LDEL[1:0]

R/W

selects the delay on luminance path with reference to

chrominance path

00*

01

10

11

no luminance delay

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

ﬁeld length control

1 and 0 FLC[1:0]

00*

01

10

11

interlaced 312.5 lines/ﬁeld at 50 Hz, 262.5 lines/ﬁeld at

60 Hz

non-interlaced 312 lines/ﬁeld at 50 Hz, 262 lines/ﬁeld at

60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at

60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at

60 Hz

Table 61: Closed caption, teletext enable register, subaddress 6Fh, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 and 6 CCEN[1:0] R/W

enables individual line 21 encoding

line 21 encoding off

00*

01

10

11

enables encoding in ﬁeld 1 (odd)

enables encoding in ﬁeld 2 (even)

enables encoding in both ﬁelds

SAA7102_SAA7103_4

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54 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 61: Closed caption, teletext enable register, subaddress 6Fh, bit description

…continued

Bit

Symbol

Access Value Description

5

TTXEN

R/W

teletext insertion

disabled

0*

1

-

enabled

4 to 0

SCCLN[4:0] R/W

selects the actual line, where closed caption or extended

data are encoded; line = (SCCLN + 4) for M-systems;

line = (SCCLN + 1) for other systems

Table 62: Active Display Window Horizontal (ADWH) start and end registers,

subaddresses 70h to 72h, bit description

Subaddress Bit

Symbol

Access Value Description

70h

71h

72h

7 to 0 ADWHS[7:0] R/W

-

active display window horizontal start;

deﬁnes the start of the active TV display

portion after the border color ^[1]

7 to 0 ADWHE[7:0] R/W

-

active display window horizontal end;

deﬁnes the end of the active TV display

portion before the border color^[1]

7

-

R/W

0

-

must be programmed with logic 0 to ensure

compatibility to future enhancements

6 to 4 ADWHE[10:8] R/W

active display window horizontal end;

deﬁnes the end of the active TV display

portion before the border color^[1]

3

-

R/W

0

-

must be programmed with logic 0 to ensure

compatibility to future enhancements

2 to 0 ADWHS[10:8] R/W

active display window horizontal start;

deﬁnes the start of the active TV display

portion after the border color ^[1]

[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.

Table 63: TTX request horizontal start register, subaddress 73h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0

TTXHS[7:0] R/W

start of signal TTXRQ on pin TTXRQ_XCLKO2

(CLK2EN = 0); see Figure 15

42h* if strapped to PAL

54h* if strapped to NTSC

Table 64: TTX request horizontal delay register, subaddress 74h, bit description

Legend: * = default value after reset and minimum value.

Bit

Symbol

Access Value Description

7 to 4 -

R/W

0h

must be programmed with logic 0 to ensure compatibility

to future enhancements

3 to 0 TTXHD[3:0] R/W

2h*

indicates the delay in clock cycles between rising edge of

TTXRQ output signal on pin TTXRQ_XCLKO2

(CLK2EN = 0) and valid data at pin TTX_SRES

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Philips Semiconductors

Digital video encoder

Table 65: CSYNC advance register, subaddress 75h, bit description

Bit Symbol Access Value Description

7 to 3 CSYNCA[4:0] R/W

-

advanced composite sync against RGB output from

0 XTAL clocks to 31 XTAL clocks

2 to 0 -

R/W

000

must be programmed with logic 0 to ensure compatibility

to future enhancements

Table 66: TTX odd request vertical start register, subaddress 76h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXOVS[7:0] R/W

with TTXOVS8 (see Table 72) ﬁrst line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

odd ﬁeld, line = (TTXOVS + 4) for M-systems and

line = (TTXOVS + 1) for other systems

05h* if strapped to PAL

06h* if strapped to NTSC

Table 67: TTX odd request vertical end register, subaddress 77h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXOVE[7:0] R/W

with TTXOVE8 (see Table 72) last line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

odd ﬁeld, line = (TTXOVE + 3) for M-systems and

line = TTXOVE for other systems

16h* if strapped to PAL

10h* if strapped to NTSC

Table 68: TTX even request vertical start register, subaddress 78h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXEVS[7:0] R/W

with TTXEVS8 (see Table 72) ﬁrst line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

even ﬁeld, line = (TTXEVS + 4) for M-systems and

line = (TTXEVS + 1) for other systems

04h* if strapped to PAL

05h* if strapped to NTSC

Table 69: TTX even request vertical end register, subaddress 79h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXEVE[7:0] R/W

with TTXEVE8 (see Table 72) last line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

even ﬁeld, line = (TTXEVE + 3) for M-systems and

line = TTXEVE for other systems

16h* if strapped to PAL

10h* if strapped to NTSC

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 70: First active line register, subaddress 7Ah, bit description

Bit Symbol Access Value Description

7 to 0 FAL[7:0]

R/W

with FAL8 (see Table 72) ﬁrst active line = (FAL + 4) for

M-systems and (FAL + 1) for other systems, measured in

lines

00h

coincides with the ﬁrst ﬁeld synchronization pulse

Table 71: Last active line register, subaddress 7Bh, bit description

Bit Symbol Access Value Description

7 to 0 LAL[7:0] R/W with LAL8 (see Table 72) last active line = (LAL + 3) for

M-systems and LAL for other system, measured in lines

00h

coincides with the ﬁrst ﬁeld synchronization pulse

Table 72: TTX mode, MSB vertical register, subaddress 7Ch, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

TTX60

R/W

0*

1

enables NABTS (FISE = 1) or European TTX (FISE = 0)

enables world standard teletext 60 Hz (FISE = 1)

see Table 71

6

5

LAL8

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

4

3

2

1

0

FAL8

R/W

see Table 70

see Table 69

see Table 67

see Table 68

see Table 66

TTXEVE8

TTXOVE8

TTXEVS8

TTXOVS8

Table 73: Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description^[1]

Subaddress Bit Symbol Access Value Description

7Eh

7Fh

7 to 0 LINE[12:5] R/W

7 to 0 LINE[20:13] R/W

-

individual lines in both ﬁelds (PAL counting)

can be disabled for insertion of teletext by the

respective bits, disabled line = LINExx (50 Hz

ﬁeld rate)

[1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.

Table 74: Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description

Subaddress Bit

Symbol

Access Value

Description

81h

82h

83h

7 to 0 PCL[07:00] R/W

7 to 0 PCL[15:08]

deﬁnes the frequency of the synthesized

pixel clock PIXCLKO;

PCL

⎛

⎝

⎞

7 to 0 PCL[23:16]

;

f

=

× f

× 8

XTAL

----------

24

PIXCLK

⎠

2

f_XTAL= 27 MHz nominal

20 F63Bh 640 × 480 to NTSC M

1B 5A73h 640 × 480 to PAL B/G (as by strapping

pins)

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 75: Horizontal offset register, subaddress 90h, bit description

Bit

Symbol

Description

7 to 0

XOFS[7:0]

with XOFS[9:8] (see Table 79) horizontal offset; deﬁnes the number of

PIXCLKs from horizontal sync (HSVGC) output to composite blanking

(CBO) output

Table 76: Pixel number register, subaddress 91h, bit description

Bit

Symbol

Description

7 to 0

XPIX[7:0]

with XPIX[9:8] (see Table 79) pixel in X direction; deﬁnes half the number

of active pixels per input line (identical to the length of CBO pulses)

Table 77: Vertical offset odd register, subaddress 92h, bit description

Bit

Symbol

Description

7 to 0

YOFSO[7:0] with YOFSO[9:8] (see Table 79) vertical offset in odd ﬁeld; deﬁnes (in the

odd ﬁeld) the number of lines from VSVGC to ﬁrst line with active CBO; if

no LUT data is requested, the ﬁrst active CBO will be output at

YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme

vertical downscaling and interlacing

Table 78: Vertical offset even register, subaddress 93h, bit description

Bit

Symbol

Description

7 to 0

YOFSE[7:0] with YOFSE[9:8] (see Table 79) vertical offset in even ﬁeld; deﬁnes (in the

even ﬁeld) the number of lines from VSVGC to ﬁrst line with active CBO; if

no LUT data is requested, the ﬁrst active CBO will be output at

YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme

vertical downscaling and interlacing

Table 79: MSBs register, subaddress 94h, bit description

Bit Symbol Description

7 and 6 YOFSE[9:8] see Table 78

5 and 4 YOFSO[9:8] see Table 77

3 and 2 XPIX[9:8]

1 and 0 XOFS[9:8]

see Table 76

see Table 75

Table 80: Line number register, subaddress 95h, bit description

Bit

Symbol

Description

7 to 0

YPIX[7:0]

with YPIX[9:8] (see Table 81) deﬁnes the number of requested input lines

from the feeding device; number of requested

lines = YPIX + YOFSE − YOFSO

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 81: Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description

Bit

Symbol Access Value Description

7

EFS

R/W

in Slave mode frame sync signal at pin FSVGC

0

1

ignored

accepted

6

5

PCBN

SLAVE

polarity of CBO signal

normal (HIGH during active video)

inverted (LOW during active video)

0

1

from the SAA7102; SAA7103 the timing to the graphics

controller is

0

1

master

slave

4

3

2

ILC

R/W

if hardware cursor insertion is active

set LOW for non-interlaced input signals

set HIGH for interlaced input signals

luminance sharpness booster

disabled

0

1

YFIL

HSL

0

1

enabled

trigger event for the horizontal state machine (device is slave

to HSVGC input)

0

1

not shifted

shifted 128 PIXCLKs adapted to a late HSVGC

see Table 80

1 and 0 YPIX[9:8]

Table 82: Sync control register, subaddress 97h, bit description

Bit

Symbol Access Value Description

7

HFS

R/W

horizontal sync is derived from

0

1

input signal (Save mode) at pin HSVGC

a frame sync signal (Slave mode) at pin FSVGC (only if EFS

is set HIGH)

6

VFS

R/W

vertical sync (ﬁeld sync) is derived from

input signal (Slave mode) at pin VSVGC

0

1

a frame sync signal (Slave mode) at pin FSVGC (only if EFS

is set HIGH)

5

4

OFS

PFS

R/W

pin FSVGC is

input

0

1

active output

polarity of signal at pin FSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 82: Sync control register, subaddress 97h, bit description …continued

Bit

Symbol Access Value Description

3

OVS

R/W

pin VSVGC is

input

0

1

active output

2

PVS

R/W

polarity of signal at pin VSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

1

0

OHS

PHS

R/W

pin HSVGC is

input

0

1

active output

polarity of signal at pin HSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

Table 83: Line length register, subaddress 98h, bit description

Bit Symbol Description

7 to 0 HLEN[7:0] with HLEN[10:8] (see Table 84) horizontal length;

number of PIXCLKs

HLEN =

– 1

-------------------------------------------------

line

Table 84: Input delay, MSB line length register, subaddress 99h, bit description

Bit

Symbol

Description

7 to 4 IDEL[3:0]

input delay; deﬁnes the distance in PIXCLKs between the active edge of

CBO and the ﬁrst received valid pixel

3

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

2 to 0 HLEN[10:8] see Table 83

Table 85: Horizontal increment register, subaddress 9Ah, bit description

Bit

Symbol

Description

7 to 0 XINC[7:0]

with XINC[11:8] (see Table 87) incremental fraction of the horizontal scaling

number of output pixels

--------------------------------------------------------

line

engine; XINC =

× 4096

---------------------------------------------------------

number of input pixels

-----------------------------------------------------

line

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 86: Vertical increment register, subaddress 9Bh, bit description

Bit

Symbol

Description

7 to 0

YINC[7:0]

with YINC[11:8] (see Table 87) incremental fraction of the vertical

number of active output lines

number of active input lines

scaling engine; YINC =

× 4096

---------------------------------------------------------------------

Table 87: MSBs vertical and horizontal increment register, subaddress 9Ch, bit description

Bit

Symbol

Description

see Table 86

see Table 85

7 to 4

3 to 0

YINC[11:8]

XINC[11:8]

Table 88: Weighting factor odd register, subaddress 9Dh, bit description

Bit

Symbol

Description

7 to 0

YIWGTO[7:0] with YIWGTO[11:8] (see Table 90) weighting factor for the ﬁrst line

YINC

2

of the odd ﬁeld; YIWGTO =

+ 2048

--------------

Table 89: Weighting factor even, subaddress 9Eh, bit description

Bit

Symbol

Description

7 to 0

YIWGTE[7:0] with YIWGTE[11:8] (see Table 90) weighting factor for the ﬁrst line

YINC – YSKIP

of the even ﬁeld; YIWGTE =

-------------------------------------

2

Table 90: Weighting factor MSB register, subaddress 9Fh, bit description

Bit

Symbol

Description

7 to 4

3 to 0

YIWGTE[11:8] see Table 89

YIWGTO[11:8] see Table 88

Table 91: Vertical line skip register, subaddress A0h, bit description

Bit

Symbol

Access Value Description

R/W with YSKIP[11:8] (see Table 92) vertical line skip;

deﬁnes the effectiveness of the anti-ﬂicker ﬁlter

000h most effective

FFFh anti-ﬂicker ﬁlter switched off

7 to 0

YSKIP[7:0]

Table 92: Blank enable for NI-bypass, vertical line skip MSB register, subaddress A1h, bit

description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

BLEN

R/W

for non-interlaced graphics in bypass mode

0*

no internal blanking

1

forced internal blanking

6 to 4

3 to 0

-

R/W

000

must be programmed with logic 0 to ensure

compatibility to future enhancements

YSKIP[11:8]

see Table 91

SAA7102_SAA7103_4

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SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 93: Border color Y register, subaddress A2h, bit description

Bit

Symbol

Description

luminance portion of border color in underscan area

7 to 0

BCY[7:0]

Table 94: Border color U register, subaddress A3h, bit description

Bit

Symbol

Description

7 to 0

BCU[7:0]

color difference portion of border color in underscan area

Table 95: Border color V register, subaddress A4h, bit description

Bit

Symbol

Description

7 to 0

BCV[7:0]

color difference portion of border color in underscan area

Table 96: Cursor color 1 R, G and B registers, subaddresses F0h to F2h, bit description

Subaddress Bit Symbol Description

F0h

F1h

F2h

7 to 0

CC1R[7:0] RED portion of ﬁrst cursor color

CC1G[7:0] GREEN portion of ﬁrst cursor color

CC1B[7:0] BLUE portion of ﬁrst cursor color

7 to 0

Table 97: Cursor color 2 R, G and B registers, subaddresses F3h to F5h, bit description

Subaddress Bit Symbol Description

F3h

F4h

F5h

7 to 0

CC2R[7:0] RED portion of second cursor color

CC2G[7:0] GREEN portion of second cursor color

CC2B[7:0] BLUE portion of second cursor color

7 to 0

Table 98: Auxiliary cursor color R, G and B registers, subaddresses F6h to F8h, bit

description

Subaddress Bit

Symbol

Description

F6h

F7h

F8h

7 to 0

AUXR[7:0] RED portion of auxiliary cursor color

AUXG[7:0] GREEN portion of auxiliary cursor color

AUXB[7:0] BLUE portion of auxiliary cursor color

7 to 0

Table 99: Horizontal cursor position and horizontal hot spot, MSB XCP registers,

subaddresses F9h and FAh, bit description

Subaddress Bit

Symbol

Description

FAh

F9h

7 to 3

XHS[4:0] horizontal hot spot of cursor

XCP[10:8] horizontal cursor position

XCP[7:0]

2 to 0

7 to 0

SAA7102_SAA7103_4

Product data sheet

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62 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 100: Vertical cursor position and vertical hot spot, MSB YCP registers, subaddresses

FBh and FCh, bit description

Subaddress Bit

Symbol

YHS[4:0] vertical hot spot of cursor

must be programmed with logic 0 to ensure compatibility to

future enhancements

1 and 0 YCP[9:8] vertical cursor position

7 to 0 YCP[7:0]

Description

FCh

7 to 3

2

-

FBh

Table 101: Input path control register, subaddress FDh, bit description

Bit

Symbol Access Value Description

7

LUTOFF R/W

color look-up table

0

1

active

bypassed

6

5

CMODE R/W

cursor mode

0

1

cursor mode; input color will be inverted

auxiliary cursor color will be inserted

LUT loading via input data stream

inactive

LUTL

R/W

0

1

color and cursor LUTs are loaded

input format

4 to 2 IF[2:0]

000

001

010

011

100

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R

5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB

5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB

8 + 8 + 8-bit 4 : 2 : 2 non-interlaced C_B-Y-C_R

8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656,

27 MHz clock) (in subaddresses 91h and 94h set

XPIX = number of active pixels/line)

101

110

8-bit non-interlaced index color

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R(special

bit ordering)

1

0

MATOFF R/W

DFOFF R/W

RGB to C_R-Y-C_Bmatrix

0

1

active

bypassed

down formatter

0

1

(4 : 4 : 4 to 4 : 2 : 2) in input path is active

bypassed

Table 102: Cursor bit map register, subaddress FEh, bit description

Data byte

Description

CURSA

RAM start address for cursor bit map; the byte following subaddress FEh points to

the ﬁrst cell to be loaded with the next transmitted byte; succeeding cells are

loaded by auto-incrementing until stop condition

SAA7102_SAA7103_4

Product data sheet

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63 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 103: Color look-up table register, subaddress FFh, bit description

Data byte

Description

COLSA

RAM start address for color LUT; the byte following subaddress FFh points to the

ﬁrst cell to be loaded with the next transmitted byte; succeeding cells are loaded by

auto-incrementing until stop condition

In subaddresses 5Bh, 5Ch, 5Dh, 5Eh and 62h all IRE values are rounded up.

8.4 Slave transmitter

Table 104: Status byte register, subaddress 00h, bit description

Bit

Symbol Access Value Description

7 to 5 VER[2:0] R

101

version identiﬁcation of the device: it will be changed with all

versions of the IC that have different programming models;

current version is 010 binary

4

3

CCRDO

CCRDE

R

1

0

1

0

set immediately after the closed caption bytes of the odd ﬁeld

have been encoded

reset after information has been written to the

subaddresses 67h and 68h

set immediately after the closed caption bytes of the even ﬁeld

have been encoded

reset after information has been written to the

subaddresses 69h and 6Ah

2

1

-

R

0

1

-

FSEQ

during ﬁrst ﬁeld of a sequence (repetition rate:

NTSC = 4 ﬁelds, PAL = 8 ﬁelds)

0

1

0

not ﬁrst ﬁeld of a sequence

during even ﬁeld

0

O_E

R

during odd ﬁeld

Table 105: Slave transmitter (slave address 89h)

Register

function

Subaddress

Data byte

D7 D6

VER2 VER1 VER0 CCRDO CCRDE

D5

D4

D3

D2

D1

FSEQ O_E

CID0

OVFL UDFL

D0

Status byte

Chip ID

00h

1Ch

80h

0

CID7 CID6 CID5 CID4

CID3

0

CID2 CID1

FIFO status

0

Table 106: Chip ID register, subaddress 1Ch, bit description

Bit Symbol Access Value Description

7 to 0 CID[7:0] R

chip ID

02h

03h

SAA7102

SAA7103

SAA7102_SAA7103_4

Product data sheet

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64 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 107: FIFO status register, subaddress 80h, bit description

Bit Symbol Access Value Description

7 to 2 -

R

0h

0

-

1

OVFL

no FIFO overﬂow

1

FIFO overﬂow has occurred; this bit is reset after this

subaddress has been read

0

UDFL

R

0

1

no FIFO underﬂow

FIFO underﬂow has occurred; this bit is reset after this

subaddress has been read

mbe737

6

G

(dB)

v

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

(1)

(2)

0

2

4

6

8

10

12

14

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig 6. Chrominance transfer characteristic 1

SAA7102_SAA7103_4

Product data sheet

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65 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

mbe735

2

G

v

(dB)

0

(1)

(2)

−2

−4

−6

0

0.4

0.8

1.2

1.6

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig 7. Chrominance transfer characteristic 2

mgd672

6

(4)

G

(dB)

v

0

(2)

(3)

−6

(1)

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

(1) CCRS[1:0] = 01.

(2) CCRS[1:0] = 10.

(3) CCRS[1:0] = 11.

(4) CCRS[1:0] = 00.

Fig 8. Luminance transfer characteristic 1 (excluding scaler)

SAA7102_SAA7103_4

Product data sheet

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66 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

mbe736

1

0

G

v

(dB)

(1)

−1

−2

−3

−4

−5

0

2

4

6

f (MHz)

(1) CCRS[1:0] = 00

Fig 9. Luminance transfer characteristic 2 (excluding scaler)

mgb708

6

G

(dB)

v

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

Fig 10. Luminance transfer characteristic in RGB (excluding scaler)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

67 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

mgb706

6

0

G

v

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

Fig 11. Color difference transfer characteristic in RGB (excluding scaler)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

68 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

9. Limiting values

Table 108: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected

together and grounded (0 V); all supply pins connected together.

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DDD

V_DDA

V_i(A)

digital supply voltage

−0.5 +4.6

analog supply voltage

V

input voltage at analog inputs

V

V_i(n)

input voltage at pins XTALI, SDA

and SCL

−0.5 V_DDD+ 0.5 V

V_i(D)

input voltage at digital inputs or outputs in 3-state

−0.5 +4.6

−0.5 +5.5

V

I/O pins

[1]

outputs in 3-state

V

∆V_SS

voltage difference between

-

100

mV

V_SSA(n)and V_SSD(n)

T_stg

storage temperature

−65

+150

70

°C

V

T_amb

V_esd

ambient temperature

0

-

[2]

[3]

electrostatic discharge voltage

human body model

machine model

2000

150

-

V

[1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V_DDD< 3.6 V.

[2] Class 2 according to JESD22-A114-B.

[3] Class A according to EIA/JESD22-A115-A.

10. Thermal characteristics

Table 109: Thermal characteristics

Symbol Parameter

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction to ambient

[1]

SAA7102E

SAA7103E

SAA7102H

SAA7103H

in free air

38

53

K/W

[1] The overall R_th(j-a)value can vary depending on the board layout. To minimize the effective R_th(j-a)all power

and ground pins must be connected to the power and ground layers directly. An ample copper area directly

under the SAA7102; SAA7103 with a number of through-hole plating, connected to the ground layer

(four-layer board: second layer), can also reduce the effective R_th(j-a). Please do not use any solder-stop

varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing

is recommended.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

69 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

11. Characteristics

Table 110: Characteristics

V_DDD= 3.0 V to 3.6 V; T_amb= 0 °C to 70 °C (typical values excluded); unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Supplies

V_DDA

V_DDD

I_DDA

analog supply voltage

digital supply voltage

analog supply current

digital supply current

3.15

3.0

1

3.3 3.45

3.3 3.6

110 140

70 90

V

[1]

[2]

mA

I_DDD

1

Inputs

V_IL

LOW-level input voltage at all digital input

pins except pins SDA and SCL

−0.5

-

+0.8

V

V_IH

HIGH-level input voltage at all digital input

pins except pins SDA and SCL

2.0

V_DDD+ 0.3 V

I_LI

C_i

input leakage current

input capacitance

-

10

8

µA

clocks

data

pF

I/Os at

8

high-impedance

Outputs; all digital output pins except pin SDA

V_OL

V_OH

LOW-level output voltage

I_OL= 2 mA

-

0.4

-

V

HIGH-level output voltage

I_OH= −2 mA

2.4

I²C-bus; pins SDA and SCL

V_IL

V_IH

I_i

LOW-level input voltage

−0.5

-

0.3V_DDD

V

HIGH-level input voltage

input current

0.7V_DDD

V_DDD+ 0.3 V

V_i= LOW or HIGH

I_OL= 3 mA

−10

+10

0.4

-

µA

V_OL

I_o

LOW-level output voltage (pin SDA)

output current

-

V

during acknowledge

3

mA

Clock timing; pins PIXCLKI and PIXCLKO

[3]

[4]

[3]

T_PIXCLK

t_d(CLKD)

δ

cycle time

22.5

-

100

-

ns

%

delay from PIXCLKO to PIXCLKI

duty factor

-

t_HIGH/T_PIXCLK

40

-

50 60

t_HIGH/T_CLKO2; output

%

[3]

t_r

rise time

fall time

-

3

ns

t_f

-

Input timing

t_SU;DAT

t_HD;DAT

input data set-up time

input data hold time

5

0

-

ns

Crystal oscillator

f_nom

nominal frequency

permissible deviation of nominal frequency

-

27

-

MHz

[5]

∆f/f_nom

−50 × 10⁻⁶

+50 × 10⁻⁶

SAA7102_SAA7103_4

Product data sheet

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70 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Table 110: Characteristics …continued

V_DDD= 3.0 V to 3.6 V; T_amb= 0 °C to 70 °C (typical values excluded); unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Crystal speciﬁcation

T_amb

C_L

ambient temperature

0

-

70

-

°C

pF

Ω

load capacitance

8

R_S

C₁

series resistance

-

80

motional capacitance (typical)

parallel capacitance (typical)

1.2

2.8

1.5 1.8

3.5 4.2

fF

C₀

pF

Data and reference signal output timing

C_o(L)

t_o(h)

t_o(d)

output load capacitance

output hold time

8

2

-

40

-

pF

ns

output delay time

16

CVBS and RGB outputs

V_o(CVBS)(p-p)output voltage CVBS (peak-to-peak value)

see Table 111

-

1.23 -

1.0

V

V_o(VBS)(p-p)output voltage VBS (S-video)

(peak-to-peak value)

-

V_o(C)(p-p)

output voltage C (S-video)

(peak-to-peak value)

see Table 111

-

0.89 -

V

V_o(RGB)(p-p)output voltage R, G, B (peak-to-peak value) see Table 111

-

0.7

2

-

V

∆V_o

inequality of output signal voltages

load resistance

-

%

R_L

-

37.5 -

Ω

B_DAC

output signal bandwidth of DACs

low frequency integral linearity error of DACs

−3 dB

15

-

MHz

LSB

ILE_lf(DAC)

DLE_lf(DAC)

3

1

low frequency differential linearity error of

DACs

-

[1] Minimum value for I²C-bus bit DOWNA = 1.

[2] Minimum value for I²C-bus bit DOWND = 1.

[3] The data is for both input and output direction.

[4] This parameter is arbitrary, if PIXCLKI is looped through the VGC.

[5] If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and

line/ﬁeld frequency.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

71 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

T

PIXCLK

t

HIGH

2.4 V

1.5 V

0.4 V

PIXCLKO

t

r

t

f

d(CLKD)

2.0 V

1.5 V

0.8 V

PIXCLKI

t

HD;DAT

t

SU;DAT

2.0 V

0.8 V

PDn

t

o(d)

t

o(h)

2.4 V

any output

0.4 V

mhb904

Fig 12. Input/output timing speciﬁcation

HSVGC

CBO

PD

XOFS

IDEL

XPIX

HLEN

mhb905

Fig 13. Horizontal input timing

HSVGC

VSVGC

CBO

YOFS

YPIX

mhb906

Fig 14. Vertical input timing

SAA7102_SAA7103_4

Product data sheet

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72 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

11.1 Teletext timing

Time t_FDis the time needed to interpolate input data TTX and insert it into the CVBS and

VBS output signal, such that it appears at t_TTX= 9.78 µs (PAL) or t_TTX= 10.5 µs (NTSC)

after the leading edge of the horizontal synchronization pulse.

Time t_PDis the pipeline delay time introduced by the source that is gated by

TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register

TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit

must be provided by the source.

Since the beginning of the pulses representing the TTXRQ signal and the delay between

the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS

and TTXHD), the TTX data is always inserted at the correct position after the leading edge

of the outgoing horizontal synchronization pulse.

Time t_i(TTXW)is the internally used insertion window for TTX data; it has a constant length

that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbit/s (PAL),

296 teletext bits at a text data rate of 5.7272 Mbit/s (world standard TTX) or 288 teletext

bits at a text data rate of 5.7272 Mbit/s (NABTS). The insertion window is not opened if

the control bit TTXEN is zero.

Using appropriate programming, all suitable lines of the odd ﬁeld (TTXOVS and TTXOVE)

plus all suitable lines of the even ﬁeld (TTXEVS and TTXEVE) can be used for teletext

insertion.

It is essential to note that the two pins used for teletext insertion must be

conﬁgured for this purpose by the correct I²C-bus register settings.

CVBS/Y

t

TTX

i(TTXW)

text bit #:

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TTX_SRES

t

FD

PD

TTXRQ_XCLKO2

mhb891

Fig 15. Teletext timing

SAA7102_SAA7103_4

Product data sheet

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73 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

C16

120 pF

L2

L3

2.7 µH

C13

C10

390 pF

560 pF

AGND

JP11

JP12

FIN

FOUT

FILTER 1

= byp.

ll act.

mhb912

Fig 17. FLTR0, FLTR1 and FLTR2 of Figure 16

12.1 Analog output voltages

The analog output voltages are dependent on the total load (typical value 37.5 Ω), the

digital gain parameters and the I²C-bus settings of the DAC reference currents (analog

settings).

The digital output signals in front of the DACs under nominal (nominal here stands for the

settings given in Table 52 to Table 56 for example a standard PAL or NTSC signal)

conditions occupy different conversion ranges, as indicated in Table 111 for a ¹⁰⁰

bar signal.

⁄₁₀₀color

By setting the reference currents of the DACs as shown in Table 111, standard compliant

amplitudes can be achieved for all signal combinations; it is assumed that in

subaddress 16h, parameter DACF = 0000b, that means the ﬁne adjustment for all DACs

in common is set to 0 %.

If S-video output is desired, the adjustment for the C (chrominance subcarrier) output

should be identical to the one for VBS (luminance plus sync) output.

Table 111: Digital output signals conversion range

Set/out

CVBS, sync tip-to-white

see Table 52 to Table 56

1014

VBS, sync tip-to-white

see Table 52 to Table 56

881

RGB, black-to-white

see Table 46 and Table 47

876

Digital settings

Digital output

Analog settings

Analog output

e.g. B DAC = 1Fh

1.23 V (p-p)

e.g. G DAC = 1Bh

1.00 V (p-p)

e.g. R DAC = G DAC = B DAC = 0Bh

0.70 V (p-p)

12.2 Suggestions for a board layout

Use separate ground planes for analog and digital ground. Connect these planes only at

one point directly under the device, by using a 0 Ω resistor directly at the supply stage.

Use separate supply lines for the analog and digital supply. Place the supply decoupling

capacitors close to the supply pins.

Use L_bead(ferrite coil) in each digital supply line close to the decoupling capacitors to

minimize radiation energy (EMC).

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

75 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

Place the analog coupling (clamp) capacitors close to the analog input pins. Place the

analog termination resistors close to the coupling capacitors.

Be careful of hidden layout capacitors around the crystal application.

Use serial resistors in clock, sync and data lines, to avoid clock or data reﬂection effects

and to soften data energy.

13. Test information

13.1 Boundary scan test

The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan

testing which allows board testing without special hardware (nails). The SAA7102;

SAA7103 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan

Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips.

The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST),

Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and

IDCODE are all supported; see Table 112. Details about the JTAG BST-TEST can be

found in the speciﬁcation “IEEE Std. 1149.1”. A ﬁle containing the detailed Boundary Scan

Description Language (BSDL) of the SAA7102; SAA7103 is available on request.

Table 112: BST instructions supported by the SAA7102; SAA7103

Instruction

Description

BYPASS

This mandatory instruction provides a minimum length serial path (1 bit)

between TDI and TDO when no test operation of the component is required.

EXTEST

SAMPLE

This mandatory instruction allows testing of off-chip circuitry and board level

interconnections.

This mandatory instruction can be used to take a sample of the inputs during

normal operation of the component. It can also be used to preload data values

into the latched outputs of the boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This

instruction addresses the bypass register while the boundary scan register is

in external test mode.

IDCODE

This optional instruction will provide information on the components

manufacturer, part number and version number.

13.1.1 Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state

(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces

the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard speciﬁes that the TAP controller will be forced

asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

76 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

13.1.2 Device identiﬁcation codes

A device identiﬁcation register is speciﬁed in “IEEE Std. 1149.1b-1994”. It is a 32-bit

register which contains ﬁelds for the speciﬁcation of the IC manufacturer, the IC part

number and the IC version number. Its biggest advantage is the possibility to check for the

correct ICs mounted after production and to determine the version number of the ICs

during ﬁeld service.

When the IDCODE instruction is loaded into the BST instruction register, the identiﬁcation

register will be connected between pins TDI and TDO of the IC. The identiﬁcation register

will load a component speciﬁc code during the CAPTURE_DATA_REGISTER state of the

TAP controller, this code can subsequently be shifted out. At board level this code can be

used to verify component manufacturer, type and version number. The device

identiﬁcation register contains 32 bits, numbered 31 to 0, where bit 31 is the most

signiﬁcant bit (nearest to TDI) and bit 0 is the least signiﬁcant bit (nearest to TDO);

see Figure 18.

MSB

31

LSB

28 27

12 11

1

0

TDI

TDO

0010

1

0111 0001 0000 0010

16-bit part number

000 0001 0101

4-bit

version

code

11-bit manufacturer

identification

mhb909

a. SAA7102.

MSB

31

LSB

28 27

12 11

1

0

TDI

TDO

0010

1

0111 0001 0000 0011

16-bit part number

000 0001 0101

4-bit

version

code

11-bit manufacturer

identification

mhb910

b. SAA7103.

Fig 18. 32 bits of identiﬁcation code

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

77 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

14. Package outline

LBGA156: plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm

SOT700-1

A

B

D

ball A1

index area

A

2

A

1

E

detail X

C

e

1

y

1/2 e

∅ v M

b

C

A

B

C

1

e

∅ w M

P

N

L

e

M

K

H

F

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

2

4

6

8

10

12

14

X

5

10 mm

0

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

1

e

2

y

D

E

v

w

y

1

2

max.

0.45 1.20 0.55 15.2 15.2

0.35 0.95 0.45 14.8 14.8

mm 1.65

0.12 0.35

1

13

0.25

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

01-05-11

01-11-06

SOT700-1

- - -

MO-192

- - -

Fig 19. Package outline SOT700-1 (LBGA156)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

78 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

y

X

A

33

23

34

22

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

θ

b

p

L

p

pin 1 index

L

12

44

detail X

1

11

w M

Z

v

M

A

D

b

p

e

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

10^o

0^o

0.25 1.85

0.05 1.65

0.4 0.25 10.1 10.1

0.2 0.14 9.9 9.9

12.9 12.9

12.3 12.3

0.95

0.55

1.2

0.8

1.2

0.8

mm

2.1

0.25

0.8

1.3

0.15 0.15

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

97-08-01

03-02-25

SOT307-2

Fig 20. Package outline SOT307-2 (QFP44)

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

79 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

15. Soldering

15.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

15.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

15.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

80 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

15.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

15.5 Package related soldering information

Table 113: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

81 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

16. Revision history

Table 114: Revision history

Document ID

Release date Data sheet status

Change notice

Doc. number

Supersedes

SAA7102_SAA7103_4 20060118

Product data sheet

CPCN200505019 -

SAA7102_SAA7103_3

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors

• Table 4: pin SCL corrected from I to I(/O) and updated description

• Table 4: updated description for pin SDA

• Package outline changed from SOT472-1 to SOT700-1

SAA7102_SAA7103_3 20040301

Product speciﬁcation -

9397 750 11445 SAA7102_03_2

9397 750 09214 SAA7102_03_1

9397 750 08371 -

SAA7102_03_2

SAA7102_03_1

20020218

20010925

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

82 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

17. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Right to make changes — Philips Semiconductors reserves the right to

18. Deﬁnitions

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

ICs with Macrovision copyright protection technology — This product

incorporates copyright protection technology that is protected by method

claims of certain U.S. patents and other intellectual property rights owned by

Macrovision Corporation and other rights owners. Use of this copyright

protection technology must be authorized by Macrovision Corporation and is

intended for home and other limited viewing uses only, unless otherwise

authorized by Macrovision Corporation. Reverse engineering or disassembly

is prohibited.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Disclaimers

20. Trademarks

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

83 of 84

SAA7102; SAA7103

Philips Semiconductors

Digital video encoder

22. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

13

13.1

13.1.1

13.1.2

Test information. . . . . . . . . . . . . . . . . . . . . . . . 76

Boundary scan test . . . . . . . . . . . . . . . . . . . . 76

Initialization of boundary scan circuit . . . . . . . 76

Device identiﬁcation codes. . . . . . . . . . . . . . . 77

14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78

15

15.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 80

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 80

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 81

Package related soldering information. . . . . . 81

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

15.2

15.3

15.4

15.5

7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Functional description . . . . . . . . . . . . . . . . . . . 7

Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . 9

Input formatter . . . . . . . . . . . . . . . . . . . . . . . . . 9

RGB LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Cursor insertion . . . . . . . . . . . . . . . . . . . . . . . 10

RGB Y-C_B-C_Rmatrix. . . . . . . . . . . . . . . . . . . . 11

Horizontal scaler. . . . . . . . . . . . . . . . . . . . . . . 11

Vertical scaler and anti-ﬂicker ﬁlter . . . . . . . . . 11

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Border generator. . . . . . . . . . . . . . . . . . . . . . . 12

Oscillator and Discrete Time Oscillator (DTO) 12

Low-pass Clock Generation Circuit (CGC) . . . 12

Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Teletext insertion and encoding (not

16

17

18

19

20

21

Revision history . . . . . . . . . . . . . . . . . . . . . . . 82

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 83

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Contact information . . . . . . . . . . . . . . . . . . . . 83

7.8

7.9

7.10

7.11

7.12

7.12.1

7.12.2

simultaneously with real-time control). . . . . . . 13

Video Programming System (VPS) encoding. 13

Closed caption encoder . . . . . . . . . . . . . . . . . 13

Anti-taping (SAA7102 only) . . . . . . . . . . . . . . 14

RGB processor . . . . . . . . . . . . . . . . . . . . . . . . 14

Triple DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Timing generator. . . . . . . . . . . . . . . . . . . . . . . 14

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15

Programming the SAA7102; SAA7103. . . . . . 16

Input levels and formats . . . . . . . . . . . . . . . . . 18

7.12.3

7.12.4

7.12.5

7.13

7.14

7.15

7.16

7.17

7.18

8

Register description . . . . . . . . . . . . . . . . . . . . 40

Bit allocation map . . . . . . . . . . . . . . . . . . . . . . 40

I²C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 44

Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . 45

Slave transmitter. . . . . . . . . . . . . . . . . . . . . . . 64

8.1

8.2

8.3

8.4

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69

Thermal characteristics. . . . . . . . . . . . . . . . . . 69

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 70

Teletext timing. . . . . . . . . . . . . . . . . . . . . . . . . 73

10

11

11.1

12

12.1

12.2

Application information. . . . . . . . . . . . . . . . . . 74

Analog output voltages . . . . . . . . . . . . . . . . . . 75

Suggestions for a board layout . . . . . . . . . . . . 75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 18 January 2006

Document number: SAA7102_SAA7103_4

Published in The Netherlands


型号：	SAA7105H/V1
厂家：	NXP
描述：	IC,TV/VIDEO CIRCUIT,VIDEO ENCODER,CMOS,QFP,64PIN,PLASTIC 编码器电视
文件：	总84页 (文件大小：407K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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