SAA7165WP_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA7165

Video Enhancement and

Digital-to-Analog processor

(VEDA2)

1996 Aug 20

Product speciﬁcation

Supersedes data of May 1995

File under Integrated Circuits, IC22

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

FEATURES

• CMOS circuit to enhance video data and to convert

luminance and colour-difference signals from

digital-to-analog

• Digital Colour Transient Improvement block (DCTI) to

increase the sharpness of colour transitions.

The improved pin-compatible SAA7165 can supersede

the SAA9065

• Controllable peaking of luminance signal

• Coring stage with controllable threshold to eliminate

noise in luminance signal

• 16-bit parallel input for 4 : 1 : 1 and 4 : 2 : 2 YUV data

• Data clock input LLC (Line-Locked Clock) for a data rate

up to 36 MHz

• Interpolation filter suitable for both formats to increase

the data rate in chrominance path

• 8-bit luminance and 8-bit multiplexed colour-difference

formats (7-bit formats optional)

• Polarity of colour-difference signals selectable

• All functions controlled via I²C-bus

• MC input to support various clock and pixel rates

• Separate digital-to-analog converters (9-bit resolution

for Y; 8-bit for colour-difference signals)

• Formatting YUV input data; 4 : 2 : 2 format,

4 : 1 : 1 format and filter characteristics selectable

• 1 V (p-p)/75 Ω outputs realized by two resistors

• No external adjustments.

• HREF input to determine the active line (number of

pixels)

QUICK REFERENCE DATA

SYMBOL

V_DDD

PARAMETER

MIN.

4.5

TYP.

MAX.

5.5

UNIT

digital supply voltage

analog supply voltage

total supply current

5

V

V_DDA

I_DD(tot)

V_IL

4.75

−

5.25

tbf

−

mA

V

LOW-level input voltage on YUV-bus

HIGH-level input voltage on YUV-bus

input data rate

−0.5

2

+0.8

V_IH

−

V_DDD+ 0.5

V

f_LLC

−

36

−

MHz

V

V_o(p-p)

R_L

output signals Y, (R − Y) and (B − Y) (peak-to-peak value)

output load resistance

−

2

125

−

Ω

ILE

DC integral linearity error in output signal (8-bit data)

DC differential error in output signal (8-bit data)

operating ambient temperature range

−

1

LSB

°C

DLE

T_amb

−

0.5

70

0

−

ORDERING INFORMATION

TYPE

PACKAGE

DESCRIPTION

NUMBER

NAME

VERSION

SOT187-2

SAA7165WP PLCC44 plastic leaded chip carrier; 44 leads

1996 Aug 20

2

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

PINNING

SYMBOL PIN

DESCRIPTION

REFL_Y

C_Y

1

low reference of luminance DAC (connected to V_SSA1

)

2

capacitor for luminance DAC (high reference)

SUB

UV0

UV1

UV2

UV3

UV4

UV5

UV6

UV7

V_DDD1

V_SSD1

Y0

3

substrate (connected to V_SSA1)

4

UV signal input bit UV7 (digital colour-difference signal)

UV signal input bit UV6 (digital colour-difference signal)

UV signal input bit UV5 (digital colour-difference signal)

UV signal input bit UV4 (digital colour-difference signal)

UV signal input bit UV3 (digital colour-difference signal)

UV signal input bit UV2 (digital colour-difference signal)

UV signal input bit UV1 (digital colour-difference signal)

UV signal input bit UV0 (digital colour-difference signal)

+5 V digital supply voltage 1

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

digital ground 1 (0 V)

Y signal input bit Y7 (digital luminance signal)

Y signal input bit Y6 (digital luminance signal)

Y signal input bit Y5 (digital luminance signal)

Y signal input bit Y4 (digital luminance signal)

Y signal input bit Y3 (digital luminance signal)

Y signal input bit Y2 (digital luminance signal)

Y signal input bit Y1 (digital luminance signal)

Y signal input bit Y0 (digital luminance signal)

connected to ground (action pin for testing)

connected to ground (shift pin for testing)

Y1

Y2

Y3

Y4

Y5

Y6

Y7

AP

SP

MC

data clock CREF (e.g. 13.5 MHz); at MC = HIGH, the LLC divider-by-two is inactive

line-locked clock signal (LL27 = 27 MHz)

data clock for YUV data inputs (for active line 768Y or 640Y long)

reset input (active LOW)

I²C-bus clock line

I²C-bus data line

LLC

HREF

RESET

SCL

SDA

V_SSD2

V_DDD2

V_DDA1

(R − Y)

V_SSA1

V_SSA2

(B − Y)

V_DDA2

V_SSA3

Y

digital ground 2 (0 V)

+5 V digital supply voltage 2

+5 V analog supply voltage for buffer of DAC 1

±(R − Y) output signal (analog signal)

analog ground 1 (0 V)

analog ground 2 (0 V)

±(B − Y) output signal (analog colour-difference signal)

+5 V analog supply voltage for buffer of DAC 2

analog ground 3 (0 V)

Y output signal (analog luminance signal)

+5 V analog supply voltage for buffer of DAC 3

V_DDA3

1996 Aug 20

4

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

SYMBOL PIN

DESCRIPTION

CUR

41

42

43

44

current input for analog output buffers

V_DDA4

C_UV

supply and reference voltage for the three DACs

capacitor for chrominance DACs (high reference)

low reference of chrominance DACs (connected to V_SSA1

REFL_UV

)

handbook, full pagewidth

UV3

UV4

UV5

7

8

9

39

38

37

36

35

34

33

32

31

30

29

Y

V

SSA3

DDA2

V

UV6 10

UV7 11

(B − Y)

V

SSA2

SAA7165

V

12

13

DDD1

SSA1

V

(R − Y)

SSD1

V

Y0 14

Y1 15

DDA1

V

DDD2

V

16

Y2

SSD2

SDA

Y3 17

MEH465

Fig.2 Pin configuration.

5

1996 Aug 20

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

FUNCTIONAL DESCRIPTION

Formatting Y and UV

The CMOS circuit SAA7165 processes digital YUV-bus

data up to a data rate of 36 MHz. The data inputs Y7 to Y0

and UV7 to UV0 (see Fig.1) are provided with 8-bit data.

The data of digital colour-difference signals U and V are in

a multiplexed state (serial in 4 : 2 : 2 or 4 : 1 : 1 format;

Tables 2 and 3).

The input data formats are formatted into the internally

used processing formats (separate for 4 : 2 : 2 and

4 : 1 : 1 formats). The IFF, IFC and IFL bits control the

input data format and determine the right interpolation filter

(see Figs 10 to 13).

Peaking and coring

Data is read with the rising edge of LLC (Line-Locked

Clock) to achieve a data rate of LLC at MC = HIGH only. If

MC is supplied with the frequency CREF (¹⁄₂LLC for

example), data is read only at every second rising edge

(see Fig.3).

Peaking is applied to the Y signal to compensate several

bandwidth reductions of the external pre-processing.

Y signals can be improved to obtain a better sharpness.

There are the two switchable bandpass filters

BF1 and BF2 controlled via the I²C-bus by the bits BP1,

BP0 and BFB. Thus, a frequency response is achieved in

combination with the peaking factor K (Figs 5 to 9;

K is determined by the bits BFB, WG1 and WG0).

The 7-bit YUV input data are also supported by means of

bit R78 (R78 = 0). Additionally, the luminance data format

is converted for internal use into a two´s complement

format by inverting the MSB. The Y input byte

(bits Y7 to Y0) represents luminance information; the UV

input byte (bits UV7 to UV0) represents one of the two

digital colour-difference signals in 4 : 2 : 2 format

(Table 2).

The coring stage with controllable threshold (4 states

controlled by CO1 and CO0 bits) reduces noise

disturbances (generated by the bandpass gain) by

suppressing the amplitude of small high-frequent signal

components. The remaining high-frequent peaking

component is available for a weighted addition after

coring.

The HREF input signal (HREF = HIGH) determines the

start and the end of an active line (see Fig.3) and the

number of pixels respectively. The analog output Y is

blanked at HREF = LOW, the (B − Y) and (R − Y) outputs

are in a colourless state. The blanking level can be set with

bit BLV. The SAA7165 is controllable via the I²C-bus.

Table 1 LLC and MC conﬁguration modes in DMSD applications (note 1)

PIN INPUT SIGNAL

LLC (LL27)

DESCRIPTION

LLC

MC

LLC

MC

LLC

MC

The data rate on YUV-bus is half the clock rate on pin LLC, e.g. in

SAA7151B, SAA7191 and SAA7191B single scan operation.

CREF

LLC (LL27)

MC = HIGH

LLC (LL27)

MC = HIGH

The data rate on YUV-bus must be identical to the clock rate on pin LLC,

e.g. in double scan applications.

The data rate on YUV-bus must be identical to the clock rate on pin LLC,

e.g. SAA9051 single scan operation.

Note

1. YUV data are only latched with the rising edge of LCC at MC = HIGH.

1996 Aug 20

6

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

Table 2 Data format 4 : 2 : 2

INPUT

Y0 (LSB)

PIXEL BYTE SEQUENCE (4 : 2 : 2 FORMAT)

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

U0

U1

U2

U3

U4

U5

U6

U7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

V0

V1

V2

V3

V4

V5

V6

V7

1

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

U0

U1

U2

U3

U4

U5

U6

U7

2

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

V0

V1

V2

V3

V4

V5

V6

V7

3

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

U0

U1

U2

U3

U4

U5

U6

U7

4

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

V0

V1

V2

V3

V4

V5

V6

V7

5

Y1

Y2

Y3

Y4

Y5

Y6

Y7 (MSB)

UV0 (LSB)

UV1

UV2

UV3

UV4

UV5

UV6

UV7 (MSB)

Y frame

UV frame

0

2

4

Table 3 Data format 4 : 1 : 1

INPUT

PIXEL BYTE SEQUENCE (4 : 1 : 1 FORMAT)

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

UV0

UV1

UV2

UV3

UV4

UV5

UV6

UV7

Y frame

UV frame

0

V6

V7

U6

U7

0

V4

V5

U4

U5

1

V2

V3

U2

U3

2

V0

V1

U0

U1

3

V6

V7

U6

U7

4

V4

V5

U4

U5

5

V2

V3

U2

U3

6

V0

V1

U0

U1

7

0

4

1996 Aug 20

7

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

handbook, full pagewidth

LL27

(LLC)

CREF

internal

bus clock

(LLC2)

HREF

start of

active line

Byte number for pixels:

0

1

2

3

4

5

6

7

Y signal

50 Hz

U and V signal

U0

V0

U2

V2

U4

V4

U6

V6

0

1

2

3

4

5

6

7

Y signal

60 Hz

U and V signal

U0

V0

U2

V2

U4

V4

U6

V6

MEH268

a. Start of active line.

handbook, full pagewidth

LL27

(LLC)

CREF

internal

bus clock

(LLC2)

HREF

end of

active line

Byte number for pixels:

714

715

716

717

718

719

Y signal

50 Hz

U and V signal

U714

V714

U716

V716

U718

V718

Y signal

714

715

716

717

718

719

60 Hz

U and V signal

U714

V714

U716

V716

U718

V718

MEH269

b. End of active line.

Fig.3 Line control by HREF for 4 : 2 : 2 format, CREF = 13.5 MHz; HREF = 720 pixel; 50 and 60 Hz field.

1996 Aug 20

8

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

In order to obtain the point of inflection, the second

derivative of the signal is calculated. The improved

transition is centred with respect to the point of inflection of

the original signal. Thus, there is no horizontal shift of the

resulting signal.

Interpolation

The chrominance interpolation filter consists of various

filter stages, multiplexers and de-multiplexers to increase

the data rate of the colour-difference signals by a factor of

2 or 4. The switching of the filters by the bits IFF, IFC and

IFL is described previously. Additional signal samples with

significant amplitudes between two consecutive signal

samples of the low data rate are generated.

The transition area length to be improved is controlled via

I²C-bus by the bits LI1 and LI0 (Table 5); the sensitivity of

the DCTI block is controlled by the bits GA1 and GA0.

The CMO bit controls the colour detail sensitivity. It should

be set to logic 1 (ON) if the video signal contains fine

colour details (recommended operation mode).

The time-multiplexed U and V samples are stored in

parallel for converting.

Data switch

Digital-to-Analog Converters (DACs)

The digital signals are adapted to the conversation range.

U and V data have 8-bit formats again; Y can have 9 bits

dependent on peaking. Blanking and switching to

colourless level is applied here. Bits can be inverted by

INV-bit to change the polarity of colour-difference output

signals.

Conversion is separate for Y, U and V. The converters use

resistor chains with low-impedance output buffers.

The minimum output voltage is 200 mV to reduce integral

non-linearity errors. The analog signal, without load on

output pin, is between 0.2 and 2.2 V floating.

An application for 1 V/75 Ω on outputs is shown in Fig.14.

Digital Colour Transient Improvement (DCTI)

Each digital-to-analog converter has its own supply and

ground pins suitable for decoupling. The reference

voltage, supplying the resistor chain of all three DACs, is

the supply voltage V_DDA4. The current into pin 41 is

0.3 mA; a larger current improves the bandwidth but

increases the integral non-linearity.

The DCTI circuit improves the transition behaviour of the

UV colour-difference signals. As the CVBS signal allows

for a 4 : 1 : 1 bandwidth representation only, the DCTI

improves the transients to the same performance as

signals coming from a 4 : 2 : 2 source, or even more.

I²C-bus format

Table 4 I²C-bus format; see notes 1 to 7

S

slave address

A

subaddress

A

data 0

A

...

data n

A

P

Notes

1. S = START condition.

2. Slave address = 1011 111X.

3. A = acknowledge; generated by the slave.

4. Subaddress = subaddress byte (Table 5);

If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

5. Data = data byte (Table 5).

6. P = STOP condition.

7. X = R/W control bit:

a) X = 0; order to write (the circuit is slave receiver).

b) X = 1; order to read (the circuit is slave transmitter).

1996 Aug 20

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Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

Table 5 I²C-bus transmission

DATA BITS

SUBADDRESS

FUNCTION

D7

D6

D5

D4

D3

D2

D1

D0

01

02

03

peaking and coring

AFB

IFF

0

CO1

IFC

0

CO0

IFL

BP1

CMO

DC0

BP0

LI1

BFB

LI0

WG1

GA1

R78

WG0

GA0

INV

input formats; interpolation

input/output setting

DC1

DRP

BLV

Table 6 Bit functions in data bytes

BIT

DESCRIPTION

CO1 and CO0

AFB, BP1, BP0, BFB

BFB, WG1 and WG0

IFF, IFC and IFL

CMO

control of coring threshold; see Table 7

bandpass ﬁlter selection; see Table 8

peaking factor K; see Table 9

input format and ﬁlter control at 13.5 MHz data rate; see Table 10

choice modiﬁcation; 0 = modiﬁcation off; 1 = modiﬁcation on.

DCTI timing range; see Table 11

LI1 and LI0

GA1 and GA0

DC1 and DC0

DRP

DCTI gain factor; see Table 12

delay compensation of luminance signal; see Table 13

UV input data code; 0 = two’s complement; 1 = offset binary

blanking level on Y output; 0 = 16 LSB; 1 = 0 LSB

YUV input data solution; 0 = 7-bit data; 1 = 8-bit data

polarity of colour-difference output signals:

0 = normal polarity equal to input signal

BLV

R78

INV

1 = inverted polarity

Table 7 Logic levels and function of CO1 and CO0

DATA BITS

FUNCTION

CO1

CO0

0

1

0

1

0

1

coring off

small noise reduction

medium noise reduction

high noise reduction

Table 8 Logic levels and function of AFB, BP1, BP0 and BFB

DATA BITS

FUNCTION

AFB

BP1

BP0

BFB

X

0

1

X

0

1

0

1

X

0

1

characteristic (see Fig.5)

characteristic (see Fig.6)

characteristic (see Fig.7)

characteristic (see Fig.8)

BF1 filter bypassed (see Fig.9a)

BF1 filter bypassed (see Fig.9b)

1

1996 Aug 20

10

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

Table 9 Logic levels and function of BFB, WG1 and WG0

DATA BITS

FUNCTION

BFB

WG1

WG0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

K = ¹⁄₈; minimum peaking

K = ¹⁄₄

K = ¹⁄₂

K = 1; maximum peaking

K = 0; peaking off

K = ¹⁄₄; minimum peaking

K = ¹⁄₂

K = 1; maximum peaking

Table 10 Logic levels and function of IFF, IFC and IFL

DATA BITS

FUNCTION

IFF

IFC

IFL

0

1

0

1

0

1

0

1

X

0

1

X

4 : 1 : 1 format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)

4 : 1 : 1 format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)

4 : 1 : 1 format; −3 dB attenuation at 1.2 MHz video frequency; (see Fig.12)

4 : 2 : 2 format; −3 dB attenuation at 1.6 MHz video frequency; (see Fig.10)

4 : 2 : 2 format; −3 dB attenuation at 600 kHz video frequency; (see Fig.11)

4 : 2 : 2 format; −3 dB attenuation at 2.5 MHz video frequency; (see Fig.13)

Table 11 Logic levels and function of LI1 and LI0

Table 13 Logic levels and function of DC1 and DC0

DATA BITS

RANGE

DATA BITS

DELAYED CLOCK

CYCLES

LI1

LI0

DC1

DC0

0

1

0

1

0

1

+4 to −4

+6 to −6

+8 to −8

+12 to −12

0

1

0

1

0

1

0

+1

−2

−1

Table 12 Logic levels and function of GA1 and GA0

DATA BITS

FACTOR

GA1

GA0

0

1

0

1

0

1

off

1

⁄

4

1

⁄

2

1

1996 Aug 20

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Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL

V_DDD1

PARAMETER

digital supply voltage 1 (pin 12)

digital supply voltage 2 (pin 31)

analog supply voltage 1 (pin 32)

analog supply voltage 2 (pin 37)

analog supply voltage 3 (pin 40)

analog supply voltage 4 (pin 42)

digital supply voltage

MIN.

MAX.

UNIT

−0.3

−0.5

−

+7

V

V_DDD2

V_DDA1

V_DDA2

V_DDA3

V_DDA4

V_DDD

∆V_GND

V_I

V

difference voltage V_SSD− V_SSA

voltage on all input pins 4 to 11, 14 to 27 and 41

voltage on analog output pins 33, 36 and 39

electrostatic handling for all pins

total power dissipation

±100

V_DDD

−

mV

V

−0.3

V_O

V

V_ESD

P_tot

±2000

V

0

tbf

mW

°C

T_stg

storage temperature

−55

0

+150

70

T_amb

operating ambient temperature

Note

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

THERMAL CHARACTERISTICS

SYMBOL

R_{th j-a}

PARAMETER

VALUE

46

UNIT

thermal resistance from junction to ambient in free air

K/W

1996 Aug 20

12

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

CHARACTERISTICS

V_DDD= 4.5 to 5.5 V; V_DDA= 4.75 to 5.25 V; LLC = LL27; MC = CREF = 13.5 MHz; T_amb= 0 to 70 °C; measurements

taken in Fig.14; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDD1

V_DDD2

V_DDA1

V_DDA2

V_DDA3

V_DDA4

I_DDD

supply voltage range (pin 12)

supply voltage range (pin 31)

supply voltage range (pin 32)

supply voltage range (pin 37)

supply voltage range (pin 40)

supply voltage range (pin 42)

for digital part

4.5

5

5.5

V

for digital part

4.5

5

5.5

V

for buffer of DAC 1

for buffer of DAC 2

for buffer of DAC 3

4.75

5

5.25

tbf

V

5

V

5

V

DAC reference voltage 4.75

5

V

supply current (I_DDD1+ I_DDD2

)

for digital part

−

tbf

mA

I_DDA

supply current (I_DDA1+ I_DDA4

)

for DACs and buffers

tbf

YUV-bus inputs (pins 4 to 11 and 14 to 21) (see Figs 3 and 4)

V_IL

V_IH

C_I

LOW-level input voltage

HIGH-level input voltage

input capacitance

−0.5

2.0

−

+0.8

V

V_DDD+ 0.5

10

V

V_I= HIGH

pF

µA

I_LI

input leakage current

−

4.5

Inputs AP, SP, MC, LLC, HREF and RESET (pins 22 to 27)

V_IL

V_IH

C_I

LOW-level input voltage

HIGH-level input voltage

input capacitance

−0.5

2.0

−

+0.8

V

V_DDD+ 0.5

V

V_I= HIGH

10

pF

µA

V

I_LI

input leakage current

MC input voltage for LL27

CREF signal on MC input

−

4.5

V₂₄

27 MHz data rate

2.0

−

V_DDD+ 0.5

CREF data rate; note 1

−

V

I²C-bus SCL and SDA (pins 28 and 29)

V_IL

V_IH

I_I

LOW-level input voltage

HIGH-level input voltage

input current

−0.5

3.0

−

+1.5

V

V_DDD+ 0.5

±10

V

V_I= LOW or HIGH

I₂₉= 3 mA

µA

V

V_ACK

output voltage at acknowledge

(pin 29)

−

0.4

I₂₉

output current

during acknowledge

3

−

mA

V

Digital-to-analog converters (pins 1, 2, 41, 42, 43 and 44)

V_DAC

input reference voltage for internal

resistor chains (pin 42)

4.75

5

5.25

I_CUR

V_1,44

C_L

input current (pin 41)

R_41-42= 15 kΩ

−

300

0

−

µA

V

reference voltage LOW

pin connected to V_SSA1

external blocking capacitor to

V_SSA1for reference voltage HIGH

(pins 2 and 43)

0.1

µF

f_LLC

data conversation rate (clock)

Fig.3

−

36

MHz

1996 Aug 20

13

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

RES_DAC

resolution

luminance DAC

chrominance DACs

8-bit data

−

9

8

−

bits

−

bits

ILE

DC integral linearity error

DC differential error

1.0

0.5

LSB

DLE

8-bit data

Y, (R − Y) and (B − Y) analog outputs (pins 33, 36 and 39)

V_o(p-p)

output signal voltage

(peak to peak value)

without load

−

2

−

V

V_33,36,39

V₃₉

output voltage range

output blanking level

output no-colour level

without load; note 2

Y output; note 3

0.2

−

2.2

−

V

16

128

LSB

V_33,36

±(R − Y), ±(B − Y);

−

note 4

R_33,36,39

internal serial output resistance

−

25

−

Ω

R_L33,36,39output load resistance

external load

125

20

−

Ω

B

t_d

output signal bandwidth

−3 dB

−

MHz

ns

signal delay from input to Y output

tbf

LCC timing (pin 25) (see Fig.3)

T_LLC

t_{p H}

t_r

cycle time

pulse width

rise time

27.7

40

−

37

50

−

41

60

5

ns

%

ns

t_f

fall time

−

6

YUV-bus timing (pins 4 to 11 and 14 to 21) (see Fig.5)

t_SU;DAT

t_HD;DAT

input data set-up time

input data hold time

10

3

−

ns

MC timing (pin 24) (see Fig.5)

t_SU;DAT

t_HD;DAT

input data set-up time

input data hold time

10

3

−

ns

RESET timing (pin 27)

t_SU

set-up time after power-on or

failure

active LOW; note 5

4 × t_LLC

−

ns

Notes

1. YUV-bus data is read at MC = HIGH (pin 24) clocked with LLC (see Fig.5); data is read only with every second rising

edge of LLC when CREF = ¹⁄₂LLC on pin 24.

2. 0.2 to 2.2 V output voltage range at 8-bit DAC input data; the data word can increase to 9-bit dependent on peaking

factor.

3. The luminance signal is set to the digital black level: 16 LSB for BLV-bit = 0; 0 LSB for BLV-bit = 1.

4. The chrominance amplitudes are set to the digital colourless level of 128 LSB.

5. The circuit is prepared for a new data initialization.

1996 Aug 20

14

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

t

r

handbook, full pagewidth

f

2.4 V

input clock

LLC (LL27)

1.5 V

0.6 V

T

LLCH

t

T

LLC

t

HD;DAT(min)

SU;DAT(min)

HD;DAT

t

2.0 V

0.8 V

input data

YUV-bus,

CREF (MC)

MEH270

data valid

Fig.4 YUV-bus data and CREF timing.

Table 14 YUV-bus data processing delay

PROCESSING DELAY

LLC CYCLES

REMARKS

YUV digital input

66

at MC = 1

YUV analog output

132

at MC = ¹⁄₂LLC

1996 Aug 20

15

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

MEH271

16

Y

handbook, full pagewidth

V

(dB)

14

(1)

12

10

(2)

8

6

(3)

4

(4)

2

0

2

0

1

3

4

5

6

7

f

(MHz)

Y

(1) K = 1

(3) K = ¹

(4) K = ¹

⁄

4

(2) K = ¹

⁄

2

8

Fig.5 Peaking frequency response with I²C-bus control bits BP1 = 0; BP0 = 0 and BFB = 0.

MEH272

16

Y

handbook, full pagewidth

V

(dB)

14

(1)

(2)

12

10

8

(3)

(4)

6

4

2

0

2

1

3

4

5

6

7

f

(MHz)

Y

(1) K = 1

(3) K = ¹

(4) K = ¹

⁄

4

(2) K = ¹

⁄

2

8

Fig.6 Peaking frequency response with I²C-bus control bits BP1 = 0; BP0 = 1 and BFB = 0.

1996 Aug 20

16

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

MEH273

16

Y

handbook, full pagewidth

V

(dB)

14

(1)

12

10

(2)

8

(3)

6

(4)

4

2

0

2

0

1

3

4

5

6

7

f

(MHz)

Y

(1) K = 1

(3) K = ¹

(4) K = ¹

⁄

4

(2) K = ¹

⁄

2

8

Fig.7 Peaking frequency response with I²C-bus control bits BP1 = 1; BP0 = 0 and BFB = 0.

MEH274

16

Y

handbook, full pagewidth

V

(dB)

14

(1)

(2)

12

10

8

6

4

2

(3)

(4)

0

2

1

3

4

5

6

7

f

(MHz)

Y

(1) K = 1

(3) K = ¹

(4) K = ¹

⁄

4

(2) K = ¹

⁄

2

8

Fig.8 Peaking frequency response with I²C-bus control bits BP1 = 1; BP0 = 1 and BFB = 0.

1996 Aug 20

17

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

MEH470

10

handbook, full pagewidth

V

Y

(dB)

8

6

4

(1)

(2)

2

(3)

(4)

0

−2

−4

2

0

1

3

4

5

6

7

f

(MHz)

Y

a. AFB = 0.

MEH471

10

handbook, full pagewidth

V

Y

(dB)

8

(1)

(2)

6

4

2

0

(3)

(4)

−2

−4

2

0

1

3

4

5

6

7

f

(MHz)

Y

b. AFB = 1.

(1) K = 1

(3) K = ¹

⁄

4

(2) K = ¹

⁄

2

(4) K = 0

Fig.9 Peaking frequency response with I²C-bus control bits BP1 = 0; BP0 = 0 and BFB = 1; bandpass filter BF1

bypassed and peaking off.

1996 Aug 20

18

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

MEH474

0

handbook, full pagewidth

V

U

(dB)

−4

−8

−12

−16

−20

−24

−28

−32

2

0

1

3

4

5

6

7

f

(MHz)

Y

Fig.10 Interpolation filter at DCTI off with I²C-bus control bits IFF = 0; IFC = 0 and IFL = 0 in 4 : 1 : 1 format and

control bits IFF = 1; IFC = 0 and IFL = 0 in 4 : 2 : 2 format; 13.5 MHz data rate.

MEH473

0

handbook, full pagewidth

V

U

(dB)

−4

−8

−12

−16

−20

−24

−28

−32

2

0

1

3

4

5

6

7

f

(MHz)

Y

Fig.11 Interpolation filter at DCTI off with I²C-bus control bits IFF = 0; IFC = 0 and IFL = 1 in 4 : 1 : 1 format and

control bits IFF = 1; IFC = 0 and IFL = 1 in 4 : 2 : 2 format; 13.5 MHz data rate.

1996 Aug 20

19

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

MEH472

0

handbook, full pagewidth

V

U

(dB)

−4

−8

−12

−16

−20

−24

−28

−32

2

0

1

3

4

5

6

7

f

(MHz)

Y

Fig.12 Interpolation filter at DCTI off with I²C-bus control bits IFF = 0; IFC = 1 and IFL = 0 in 4 : 1 : 1 format;

13.5 MHz data rate.

MEH475

0

handbook, full pagewidth

V

U

(dB)

−3 dB

−8

−16

−24

−32

−40

−48

−56

−64

2

0

1

3

4

5

6

7

f

(MHz)

Y

Fig.13 Interpolation filter with I²C-bus control bits IFF = 1; IFC = 1 and IFL = X in 4 : 2 : 2 format;

13.5 MHz data rate.

1996 Aug 20

20

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

PACKAGE OUTLINE

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

e

E

D

y

X

A

39

29

b

p

Z

E

28

40

b

1

w

M

44

1

H

E

pin 1 index

A

1

A

4

e

(A )

3

6

18

k

1

β

L

p

k

detail X

7

17

v

M

A

e

Z

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

(1)

A

min.

A

max.

k

1

max.

Z

E

(1)

1

4

D

UNIT

mm

A

b

D

E

e

H

k

L

p

v

w

y

β

b

D

E

D

E

3

p

1

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22

14.99 14.99 17.40 17.40 1.07

1.44

1.02

0.53

0.33

0.51

0.51 0.25 3.05

0.020 0.01 0.12

1.27

0.05

0.18 0.18 0.10 2.16 2.16

o

45

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.630 0.630 0.695 0.695 0.048

0.590 0.590 0.685 0.685 0.042

0.057

0.040

0.021

0.013

inches

0.020

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-25

97-12-16

SOT187-2

112E10

MO-047AC

1996 Aug 20

22

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

SOLDERING

Introduction

Wave soldering

Wave soldering techniques can be used for all PLCC

packages if the following conditions are observed:

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering

technique should be used.

• The longitudinal axis of the package footprint must be

parallel to the solder flow.

• The package footprint must incorporate solder thieves at

the downstream corners.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Reﬂow soldering

Reflow soldering techniques are suitable for all PLCC

packages.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

The choice of heating method may be influenced by larger

PLCC packages (44 leads, or more). If infrared or vapour

phase heating is used and the large packages are not

absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our “Quality

Reference Handbook” (order code 9397 750 00192).

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

1996 Aug 20

23

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1996 Aug 20

24

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

NOTES

1996 Aug 20

25

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

NOTES

1996 Aug 20

26

Philips Semiconductors

Product speciﬁcation

Video Enhancement and Digital-to-Analog

processor (VEDA2)

SAA7165

NOTES

1996 Aug 20

27

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Belgium: see The Netherlands

Brazil: see South America

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 926 5361, Fax. +7 095 564 8323

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Colombia: see South America

Czech Republic: see Austria

Slovakia: see Austria

Slovenia: see Italy

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 1949

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 615 800, Fax. +358 615 80920

South America: Rua do Rocio 220, 5th floor, Suite 51,

04552-903 São Paulo, SÃO PAULO - SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 829 1849

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. +30 1 4894 339/911, Fax. +30 1 4814 240

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 481 7730

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,

Chung Hsiao West Road, Sec. 1, P.O. Box 22978,

TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 825 344, Fax.+381 11 635 777

Middle East: see Italy

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Internet: http://www.semiconductors.philips.com

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA51

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

657021/1200/02/pp28

Date of release: 1996 Aug 20

Document order number: 9397 750 01047


型号：	SAA7165WP
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PQCC44, PLASTIC, LCC-44, Consumer IC:Other
文件：	总28页 (文件大小：133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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