SAA7710T [NXP]
Dolby* Pro Logic Surround; Incredible Sound; *杜比定向逻辑环绕声;令人难以置信的声音
| 型号： | SAA7710T |
| 厂家： | 
NXP |
| 描述： | Dolby* Pro Logic Surround; Incredible Sound |
| 文件： | 总28页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7710T
Dolby* Pro Logic Surround;
Incredible Sound
1998 Mar 13
Product specification
Supersedes data of 1997 Oct 03
File under Integrated Circuits, IC01
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
FEATURES
• Two stereo I2S-bus digital input channels
• Three stereo I2S-bus digital output channels
• I2C-bus mode control
• Up to 45 ms on-chip delay-line (fs = 44.1 kHz)
• Optional clock divider for crystal oscillator
• Package: SO32L
• Hall/matrix surround sound functions
• Incredible sound functions
• Operating supply voltage range: 4.5 to 5.5 V.
• 5-band parametric equalizer on main channels left,
centre, right (fs = 32 kHz)
Functions
• Tone control (bass/treble) on all four output channels
(fs = 44.1 kHz).
• 4-channel active surround, 20 Hz to 20 kHz
(maximum 1⁄2fs)
• Adaptive matrix
GENERAL DESCRIPTION
• 7 kHz low-pass filters
This data sheet describes the 104 ROM-code version of
the SAA7710T chip. The SAA7710T chip is a high quality
audio-performance digital add-on processor for digital
sound systems. It provides all the necessary features for
complete Dolby Pro Logic surround sound on chip.
In addition to the Dolby Pro Logic surround function, this
device also incorporates a 5-band parametric equalizer, a
tone control section and a volume control. Instead of Dolby
Pro Logic surround, the Hall/matrix surround and
Incredible sound functions can be used together with the
equalizer or tone control.
• Adjustable delay for surround channel
• Modified Dolby B noise reduction
• Noise sequencer
• Variable output matrix
• Sub woofer
• Centre mode control: on/off, normal, phantom, wide
• Output volume control
• Automatic balance and master level control with
DC-offset filter
QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+6.5
550
VDD + 0.5 V
UNIT
DC supply voltage
V
∆VDD
Vi
voltage difference between two VDDx pins
maximum input voltage
DC supply current
−
mV
−0.5
−
IDD
50
mA
ISS
DC supply current
−
50
mA
°C
Tamb
Tstg
ambient operating temperature
storage temperature range
−40
−65
+85
+150
°C
Remark Dolby*: Dolby’ and ‘Pro Logic’ are trademarks of Dolby Laboratories Licensing Corporation. They are available
only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and
application information must be obtained.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SAA7710T/N104
1998 Mar 13
SO32
plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
2
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22
23
2
1
2
2
I S_BCKIN1
I S_BCKOUT
2
I S_WSOUT
2
2
I S input 1
I S_WSIN1
SAA7710T
S
24
2
I S_DATAIN1
SURROUND
CHANNEL
DELAY LINE
2
I S outputs
28
29
30
2
2
2
I S_DATAOUT1
I S
I S OUT 1
L
C
INPUT
SWITCH
CIRCUIT
5-BAND
PARAMETRIC
EQUALIZER
OR
TONE
CONTROL
DOLBY PRO LOGIC
OR
DOLBY 3 STEREO
OR
HALL/MATRIX
OR
INCREDIBLE
SOUND
25
27
26
2
I S_DATAIN2
VARIABLE
OUTPUT
MATRIX
data 1
2
2
I S_DATAOUT2
I S OUT 2
R
2
2
I S input 2
I S_BCKIN2
SW
2
I S_WSIN2
2
2
I S_DATAOUT3
I S OUT 3
17
DSP_RESET
5
12
32
V
DD1
13
3
AUTO BALANCE
FUNCTION
V
TSCAN
RTCB
DD2
+
TEST
+
V
DD3
19
18
V
DD_XTAL
2
I C BUS
FLAG TEST
CONTROL
OSCILLATOR
TRANSCEIVER
V
SS_XTAL
6
V
SS1
11
31
V
SS2
V
SS3
7
8
9
10
15
16
14
21
20
4
MGE751
DSP_IN1
DSP_IN2
SDA
DSP_OUT1
SCL
A0
OSC
XTAL
SHTCB
DSP_OUT2
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
PINNING
SYMBOL
PIN
DESCRIPTION
I2S_WSOUT
1
I2S-bus slave word-select
output
I2S_BCKOUT
RTCB
2
3
I2S-bus slave bit-clock output
asynchronous reset test control
block input (active LOW)
SHTCB
4
clock divider switch enable
input (LOW = divide)
handbook, halfpage
VDD1
5
6
7
8
9
positive power supply
ground power supply
flag input 1
2
I S_WSOUT
V
V
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DD3
SS3
VSS1
2
I S_BCKOUT
DSP_IN1
DSP_IN2
DSP_OUT1
DSP_OUT2
VSS2
2
RTCB
I S_DATAOUT3
3
flag input 2
2
SHTCB
I S_DATAOUT2
4
flag output 1
2
V
I S_DATAOUT1
5
10 flag output 2
DD1
2
11 ground power supply
12 positive power supply
13 scan control input
14 I2C-bus slave address
selection input
15 I2C-bus serial data input/output
16 I2C-bus serial clock input
V
I S_BCKIN2
6
SS1
VDD2
2
DSP_IN1
DSP_IN2
I S_WSIN2
7
TSCAN
A0
2
I S_DATAIN2
8
SAA7710T
2
DSP_OUT1
DSP_OUT2
I S_DATAIN1
9
2
I S_WSIN1
10
11
12
13
14
15
16
SDA
2
SCL
V
I S_BCKIN1
SS2
DSP_RESET
VSS_XTAL
17 chip reset input (active LOW)
V
OSC
DD2
18 ground power supply crystal
oscillator
TSCAN
A0
XTAL
V
DD_XTAL
VDD_XTAL
19 positive power supply crystal
oscillator
V
SDA
SCL
SS_XTAL
XTAL
20 crystal oscillator output
21 crystal oscillator input
DSP_RESET
OSC
MGE750
I2S_BCKIN1
I2S_WSIN1
22 I2S-bus master bit-clock input 1
23 I2S-bus master word-select
input 1
I2S_DATAIN1
I2S_DATAIN2
I2S_WSIN2
24 I2S-bus master data input 1
25 I2S-bus master data input 2
26 I2S-bus master word-select
input 2
I2S_BCKIN2
I2S_DATAOUT1
I2S_DATAOUT2
I2S_DATAOUT3
VSS3
27 I2S-bus master bit-clock input 2
28 I2S-bus slave data output 1
29 I2S-bus slave data output 2
30 I2S-bus slave data output 3
31 ground power supply
Fig.2 Pin configuration.
VDD3
32 positive power supply
1998 Mar 13
4
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
• Equalizer (3- or 5-band on L, C and R) or tone control
(L, C, R and S); fixed output matrix(1); volume control
FUNCTIONAL DESCRIPTION
Figure 1 shows the block diagram of the SAA7710T.
The SAA7710T consists of a Dolby Pro Logic decoder
together with equalizer or tone control. The Dolby Pro
Logic part of the IC may be used to decode audio
soundtracks (Dolby surround movies or Dolby surround
video productions) from for example, a video recorder
(VCR) or a CD laser disc into four channels Left, Centre,
Right and Surround (L, C, R and S).
If desired, post-processing with either an equalizer or a
tone control section is possible. In addition to this, a Sub
Woofer (SW) channel, digital volume control and a
user-programmable variable output matrix are
implemented.
• Equalizer (5-band on L, C and R); variable output
matrix(1); volume control
• Extra sub woofer(1).
THE DOLBY 3 STEREO MODE
In Dolby 3 stereo mode, several blocks must be initialized
and controlled during operation:
• Noise generator and noise sequencer
• Centre channel mode(1) (normal, phantom, wide and off)
• Combining network coefficients
• Incredible Sound widening of the stereo base on two
Hall/matrix surround sound functions are implemented for
material not encoded using Dolby Surround. These
features can be used as an alternative to Dolby Pro Logic
and can also be combined with the equalizer or tone
control sections.
speakers
• Effect is user adjustable.
THE HALL/MATRIX SURROUND MODE
In hall/matrix surround mode, the blocks listed below must
be initialized and controlled during operation:
Incredible sound is a Philips patented technology which
substantially improves the stereo effect of a television or
audio system. Using advanced signal processing,
speakers that are positioned close together can imitate the
sound produced by speakers that are far apart.
• Input balance control
• Hall or matrix surround Mode setting
• All-pass and filter transfer characteristics(1)
• 7 kHz low-pass filter in surround channel(1)
• Surround channel delay(1).
Functional modes
The device thus supports three main modes, Dolby Pro
Logic/Dolby 3 stereo or hall/matrix surround or Incredible
sound mode. All modes can be combined with equalizing
(3-band or 5-band) or tone control depending on fs and
available cycle budget.
Possible post-processing modes for hall/matrix surround
are as above:
• Volume control only
• Equalizer (5-band on L, C and R) or tone control
(L, C, R and S); fixed output matrix(1); volume control
• Equalizer (5-band on L,C,R); variable output matrix(1);
volume control
THE DOLBY PRO LOGIC MODE
In Dolby Pro Logic mode, several blocks must be initialized
and controlled during operation:
• Extra sub woofer(1).
• Noise generator and noise sequencer
• Centre channel mode(1) (normal, phantom, wide, off)
• Combining network coefficients
• 7 kHz low-pass filter in surround channel(1)
• Surround channel delay time(1)
THE INCREDIBLE SOUND MODE
In the Incredible sound mode the blocks listed below must
be initialized and controlled during operation:
• Incredible sound coefficients
• Modified Dolby B noise reduction must be on.
• Combining network coefficients.
Possible post-processing modes for Dolby Pro Logic are:
Possible post-processing modes for incredible sound are
as follows:
• Volume control only
• Volume control only
• Equalizer (5-band on L and R) or tone control (L and R);
(1) The coefficient set used to initialize and control the operation
of the Dolby Pro Logic mode depends upon the selected
sampling frequency fs = 32, 44.1 or 48 kHz.
variable output matrix(1), volume control
• Extra sub-woofer(1).
1998 Mar 13
5
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
The slave oscillator mode: in this mode (see Fig.4),
the oscillator circuit acts as a slave driven by a master
system clock. The clock divider can be switched on or off
using pin SHTCB. When the divider is not used, the duty
cycle of the clock will depend on the master system
clock duty cycle and the rising and falling edge times.
This places a tolerance of 5% on the 50% duty cycle of
the master system clock (see Chapter “AC
ADDITIONAL INFORMATION
The possible modes of operation are discussed in more
detail in the “SAA7710T Dolby Pro Logic Programming
Guide, Application Note AN95063”. This also includes
which features are available for a given system clock
frequency and sample frequency and the possible input
configurations.
characteristics”).
Clock circuit and oscillator
In order to be able to control the phase of the clock signal
during testing the divider is skipped and the signal is
directly fed to the circuit via the multiplexer in the TEST
position.
The chip has an on board crystal clock oscillator. The block
schematic of this Pierce oscillator is shown in
Figs 3 and 4. The active element needed to compensate
for the loss resistance of the crystal is the amplifier Gm.
This amplifier is placed between the XTAL (output) pin and
the OSC (sense) pin. The gain of the oscillator is internally
controlled by the automatic gain control. This prevents too
much power loss in the crystal. The higher harmonics are
then as low as possible. The signals on the OSC and XTAL
pin are differentially amplified.
SUPPLY OF THE CRYSTAL OSCILLATOR
The power supply connections to the oscillator are
separated from the other supply lines to minimise
feedback from on-chip ground bounce to the oscillator
circuit. Noise on the power supply affects the AGC
operation so the power supply should be decoupled.
The VSS_XTAL pin is used as ground supply and the
VDD_XTAL as positive supply.
The oscillator has these two modes of operation:
The crystal oscillator mode: in this mode (see Fig.3),
a quartz crystal oscillator is used to generate a clock
signal which is subsequently divided by 2 to ensure that
the final clock signal has a 50% duty cycle.
The oscillator circuit components Rbias and C1, C2
depend on the crystal. In the case of an overtone
oscillator, the ground harmonic is filtered out by L1 and
C3. Pin SHTCB is held low so that the divided signal is
selected. Only a quartz crystal should be used in this
mode.
1998 Mar 13
6
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
CLOCK
BUFFER
0
1
DIVIDE
BY 2
Gm
AGC
TEST
4
ON CHIP
21
20
19
V
18
MGE752
OSC
XTAL
V
SHTCB
= 0
DD_XTAL
SS_XTAL
OFF CHIP
100 kΩ
L1
4.7 µH
R
bias
C3
1 nF
C1
10 pF
C2
10 pF
Fig.3 Block diagram crystal oscillator circuit.
CLOCK
BUFFER
0
1
DIVIDE
BY 2
Gm
AGC
TEST
4
ON CHIP
21
20
19
V
18
MGE753
OSC
XTAL
V
SHTCB
= 1
DD_XTAL
SS_XTAL
OFF CHIP
100 kΩ
40 pF
10 pF
10 nF
slave
input
Fig.4 Block diagram slave oscillator circuit.
7
1998 Mar 13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I2S-bus Interfaces and system clock
I2S-BUS BASICS
T
cy
t
≥0.35 T
HC
t
≥0.35 T
≥0.2 T
LC
V
(70%)
(20%)
IH
SCK
V
IL
t
t
≥0
hr
sr
V
(70%)
(20%)
IH
SD WS
V
IL
SCK
WS
MSB
LEFT
MSB
RIGHT
SD
MBH173
Fig.5 I2S-bus timing and format.
I2S-BUS INPUT CIRCUIT
For communication with external digital sources and or
additional external processors the I2S-bus digital interface
bus is used. It is a serial 3-line bus, with one line for data,
one line for clock and one line for the word select.
The I2S-bus input circuits can be configured in the
following way using the SEL-IN1/IN2 bit (see Table 4):
1. I2S input 1 is master
(SEL-IN1/IN2 bit = logic 0(default))
2. I2S input 2 is master (SEL-IN1/IN2 bit = logic 1).
Figure 5 shows an excerpt of the Philips I2S-bus
specification interface report regarding the general timing
and format of I2S-bus. Word Select (WS) logic 0 means left
channel word, logic 1 means right channel word.
The incoming bit-clock frequency defines the accuracy in
terms of number of bits of the incoming data samples.
The input circuit is designed to accept any number of bits
per channel up to a maximum of 18 bits. The accepted
data format is MSB-first.
The serial data is transmitted in two’s complement with the
MSB first. One clock period after the negative edge of the
word select line the MSB of the left channel is transmitted.
Data is synchronised with the negative edge of the clock
and latched at the positive edge.
1998 Mar 13
8
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
Table 1 Data Accuracy in I2S-bus Interface
INCOMING DATA WIDTH
I2S-BUS IN DATA WIDTH
I2S-BUS OUT DATA WIDTH
A < 18
A
A
B ≥18
18
18
interface: I2S_WSOUT, I2S_BCKOUT. These two output
signals can be 3-stated by setting the DIS_BCKWS bit
(see Table 4). The 3-state output of the I2S_DATAOUT3
signal can be enabled by setting the ENA_I2S3 bit (see
Table 4).
THE I2S-BUS OUTPUT INTERFACE
The I2S-bus data output interfaces (see Fig.1) I2S OUT 1,
I2S OUT 2 and I2S OUT 3 use the same I2S-bus data
signals which are selected by the input switch circuit. The
I2S-bus WS and BCK output signals remain in phase with
the external input signals at all times. The output data is
1/fs cycle delayed relative to the input data. The selected
word-select and bit-clock are included as part of the output
The timing diagram of the I2S-bus outputs is shown in
Fig.6. The timing details can be found in Chapter “AC
characteristics”.
t
CL
LC
2
I S_BCKIN1, 2
2
t
I S_BCKOUT
HC
t
t
t
d1
f
r
t
r
t
f
2
I S_WSIN1, 2
WS
2
I S_WSOUT
t
d2
t
s2
2
DATA (in)
I S_DATAIN1, 2
MSB
DATA VALID
t
d3
t
t
t
r
f
acc
2
DATA (out)
I S_DATAOUT1, 2, 3
MSB
MGE755
Fig.6 Timing diagram of I2S-bus output interface.
1998 Mar 13
9
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I2C-bus control and commands
DATA TRANSFER
CHARACTERISTICS OF THE I2C-BUS
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.9).
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to the VDDX via a pull-up resistor when
connected to the output stages of a microprocessor.
Data transfer can only be initiated when the bus is not
busy.
ACKNOWLEDGE
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set up and hold times
must be taken into account. A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a STOP
condition (see Fig.10).
BIT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.7).
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.8).
SDA
SCL
MLC160
data line
stable
change
of data
data valid
allowed
Fig.7 Bit transfer on the I2C-bus.
10
1998 Mar 13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
a
SDA
SCL
S
P
START condition
STOP condition
MLC161
Fig.8 START and STOP conditions.
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete
interrupt within receiver
clock line held LOW while
interrupts are serviced
SCL
1
2
7
8
9
1
2
3 to 8
9
ACK
S
START condition
P
STOP condition
MLC162
Fig.9 Data transfer on the I2C-bus.
11
1998 Mar 13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
data output
from transmitter
not acknowledge
data output
from receiver
acknowledge
SCL from
master
1
2
7
8
9
MLC163
S
clock pulse for
START condition
acknowledgement
Fig.10 Acknowledge on the I2C-bus.
Write cycles
I2C-BUS FORMAT
Addressing
The I2C-bus configuration for a write cycle is shown in
Fig 12. The write cycle is used to write in the input selector
control register and to initialise or update coefficient
values.
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the START
procedure.
The data length is 2 bytes or 3 bytes depending of the
accessed memory. If the Y-memory is addressed the data
length is 2 bytes, in case of the X-memory the length is
3 bytes. The slave receiver detects the address and
adjusts the bytes accordingly.
Slave address (pin A0)
The chip acts as a slave receiver or a slave transmitter.
Therefore the clock signal SCL is only an input signal.
The data signal SDA is a bidirectional line. The chip slave
address is shown in Table 2.
Read cycles
The I2C-bus configuration for a Read cycle is shown in
Fig 13. The read cycle is used to read data values from
XRAM or YRAM.
The sub address bit A0 corresponds to the hardware
address pin A0 which allows the device to have 1 of 2
different addresses.
1998 Mar 13
12
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
During the write cycle, the I2C-bus clock frequency must
be reduced.
I2C-BUS FUNCTION BITS
Input selector control register
The I2C-bus clock frequency has the following constraints:
The write only, two byte, input selector control register is
located on absolute address 0FFFH (4095) and consists
of 16 bits, starting with bit 0 and ending with bit 15.
fs > 2 × fIIC
fs = I2S-bus sampling frequency
fIIC = I2C-bus clock frequency.
Deviation from the I2C-bus specification
If this constraint cannot be met, a higher I2C-bus frequency
can be obtained in the following way:
By making the I2C-bus master insert a delay (td) after the
acknowledge pulse (see Fig.11). The delay should be
larger than or equal to 1/fs where fs is the I2S-bus
sampling frequency.
1. The data hold time (tHD;DAT) for this device (≥0 ns as
stated in the I2C-bus specification) should be as
follows:
a) For the crystal oscillator mode (SHTCB = 0):
6
≥
---------
fxtal
By not using the auto-increment feature. This means
that each data word must be preceded by its intended
destination address.
b) For the slave oscillator mode (SHTCB = 0):
6
≥
-------------
fslave
c) For the slave oscillator mode (SHTCB = 1):
3
≥
-------------
fslave
SCL
SDA
ACKNOWLEDGE AFTER WORD
auto-increment address register
MGE756
t
d
Fig.11 Timing of reduced I2C-bus frequency.
1998 Mar 13
13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
Table 2 Slave address
MSB
LSB
0
0
1
1
1
1
A0
R/W
Table 3 Location of input selector control register bits in I2C-bus serial transmission; note 1
MSB
LSB
DATAH
DATAL
15
14
13
12
11
10
9
8
A
7
6
5
4
3
2
1
0
A
P
Note
1. Explanation for the contents of the register bits:
a) A = standard I2C-bus acknowledge.
b) Number = bit number according to Table 4.
c) P = standard I2C-bus STOP condition.
Table 4 Input selector control bits
SYMBOL
SEL-IN1/IN2
DIS_BCKWS
ENA-I2S3
FUNCTION
NUMBER OF BITS
ON RESET
IN1(0)
BIT NO
I2S input 1 or I2S input 2 input
disable I2S_BCKOUT and I2S_WSOUT
enable I2S_DATAOUT3
1
1
1
1
5
7
enable(0)
disable(0)
resets(0)
13
15
IMODE
I flag resets/background tasking
XRAM format
The XRAM block consists of 256 18-bit RAM locations 0 to 255 and is located on the absolute address range of 0000H
to 00FFH. The I2C-bus transfer consists of 18 useful bits out of 24 bits.
Table 5 Format XRAM bits; note 1
MSB
LSB
DATAH
DATAM
DATAL
D
D
D
D
D
D
17 16
A
15 14 13 12 11 10
9
8
A
7
6
5
4
3
2
1
0
A
P
Note
1. Explanation for the contents of the register bits:
a) D = contents of I2C-bus data register bit is don’t care.
b) A = standard I2C-bus acknowledge.
c) Number = bit number being useful bit XRAM memory.
d) P = standard I2C-bus STOP condition.
1998 Mar 13
14
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
YRAM format
The YRAM block consists of 256 12-bit RAM locations 0 to 255 and is located on the absolute address range of
0800H to 08FFH. The I2C-bus transfer consists of 12 useful bits out of 16 bits.
Table 6 Format YRAM bits; note 1
MSB
LSB
DATAH
11
DATAM
D
D
D
D
10
9
8
A
7
6
5
4
3
2
1
0
A
P
Note
1. Explanation for the contents of the register bits:
a) D = contents of I2C-bus data register bit is don’t care.
b) A = standard I2C-bus acknowledge.
c) Number = bit number being useful bit XRAM memory.
d) P = standard I2C-bus STOP condition.
Error processing
If a read action is done without first initialising the memory address the acknowledge after the read command will not be
generated by the chip. This should be treated as an error message:
Table 7
S Write ACK ADDRH ACK ADDRL ACK S Read
S Read NEG ACK
Correct read sequence
Incorrect read sequence; address is not initialized
1998 Mar 13
15
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A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
0
0
1
1
1
1 A
0
ADDR H
ADDR L
DATA H
DATA M
P
DATA L
S
0
auto increment if repeated n-groups of 3 (2) bytes
address
MBH529
R/W
Fig.12 Master transmitter writes to chip.
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
0
0
1
1
1
1 A
0
ADDR H
ADDR L
0
S
0
1
1
1
1 A
1
0
DATA H
P
DATA M
DATA L
S
0
auto increment if repeated n-groups of 3 (2) bytes
address
MBH528
R/W
R/W
Fig.13 Master transmitter reads from chip.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
When the level on the DSP_RESET pin is HIGH, the DSP
program starts to run.
DSP_RESET
The DSP_RESET pin is active LOW and has an internal
pull-up resistor. To enable a proper switch-on of the supply
voltage a capacitor should be connected between this pin
and VSS. The capacitor value is such that the chip is in a
reset state as long as the power supply is not stabilized.
When the level on the DSP_RESET pin is low, the SDA pin
is asynchronously set to a high-impedance state. In the
absence of a clock and during the power-up reset, the SDA
line is high-impedance.
The DSP_RESET has the following functions:
TEST MODE CONNECTIONS (TSCAN, RTCB AND SHTCB
PINS)
• The bits of the input selector control register are set to
logic 0 (see Table 4)
The TSCAN, RTCB and SHTCB pins are used to put the
chip in test mode and to test the internal connections.
Each pin has an internal pull-down resistor to ground.
In the application these pins can be left open-circuit or
connected to ground.
• The program counter is set to address 0000H
• The I2C-bus interface is initialised; the SDA pin is
guaranteed high-impedance.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL PARAMETER CONDITIONS
VDD DC supply voltage
MIN.
−0.5
MAX.
+6.5
550
VDD + 0.5 V
UNIT
V
∆VDD
Vi(max)
lIK
voltage difference between two VDDx pins
maximum input voltage
−
mV
−0.5
−
DC input clamp diode current
Vi < −0.5 V or
10
20
20
20
mA
Vi > VDD + 0.5 V
lOK
lO
DC output clamp diode current output
type 4 mA
Vo < −0.5 V or
Vo > VDD + 0.5 V
−
−
−
mA
mA
mA
DC output source or sink current output
type 4 mA
−0.5 V < Vo < VDD + 0.5 V
−0.5 V < Vo < VDD + 0.5 V
lDD
DC output source or sink current output
type 4 mA
lDD
DC VDD supply current per pin
DC VSS supply current per pin
ESD sensitivity for all pins
human body model
−
−
50
50
mA
mA
lSS
VESD
100 pF; 1500 Ω
3000
300
250
100
−
−
V
machine model all pins except pin OSC 200 pF; 2.5 µH; 0 Ω
−
V
machine model pin OSC
latch-up protection
200 pF; 2.5 µH; 0 Ω
−
V
LTCH
Ptot
CIC spec/test method
−
mA
mW
°C
°C
total power dissipation
operating ambient temperature
storage temperature
700
+85
+150
Tamb
Tstg
−40
−65
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
57
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
K/W
1998 Mar 13
17
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
DC CHARACTERISTICS
VDD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = −40 to +85 °C; note 1; unless otherwise specified.
SYMBOL
VDDtot
IDD(tot)
PARAMETER
total DC supply voltage
total DC supply current
CONDITIONS
MIN.
4.5
TYP.
MAX.
5.5
UNIT
5
V
DSP frequency = 18 MHz;
maximum activity DSP
−
50
55
mA
Ptot
total power dissipation
DSP frequency = 18 MHz;
maximum activity DSP
−
250
300
mW
VIH
HIGH level input voltage
all digital inputs and I/Os
pin types I1, I2 and I3
pin type I4
0.7VDDX
−
−
V
V
V
V
V
V
0.8VDDX
−
−
VIL
LOW level input voltage
all digital inputs and I/Os
pin types I1, I2 and I3
pin type I4
−
−
0.3VDDX
−
−
0.2VDDX
Vhys
VOH
hysteresis voltage
pin type I4
−
0.33VDDX
−
−
HIGH level output voltage VDDX = 4.5 V; Io = −4 mA;
digital outputs pin type O1 and O2
LOW level output voltage VDDX = 4.5 V; Io = 4 mA;
4.0
−
VOL
ILI
−
−
−
−
−
−
0.5
1
V
digital outputs
pin types I3, O1 and O2
input leakage current
Vi = 0 or VDDX voltage;
pin type I1
−
µA
µA
kΩ
kΩ
ILO
output leakage current
3-state outputs
Vo = 0 or VDDX voltage;
pin type I3 and O2
−
5
Rpu(VDDX)(int) internal pull-up resistor to pin type I4
VDDX
17
17
134
134
Rpd(VSSD)(int) internal pull-down resistor pin type I2
to VSSD
Crystal oscillator
VDDX
positive supply voltage
crystal oscillator
4.5
5
5.5
V
Note
1. VDDX = VDD_XTAL
.
1998 Mar 13
18
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
AC CHARACTERISTICS
V
DD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP.
crystal frequency see Fig.3
MAX.
36.864
UNIT
fxtal
−
−
MHz
dB
αf
spurious frequency attenuation
current through crystal
transconductance
20
−
−
−
Ixtal
at input voltage swing 0.2 V
at start-up
500
8
−
µA
mS
mV
pF
gm(XTAL)
Vxtal
CL(XTAL)
Rxtal
4
−
voltage across crystal
load capacitance
note 1
−
500
25
20
−
−
−
allowed loss resistor of crystal Cp = 5 pF; C1 = 10 pF;
C2 = 10 pF
−
60
Ω
Slave oscillator
fslave
slave frequency
no divider; see Fig.4
see Fig.4
−
−
−
−
−
18.432
−
MHz
V
SLVOLT
slave drive voltage
input rise times
input fall times
3.75
−
tr
tf
0.1 to 0.9VDD_XTAL; note 2
0.1 to 0.9VDD_XTAL; note 2
20
ns
−
20
ns
Timing
I2C-BUS INPUTS/OUTPUT
tf
fall time I2C-bus
maximum input frequency
0.1 to 0.9VDD
SDA, SCL
−
−
5.7
−
ns
fi(max)
−
100
kHz
I2S-BUS INPUTS/OUTPUTS
tr
rise time I2S-bus (O2)
CL = 30 pF; 0.1 to 0.9VDD
CL = 30 pF; 0.1 to 0.9VDD
−
7.3
8.3
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
tf
fall time I2S-bus (O2)
CL pulse width HIGH
CL pulse width LOW
WS out delay time
data in hold time
−
−
tHC
tLC
td1
td2
ts2
td3
tacc
112
112
0
−
−
−
−
−
0
−
−
data in set-up time
data out delay time
data out access time
25
0
−
−
−
5
(3)
−
−
5 + 0.5 × CL
ALL OTHER OUTPUTS (O1)
tr
tf
rise time
fall time
CL = 30 pF; 0.1 to 0.9VDD
CL = 30 pF; 0.1 to 0.9VDD
−
−
7.3
8.3
−
−
ns
ns
ALL OTHER INPUTS
tr
tf
input rise times
input fall times
VDD = 5.5 V
VDD = 5.5 V
−
−
6
6
200
200
ns
ns
Notes
1. The load capacitance is the sum of the series connection of C1 and C2 (see Fig.3) and the parasitic parallel capacitor
of the crystal Cp.
2. With a 50%, ±5% duty cycle on oscillator drive input (see Fig.4).
3. The value for the capitative load CL is given in pF.
1998 Mar 13
19
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
INTERNAL CIRCUITRY
DC VOLTAGE
(V)
PIN
SYMBOL
PIN TYPE
INTERNAL CIRCUIT
7
8
DSP_IN1
DSP_IN2
I1
I1
I1
I1
I1
I1
I1
I1
I1
I4
7, 8, 16, 22, 23,
24, 25, 26, 27
16 SCL
22 I2S_BCKIN1
23 I2S_WSIN1
24 I2S_DATAIN1
25 I2S_DATAIN2
26 I2S_WSIN2
27 I2S_BCKIN2
17 DSP_RESET
MGE758
17
+
MGE759
3
4
RTCB
I2
I2
I2
I1
SHTCB
13 TSCAN
14 A0
3, 4, 13, 14
MGE760
1
2
9
I2S_WSOUT
I2S_BCKOUT
O2
O2
O2
O2
DSP_OUT1
1, 2, 9, 30
30 I2S_DATAOUT3
MGE761
1998 Mar 13
20
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
DC VOLTAGE
(V)
PIN
SYMBOL
PIN TYPE
INTERNAL CIRCUIT
15 SDA
I3
15
MGE762
10 DSP_OUT2
O1
O1
O1
28 I2S_DATAOUT1
29 I2S_DATAOUT2
10, 28, 29
MGE763
5
6
VDD1
VSS1
tbf
0
11 VSS2
0
12 VDD2
31 VSS3
5
0
32 VDD3
21 OSC
20 XTAL
19 VDD_XTAL
18 VSS_XTAL
5
tbf
tbf
5
19
20
21
0
18
MGE764
1998 Mar 13
21
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ahdnbok,uflapegwidt
220 Ω
220 Ω
220 Ω
2
220 Ω
220 Ω
220 Ω
2
I S_BCKIN1
22
23
2
1
I S_BCKOUT
220 pF
220 pF
220 Ω
2
220 Ω
2
I S_WSIN1
I S_WSOUT
2
I S input 1
220 pF
220 pF
SAA7710T
S
2
220 Ω
220 Ω
220 Ω
220 Ω
220 Ω
I S_DATAIN1 24
SURROUND
CHANNEL
DELAY LINE
220 pF
2
I S outputs
2
220 Ω
25
27
I S_DATAIN2
220 Ω
220 Ω
220 Ω
220 Ω
2
28 I S_DATAOUT1
2
I2S
INPUT
SWITCH
CIRCUIT
I S OUT 1
220 pF
L
C
220 pF
5-BAND
PARAMETRIC
EQUALIZER
OR
TONE
CONTROL
220 Ω
2
I S_BCKIN2
DOLBY PRO LOGIC
OR
DOLBY 3 STEREO
OR
HALL/MATRIX
OR
INCREDIBLE
SOUND
2
VARIABLE
OUTPUT
MATRIX
220 Ω
2
I S input 2
29 I S_DATAOUT2
2
I S OUT 2
220 pF
R
data 1
220 pF
220 Ω
SW
2
220 Ω
I S_DATAOUT3
30
5
2
2
I S OUT 3
220 pF
26
I S_WSIN2
220 pF
V
DD1
DSP_RESET 17
470 pF
100
nF
BLM32A07
+5 V
AUTO BALANCE
FUNCTION
V
TSCAN
RTCB
12
32
13
3
DD2
+
100
nF
TEST
+
V
DD3
100 µF
(6.3 V)
100
nF
BLM32A07
+5 V
V
DD_XTAL
19
100
nF
100 µF
(6.3 V)
2
FLAG TEST
CONTROL
I C BUS
OSCILLATOR
TRANSCEIVER
V
SS_XTAL
18
6
V
V
SS1
11 SS2
V
31 SS3
7
8
9
10
15
16
14
A0
21
20
4
SDA
SCL
OSC
XTAL
SHTCB
DSP_IN1
DSP_OUT1
DSP_OUT2
220
Ω
220
Ω
10
kΩ
10
kΩ
DSP_IN2
4.7 µH
100 kΩ
+5 V
+5 V
1
nF
10
pF
10
pF
100
pF
100
pF
MGE757
Fig.14 Application diagram.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
PACKAGE OUTLINE
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
3
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
E
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.086
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches 0.10
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-25
97-05-22
SOT287-1
1998 Mar 13
23
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1998 Mar 13
24
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Mar 13
25
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
NOTES
1998 Mar 13
26
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
NOTES
1998 Mar 13
27
Philips Semiconductors – a worldwide company
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Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
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Tel. +1 800 234 7381
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Tel. +7 095 755 6918, Fax. +7 095 755 6919
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South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 488 3263
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Vietnam: see Singapore
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/1200/04/pp28
Date of release: 1998 Mar 13
Document order number: 9397 750 03268
相关型号：
SAA7715AH
IC 0-BIT, 24.576 MHz, OTHER DSP, PQFP44, 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44, Digital Signal Processor
NXP
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