SAA8117HL [NXP]
Digital camera USB interface IC; 数码相机的USB接口IC
| 型号： | SAA8117HL |
| 厂家： | 
NXP |
| 描述： | Digital camera USB interface IC |
| 文件： | 总60页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA8117HL
Digital camera USB interface IC
1999 Apr 02
Product specification
File under Integrated Circuits, IC22
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
CONTENTS
15
PACKAGE OUTLINE
SOLDERING
16
1
2
3
4
5
6
7
8
FEATURES
16.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
16.2
16.3
16.4
16.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
PINNING
17
18
19
DEFINITIONS
FUNCTIONAL DESCRIPTION
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Video synchronization
CIF formatter
Compression engine
Transfer buffer
SNERT interface
Sensor pulse generator
Pulse diagrams
USB video FIFO
PSIE-MMU, I2C-bus interface and USB RAM
space
8.10
8.11
8.12
ATX and external ATX interface
Audio
Power management
9
CONTROL REGISTER DESCRIPTION
9.1
9.2
SNERT (UART)
I2C-bus interface
Commands
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
End-points
Control top registers
Video FIFO registers
ADIF top registers
10
11
12
13
14
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING
APPLICATION INFORMATION
1999 Apr 02
2
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
1
FEATURES
2
APPLICATIONS
• Medium resolution CCD sensors (PAL non-interlaced
• Low-cost desktop video applications with USB interface.
mode) or VGA CCD sensors (progressive mode)
• D1 digital video input (8 bits YUV 4 : 2 : 2,
time multiplexed)
3
GENERAL DESCRIPTION
The SAA8117HL is a monolithic integrated circuit which
can be used in PC video cameras to convert D1 video
signals and analog audio signals to properly formatted
USB packets.
• Internal Pulse Pattern Generator (PPG) dedicated for
medium resolution Sharp or compatible sensors and
VGA sensors and for frame rate selection
• Video formatter (programmable CIF formatter and
compression engine) controlled via SNERT (UART)
interface
It is designed as a back-end for the SAA8110G or
SAA8112HL (general camera digital processing ICs) and
is optimized for use with the TDA8784/87 (camera
pre-processing IC) and the 83C51RC (microcontroller).
• Selectable output frame rate (1 fps in VGA, up to 15 fps
in CIF format)
• Video packetizer FIFO
• I2C-bus interface for communication between the USB
protocol hardware and the external microcontroller
• Integrated analog bus driver (ATX)
• Microphone/audio input to USB (FGA, ADC, PLL and
decimator filter)
• Integrated analog bus driver (ATX)
• Integrated main oscillator
• Miscellaneous functions e.g. power management,
PLL backup oscillator.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA8117HL
LQFP100
plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1
1999 Apr 02
3
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
5
QUICK REFERENCE DATA
Measured over full voltage and operating temperature range.
SYMBOL
PARAMETER
digital supply voltage
CONDITIONS
MIN.
3.0
TYP.
3.3
MAX.
3.6
UNIT
VDDD
VDDA
IDD(tot)
Vi(bus)
Vo(bus)
Vi(n)
V
V
analog supply voltage
3.0
3.3
91
3.6
total supply current
VDD = 3.3 V
−
−
mA
input voltage on I2C-bus interface pins
output voltage on I2C-bus interface pin SDA
input signal voltage on other pins
output signal voltage on other pins
clock frequency
5 V tolerant TTL compatible V
5 V tolerant TTL compatible V
3.0 V < VDD < 3.6 V low voltage TTL compatible
3.0 V < VDD < 3.6 V low voltage TTL compatible
V
Vo(n)
fclk
V
−
48
300
−
−
MHz
mW
°C
°C
°C
Ptot
total power dissipation
Tamb = 25 °C
Tamb = 70 °C
−
−
Tstg
storage temperature
−55
0
+150
70
Tamb
Tj
operating ambient temperature
junction temperature
25
−
−40
+125
1999 Apr 02
4
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a
SNAPSHOT
CLOCKON
UCINT
SUSREADYNOT
DCDCON
SMP
RESET
51
GENPOR
76
TRC
SCL SDA
UCPOR
CLOCK
94
95
93 64 77 96 100 97 99 98
58
56
55
57
63
65
SNCL
SNDA
SPEED
2
I C-BUS
POWER
MANAGEMENT
SUSPEND
INTERFACE
66
67
SNERT
INTERFACE
AND HATCH
SNRES
VM
VP
SAA8117HL
EXTERNAL
ATX
INTERFACE
68
71
72
73
53
52
RCV
USB
RESERVED2
RESERVED1
RAM SPACE
VMO
35, 36,
37, 38,
42, 43
44, 45
VPO
OEBAR
YUV0
to
YUV7
USB
VIDEO
FIFO
PSIE
MMU
CIF
FORMATTER
COMPRESSION
ENGINE
TRANSFER
BUFFER
74
ATXCTRL
60
61
ATXDP
ATXDM
49
50
47
ATX
HREF
VSYNC
LLC
AUDIO
ADC
VIDEO
SYNCHRONISATION
V
V
V
to V
DD3
32, 25, 15
DD1
to V
85, 84, 62, 7
70, 48, 41, 39
DDA1
DDD1
DDA4
DDD4
to V
2
MAIN
OSCILLATOR
AUDIO
PLL
AUDIO
AMP
I S-BUS
PATTERN PULSE GENERATOR
(PPG)
GND1 to GND4
54, 34, 26, 14
INTERFACE
88, 80, 78, 59, 4
92, 75, 69, 46, 40
AGND1 to AGND5
DGND1 to DGND5
13, 12 23, 22,
11, 10 21
19, 18
17, 16
24 20 28 29 27 33
8
9
31 30
5
6
86
87
79
89 90 91
3, 2, 1
81, 82, 83
FCE130
B1 to B4
C1 to C3
RG
SHP
CLK1 CLPDM
HD
XIN1
XIN2
XOUT2
MIC
WS
BCK
REF1 to REF3
M0 to M2
XOUT1
DA
A1 to A4
SHUTTER SHD
CLK2 CLPOB
VD
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
7
PINNING
SYMBOL
PIN TYPE
DESCRIPTION
M2
1
I
test mode control signal bit 2
test mode control signal bit 1
test mode control signal bit 0
M1
M0
2
I
3
I
AGND1
XIN1
XOUT1
VDDA1
CLPDM
CLPOB
B4
4
P
I
analog ground 1 for main oscillator (48 MHz, 3rd overtone)
5
oscillator input
oscillator output
6
O
P
O
O
O
O
O
O
P
P
O
O
O
O
O
O
O
O
O
P
P
O
O
O
O
O
P
O
P
I
7
analog supply voltage 1 for main oscillator (48 MHz, 3rd overtone)
dummy clamp pulse output to TDA8784/87
optical black clamp pulse output to TDA8784/87
vertical CCD load pulse output (VH1X)
vertical CCD load pulse output (VH3X)
vertical CCD load pulse output
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
B3
B2
B1
vertical CCD load pulse output
GND1
VDD1
A4
ground 1 for output buffers
supply voltage 1 for output buffers
vertical CCD transfer pulse output (V4X)
vertical CCD transfer pulse output (V3X)
vertical CCD transfer pulse output (V2X)
vertical CCD transfer pulse output (V1X)
shutter control output for CCD charge reset
horizontal CCD transfer pulse output
horizontal CCD transfer pulse output (FH1)
horizontal CCD transfer pulse output (FH2)
reset output for CCD output amplifier gate
supply voltage 2 for output buffers
A3
A2
A1
SHUTTER
C3
C2
C1
RG
VDD2
GND2
CLK1
SHP
SHD
VD
ground 2 for output buffers
pixel clock output to TDA8784/87and SAA8110G
preset sample-and-hold pulse output to TDA8784/87 (FCDS)
data sample-and-hold pulse output to TDA8784/87 (FS)
vertical definition pulse output to SAA8110G
horizontal definition pulse output to SAA8110G
supply voltage 3 for output buffers
HD
VDD3
CLK2
GND3
YUV0
YUV1
YUV2
YUV3
VDDD1
double pixel clock output to SAA8110G
ground 3 for output buffers
multiplexed input YUV-bit 0 (LSB)
I
multiplexed input YUV-bit 1 input
I
multiplexed input YUV-bit 2 input
I
multiplexed input YUV-bit 3 input
P
digital supply voltage 1 for input buffers and predrivers and one part of the digital
core
1999 Apr 02
6
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
DGND1
PIN TYPE
DESCRIPTION
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
P
P
I
digital ground 1 for input buffers and predrivers and for the digital core
digital supply voltage 2 for digital core
VDDD2
YUV4
multiplexed input YUV-bit 4
YUV5
I
multiplexed input YUV-bit 5
YUV6
I
multiplexed input YUV-bit 6
YUV7
I
multiplexed input YUV-bit 7
DGND2
LLC
P
I
digital ground 2 for input buffers and predrivers and for the digital core
line-locked clock input (delayed CLK2) for YUV-port from SAA8110G
digital supply voltage 3 for digital core
VDDD3
P
I
HREF
horizontal reference input for YUV-port from SAA8110G
vertical synchronization input for YUV-port from SAA8110G
Power-on reset input (for video processing and PPG)
test pin (should not be used)
VSYNC
RESET
RESERVED1
RESERVED2
GND4
I
I
−
−
P
I/O
test pin (should not be used)
ground 4 for output buffer
SNDA
data I/O for SNERT-interface (communication between SAA8117HL and
SAA8110G)
SNCL
56
57
I
input clock for SNERT-interface (communication between SAA8117HL and
SAA8110G)
SNRES
O
output reset for SNERT-interface (communication between SAA8117HL and
SAA8110G)
SMP
58
59
60
61
62
63
64
65
66
67
68
69
70
O
P
output switch mode pulse for DC-to-DC power supply
analog ground 2 for ATX (transceiver)
AGND2
ATXDP
ATXDM
VDDA2
SPEED
UCINT
SUSPEND
VM
I/O
I/O
P
positive driver of the differential data pair input/output (ATX)
negative driver of the differently data pair input/output (ATX)
analog supply voltage 2 for ATX
O
O
O
O
O
I
required output for ATX-backup solution
interrupt output from USB protocol hardware to microcontroller
control output from USB protocol hardware to microcontroller
required output for ATX-backup solution (txdn)
required output for ATX-backup solution (txdp)
required output for ATX-backup solution
VP
RCV
DGND3
VDDD4
P
digital ground 3 for input buffers and predrivers and for the digital core
P
digital supply voltage 4 for one part of input buffers and predrivers and for the
digital core
VMO
71
72
73
74
75
76
I
I
required input or ATX-backup solution (rxdn)
required input for ATX-backup solution (rxdp)
required output for ATX-backup solution
VPO
OEBAR
ATXCTRL
DGND4
GENPOR
O
I
required input for ATX-backup solution
P
I
digital ground 4 for input buffers and predrivers and for the digital core
Power-on reset input (for USB protocol hardware)
1999 Apr 02
7
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
UCPOR
PIN TYPE
DESCRIPTION
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
P
I
output control from USB protocol hardware to microcontroller
analog ground 3 for FGA
AGND3
MIC
microphone input
AGND4
REF1
P
I
analog ground 4 for FGA/ADC
reference input voltage 1 for FGA/ADC (double-bonding)
reference input voltage 2 for DACn (used in the ADC)
reference input voltage 3 for DACp (used in the ADC)
analog supply voltage 3 for FGA/ADC
REF2
I
REF3
I
VDDA3
P
P
I
VDDA4
analog supply voltage 4 for PLL
XIN2
oscillator input required for PLL backup solution
oscillator output required for PLL backup solution
analog ground 5 for PLL
I2S-bus word select (required for FGA/ADC backup solution)
I2S-bus data (required for FGA/ADC backup solution)
I2S-bus clock (required for FGA/ADC backup solution)
XOUT2
AGND5
WS
O
P
I
DA
I
BCK
I
DGND5
CLOCK
SCL
P
O
I
digital ground 5 for input buffers and predrivers and for the digital core
clock output from USB protocol hardware to microcontroller
slave I2C-bus clock input
SDA
I/O
O
I
slave I2C-bus data input/output
CLOCKON
SNAPSHOT
DCDCON
SUSREADYNOT
TRC
control output for main oscillator switched on
input for remote wake-up (snapshot)
O
I
control output from USB protocol hardware to power supply module
input from microcontroller for SUSPEND mode
threshold control input for enabling the clock (switching for power management)
I
1999 Apr 02
8
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
DGND4
75
M2
M1
1
2
3
4
5
6
7
8
9
74 ATXCTRL
73 OEBAR
72 VPO
M0
AGND1
XIN1
71
70
69
68
67
VMO
V
XOUT1
DDD4
V
DGND3
RCV
VP
DDA1
CLPDM
CLPOB
B4 10
66 VM
11
12
13
14
15
16
B3
B2
65 SUSPEND
64
63
62
61
60
59
UCINT
SAA8117HL
B1
SPEED
GND1
V
DDA2
V
ATXDM
ATXDP
AGND2
DD1
A4
A3 17
18
A2
A1 19
20
58 SMP
57 SNRES
56 SNCL
SHUTTER
C3 21
C2 22
C1 23
55
54
53
52
51
SNDA
GND4
RESERVED2
RESERVED1
24
25
RG
V
RESET
DD2
FCE131
Fig.2 Pin configuration.
9
1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
This prefilter must be chosen by selecting prefilter B and
setting SN_Prefilter_B_Comb. Prefilter B-comb can be
used independently from prefilter A.
8
FUNCTIONAL DESCRIPTION
Video synchronization
8.1
The video synchronization module (see Fig.1) is capable
of locking onto the video signal thereby implementing a
horizontal gate signal HREF (HREF = HIGH when data is
valid) and a VS signal indicating the start of a new video
frame. This module expects, in the PAL mode, 288 active
lines from a total of 292 lines and in the VGA mode,
480 active lines from a total of 486 lines. The module
generates control signals for the CIF formatter.
The incoming 4 : 2 : 2 data is vertically filtered to 4 : 2 : 0
by throwing away colour samples. In the even lines the
V-samples are discarded, in the odd lines the U-samples.
The vertical scaling in PAL mode is from CIF (352 × 288)
to QCIF (176 × 144) only. This is done via a vertical
prefilter A (3 taps). In VGA mode a VPD-4 vertical filter is
applied to scale from 640 × 480 to CIF and QCIF.
From the QCIF image a sub-QCIF cut (128 × 96) can be
made. Due to the granularity of the cropping origin, a
UV interchange can occur. This interchange can be
corrected with SN_EIRRAH.
8.2
CIF formatter
The video data must be progressive (or non-interlaced)
and in 4 : 2 : 2 (UYVY) format. The CIF formatter module
(see Figs 1 and 3) is programmable to perform down
scaling from 512 × 288 (PAL mode) or 640 × 480 (VGA
mode) to 352 × 288 or 176 × 144 without affecting the
aspect ratio.
In VGA mode the CIF formatter can be bypassed to create
a full resolution snapshot. The snapshot can be in 4 : 2 : 0
and in 4 : 2 : 2 format, selectable with SN_4 : 2 : 2.
8.3
Compression engine
The horizontal scaling is achieved with a Variable Phase
Delay filter (VPD-4). To avoid aliasing, this module also
contains a prefilter which has three modes:
The compression engine module (see Figs 1 and 3) works
on CIF format only. The CIF data is compressed to a fixed
number of bytes per frame. This number can be selected
leading a compression factor of either 3 or 4. As a result
the data stream of CIF 4 : 2 : 0 equals the data stream of
QCIF 4 : 2 : 2 (3 times compression) or QCIF 4 : 2 : 0
(4 times compression). The algorithm is Philips
• Prefilter A (3 taps)
• Prefilter B (7 taps)
• Prefilter B-comb (13 taps).
Prefilter B-comb is similar to prefilter B, but inserts extra
taps with amplification 0.
proprietary. Real-time decoding can be done in software
on any Pentium platform.
SN_4:2:2
SN_EIRRAH
SN_PAL_VGA
SN_Prefilter A_On/Off
SN_Output_Format_Select
to
transfer
buffer
YUV0 to YUV7
PREFILTER
A
DOWN
SCALER
PREFILTER
B
COMPRESSION
ENGINE
SN_Prefilter B_On/Off
SN_Prefilter B_Comb
SN_Compress
SN_Compression_Ratio
SN_Clk_Compress_On
FCE132
Fig.3 The CIF formatter and compression engine.
10
1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
It should be noted that in case of medium resolution Sharp
or compatible sensors an external inverter driver is
required to convert the 3 V pulses into a voltage suitable
for the used CCD sensor. For the medium resolution Sharp
CCD sensor driver, the name of the pins to which the PPG
pulses must be connected are indicated between brackets
in the SAA8117HL pinning list (pins C3, B1 and B2 are not
used).
8.4
Transfer buffer
The transfer buffer module (see Fig.1) ensures a smooth
transfer of the data to the FIFO of the USB. Moreover the
transfer buffer can insert in band synchronization words in
the video data stream.
This function can be switched on and off with
SN_In band_Control in register CONTROL17_0.
The synchronization words can only be used with
non-compressed data streams and are formatted like
0x00 0xFF 0x<framecounter>7<linecounter>9.
The subscript denotes the number of bits and the frame
counter is circular incrementing.
For both type of sensors the PPG generates 8 different
frame rates (see Table 6). The active video size is
512 × 288 for PAL and 640 × 480 for VGA. The total H × V
size is 685 × 292 for PAL and 823 × 486 for VGA.
It should be noted that additional HD pulses are added
during the vertical blanking interval to reach a total of
312 lines in PAL mode and 525 lines in VGA mode as
required by the SAA8110G.
The non-compressed data is formatted like:
4 : 2 : 0: <optional sync word><Y0><Y1><Y2><Y3>
<C0><C2><Y4><Y5><Y6><Y7><C4><C6>....,
4 : 2 : 2: <optional sync word><Y0><Y1><Y2><Y3>
<U0><V0><U2><V2><Y4>....,
The following registers are associated with the PPG:
• CONTROL17_0
where C denotes U-data in the even lines (0, 2, 4, etc.)
and V-data in the odd lines (1, 3, 5, etc.).
• CONTROL17_2
• PPG_SHUTTERSPEED_0
• PPG_SHUTTERSPEED_1
• PPG_CLPOB_START_LSB
• PPG_CLPOB_STOP_LSB
• PPG_CLPDM_START_LSB
• PPG_CLPDM_STOP_LSB
• CLPMSB.
8.5
SNERT interface
In a USB camera the SAA8110G will operate on a clock
frequency which depends on the actual frame rate. For the
slowest frame rates, this frequency can be so low that the
SNERT communication is no longer functional over the
specified entire frequency range of the microcontroller.
The microcontroller must adapt its SNERT bus frequency
to a frequency appropriate for the current mode in which
the SAA8110G is operating.
8.7
Pulse diagrams
The SAA8117HL itself is also partly controlled via SNERT.
The CIF formatter, compression engine and the PPG
function are controlled via SNERT. This SNERT interface
works independently from the frame rate and can always
be operated in the full frequency range.
For medium resolution CCD sensors (PAL):
• High-speed pulses, see Figs 4 and 5
• Horizontal pulses, see Fig.6
• Vertical pulses, see Figs 7 to 11.
For VGA-sensors:
8.6
Sensor pulse generator
• High-speed pulses, see Figs 12 to 14
• Horizontal pulses, see Fig.15
• Vertical pulses, see Figs 16 to 21.
The SAA8117HL incorporates a Pulse Pattern Generator
(PPG) function. The PPG can be used for PAL medium
resolution Sharp sensors (LZ2423) or compatible CCD
sensors. The SAA8117HL can also handle VGA type CCD
sensors, so a set of pulses is provided to simplify the use
of such sensors. Depending on the type of sensor, it will be
necessary to reformat these pulses externally according to
the sensor specification.
1999 Apr 02
11
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CCD OUTPUT
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
CLOCK ENABLE
C1 (FH1)
C2 (FH2)
RG (FR)
SHD (FS)
SHP(FCDS)
CLK1
CLK2
FCE133
mode 0: 1/(4.8 MHz)
Fig.4 High-speed pulses for PAL medium resolution (1).
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CCD OUTPUT
0
1
2
3
0
1
2
3
0
3
0
1
2
3
0
1
2
3
CLOCK ENABLE
C1 (FH1)
C2 (FH2)
RG (FR)
SHD (FS)
SHP (FCDS)
CLK1
CLK2
FCE134
mode 1: 1/(4 MHz)
mode 2: 1/(3 MHz)
mode 3: 1/(2.4 MHz)
mode 4: 1/(2 MHz)
mode 5: 1/(1.5 MHz)
mode 6: 1/(1 MHz)
mode 7: 1/(750 kHz)
Fig.5 High-speed pulses for PAL medium resolution (2).
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1
4
0
HD
15
91
CLOCK ENABLE
CLPOB
(1)
(1)
(1)
(1)
CLPDM
64
72
SHUTTER (OFDX)
A1 (V1X)
FCE135
29
49
39
59
A2 (V2X)
24
54
A3 (V3X)
34
64
A4 (V4X)
(1) CLPOB and CLPDM are programmable.
Fig.6 Horizontal pulses for PAL medium resolution.
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ahdnbok,uflapegwidt
A285
289
A286
290
A287
291
A288
292
Hd
1
Hd
2
AL1
3
AL2
4
A1
5
A2
6
INE#
HD
VD
CLPOB (DCP)
CLPDM (BCP)
B4 (VH1X)
B3 (VH3X)
SHUTTER (OFDX)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE136
Fig.7 Vertical pulses for PAL medium resolution (1).
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ahdnbok,uflapegwidt
INE#
HD
292
1
2
SHUTTER (OFDX)
B4 (VH1X)
B3 (VH3X)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE137
Fig.8 Vertical pulses for PAL medium resolution (2).
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ahdnbok,uflapegwidt
INE#
HD
1
2
3
SHUTTER (OFDX)
B4 (VH1X)
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 8
B3 (VH3X)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE138
Fig.9 Vertical pulses for PAL medium resolution (3).
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ahdnbok,uflapegwidt
INE#
HD
2
3
4
SHUTTER (OFDX)
B4 (VH1X)
B3 (VH3X)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE139
Fig.10 Vertical pulses for PAL medium resolution (4).
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INE#
HD
3
4
5
SHUTTER (OFDX)
B4 (VH1X)
B3 (VH3X)
A1 (V1X)
A2 (V2X)
A3 (V3X)
A4 (V4X)
FCE140
Fig.11 Vertical pulses for PAL medium resolution (5).
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ahdnbok,uflapegwidt
CCD OUTPUT
0
1
2
3
4
0
1
2
3
4
0
4
0
1
2
3
4
0
1
2
3
4
CLOCK ENABLE
C1
C2
C3
RG
SHD
SHP
CLK1
CLK2
FCE141
mode 0: 1/(9.6 MHz)
Fig.12 High-speed pulses for VGA sensors (1).
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a
CCD OUTPUT
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
CLOCK ENABLE
C1
C2
C3
RG
SHD
SHP
CLK1
CLK2
mode 1: 1/(8 MHz)
mode 3: 1/(4 MHz)
FCE142
Fig.13 High-speed pulses for VGA sensors (2).
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a
CCD OUTPUT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
CLOCK ENABLE
C1
C2
C3
RG
SHD
SHP
CLK1
CLK2
FCE143
mode 2: 1/(6 MHz)
mode 4: 1/(3 MHz)
mode 5: 1/(2 MHz)
mode 6: 1/(1.5 MHz)
mode 7: 1/(1 MHz)
Fig.14 High-speed pulses for VGA sensors (3).
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a
751 755
HD
15
63
CLOCK ENABLE
(1)
(1)
CLPOB
CLPDM
SHUTTER
A1
(1)
(1)
2
2
2
22
22
22
FCE144
A2
A3
A4
25 28
B1
27 30
B2
24
29
B3
26
31
B4
(1) CLPOB and CLPDM are programmable.
Fig.15 Horizontal pulses for VGA sensors.
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a
A476
482
A480
486
Hd
1
Hd
2
Hd
3
Hd
4
AL1
5
AL2
6
A1
7
INE#
HD
483
485
VD
CLPOB
CLPDM
SHUTTER
A1
A2
A3
A4
B1
B2
B3
B4
FCE145
Fig.16 Vertical pulses for VGA sensors (1).
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a
INE#
HD
486
1
2
SHUTTER
RESET_DATA [9 to 0]
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
RESET_DATA [9 to 0] + 20
A1
A2
A3
A4
B1
B2
B3
B4
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
FCE146
Fig.17 Vertical pulses for VGA sensors (2).
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a
INE#
HD
1
2
3
SHUTTER
RESET_DATA [9 to 0]
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
RESET_DATA [9 to 0] + 20
A1
A2
A3
A4
B1
B2
B3
B4
RESET_DATA [9 to 0]
RESET_DATA [9 to 0] + 20
FCE147
Fig.18 Vertical pulses for VGA sensors (3).
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a
INE#
HD
2
3
4
SHUTTER
A1
A2
A3
A4
B1
B2
B3
B4
FCE148
Fig.19 Vertical pulses for VGA sensors (4).
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a
INE#
3
4
5
HD
SHUTTER
A1
A2
A3
A4
B1
B2
B3
B4
FCE149
Fig.20 Vertical pulses for VGA sensors (5).
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a
1/(6 MHz) = 0.167 µs
INE#
0
1
2
3
489
490
491
492
493
494
518
519
520
521
522
A1
A2
A3
A4
B1
B2
B3
B4
FCE150
Fig.21 Vertical pulses for VGA sensors (6).
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Moreover the FIFO is enabled and disabled with
8.8
USB video FIFO
I2C_Active.
The USB video FIFO is programmed via the I2C-bus
(see Fig.22). The FIFO is designed to achieve three
different packets containing video on the isochronous USB
channel. Video data is contained in a chain of equally sized
USB packets, except for the last packet of a video frame
which is always smaller. The video frames can be
separated from each other by one or more 0-length
packets. For low frame rates (below 10 frames/s) there are
always 0-length packets in the stream. The host can
synchronize on the smaller packets for the high frame
rates and on the 0-length packets for the low frame rates.
The write process to the FIFO is controlled by the transfer
buffer and is not programmable.
The read process is executed in the PSIE-MMU and is
driven by the USB frame interval (1 ms). Every frame
interval the PSIE-MMU tries to read I2C_Packet_Size
bytes from the FIFO. This read process will not be started
when a new video frame is stored in the FIFO and there
are less than I2C_FIFO_Offset bytes written. The read
process stops if the next bytes are of another video frame,
or if the read-pointer overtakes the write-pointer.
For every mode the FIFO must be adjusted. There are
three parameters to program the video FIFO:
• I2C_Packet_Size: this value indicates the length of all
packets with video data except for the last packet of a
video frame
I2C_Read_Spacing determines the read rate. Its value can
easily be determined with the formula:
I2C_Read_Spacing <
12000
---------------------------------------------
I2C_Packet_Size
• I2C_FIFO_Offset: this value indicates the number of
data in the FIFO before a new packet is transmitted over
the USB
• I2C_Read_Spacing: this value indicates the number of
12 MHz clock cycles between read actions from the
FIFO.
data to PSIE-MMU
read
data from transfer buffer
FIFO
2
I C_FIFO_Offset
write
read
2
I C_Packet_Size
enable
2
I C_Read_Spacing
WRITE
SYNC
2
I C_Active
FCE151
Ptr_to_start_Vframe
Fig.22 USB video FIFO.
30
1999 Apr 02
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
PSIE-MMU, I2C-bus interface and USB RAM
space
8.10 ATX and external ATX interface
8.9
The SAA8117HL contains an analog bus driver, called the
ATX. It incorporates a differential and two single-ended
receivers and a differential transmitter. The interface to the
bus consists of a differential data pair (ATXDM and
ATXDP). The SAA8117HL contains also an interface to an
external ATX as backup solution.
The Programmable Serial Interface Engine (PSIE) and
Memory Management Unit (MMU) is the heart of the USB
protocol hardware (see Fig.23). It formats the actual
packets that are transferred to the USB and passes the
incoming packets to the right end-point buffers. These
buffers are allocated as part of the USB RAM space.
The microcontroller communicates via the I2C-bus with the
PSIE-MMU. The I2C-bus protocol distinguishes three
register spaces. These spaces are addressed via different
commands. The command is sent to the command
address. Depending on the command it is sent to the
PSIE-MMU and/or to the command interpreter which
configures the (de-)mux to open the path to the right
register space. Subsequent write/read to/from the data
address store or retrieve data from the register space is
selected by the command.
PSIE-MMU
REGISTER
SPACE
PI_Address + 0X
(DE)MUX
SET MODE
REGISTER
SPACE
to/from
microcontroller
2
I C-BUS
INTERFACE
NON USB
AND
VIDEO FIFO
REGISTERS
COMMAND
INTERPRETER
PI_Address + 10
FCE152
to
PSIE-MMU
Fig.23 I2C-bus interface and register map.
1999 Apr 02
31
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
8.11 Audio
8.12 Power management
The PLL converts the 48 MHz to 256fs (fs = audio sample
frequency). There are three modes for the PLL to achieve
the sample frequencies of 48, 44.1 or 32 kHz
(see Table 1).
The USB requires the device to switch power states.
The SAA8117HL contains a power management module
since the device may not consume more than 500 µA
during the power state called SUSPEND. This requires
that even the crystal oscillator must be switched off.
The SAA8117HL is also not functional except for some
logic that enables the IC to wake-up the camera. After
wake-up of the SAA8117HL first the clock to the
In the Fixed Gain Amplifier (FGA) the microphone input is
amplified by 20 dB.
The bit stream ADC samples the audio signal. It runs at an
oversample rate of 256 times the base sample rate. In the
application, the bit stream can be converted to parallel
16-bit samples. This conversion is programmable with
respect to the effective sample frequency (dropping
sample results in a lower effective sample frequency) and
sample resolution. As a result the effective sample rate
can be determined.
microcontroller is generated and thereafter an interrupt is
generated to wake-up the controller. Therefore the clock of
the microcontroller is generated by the SAA8117HL.
The power management module also sets a flag in register
I2C_SET_MODE_AND_READ. After a reset the
microcontroller should check this register via the I2C-bus
and find the cause of the wake-up. Different causes may
require different start-up routines.
Table 1 ADC clock frequencies and sample frequencies
The internal video processing core uses another
VDDD domain which can be switched during SUSPEND.
SAMPLE
FREQUENCY
(kHz)
CLOCK
(MHz)
DIVIDING
NUMBER
ADCCLOCK
(MHz)
The PPG is switched off by setting SN_Resume and
resetting SN_PAL_VGA. In non CIF modes the power
consumption is reduced by resetting SN_Compress and
SN_CLK_Compress_On.
8.1920
1
2
4
8
1
2
4
8
1
2
4
8
32
16
4.096
2.048
1.042
note 1
5.6448
2.8224
1.4112
0.7056
6.144
3.072
1.536
0.768
8
The SAA8117HL has the feature to independently
wake-up from SUSPEND, but requires a signal from the
microcontroller before going into SUSPEND (via the signal
on pin SUSREADYNOT).
note 1
44.1
22.05
11.025
5.5125
48
11.2996
12.2880
Since the main oscillator of the SAA8117HL is switched off
during SUSPEND precautions are needed to avoid
undefined states when the clock is switched on. This is
ensured via the pins CLOCKON and TRC.
Pin CLOCKON goes HIGH as soon as the main oscillator
is switched on. The oscillator will need some time to make
a stable 48 MHz signal. However, the clock is only passed
through to other parts of the SAA8117HL when the level on
pin TRC reaches a certain threshold. The time needed to
reach the threshold can be trimmed with an RC-circuit.
24
12
6
Note
1. Not supported.
1999 Apr 02
32
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
9
CONTROL REGISTER DESCRIPTION
This Chapter gives an overview of all registers.
9.1
SNERT (UART)
The following registers are accessible via SNERT (see Table 2).
Table 2 SNERT write registers of the SAA8117HL
ADDRESS
NAME
FUNCTION
FORMAT
C0
C1
C2
C3
C4
−
−
reserved
−
reserved
−
CONTROL17_0
various control bits
various control bits
see Table 3
see Table 5
CONTROL17_1
VP_SQCIF_OFFSET
vertical (MSN) and horizontal (LSN) offset for sub-QCIF
mode
nibble
C5
C6
C7
C8
C9
CA
CB
CC
CONTROL17_2
various control bits
see Table 6
see Table 8
see Table 9
byte
PPG_SHUTTERSPEED_0
PPG_SHUTTERSPEED_1
bits of shutter speed 0
bits of shutter speed 1
PPG_CLPOB_START_LSB LSB start position control for CLPOB pulse
PPG_CLPOB_STOP_LSB LSB stop position control for CLPOB pulse
PPG_CLPDM_START_LSB LSB start position control for CLPDM pulse
byte
byte
PPG_CLPDM_STOP_LSB
CLPMSB
LSB stop position control for CLPDM pulse
byte
MSBs of CLPOB_Start, CLPOB_Stop, CLPDM_Start and see Table 10
CLPDM_Stop
1999 Apr 02
33
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 3 Detailed description of SNERT register CONTROL17_0 (address 0xC2)
7
6
5
4
3
2
1
0
PARAMETER
EIRRAH
X
exchanges the chrominance irregularities when needed; toggle the bit to ensure
timing of chrominance signal; the value must be determined experimentally (can
be different for different modes)
Snapshot
1
transported in 4 : 2 : 2 format
transported in 4 : 2 : 0 format
Inband_Control
0
1
in band synchronization words are inserted in the video data stream
only active video data is transmitted over USB
Compression_Ratio
0
1
ratio is 4 times
0
ratio is 3 times
Compress
1
compression is active; only to be used in case (for this register) bit 2 = 1 and
bit 1 = 0 since compression functions are for CIF only; CIF format must be
compressed unless the frame rate is 3.75 Hz
0
compression module is switched off and power consumption is minimized for this
module
Output_Format_Select
see Table 4
X
X
PAL_VGA
1
PAL sensor
0
VGA sensor
Table 4 Detailed description of bit 2 and bit 1 of SNERT register CONTROL17_0
OUTPUT_FORMAT_SELECT
2
1
FRAME RATE WITH RESPECT TO OUTPUT FORMAT
PARAMETER
0
0
sub-QCIF
QCIF
24
24
−
20
20
−
15
15
15
−
12
12
12
−
10
10
10
−
7.5
7.5
7.5
−
5
5
5
−
3.75
3.75
3.75
−
−
0
1
1
1
0
1
−
CIF
−
VGA; note 1
−
−
0.9375
Note
1. Only valid when a VGA sensor is applied. The VGA output is not compressed.
1999 Apr 02
34
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 5 Detailed description of SNERT register CONTROL17_1 (address 0xC3)
7
6
5
4
3
2
1
0
PARAMETER
X
X
X
X
reserved
CLK_Compress_On
compression clock active
1
0
compression module is brought to low power state
Prefilter B_Comb
1
horizontal scaling factor exceeds 3 (only functioning if bit 1 is also set to logic 1);
this bit switches prefilter B to 13 taps
0
prefilter B is as described for bit 1
Prefilter B_On/Off
1
horizontal scaling factor exceeds 2; the prefilter with 7 taps is switched on
prefilter B is bypassed
0
Prefilter A_On/Off
1
prefilter A with 3 taps is on; must be set to logic 1 when bit 2 is set to logic 1 to
obtain the overall wanted frequency response
0
prefilter A is bypassed
Table 6 Detailed description of SNERT register CONTROL17_2 (address 0xC5)
PARAMETER
7
6
5
4
3
2
1
0
PIX_nr0 to PIX_nr2
X
X
X
3 LSBs of 10 bits pixel number for autoexposure control (7 LSBs in register 0xC6)
Shutter_Update_Buffer
1
update of the shutter speed is buffered
0
no buffering (immediately destroying of the current video frame)
Resume
1
video processing and PPG are switched of; if a VGA sensor is selected the vertical
transport pulses are not switched off but this must be done by selecting a PAL
sensor (register 0xC2 bit 0)
0
PGG pulses generated
PPG_Mode_Frame_Rate
see Table 7
X
X
X
1999 Apr 02
35
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 7 Detailed description of bit 2 to bit 0 of SNERT register CONTROL17_2
BIT
1
PARAMETER OF PPG_MODE_FRAME_RATE
2
0
VGA
PAL
0
0
0
1
1
0
0
1
1
0
24
20
24
20
0
0
0
1
1
1
1
1
0
1
0
1
0
1
15
15
10
12
7.5
5
10
7.5
5
3.75
0.9375
3.75
Table 8 Detailed description of SNERT register PPG_SHUTTERSPEED_0 (address 0xC6)
7
6
5
4
3
2
1
0
PARAMETER
X
1 LSB of 9-bit line number (8 MSBs in register 0xC7)
7 MSBs of 10-bit pixel number (3 LSBs in register 0xC5)
X
X
X
X
X
X
X
Table 9 Detailed description of SNERT register PPG_SHUTTERSPEED_1 (address 0xC7)
7
6
5
4
3
2
1
0
PARAMETER
X
X
X
X
X
X
X
X
8 MSBs of 9-bit line number (LSB in register 0xC6)
Table 10 Detailed description of SNERT register CLPMSB (address0xCC)
7
6
5
4
3
2
1
0
PARAMETER
X
X
2 MSBs of CLPOB_Start (LSBs in register 0xC8)
2 MSBs of CLPOB_Stop (LSBs in register 0xC9)
2 MSBs of CLPDM_Start (LSBs in register 0xCA)
2 MSBs of CLPDM_Stop (LSBs in register 0xCB)
X
X
X
X
X
X
1999 Apr 02
36
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
9.2
I2C-bus interface
The I2C-bus interface uses two addresses:
• Command address for writing commands to the Memory Manager (MM)
• Data address for writing/reading data to/from the Memory Manager (MM).
The 6 MSBs of the two addresses are equal and are defined by the PI_address = 010111 (see Table 11). The LSBs of
the addresses differentiate between the command address and the data address. When bit 1 is logic 1 the address is
the command address (0x5E) and when bit 1 is logic 0 the address is one of the data addresses (0x5C or 0x5D).
Table 11 I2C-bus addresses
BIT
ADDRESS
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0x5C: for writing data to the memory manager
0x5D: for reading data from the memory manager
0x5E: for writing commands
0x5F: not in use
9.2.1
COMMANDS
The commands listed in Table 12 must be sent to the I2C-bus address 0x5E.
Table 12 I2C-bus USB command codes
BIT
FUNCTION
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
end-point number
end-point number
end-point number
select end-point
read/write status
initialize/read status information
read/write register bank
not used
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
address
0
1
0
0
0
1
0
0
0
0
0
X
0
0
0
0
0
1
1
1
1
0
X
0
0
0
1
1
0
0
1
1
1
X
0
0
1
0
0
0
1
0
1
1
set non-USB register
read/write data
acknowledge setup
set buffer empty
set buffer full
read interrupt register
read current frame number
send resume
set status change bits
set mode
1999 Apr 02
37
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 13 Set mode and write register overview
BYTE
SET MODE AND WRITE
N1 timer; programmable timer for power management; counts 12 MHz cycles; must be bigger than number
1
2
3
of cycles needed for the microcontroller to go in power-down state after pin SUSREADYNOT is made LOW
N2 timer; programmable timer for power management; counts 12 MHz cycles; determines the time between
when the microcontroller clock is switched off and the main clock is switched off
PSIE-MMU control byte (see Table 14)
Table 14 Detailed description of PSIE-MMU control byte (byte 3)
7
6
5
4
3
2
1
0
PARAMETER
X
X
X
reserved
interrupt after isochronous audio transfer
1
0
for each isochronous audio transfer an interrupt to the microcontroller will
be generated; default set to logic 1 upon general Power-on reset and/or
bus reset by the SAA8117HL
no interrupts are given to the microcontroller
interrupt after isochronous video transfer
1
0
for each isochronous video transfer an interrupt to the microcontroller will
be generated; default set to logic 1 upon general Power-on reset and/or
bus reset by the SAA8117HL
no interrupts are given to the microcontroller
audio end-point
1
0
audio end-point enabled; default set to logic 1 upon general Power-on reset
and/or bus reset by the SAA8117HL
audio end-point disabled; the PSIE-MMU will not react on in-tokens on the
audio end-point
video end-point
1
0
video end-point enabled; default set to logic 1 upon general Power-on reset
and/or bus reset by the SAA8117HL
video end-point disabled; the PSIE-MMU will not react on in-tokens on the
video end-point
error debug mode
1
0
interrupts are generated only in the event that the transfer is not
successfully completed; the microcontroller can read data from the interrupt
and status registers to see the cause of this error
all successful USB transactions are reported to the microcontroller via an
interrupt; default set to logic 0 upon general Power-on reset by the
SAA8117HL
1999 Apr 02
38
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 15 Detailed description of PSI-MMU set mode and status byte
7
6
5
4
3
2
1
0
PARAMETER
X
X
X
X
reserved
remote wake-up status flag
1
0
remote wake-up when device is in SUSPEND mode
no remote wake-up
resume status flag
1
0
bus resume by the host when device is in SUSPEND mode
no bus resume
bus reset status flag
1
0
bus reset
no bus reset
power-up status flag
1
0
general power up reset
no power up reset
9.2.2
END-POINTS
The SAA8117HL has 6 logical end-points which are listed in Table 16.
Table 16 Mapping of logic to physical end-point numbers for used end-points
PHYSICAL END-POINT
LOGIC
END-POINT
END-POINT NAME
Control end-point
BUFFER SIZE
OUT
IN
0
1
2
3
4
5
8
8
0
2
−
−
−
−
1
3
4
5
6
7
Control end-point
Interrupt end-point
Interrupt end-point
Iso video end-point
Iso video end-point
8
8
96.0
35.1
1999 Apr 02
39
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
9.2.3
CONTROL TOP REGISTERS
The following registers can be written on I2C-bus address 1 after the command 0xE8 on I2C-bus address 0.
Table 17 I2C-bus control top registers (base address 0x08)
ADDRESS
0x08
NAME
CLKSHOP CONTROL
FUNCTION
clock control
0x09
0x0A
0x0B
RSTGEN AND_PLL CONTROL
I/O MUX CONTROL
reset control
mux block control
POWER CONTROL ANALOG MODULES
power-on analog modules control
Table 18 Detailed description of I2C-bus control top register CLKSHOP CONTROL (address 0x08)
7
6
5
4
3
2
1
0
PARAMETER
select ADC clock source
1
0
sel_ad: clock generated from ADC
sel_pll: clock generated from PLL
set clock dividers for ADC
set_divide00: divided by 1
set_divide01: divided by 2
set_divide10: divided by 4
set_divide11: divided by 8
reserved
0
0
1
1
0
1
0
1
X
disable 48 MHz clock
dis_clk_48: disable 48 MHz clock
enable clock
1
0
disable receiver clock
dis_clk_rec: disable receiver clock
enable clock
1
0
disable ADC clock
1
0
dis_clk_ad: disable ADC clock
enable clock
X
reserved
1999 Apr 02
40
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 19 Detailed description of I2C-bus control top register RSTGEN AND PLL CONTROL (address 0x09)
7
6
5
4
3
2
1
0
PARAMETER
set PLL frequency
0
0
1
1
0
1
0
1
fcode00: 256 × 44.1 kHz
fcode01: 256 × 32 kHz
fcode10: 256 × 48 kHz
fcode11: 256 × 44.1 kHz
reserved
X
X
reset PSIE-MMU top module
1
0
upc_rst_mmu: resetting the USB protocol block (called PSIE-MMU) during
tests or in the event of errors
no reset
X
reserved
reset ADIF top module
1
0
upc_rst_adif: resetting the digital audio part during tests or in the event of
errors
no reset
reset AGC module
1
0
upc_rst_AGC: resetting the AGC control during tests or in the event of
errors
no reset
Table 20 Detailed description of I2C-bus control top register I/O MUX CONTROL (address 0x0A)
7
6
5
4
3
2
1
0
PARAMETER
X
X
X
X
X
X
X
X
reserved
1999 Apr 02
41
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
Table 21 Detailed description of I2C-bus control top register POWER CONTROL OF ANALOG MODULES
(address 0x0B)
7
6
5
4
3
2
1
0
PARAMETER
X
X
reserved
power control PLL module
upc_pll_off: PLL power off
power on
1
0
X
reserved
power control ADC module left channel
upc_adl_off: power off
power on
1
0
power control ADC module right channel
upc_adr_off: power off
power on
1
0
power control AGC module left channel
upc_AGCl_off: power off
power on
1
0
power control AGC module right channel
upc_AGCr_off: power off
power on
1
0
1999 Apr 02
42
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
9.2.4
Table 22 Overview of I2C-bus video FIFO registers (base address 0x04)
ADDRESS NAME
0x04
VIDEO FIFO REGISTERS
FUNCTION
8 LSBs of the offset value
FIFO OFFSET
0x05
0x06
0x07
FIFO ACTIVE AND FIFI OFFSET
PACKET SIZE
FIFO active and 3 MSBs of the offset value
8 LSBs of packet size value
READ SPACING AND PACKET SIZE
read spacing and 2 MSBs of packet size value
Table 23 Detailed description of I2C-bus video FIFO register FIFO OFFSET (address0x04)
7
6
5
4
3
2
1
0
PARAMETER
FIFO offset
X
X
X
X
X
X
X
X
mode_fifo_offset: sets the minimum contents of the FIFO that has to be
reached, before a new video frame will be put on the USB bus. This value
can be set between 0 and 2047. Total of 11 bits with 8 LSBs in this register
and 3 MSBs in register 0x05.
Table 24 Detailed description of I2C-bus video FIFO register FIFO ACTIVE AND FIFI OFFSET (address 0x05)
7
6
5
4
3
2
1
0
PARAMETER
FIFO active
1
0
mode_active: FIFO is active and the contents of the other mode registers
should not be updated by the microcontroller (maledictive)
FIFO not active
X
X
X
X
reserved
FIFO offset
X
X
X
3 MSBs of the offset value; see also register 0x04
Table 25 Detailed description of I2C-bus video FIFO register PACKET SIZE (address 0x06)
7
6
5
4
3
2
1
0
PARAMETER
packet size
X
X
X
X
X
X
X
X
mode_packet_size: sets the packet size of the USB video channel. Packets
can vary in size between 0 and 1023. Total of 10 bits with 8 LSBs in this
register and 2 MSBs in register 0x07.
Table 26 Detailed description of I2C-bus video FIFO register READ SPACING AND PACKET SIZE (address 0x07)
7
6
5
4
3
2
1
0
PARAMETER
read spacing
X
X
X
X
X
X
mode_read_spacing: sets the periodicity of the read pulses; the periodicity
can be set from 1 to 63 (from ‘000001’ to ‘111111’)
packet size
X
X
mode_packet_size: 2 MSBs of the value (8 LSBs in register 0x06)
1999 Apr 02
43
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
9.2.5
ADIF TOP REGISTERS
Table 27 Overview of I2C-bus ADIF top registers (base address 0x0C)
ADDRESS
NAME
FUNCTION
0x0C
0x0D
0x0E
0x0F
AGC CONTROL GENERAL
AGC CONTROL GAIN LEFT
AGC CONTROL GAIN RIGHT
ADIF CONTROL
AGC control general
AGC control gain left
AGC control gain right
I2S-bus input and ADIF2MMU
Table 28 Detailed description of I2C-bus ADIF top register ADIF CONTROL (address 0x0F)
7
6
5
4
3
2
1
0
PARAMETER
X
reserved
number of bytes per sample
0 (reserved)
0
0
1
1
0
1
0
1
1 (8 bits audio samples)
2 (16 bits audio samples)
3 (24 bits audio samples)
selection mono/stereo operation
mono
0
1
stereo
selection input for ADC path (ADIF mux)
digital input (from I2S-bus)
analog input (from Vin_left and Vin_right)
0
1
selection high-pass filter (DC filter) for ADC down-sample filter
high-pass filter off
0
1
high-pass filter on
selection UDAI serial input format
I2S-bus
0
0
1
1
0
1
0
1
LSB justified, 16 bits
LSB justified, 18 bits
LSB justified, 20 bits
1999 Apr 02
44
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
UNIT
analog supply voltage
digital supply voltage
voltage on
+4.0
+4.0
V
V
VDDD
−0.5
Vn
pins AGND and DGND
pins SCL and SDA
all other pins
−0.5
−0.5
−0.5
− 55
0
+4.0
+5.5
V
note 1
V
VDD + 0.5
V
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
+150
70
°C
°C
°C
−40
+125
Note
1. 5 V tolerant buffers.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
51
K/W
1999 Apr 02
45
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
12 CHARACTERISTICS
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C.
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
VDDA
VDGND
VAGND
IDDD
digital supply voltage
3.0
3.0
0
3.3
3.6
3.6
0
V
V
V
V
analog supply voltage
voltage on pins DGND
voltage on pins AGND
digital supply current
3.3
0
0
0
0
Tamb = 25 °C
Tamb = 25 °C
−
70
20
25
−
mA
mA
°C
IDDA
analog supply current
operating ambient temperature
−
−
Tamb
0
70
Inputs
DATA AND CONTROL INPUTS: PINS M0 TO M2, YUV0 TO YUV7, LLC, HREF, VSYNC, RESET, GENPOR, ATXCTRL,
RCV, VM0 AND VP0
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.8
V
V
2
−
Outputs
DATA AND CONTROL OUTPUTS: PINS CLK2, SMP, SPEED, SUSPEND, VM, VP AND OEBAR
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
−
−
0.1VDDD
V
V
0.85VDDD
−
CONTROL OUTPUTS: PINS RG, SHUTTER, C1 TO C3, CLK1, SHP AND SHD
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
−
−
0.8
V
V
2.0
−
CONTROL OUTPUTS: PINS A1 TO A4 AND B1 TO B4
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
−
−
0.8
V
V
2.6
−
CONTROL OUTPUTS: PINS CLPDM AND CLPOB
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
−
−
−
0.6
V
V
2.2
−
Interfaces
I2S-BUS: PINS DA, BCK AND WS
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.3VDDD
V
V
0.7VDDD
−
I2C-BUS AND SNERT BUS: PINS SDA, SCL, SNDA, SNCL AND SNRES
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
−
−
0.7
V
V
V
V
VIH
VOL
VOH
0.2VDDD + 0.9 −
VDDD + 0.5
note 1
note 1
−
−
−
0.4
V
DDD − 0.7
−
1999 Apr 02
46
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
MICROCONTROLLER INTERFACE: PINS SUSREADYNOT, UCPOR, UCINT, CLOCK, CLOCKON, TRC, SNAPSHOT
AND DCDCON
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
note 2
note 2
note 3
note 3
−
−
0.7
V
V
V
V
VIH
VOL
VOH
0.2VDDD + 0.9 −
VDDD + 0.5
−
−
−
0.4
V
DDD − 0.7
−
Audio Phase-Locked Loop (PLL)
fi
clock input frequency
clock output frequency
bandwidth
−
−
−
−
48
−
−
−
−
MHz
MHz
kHz
fo
B
ζ
note 4
11.2996
2.3
damping
0.98
∑∆ convertor
INPUTS
fi
input signal frequency
1
−
20
kHz
mV
Vi(rms)
input voltage (RMS value)
−
800
−
TRANSFER FUNCTION
N
order of the ∑∆
−
−
−
−
−
−
3
−
Nbit
Neqbit
DRi
fclk
δ
number of output bits
1
−
equivalent output resolution (bit)
dynamic range at input
clock frequency
16
96.6
−
−
note 5
−
dB
5.6448
MHz
%
clock frequency duty factor
50
−
Fixed Gain Amplifier (FGA)
LOAD
RL
CL
load resistance
5
−
−
−
kΩ
load capacitance
−
15
pF
TRANSFER FUNCTION
Vi(nom)(p-p)
nominal input voltage
−
226.3
−
mV
(peak-to-peak value)
A1
amplification
−
−
−
−
20
−
−
−
−
dB
mV
dB
dB
Vo(nom)(rms) nominal output voltage (RMS value)
800
60
S/N
signal-to-noise ratio
note 6
THD
total harmonic distortion
at HIGH-level;
note 7
−65
Ri
Ro
fi
input impedance
output impedance
input frequency
3.35
−
4.7
−
6.0
kΩ
Ω
100
±3 dB range
100
−
20000
Hz
1999 Apr 02
47
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BIASING
Iref
reference current
−
25
−
µA
FGA/∑∆ path
TRANSFER FUNCTION
A1
amplification
signal-to-noise ratio
total harmonic distortion
−
20
−
dB
dB
dB
S/N
THD
51
−70
60
70
−66
−61
ATX transceiver
DRIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM
fo(sample)
tt(rise)
tt(fall)
audio sample output frequency
rise transition time
4
−
−
−
−
−
−
48
MHz
ns
ns
%
CL = 50 pF
CL = 50 pF
note 8
4
20
fall transition time
4
20
tt(match)
Vo(cr)
Zo
transition time matching
output signal crossover voltage
driver output impedance
90
1.3
30
110
2.0
42
V
steady state
drive
Ω
RECEIVER CHARACTERISTICS IN FULL SPEED MODE: PINS ATXDP AND ATXDM
fs
audio sample input frequency
data input frequency rate
frame interval
5
−
−
−
55
−
kHz
fi(D)
tframe
12.00
1.000
Mbits/s
ms
−
Notes
1. This applies the outputs: pins SDA and SNDA.
2. This applies the inputs: pins SUSREADYNOT, TRC and SNAPSHOT.
3. This applies the outputs: pins CLOCK, UCINT, UCPOR, CLOCKON and DCDCON.
4. Frequencies depend on PLL settings (see Table 1).
Vi
5. Defined here as: 20 × log------------------ where Vi = input voltage and Vn(i)(eq) = equivalent input noise voltage.
Vn(i)(eq)
6. The noise is measured with A-weighting at the nominal input voltage.
7. The distortion is measured at a maximum output voltage of 2.4 V (p-p).
tt(rise)
8. Transition time matching: tt(match)
=
------------
tt(fall)
1999 Apr 02
48
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
13 TIMING
VDDD = VDDA = 3.3 V ±10%; load capacitance = 10 pF; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Data input related to LCC (see Fig.24)
Pins YUV0 toYUV7, HREF and VSYNC
tsu(i)(D)
th(i)(D)
data input set-up time
data input hold time
1
1
−
−
−
−
ns
ns
PPG high-speed pulses for PAL medium resolution sensors; mode 0 (see Fig.25)
td1
delay between falling edge C2 and rising edge C1
delay between rising edge C2 and falling edge C1
delay between falling edge C1 and rising edge SHP
delay between rising edge C1 and rising edge SHD
delay between rising edge C1 and falling edge RG
delay between falling edge CLK1 and rising edge C1
delay between rising edge CLK1 and falling edge C1
delay between rising edge CLK2 and rising edge C1
C1 pulse width HIGH
−2
−1.5
0
2
ns
ns
ns
td2
1
1.5
td3
−3
−1.5 −1
td4
−0.5
0.5
0
0
+0.5 ns
td5
1
2
2
ns
ns
td6
1
td7
−0.5
−2
0
+0.5 ns
td8
0
+2
−
ns
ns
ns
ns
ns
ns
ns
ns
tWH(C1)
tWL(C2)
tWL(SHP)
tWL(SHD)
tWL(RG)
164
166
81
165
167
82
82
84
165
80
C2 pulse width LOW
−
SHP pulse width LOW
−
SHD pulse width LOW
81
−
RG pulse width LOW
83
−
tWL(CLK1) CLK1 pulse width LOW
tWH(CLK2) CLK2 pulse width HIGH
164
79
−
−
tr
rise time
pulse C1
note 1
−
−
−
−
−
4.5
4
−
−
−
−
−
ns
ns
ns
ns
ns
pulse C2
pulse RG
pulse SHP
pulse SHD
4
4
4
tf
fall time
note 1
pulse C1
pulse C2
pulse RG
pulse SHP
pulse SHD
−
−
−
−
−
4
−
−
−
−
−
ns
ns
ns
ns
ns
4
4
4.5
4.5
1999 Apr 02
49
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
SYMBOL
PARAMETER
CONDITIONS MIN. TYP. MAX. UNIT
PPG high-speed pulses for VGA sensors (see Fig.26)
td1
delay between rising edge C2 and rising edge C1
delay between rising edge C3 and rising edge C2
delay between rising edge SHP and falling edge C3
delay between falling edge SHD and rising edge C2
delay between rising edge SHD and rising edge C3
delay between rising edge RG and rising edge C1
delay between rising edge C1 and falling edge CLK1
delay between rising edge C1 and rising edge CLK2
C1 pulse width HIGH
61
61
62
62
63
63
ns
ns
td2
td3
−1.5 −1
+0.5 ns
td4
8
9
10
ns
ns
td5
−12
−0.5
18
20
81
81
82
21
43
21
81
41
−11
0
−10
td6
+0.5 ns
td7
19
21
82
82
85
22
44
22
82
43
21
22
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td8
tWH(C1)
tWH(C2)
tWH(C3)
tWL(SHP)
tWL(SHD)
tWL(RG)
C2 pulse width HIGH
−
C3 pulse width HIGH
−
SHP pulse width LOW
−
SHD pulse width LOW
−
RG pulse width LOW
−
tWH(CLK1) CLK1 pulse width HIGH
tWH(CLK2) CLK2 pulse width HIGH
−
−
Note
1. Load capacity = 11 pF; VDDD = VDDA = 3.3 V; Tamb = 25 °C.
LCC
t
t
h(i)D
su(i)D
data input
FCE153
Fig.24 Data input timing.
1999 Apr 02
50
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
t
WH(C1)
C1
50%
50%
50%
t
t
d1
d2
C2
50%
50%
t
WL(C2)
50%
50%
SHP
SHD
t
t
t
t
d4
d3
WL(SHD)
50%
WL(SHP)
50%
t
WL(RG)
t
d5
50%
50%
RG
t
t
d7
d6
CLK1
50%
50%
t
WL(CLK1)
t
d8
CLK2
50%
50%
t
FCE154
WH(CLK2)
Fig.25 PPG high-speed pulses for PAL medium resolution sensors (mode 0).
1999 Apr 02
51
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
t
WH(C1)
C1
50%
50%
50%
t
t
d1
WH(C2)
C2
C3
50%
50%
t
d2
50%
t
t
WH(C3)
d3
t
WL(SHP)
50%
50%
SHP
SHD
t
t
d5
d4
50%
t
50%
t
d6
WL(SHD)
RG
50%
50%
t
t
d7
WL(RG)
CLK1
50%
50%
50%
t
t
d8
WH(CLK1)
CLK2
50%
t
50%
FCE155
WH(CLK2)
Fig.26 PPG high-speed pulses for VGA sensors (mode 2).
1999 Apr 02
52
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
14 APPLICATION INFORMATION
MIC
SYNC
YUV
SAA8110G
OR
SAA8112HL
USB
48 MHz
TDA8784/87
SENSOR
SAA8117HL
CLOCKON
TRC
PPG pulses
2
I C-BUS
SNERT
power
management
MICRO-
CONTROLLER
FCE157
Fig.27 Application diagram.
1999 Apr 02
53
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
15 PACKAGE OUTLINE
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.20 1.5
0.05 1.3
0.28 0.18 14.1 14.1
0.16 0.12 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT407-1
1999 Apr 02
54
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
If wave soldering is used the following conditions must be
observed for optimal results:
16 SOLDERING
16.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
16.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
16.4 Manual soldering
16.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Apr 02
55
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Apr 02
56
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
17 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Apr 02
57
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
NOTES
1999 Apr 02
58
Philips Semiconductors
Product specification
Digital camera USB interface IC
SAA8117HL
NOTES
1999 Apr 02
59
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© Philips Electronics N.V. 1999
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545006/750/01/pp60
Date of release: 1999 Apr 02
Document order number: 9397 750 04381
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