SC68C2550BIB48,157_技术文档

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte

FIFOs and 68 mode µP interface

Rev. 03 — 9 October 2009

Product data sheet

1. General description

The SC68C2550B is a two channel Universal Asynchronous Receiver and Transmitter

(UART) used for serial data communications. Its principal function is to convert parallel

data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC68C2550B provides enhanced UART functions with 16-byte FIFOs, modem

control interface, DMA mode data transfer. The DMA mode data transfer is controlled by

the FIFO trigger levels and the TXRDYn and RXRDYn signals. On-board status registers

provide the user with error indications and operational status. System interrupts and

modem control features may be tailored by software to meet speciﬁc user requirements.

An internal loopback capability allows on-board diagnostics. Independent programmable

baud rate generators are provided to select transmit and receive baud rates.

The SC68C2550B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,

and is available in a plastic LQFP48 package.

2. Features

I 2 channel UART with 68 mode (Motorola) µP interface

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range

I Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V

I 16-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 16-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I Independent transmit and receive UART control

I Four selectable Receive FIFO interrupt trigger levels

I Software selectable baud rate generator

I Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

I Transmit, Receive, Line Status, and Data Set interrupts independently controlled

I Fully programmable character formatting:

N 5, 6, 7, or 8-bit characters

N Even, odd, or no-parity formats

N 1, 1¹⁄₂, or 2-stop bit

N Baud generation (DC to 5 Mbit/s)

I False start-bit detection

1. For data bus pins D7 to D0, see Table 22 “Limiting values”.

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS, DSR, DTR, RI, CD)

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC68C2550BIB48

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads;

SOT313-2

body 7 × 7 × 1.4 mm

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

2 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

4. Block diagram

SC68C2550B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTER

DATA BUS

AND

D0 to D7

R/W

RESET

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTER

SELECT

LOGIC

A0 to A3

CS

DTRA, DTRB

RTSA, RTSB

OP2A, OP2B

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

IRQ

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aab334

XTAL1

XTAL2

Fig 1. Block diagram of SC68C2550B

SC68C2550B_3

Product data sheet

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3 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

5. Pinning information

5.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D5

D6

RESET

DTRB

DTRA

RTSA

OP2A

RXRDYA

IRQ

3

D7

4

RXB

RXA

TXRDYB

TXA

TXB

OP2B

CS

5

6

SC68C2550BIB48

7

8

n.c.

9

A0

10

11

12

A1

A3

A2

n.c.

002aab335

Fig 2. Pin conﬁguration for LQFP48

5.2 Pin description

Table 2.

Symbol

A0

Pin description

28

27

26

11

Type

Description

I

Address 0 select bit. Internal register address selection.

Address 1 select bit. Internal register address selection.

Address 2 select bit. Internal register address selection.

A1

A2

A3

Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects Channel A,

and a logic HIGH selects Channel B. (See Table 3.)

CDA

CDB

40

16

I

Carrier Detect (active LOW). These inputs are associated with individual UART channels A

through B. A logic 0 on this pin indicates that a carrier has been detected by the modem for

that channel.

CS

10

I

Chip Select (active LOW). This pin enables data transfers between the user CPU and the

SC68C2550B for the channel(s) addressed. Individual UART sections (A, B) are addressed

by A3. See Table 3.

CTSA

CTSB

38

23

I

Clear to Send (active LOW). These inputs are associated with individual UART channels, A

through B. A logic 0 on the CTSn pin indicates the modem or data set is ready to accept

transmit data from the SC68C2550B. Status can be tested by reading MSR[4]. This pin has

no effect on the UART’s transmit or receive operation.

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

4 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2.

Symbol

D0

Pin description …continued

44

45

46

47

48

1

Type

I/O

I

Description

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring

information to or from the controlling CPU. D0 is the least signiﬁcant bit and the ﬁrst data bit

in a transmit or receive serial data stream.

D1

D2

D3

D4

D5

D6

2

D7

3

DSRA

DSRB

39

20

Data Set Ready (active LOW). These inputs are associated with individual UART channels,

A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is

ready for data exchange with the UART. This pin has no effect on the UART’s transmit or

receive operation.

I

DTRA

DTRB

34

35

O

Data Terminal Ready (active LOW). These outputs are associated with individual UART

channels, A through B. A logic 0 on this pin indicates that the SC68C2550B is powered-on

and ready. This pin can be controlled via the modem control register. Writing a logic 1 to

MCR[0] will set the DTRn output pin to logic 0, enabling the modem. This pin will be a logic 1

after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s

transmit or receive operation.

GND

IRQ

17, 24

30

I

Signal and power ground.

O

Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to function

as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable

register) whenever a UART channel(s) requires service. Individual channel interrupt status

can be determined by addressing each channel through its associated internal register,

using CS and A3. An external pull-up resistor must be connected between this pin and V_CC

.

OP2A

OP2B

32

9

O

Output 2 (user-deﬁned). This function is associated with individual channels A and B. The

state of these pins is deﬁned by the user through the software settings of MCR[3].

OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when

MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.

R/W

15

36

I

A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an external

CPU to an internal register that is deﬁned by address bits A[2:0]. A logic HIGH on this pin

will load the contents of an internal register deﬁned by address bits A[2:0] on the

SC68C2550B data bus (D[7:0]) for access by an external CPU.

RESET

Reset (active LOW). A logic 0 on this pin will reset the internal registers and all the outputs.

The UART transmitter output and the receiver input will be disabled during reset time. (See

Section 7.10 “SC68C2550B external reset condition” for initialization details.)

RIA

RIB

41

21

I

Ring Indicator (active LOW). These inputs are associated with individual UART channels,

A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate an interrupt.

RTSA

RTSB

33

22

O

Request to Send (active LOW). These outputs are associated with individual UART

channels, A through B. A logic 0 on the RTSn pin indicates the transmitter has data ready

and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin

to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin

has no effect on the UART’s transmit or receive operation.

RXA

RXB

5

4

I

Receive data A, B. These inputs are associated with individual serial channel data to the

SC68C2550B receive input circuits, A-B. The RXn signal will be a logic 1 during reset, idle

(no data), or when the transmitter is disabled. During the local Loopback mode, the RXn

input pin is disabled and transmit data is connected to the UART receive input, internally.

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

5 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2.

Symbol

RXRDYA

Pin description …continued

Type

O

Description

31

Receive Ready A, B (active LOW). These outputs provide the receive FIFO/RHR status for

individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1

transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to

read/upload, that is, receive ready status with one or more receive characters available in

the FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed

trigger level has not been reached. This signal can also be used for single mode transfers

(DMA mode 0).

RXRDYB 18

O

TXA

TXB

7

8

O

Transmit data A, B. These outputs are associated with individual serial transmit channel

data from the SC68C2550B. The TXn pin will be a logic 1 during reset, idle (no data), or

when the transmitter is disabled. During the local Loopback mode, the TXn output pin is

disabled and transmit data is internally connected to the UART receive input.

TXRDYA

TXRDYB

43

6

O

Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR status for

individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA

mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB

buffer ready status is indicated by logic 0, that is, at lease one location is empty and

available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no

more empty locations in the FIFO or THR. This signal can also be used for single mode

transfers (DMA mode 0).

V_CC

19, 42

13

I

Power supply input

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external clock input.

A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit.

Alternatively, an external clock can be connected to this pin to provide custom data rates.

(See Section 6.5 “Programmable baud rate generator”.) See Figure 3.

XTAL2

n.c.

14

O

-

Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator

output or buffered clock output. Should be left open if an external clock is connected to

XTAL1. For extended frequency operation, this pin should be tied to V_CCvia a 2 kΩ resistor.

12, 25,

29, 37

not connected

SC68C2550B_3

Product data sheet

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6 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6. Functional description

The SC68C2550B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these functions is fairly complex, especially

when manufactured on a single integrated silicon chip. The SC68C2550B represents such

an integration with greatly enhanced features. The SC68C2550B is fabricated with an

advanced CMOS process.

The SC68C2550B is an upward solution that provides a dual UART capability with

16 bytes of transmit and receive FIFO memory. The SC68C2550B is designed to work

with high speed modems and shared network environments that require fast data

processing time. Increased performance is realized in the SC68C2550B by the transmit

and receive FIFOs. This allows the external processor to handle more networking tasks

within a given time. For example, the ST16C2450 without a receive FIFO, will require

unloading of the RHR in 93 microseconds (this example uses a character length of

11 bits, including start/stop bits at 115.2 kbit/s). This means the external CPU will have to

service the receive FIFO less than every 100 microseconds. However, with the 16-byte

FIFO in the SC68C2550B, the data buffer will not require unloading/loading for 1.53 ms.

This increases the service interval, giving the external CPU additional time for other

applications and reducing the overall UART interrupt servicing time. In addition, the four

selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data

throughput performance especially when operating in a multi-channel environment. The

FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,

increases performance, and reduces power consumption.

The SC68C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a

crystal or external clock input of 7.3728 MHz, the user can select data rates up to

460.8 kbit/s.

The rich feature set of the SC68C2550B is available through internal registers. Selectable

receive FIFO trigger levels, selectable transmit and receive baud rates, and modem

interface controls are all standard features.

6.1 UART A-B functions

The UART provides the user with the capability to bidirectionally transfer information

between an external CPU, the SC68C2550B package, and an external serial device. A

logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to conﬁgure, send

data, and/or receive data via UART channels A and B. Individual channel select functions

are shown in Table 3.

Table 3.

Channel selection using CS pin

CS

1

A3

-

UART select

none

0

channel A

channel B

0

1

SC68C2550B_3

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.2 Internal registers

The SC68C2550B provides two sets of internal registers (A and B) consisting of

12 registers each for monitoring and controlling the functions of each channel of the

UART. These registers are shown in Table 4. The UART registers function as data holding

registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control

register (FCR), line status and control registers (LCR/LSR), modem status and control

registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a

user accessible scratchpad register (SPR).

Table 4.

A2

Internal registers decoding

A0 Read mode

A1

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register

(FCR) bit 0. The user can set the receive trigger level via FCR[7:6], but not the transmit

trigger level. The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 5.

Flow control mechanism

Selected trigger level (characters)

IRQ pin activation

1

4

8

14

SC68C2550B_3

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.4 Hardware/software and time-out interrupts

The interrupts are enabled by IER[3:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C2550B

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR register provides the current singular highest priority

interrupt only. A condition can exist where a higher priority interrupt may mask the lower

priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority

interrupt(s) be reﬂected in the status register. Servicing the interrupt without investigating

further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC68C2550B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive

Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the

center of each stop bit received or each time the receive holding register (RHR) is read.

The actual time-out value is 4 character time, including data information length, start bit,

parity bit, and the size of stop bit, that is, 1×, 1.5×, or 2× bit times.

6.5 Programmable baud rate generator

The SC68C2550B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

The SC68C2550B can support a standard data rate of 921.6 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent transmit/receive channel control. The programmable Baud Rate Generator

(BRG) is capable of operating with a frequency of up to 80 MHz. To obtain maximum data

rate, it is necessary to use full rail swing on the clock input. The SC68C2550B can be

conﬁgured for internal or external clock operation. For internal clock oscillator operation,

an industry standard microprocessor crystal is connected externally between the XTAL1

and XTAL2 pins. Alternatively, an external clock can be connected to the XTAL1 pin to

clock the internal baud rate generator for standard or custom rates (see Table 6).

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). The

SC68C2550B divides the basic external clock by 16. The basic 16× clock provides table

rates to support standard and custom applications using the same system design. The

rate table is conﬁgured via the DLL and DLM internal register functions. Customized baud

rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 6 shows the

selectable baud rate table available when using a 1.8432 MHz external clock input.

SC68C2550B_3

Product data sheet

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

XTAL1

XTAL2

X1

1.8432 MHz

C1

22 pF

C2

33 pF

002aab325

Fig 3. Crystal oscillator connection

Table 6. Baud rate generator programming table using a 1.8432 MHz clock

Output

DLM

DLL

baud rate

16× clock divisor

(decimal)

16× clock divisor

(HEX)

program value

(HEX)

program value

(HEX)

50

2304

1536

1047

768

384

192

96

900

600

417

300

180

C0

60

09

06

04

03

01

00

17

00

80

C0

60

30

20

18

10

0C

06

03

02

01

75

110

150

300

600

1200

2400

3600

4800

7200

9600

19.2 k

38.4 k

57.6 k

115.2 k

48

30

32

20

24

18

16

10

12

0C

06

6

3

03

2

02

1

01

6.6 DMA operation

The SC68C2550B FIFO trigger level provides additional ﬂexibility to the user for block

mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an

empty location(s). The user can optionally operate the transmit and receive FIFOs in the

DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA

mode is de-activated (DMA Mode 0), the SC68C2550B activates the interrupt output pin

for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),

the user takes the advantage of block mode operation by loading or unloading the FIFO in

a block sequence determined by the receive trigger level and the transmit FIFO. In this

mode, the SC68C2550B sets the TXRDYn (or RXRDYn) output pin when characters in the

transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive

trigger level.

SC68C2550B_3

Product data sheet

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

6.7 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally

(see Figure 4). MCR[3:0] register bits are used for controlling loopback diagnostic testing.

In the Loopback mode, the transmitter output pin (TXn) and the receiver input pin (RXn)

are disconnected from their associated interface pins, and instead are connected together

internally. The CTSn, DSRn, CDn, and RIn pins are disconnected from their normal

modem control inputs pins, and instead are connected internally to MCR[1] RTS, MCR[0]

DTR, MCR[3] (OP2) and MCR[2] (OP1). Loopback test data is entered into the transmit

holding register via the user data bus interface, D0 to D7. The transmit UART serializes

the data and passes the serial data to the receive UART via the internal loopback

connection. The receive UART converts the serial data back into parallel data that is then

made available at the user data interface D0 to D7. The user optionally compares the

received data to the initial transmitted data for verifying error-free operation of the UART

transmit/receive circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem

Control Interrupts are also operational.

SC68C2550B_3

Product data sheet

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

SC68C2550B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

DATA BUS

AND

D0 to D7

R/W

RESET

CONTROL

LOGIC

MCR[4] = 1

RECEIVE

FIFO

REGISTERS

RECEIVE

SHIFT

REGISTER

RXA, RXB

REGISTER

SELECT

LOGIC

A0 to A3

CS

RTSA, RTSB

CTSA, CTSB

DTRA, DTRB

MODEM

CONTROL

LOGIC

DSRA, DSRB

(OP1A, OP1B)

IRQ

TXRDYA, TXRDYB

RXRDYA, RXRDYB

INTERRUPT

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

RIA, RIB

(OP2A, OP2B)

CDA, CDB

002aab336

XTAL1 XTAL2

Fig 4. Internal Loopback mode diagram

SC68C2550B_3

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7. Register descriptions

Table 7 details the assigned bit functions for the SC68C2550B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.10.

Table 7.

SC68C2550B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General register set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

0

bit 4

0

bit 3

bit 2

bit 1

bit 0

modem receive transmit receive

status line holding holding

interrupt status register register

interrupt interrupt

0

1

0

1

FCR

ISR

00

01

00

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

reserved reserved DMA

XMIT RCVR

FIFO FIFO

FIFOs

enable

0

mode

select

reset

FIFOs

enabled enabled

FIFOs

0

INT

status

priority

bit 2

priority

bit 1

priority

bit 0

LCR

divisor

latch

enable

set break set parity even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

1

0

1

MCR

LSR

00

60

0

loop back OP2

control

(OP1)

RTS

DTR

FIFO

data

error

THR and THR

TSR

empty

break

framing parity

overrun receive

error

empty

interrupt error

error

data

ready

1

0

1

MSR

SPR

X0

FF

CD

RI

DSR

bit 5

CTS

bit 4

∆CD

∆RI

∆DSR

∆CTS

bit 7

bit 6

bit 3

bit 2

bit 1

bit 0

Special register set^[3]

0

1

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown in represents the register’s initialized hexadecimal value; X = n/a.

[2] Accessible only when LCR[7] is logic 0.

[3] Baud rate registers accessible only when LCR[7] is logic 1.

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag in the

LSR register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC68C2550B and

receive FIFO by reading the RHR register. The receive section provides a mechanism to

SC68C2550B_3

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16× clock rate. After 7¹⁄₂clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled, and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the IRQ output pin.

Table 8.

Interrupt Enable Register bits description

Bit

7:4

3

Symbol

IER[7:4]

IER[3]

Description

not used

Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

2

1

IER[2]

IER[1]

Receive Line Status interrupt. This interrupt will be issued whenever a

receive data error condition exists as reﬂected in LSR[4:1].

logic 0 = disable the receiver line status interrupt (normal default

condition)

logic 1 = enable the receiver line status interrupt

Transmit Holding Register interrupt. In the 16C450 mode, this interrupt will

be issued whenever the THR is empty, and is associated with LSR[5]. In the

FIFO modes, this interrupt will be issued whenever the FIFO is empty.

logic 0 = disable the Transmit Holding Register Empty (TXRDY) interrupt

(normal default condition)

logic 1 = enable the TXRDY (ISR level 3) interrupt

0

IER[0]

Receive Holding Register. In the 68C450 mode, this interrupt will be issued

when the RHR has data, or is cleared when the RHR is empty. In the FIFO

mode, this interrupt will be issued when the FIFO has reached the

programmed trigger level or is cleared when the FIFO drops below the

trigger level.

logic 0 = disable the receiver ready (ISR level 2, RXRDY) interrupt

(normal default condition)

logic 1 = enable the RXRDY (ISR level 2) interrupt

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7.2.1 IER versus Transmit/Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU

when the receive FIFO has reached the programmed trigger level. It will be cleared

when the receive FIFO drops below the programmed trigger level.

• Receive FIFO status will also be reﬂected in the user accessible ISR register when

the receive FIFO trigger level is reached. Both the ISR register receive status bit and

the interrupt will be cleared when the FIFO drops below the trigger level.

• The receive data ready bit (LSR[0]) is set as soon as a character is transferred from

the shift register (RSR) to the receive FIFO. It is reset when the FIFO is empty.

• When the Transmit FIFO and interrupts are enabled, an interrupt is generated when

the transmit FIFO is empty due to the unloading of the data by the TSR and UART for

transmission via the transmission media. The interrupt is cleared either by reading the

ISR register, or by loading the THR with new data characters.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC68C2550B in the FIFO polled

mode of operation. In this mode, interrupts are not generated and the user must poll the

LSR register for transmit and/or receive data status. Since the receiver and transmitter

have separate bits in the LSR either or both can be used in the polled mode by selecting

respective transmit or receive control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of receive errors, or a receive break, if encountered.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will show if any FIFO data errors occurred.

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger

levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1 Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to

the 68C450 mode. Transmit Ready pin (TXRDYn) will go to a logic 0 whenever the FIFO

(THR, if FIFO is not enabled) is empty. Receive Ready pin (RXRDYn) will go to a logic 0

whenever the Receive Holding Register (RHR) is loaded with a character.

7.3.1.2 Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when

the transmit FIFO is empty. TXRDYn pin remains a logic 0 as long as one empty FIFO

location is available. The receive interrupt is set when the receive FIFO ﬁlls to the

SC68C2550B_3

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SC68C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

programmed trigger level. However, the FIFO continues to ﬁll regardless of the

programmed level until the FIFO is full. RXRDYn pin packages transitions LOW when the

FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.

7.3.2 FIFO mode

Table 9.

FIFO Control Register bits description

Bit

Symbol Description

7:6

FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive FIFO

interrupt.

logic 0 (or cleared) = normal default condition

logic 1 = receive trigger level

An interrupt is generated when the number of characters in the FIFO equals the

programmed trigger level. However, the FIFO will continue to be loaded until it

is full. Refer to Table 10.

5:4

3

FCR[5:4] not used; initialized to logic 0

FCR[3]

DMA mode select

logic 0 = set DMA mode ‘0’

logic 1 = set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC68C2550B is in the 68C450

mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled;

FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the

transmit FIFO or transmit holding register, the TXRDYn pin will be a logic 0.

Once active, the TXRDYn pin will go to a logic 1 after the ﬁrst character is

loaded into the transmit holding register.

Receive operation in mode ‘0’: When the SC68C2550B is in mode ‘0’

(FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0) and there is at least

one character in the receive FIFO, the RXRDYn pin will be a logic 0. Once

active, the RXRDYn pin will go to a logic 1 when there are no more characters

in the receiver.

Transmit operation in mode ‘1’: When the SC68C2550B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a logic 1 when the

transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations

are empty.

Receive operation in mode ‘1’: When the SC68C2550B is in FIFO mode

(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a

Receive Time-Out has occurred, the RXRDYn pin will go to a logic 0. Once

activated, it will go to a logic 1 after there are no more characters in the FIFO.

2

1

FCR[2]

FCR[1]

XMIT FIFO reset

logic 0 = transmit FIFO not reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit will

return to a logic 0 after clearing the FIFO.

RCVR FIFO reset

logic 0 = receive FIFO not reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO counter

logic (the receive shift register is not cleared or altered). This bit will return to

a logic 0 after clearing the FIFO.

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SC68C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 9.

FIFO Control Register bits description …continued

Bit

Symbol Description

0

FCR[0]

FIFOs enabled

logic 0 = disable the transmit and receive FIFO (normal default condition).

logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’ when

other FCR bits are written to, or they will not be programmed.

Table 10. RCVR trigger levels

FCR[7]

FCR[6]

Receive FIFO trigger level

0

1

0

1

0

1

01

04

08

14

7.4 Interrupt Status Register (ISR)

The SC68C2550B provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. A lower level interrupt may be seen after servicing the

higher level interrupt and re-reading the interrupt status bits. Table 11 shows the data

values (bit 0 to bit 3) for the four prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels.

Table 11. Interrupt source

Priority ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

level

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data Time-out)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

Table 12. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not

being used in the 68C450 mode. They are set to a logic 1 when the

FIFOs are enabled in the SC68C2550B mode.

logic 0 or cleared = default condition

not used

5:4

3:1

ISR[5:4]

ISR[3:1]

INT priority bits 2 to 0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).

logic 0 or cleared = default condition

INT status

0

ISR[0]

logic 0 = an interrupt is pending and the ISR contents may be used as

a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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SC68C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 13. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor Latch enable. The internal baud rate counter latch and

Enhanced Feature mode enable.

logic 0 = Divisor Latch disabled (normal default condition).

Logic 1 = Divisor Latch enabled.

6

LCR[6]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TXn output is forced to a logic 0 state).

This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no break condition (normal default condition)

logic 1 = forces the transmitter output (TXn) to a logic 0 for alerting

the remote receiver to a line break condition

5:3

2

LCR[5:3]

LCR[2]

programs the parity conditions (see Table 14)

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with

the programmed word length (see Table 15).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 16).

logic 0 or cleared = default condition

Table 14. LCR[5:3] parity selection

LCR[5] LCR[4] LCR[3] Parity selection

X

0

1

X

0

1

0

1

0

1

no parity

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 15. LCR[2] stop bit length

LCR[2]

Word length

5, 6, 7, 8

5

Stop bit length (bit times)

0

1

1¹⁄₂

6, 7, 8

2

Table 16. LCR[1:0] word length

LCR[1]

LCR[0]

Word length

0

1

0

1

0

1

5

6

7

8

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SC68C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 17. Modem Control Register bits description

Bit

7:5

4

Symbol

MCR[7:5]

MCR[4]

Description

reserved; set to ‘0’

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TXn) and the receiver input (RXn), CTSn, DSRn, CDn,

and RIn pins are disconnected from the SC68C2550B I/O pins. Internally

the modem data and control pins are connected into a loopback data

conﬁguration (see Figure 4). In this mode, the receiver and transmitter

interrupts remain fully operational. The Modem Control Interrupts are also

operational, but the interrupts’ sources are switched to the lower four bits of

the Modem Control. Interrupts continue to be controlled by the IER

register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

OP2 control

3

2

MCR[3]

MCR[2]

logic 0 = forces OP2n output pin to HIGH state

logic 1 = forces OP2n output pin to LOW state. In Loopback mode,

controls MSR[7].

(OP1). OP1A/OP1B are not available as an external signal in the

SC68C2550B. This bit is instead used in the Loopback mode only. In the

Loopback mode, this bit is used to write the state of the modem RIn

interface signal.

1

0

MCR[1]

MCR[0]

RTS

logic 0 = force RTSn output pin to a logic 1 (normal default condition)

logic 1 = force RTSn output pin to a logic 0

DTR

logic 0 = force DTRn output pin to a logic 1 (normal default condition)

logic 1 = force DTRn output pin to a logic 0

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SC68C2550B

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7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC68C2550B and

the CPU.

Table 18. Line Status Register bits description

Bit Symbol Description

7

LSR[7]

FIFO data error

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when there are no remaining error ﬂags

associated with the remaining data in the FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the Transmit Holding Register and the Transmit Shift Register

are both empty. It is reset to logic 0 whenever either the THR or TSR contains a

data character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO

and transmit shift register are both empty.

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the Transmit Holding Register into the Transmit Shift Register.

The bit is reset to a logic 0 concurrently with the loading of the Transmit Holding

Register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is

empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RXn was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the Receive Shift Register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready

logic 0 = no data in Receive Holding Register or FIFO (normal default

condition)

logic 1 = data has been received and is saved in the Receive Holding Register

or FIFO

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC68C2550B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 19. Modem Status Register bits description

Bit

Symbol Description

7

MSR[7]

MSR[6]

MSR[5]

MSR[4]

MSR[3]

CD. During normal operation, this bit is the complement of the CDn input pin.

Reading this bit in the Loopback mode produces the state of MCR[3] (OP2).

6

5

4

3

RI. During normal operation, this bit is the complement of the RIn input pin.

Reading this bit in the Loopback mode produces the state of MCR[2] (OP1).

DSR. During normal operation, this bit is the complement of the DSRn input

pin. During the Loopback mode, this bit is equivalent to the state of MCR[0].

CTS. During normal operation, this bit is the complement of the CTSn input

pin. During the Loopback mode, this bit is equivalent to the state of MCR[1].

∆CD ^[1]

logic 0 = no change of state on CDn pin (normal default condition)

logic 1 = the CDn input pin to the SC68C2550B has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

2

1

0

MSR[2]

MSR[1]

MSR[0]

∆RI ^[1]

logic 0 = no change of state on RIn pin (normal default condition)

logic 1 = the RIn input pin to the SC68C2550B has changed from a logic 0

to a logic 1. A Modem Status Interrupt will be generated.

∆DSR ^[1]

logic 0 = no change of state on DSRn pin (normal default condition)

logic 1 = the DSRn input pin to the SC68C2550B has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

∆CTS ^[1]

logic 0 = no change of state on CTSn pin (normal default condition)

logic 1 = the CTSn input pin to the SC68C2550B has changed state since

the last time it was read. A Modem Status Interrupt will be generated.

[1] Whenever any MSR bit 0 to bit 3 is set to logic 1, a Modem Status Interrupt will be generated.

SC68C2550B_3

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7.9 Scratchpad Register (SPR)

The SC68C2550B provides a temporary data register to store 8 bits of user information.

7.10 SC68C2550B external reset condition

Table 20. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

FCR

ISR

FCR[7:0] = 0

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

SFR[7:0] = 1

MSR

SPR

DLL

DLL[7:0] = X

DLM

DLM[7:0] = X

Table 21. Reset state for outputs

Output

Reset state

logic 1

TXA, TXB

OP2A, OP2B

RTSA, RTSB

DTRA, DTRB

IRQ

logic 1

3-state condition

8. Limiting values

Table 22. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_CC

V_n

supply voltage

-

7

voltage on any other pin

at D7 to D0

GND − 0.3 V_CC+ 0.3

GND − 0.3 5.3

V

at any input only pin

operating

V

T_amb

T_stg

ambient temperature

storage temperature

−40

−65

-

+85

°C

mW

+150

500

P_tot/pack total power dissipation

per package

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SC68C2550B

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9. Static characteristics

Table 23. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5.0 V

Unit

Min

−0.3

1.8

Max

0.45

V_CC

0.65

-

Min

−0.3

2.4

Max

0.6

V_CC

0.8

-

Min

−0.5

3.0

Max

0.6

V_CC

0.8

-

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

V

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

except X1 clock

on all outputs

−0.3

1.6

−0.3

2.0

−0.5

2.2

V_IH

[1]

V_OL

I_OL= 5 mA

(data bus)

-

0.4

V

I_OL= 4 mA

(other outputs)

-

0.4

-

0.4

-

I_OL= 2 mA

(data bus)

-

I_OL= 1.6 mA

(other outputs)

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(data bus)

-

2.4

I_OH= −1 mA

(other outputs)

-

2.0

-

I_OH= −800 µA

(data bus)

1.85

-

I_OH= −400 µA

(other outputs)

-

I_LIL

LOW-level input leakage

current

±10

±10 µA

±30 µA

I_L(clk)

I_CC

C_i

clock leakage current

supply current

-

±30

3.5

5

-

±30

4.5

5

-

f = 5 MHz

4.5

5

mA

pF

input capacitance

[1] Except XTAL2, V_OL= 1 V typical.

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SC68C2550B

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

10. Dynamic characteristics

Table 24. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_CC± 10 %, unless speciﬁed otherwise.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V and 5 V Unit

Min

Max

-

Min

10

20

-

Max

-

t_d1

t_d2

t_d3

t_d4

t_d6

t_d7

t_d8

R/W to chip select

10

20

-

ns

read cycle delay

25 pF load

-

delay from CS to data

data disable time

77

15

-

26

15

-

write cycle delay

25

-

25

-

delay from write to output

25 pF load

100

33

24

delay to set interrupt from modem 25 pF load

input

-

t_d9

delay to reset interrupt from read

delay from stop to set interrupt

delay from read to reset interrupt

delay from start to set interrupt

delay from write to transmit start

delay from write to reset interrupt

delay from stop to set RXRDY

delay from read to reset RXRDY

delay from write to set TXRDY

delay from start to reset TXRDY

R/W hold time from CS

data hold time

25 pF load

-

100

1T_RCLK

100

-

24

1T_RCLK

29

ns

MHz

ns

[1]

t_d10

t_d11

t_d12

t_d13

t_d14

t_d15

t_d16

t_d17

t_d18

t_h2

-

25 pF load

-

100

-

100

[1]

8T_RCLK

24T_RCLK

100

8T_RCLK

24T_RCLK

70

-

[1]

1T_RCLK

-

100

-

75

-

100

-

70

[1]

-

16T_RCLK

-

16T_RCLK

10

15

10

-

10

15

6

-

t_h3

t_h4

address hold time

-

t_WH

t_WL

pulse width HIGH

-

pulse width LOW

-

6

-

[2][3]

[4]

f_XTAL

t_(RESET)

t_su1

t_su2

t_w(CS)

clock speed

48

-

80

-

RESET pulse width

200

10

16

77

200

10

16

30

address set-up time

-

data set-up time

-

CS pulse width

-

[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[2] Applies to external clock; crystal oscillator maximum = 24 MHz.

1

[3] f _XTAL

=

--------------

t_w(clk)

[4] Reset pulse must happen when CS is inactive.

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

10.1 Timing diagrams

A0 to A3

valid address

t

h4

t

su1

t

d2

w(CS)

CS

R/W

t

d4

d1

t

d3

D0 to D7

valid data

002aae395

Fig 5. General read timing

A0 to A3

valid address

t

h4

su1

t

w(CS)

CS

R/W

t

d6

d1

h2

t

h3

t

su2

D0 to D7

valid data

002aae396

Fig 6. General write timing

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

(1)

active

CS (write)

t

d7

RTSA, RTSB

DTRA, DTRB

change of state

CDA, CDB

CTSA, CTSB

DSRA, DSRB

change of state

t

d8

IRQ

active

t

d9

(2)

CS (read)

active

t

d8

change of state

RIA, RIB

002aab089

(1) CS timing during a write cycle. See Figure 6.

(2) CS timing during a read cycle. See Figure 5.

Fig 7. Modem input/output timing

t

WH

WL

external clock

t

w(clk)

002aac357

1

f _XTAL

=

--------------

t_w(clk)

Fig 8. External clock timing

SC68C2550B_3

Product data sheet

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Start

bit

parity Stop Start

bit

data bits (0 to 7)

RXA, RXB

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d10

active

IRQ

t

d11

CS (read)

active

16 baud rate clock

002aab090

Fig 9. Receive timing

Start

bit

parity Stop Start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

t

d15

active data

ready

RXRDYA,

RXRDYB

t

d16

CS (read)

active

002aab091

Fig 10. Receive ready timing in non-FIFO mode

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Start

bit

parity Stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

first byte that

reaches the

trigger level

t

d15

active data

ready

RXRDYA,

RXRDYB

t

d16

CS (read)

active

002aab092

Fig 11. Receive ready timing in FIFO mode

Start

bit

parity Stop Start

bit bit bit

data bits (0 to 7)

D0

D1

D2

D3

D4

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

active

transmitter ready

IRQ

t

d12

t

d14

t

d13

active

CS (write)

16 baud rate clock

002aab093

Fig 12. Transmit timing

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Product data sheet

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Start

bit

parity Stop Start

bit

data bits (0 to 7)

D3 D4

TXA,

TXB

D0

D1

D2

D5

D6

D7

active

CS (write)

D0 to D7

byte #1

t

d18

t

d17

active

transmitter ready

TXRDYA,

TXRDYB

transmitter

not ready

002aab094

Fig 13. Transmit ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA,

TXB

5 data bits

6 data bits

7 data bits

CS (write)

D0 to D7

active

t

d18

byte #16

t

d17

TXRDYA,

TXRDYB

trigger

lead

002aab337

Fig 14. Transmit ready timing in FIFO mode

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

11. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 15. Package outline SOT313-2 (LQFP48)

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC68C2550B_3

Product data sheet

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 16) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 25 and 26

Table 25. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 26. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 16.

SC68C2550B_3

Product data sheet

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SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 16. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 27. Abbreviations

Acronym

CPU

Description

Central Processing Unit

DMA

FIFO

ISDN

LSB

Direct Memory Access

First In/First Out

Integrated Service Digital Network

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver and Transmitter

UART

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Product data sheet

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

14. Revision history

Table 28. Revision history

Document ID

SC68C2550B_3

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20091009

Product data sheet

-

SC68C2550B_2

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Data sheet descriptive title changed from “... Motorola µP interface” to “... 68 mode µP interface”

• Section 2 “Features”: added (new) 3^rdbullet item and Footnote 1

• Table 2 “Pin description”:

–

Description for RXRDYA, RXRDYB: deleted “This function is associated with PLCC44 and

LQFP48 packages only.”

–

Description for TXRDYA, TXRDYB: deleted “This function is associated with PLCC44 and

LQFP48 packages only.”

• Table 22 “Limiting values”:

–

parameter description for symbol V_nchanged from “voltage at any pin” to “voltage on any other

pin”; added separate conditions for “at D7 to D0” and “at any input only pin”

parameter description for symbol T_ambchanged from “operating temperature” to “ambient

temperature” (moved “operating” to Conditions column)

symbol for ‘total power dissipation per package” changed from “P_tot(pack)” to “P_tot/pack”

• Table 23 “Static characteristics”:

–

descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %” to

“tolerance of V_CC± 10 %”

symbol/parameter changed from “V_IL(CK), LOW-level clock input voltage” to “V_IL(clk), clock

LOW-level input voltage”

symbol/parameter changed from “V_IH(CK), HIGH-level clock input voltage” to “V_IH(clk), clock

HIGH-level input voltage”

symbol/parameter changed from “I_CL, clock leakage” to “I_L(clk), clock leakage current”

• Table 24 “Dynamic characteristics”:

–

descriptive line below table title changed from “V_CC= 2.5 V, 3.3 V or 5.0 V ± 10 %” to

“tolerance of V_CC± 10 %”

–

symbol “t_1w, t_2w” (clock cycle period) separated into 2 symbols “t_WH, pulse width HIGH” and

“t_WL, pulse width LOW”

–

symbol “t_w1, CS strobe width” changed to “t_w(CS), CS pulse width”

Table note [3]: changed denominator from “t_3w” to “t_w(clk)

added Table note [4] and its reference at t_(RESET)

”

• Figure 5 “General read timing”: changed symbol from “t_w1” to “t_w(CS)

”

• Figure 6 “General write timing”: changed symbol from “t_w1” to “t_w(CS)

”

• Figure 8 “External clock timing”:

–

symbol changed from “t_1w” to “t_WH

symbol changed from “t_2w” to “t_WL

symbol changed from “t_3w” to “t_w(clk)

”

• updated soldering information

SC68C2550B_2

(9397 750 14941)

20050428

Product data sheet

-

SC68C2550B_1

-

SC68C2550B_1

(9397 750 14698)

20050329

Product data sheet

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

34 of 36

SC68C2550B

NXP Semiconductors

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC68C2550B_3

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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

13

14

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33

Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 35

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.1

15.2

15.3

15.4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 35

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6

Functional description . . . . . . . . . . . . . . . . . . . 7

UART A-B functions . . . . . . . . . . . . . . . . . . . . . 7

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 8

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hardware/software and time-out interrupts. . . . 9

Programmable baud rate generator . . . . . . . . . 9

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 10

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . 11

6.1

6.2

6.3

6.4

6.5

6.6

6.7

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 13

Transmit Holding Register (THR) and

Receive Holding Register (RHR) . . . . . . . . . . 13

Interrupt Enable Register (IER) . . . . . . . . . . . 14

IER versus Transmit/Receive FIFO interrupt

7.2

7.2.1

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 15

IER versus Receive/Transmit FIFO polled

7.2.2

mode operation. . . . . . . . . . . . . . . . . . . . . . . . 15

FIFO Control Register (FCR) . . . . . . . . . . . . . 15

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mode 0 (FCR bit 3 = 0). . . . . . . . . . . . . . . . . . 15

Mode 1 (FCR bit 3 = 1). . . . . . . . . . . . . . . . . . 15

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt Status Register (ISR) . . . . . . . . . . . . 17

Line Control Register (LCR) . . . . . . . . . . . . . . 18

Modem Control Register (MCR) . . . . . . . . . . . 19

Line Status Register (LSR). . . . . . . . . . . . . . . 20

Modem Status Register (MSR). . . . . . . . . . . . 21

Scratchpad Register (SPR) . . . . . . . . . . . . . . 22

SC68C2550B external reset condition . . . . . . 22

7.3

7.3.1

7.3.1.1

7.3.1.2

7.3.2

7.4

7.5

7.6

7.7

7.8

7.9

7.10

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22

Static characteristics. . . . . . . . . . . . . . . . . . . . 23

Dynamic characteristics . . . . . . . . . . . . . . . . . 24

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 25

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 31

Introduction to soldering . . . . . . . . . . . . . . . . . 31

Wave and reﬂow soldering . . . . . . . . . . . . . . . 31

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 32

12.1

12.2

12.3

12.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 October 2009

Document identifier: SC68C2550B_3


型号：	SC68C2550BIB48,157
厂家：	NXP
描述：	SC68C2550B - 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode uP interface QFP 48-Pin 通信时钟数据传输先进先出芯片外围集成电路
文件：	总36页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC68C2550BIB48,157 [NXP]

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