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SSTV16857DGG,518 [NXP]

SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin;
SSTV16857DGG,518
型号： SSTV16857DGG,518
厂家： NXP    NXP
描述：

SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin

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INTEGRATED CIRCUITS  
SSTV16857  
14-bit SSTL_2 registered driver  
with differential clock inputs  
Product data  
2002 Sep 27  
Supersedes data of 2002 Jun 05  
Philips  
Semiconductors  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
FEATURES  
PIN CONFIGURATION  
• Stub-series terminated logic for 2.5 V V  
(SSTL_2)  
DDQ  
• Optimized for DDR (Double Data Rate) SDRAM applications  
• Inputs compatible with JESD8–9 SSTL_2 specifications.  
• Flow-through architecture optimizes PCB layout  
48 D1  
Q1  
Q2  
1
2
3
47  
46  
45  
44  
D2  
GND  
GND  
• ESD classification testing is done to JEDEC Standard JESD22.  
V
4
5
V
CC  
DDQ  
Q3  
Protection exceeds 2000 V to HBM per method A114.  
D3  
• Latch-up testing is done to JEDEC Standard JESD78, which  
43 D4  
42 D5  
Q4  
Q5  
6
7
8
9
exceeds 100 mA.  
• Same form, fit, and function as SSTL16877  
41  
40  
GND  
D6  
D7  
• Full DDR 200/266 solution @ 2.5 V when used with PCKV857  
• See SSTV16856 for driver/buffer version with mode select.  
• Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages  
V
DDQ  
39 CLK–  
38 CLK+  
Q6 10  
Q7 11  
DESCRIPTION  
The SSTV16857 is a 14-bit SSTL_2 registered driver with differential  
37  
36  
35  
V
CC  
V
12  
DDQ  
clock inputs, designed to operate between 2.3 V and 2.7 V. V  
DDQ  
GND 13  
Q8 14  
Q9 15  
GND  
must not exceed V . Inputs are SSTL_2 type with V  
normally at  
CC  
REF  
V
REF  
0.5*V . The outputs support class I which can be used for  
DDQ  
standard stub-series applications or capacitive loads. Master reset  
(RESET) asynchronously resets all registers to zero.  
34 RESET  
33 D8  
V
16  
DDQ  
The SSTV16857 is intended to be incorporated into standard DIMM  
(Dual In-Line Memory Module) designs defined by JEDEC, such as  
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.  
Different from traditional SDRAM, DDR SDRAM transfers data on  
both clock edges (rising and falling), thus doubling the peak bus  
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of  
266 MHz. The modules require between 23 and 27 registered  
control and address lines, so two 14-bit wide devices will be used on  
each module. The SSTV16857 is intended to be used for SSTL_2  
input and output signals.  
32 D9  
GND 17  
Q10 18  
Q11 19  
Q12 20  
31  
30  
D10  
D11  
D12  
29  
28  
V
21  
V
DDQ  
CC  
27 GND  
GND 22  
Q13 23  
Q14 24  
26  
25  
D13  
D14  
The device data inputs consist of differential receivers. One  
differential input is tied to the input pin while the other is tied to a  
reference input pad, which is shared by all inputs.  
SW00685  
The clock input is fully differential to be compatible with DRAM  
devices that are installed on the DIMM. However, since the control  
inputs to the SDRAM change at only half the data rate, the device  
must only change state on the positive transition of the CLK signal.  
In order to be able to provide defined outputs from the device even  
before a stable clock has been supplied, the device must support an  
asynchronous input pin (reset), which when held to the LOW state  
will assume that all registers are reset to the LOW state and all  
outputs drive a LOW signal as well.  
QUICK REFERENCE DATA  
GND = 0 V; T  
= 25°C; t =t v2.5 ns  
amb  
r
f
SYMBOL  
/t  
PARAMETER  
CONDITIONS  
= 2.5 V  
TYPICAL  
UNIT  
ns  
t
Propagation delay; CLK to Qn  
Input capacitance  
C = 30 pF; V  
2.4  
2.9  
PHL PLH  
L
DDQ  
C
V
CC  
= 2.5 V  
pF  
I
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE  
0 to +70 °C  
ORDER CODE  
SSTV16857DGG  
SSTV16857DGV  
SSTV16857EV  
DWG NUMBER  
SOT362-1  
48-Pin Plastic TSSOP  
48-Pin Plastic TSSOP (TVSOP)  
56-Ball Plastic VFBGA  
0 to +70 °C  
SOT480-1  
0 to +70 °C  
SOT702-1  
2
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
PIN DESCRIPTION  
LOGIC DIAGRAM  
PIN NUMBER  
SYMBOL  
NAME AND FUNCTION  
LVCMOS  
asynchronous master reset  
(Active LOW)  
RESET  
V
REF  
D1  
34  
RESET  
REGISTER  
REGISTER  
Q1  
Q2  
48, 47, 44, 43,  
42, 41, 40, 33,  
32, 31, 30, 29,  
26, 25  
D2  
D1 – D14 SSTL_2 data inputs  
Q1 – Q14 SSTL_2 data outputs  
D3  
D4  
REGISTER  
REGISTER  
REGISTER  
REGISTER  
Q3  
Q4  
1, 2, 5, 6, 7, 10,  
11, 14, 15, 18,  
19, 20, 23, 24  
35  
V
SSTL_2 input reference level  
Ground (0 V)  
REF  
D5  
D6  
Q5  
Q6  
3, 8, 13, 17, 22,  
27, 36, 46  
GND  
28, 37, 45  
V
Positive supply voltage  
Output supply voltage  
CC  
4, 9, 12, 16, 21  
V
DDQ  
D7  
D8  
REGISTER  
REGISTER  
REGISTER  
REGISTER  
Q7  
Q8  
38  
39  
CLK+  
CLK–  
Differential clock inputs  
FUNCTION TABLE  
D9  
INPUTS  
OUTPUT  
Q9  
Q
RESET  
CLK  
CLK  
D
X
H
L
D10  
Q10  
L
H
H
H
X
↓
X
L
H
L
↑
↑
D11  
D12  
REGISTER  
REGISTER  
Q11  
Q12  
↓
L or H  
L or H  
X
Q
0
H = High voltage level  
L = High voltage level  
↓ = High-to-Low transition  
↑ = Low-to-High transition  
X = Don’t care  
D13  
D14  
REGISTER  
REGISTER  
Q13  
Q14  
CLK+  
CLK–  
SW00763  
3
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
BALL CONFIGURATION  
1
2
3
4
5
6
A
B
Q1  
NC  
NC  
NC  
NC  
D1  
GND  
Q4  
Q2  
Q3  
V
V
D2  
D3  
GND  
D4  
CC  
CC  
C
D
Q5  
D5  
V
V
GND  
Q7  
Q6  
CLK–  
D6  
D7  
CC  
CC  
E
F
CLK+  
V
CC  
GND  
Q8  
V
GND  
D8  
REF  
V
GND  
Q9  
RESET  
D10  
D9  
G
CC  
H
J
Q11  
GND  
Q14  
Q12  
Q13  
NC  
Q10  
D12  
D13  
NC  
D11  
GND  
D14  
V
V
CC  
CC  
K
NC  
NC  
SW00952  
1
ABSOLUTE MAXIMUM RATINGS  
LIMITS  
UNIT  
SYMBOL  
PARAMETER  
CONDITION  
MIN  
–0.5  
—
MAX  
V
I
DC supply voltage  
+4.6  
–50  
V
mA  
V
CC  
DC input diode current  
V < 0  
I
IK  
3
V
I
DC input voltage  
–0.5  
—
V
+ 0.5  
DDQ  
I
DC output diode current  
V
O
< 0  
–50  
+ 0.5  
DDQ  
mA  
V
OK  
3
V
OUT  
DC output voltage  
–0.5  
—
V
DC output current  
V
O
= 0 to V  
±50  
±100  
+150  
DDQ  
I
mA  
OUT  
4
Continuous current  
V
, V , or GND  
DDQ  
—
CC  
2
T
stg  
Storage temperature range  
–65  
°C  
NOTES:  
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the  
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute-maximum-rated conditions for extended periods may affect device reliability.  
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction  
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.  
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
4. The continuous current at V , V  
, or GND should not exceed ±100 mA.  
DDQ  
CC  
4
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
1
RECOMMENDED OPERATING CONDITIONS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN  
2.3  
TYP  
2.5  
MAX  
2.7  
UNIT  
V
V
CC  
Supply voltage  
V
Output supply voltage  
Reference voltage  
2.3  
2.5  
2.7  
V
DDQ  
1.15  
1.25  
1.35  
V
V
REF  
(V  
REF  
= 0.5 x V  
)
DDQ  
V
Termination voltage  
Input voltage  
V
REF  
– 40 mV  
V
V + 40 mV  
REF  
V
V
TT  
REF  
V
0
—
V
CC  
I
V
AC HIGH-level input voltage  
AC LOW-level input voltage  
DC HIGH-level input voltage  
DC LOW-level input voltage  
HIGH-level output current  
LOW-level output current  
Operating free-air temperature range  
All inputs  
All inputs  
All inputs  
All inputs  
V
V
+ 350 mV  
—
—
—
—
—
—
—
—
V
IH  
REF  
V
—
V
– 350 mV  
V
IL  
REF  
V
IH  
+ 180 mV  
V
+ 0.5 V  
V
REF  
DDQ  
V
V
– 0.5 V  
V
REF  
– 180 mV  
–20  
V
IL  
SS  
I
—
—
0
mA  
mA  
°C  
OH  
I
OL  
20  
T
amb  
70  
NOTE:  
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.  
DC ELECTRICAL CHARACTERISTICS  
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
Temp = 0 to +70 °C  
UNIT  
2
MIN  
TYP  
—
MAX  
–1.2  
—
V
I/O supply voltage  
V
V
= 2.3 V; I = –18 mA  
—
IK  
CC  
I
= 2.3 V to 2.7 V; I = –100 µA  
V
– 0.2  
—
V
V
CC  
OH  
CC  
V
OH  
HIGH level output voltage  
V
CC  
V
CC  
V
CC  
= 2.3 V; I = –16 mA  
1.95  
—
—
—
—
0.2  
0.35  
1.53  
—
OH  
= 2.3 V to 2.7 V; I = 100 µA  
OL  
V
OL  
LOW level output voltage  
= 2.3 V; I = 16 mA  
—
—
OL  
V
CLK, CLK  
CLK, CLK  
Common mode range for reliable performance  
Minimum peak-to-peak input to ensure logic state  
0.97  
360  
—
—
V
CMR  
V
—
mV  
PP  
V
V
V
V
V
V
= 2.7 V; V = 1.7 V or 0.8 V  
0.01  
0.01  
0.05  
0.05  
0.05  
0.5  
±5  
CC  
CC  
CC  
CC  
CC  
CC  
I
Data inputs, RESET  
CLK, CLK  
V
= 1.15 V or 1.35 V  
µA  
µA  
REF  
= 2.7 V; V = 2.7 V or 0 V  
—
±5  
I
= 2.7 V; V = 1.7 V or 0.8 V  
—
±5  
I
I
I
V
V
= 1.15 V or 1.35 V  
= 1.15 V or 1.35 V  
REF  
= 2.7 V; V = 2.7 V or 0 V  
—
±5  
I
V
REF  
= 2.7 V  
—
±5  
µA  
µA  
REF  
Quiescent supply current  
CLK and CLK in opposite  
= 2.7 V; V = 1.7 V or 0.8 V  
RESET = GND  
—
10  
I
I
CC  
1
V
CC  
= 2.7 V; V = 2.7 V or 0 V  
RESET = V  
—
10  
25  
mA  
state  
I
CC  
NOTES:  
1. When CLK and CLK are HIGH, typical I = 25 mA.  
CC  
2. All typical values are at V = 2.5 V and T  
= 25 °C (unless otherwise specified).  
CC  
amb  
5
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
TIMING REQUIREMENTS  
Over recommended operating conditions; T  
= 0 to +70 °C (unless otherwise noted) (see Figure 1)  
amb  
LIMITS  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
UNIT  
V
CC  
= 2.5 V ±0.2 V  
MIN  
—
MAX  
f
Clock frequency  
200  
—
MHz  
ns  
clock  
t
w
Pulse duration, CLK, CLK HIGH or LOW  
1.0  
0.2  
0.8  
0.75  
Data before CLK↑, CLK↓  
—
t
su  
Setup time  
Hold time  
ns  
ns  
RESET HIGH before CLK↑, CLK↓  
—
t
h
—
SWITCHING CHARACTERISTICS  
Over recommended operating conditions; T  
= 0 to +70 °C; V  
= 2.3 – 2.7 V and V  
does not exceed V  
CC.  
amb  
DDQ  
DDQ  
Class I, V  
= V = V  
× 0.5 and C = 10 pF (unless otherwise noted) (see Figure 1)  
DDQ L  
REF  
TT  
LIMITS  
= 2.5 V ±0.2 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
SYMBOL  
UNIT  
V
CC  
MIN  
200  
1.0  
MAX  
f
Maximum clock frequency  
CLK and CLK  
—
MHz  
ns  
max  
t
/t  
Q
Q
2.8  
4.0  
PLH PHL  
t
RESET  
2.0  
ns  
PHL  
184/200-pin DDR SDRAM DIMM  
FRONT SIDE  
SSTV16857  
SSTV16857  
PCKV857  
The PLL clock distribution device and SSTV registered drivers reduce  
signal loads on the memory controller and prevent timing delays and  
waveform distortions that would cause unreliable operation  
SW00686  
6
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
PARAMETER MEASUREMENT INFORMATION  
AC WAVEFORMS  
V
IH  
t
W
V
IH  
CLK  
V
V
REF  
REF  
INPUT  
V
V
REF  
REF  
V
V
IL  
t
t
PHL  
PLH  
V
IL  
OH  
SW00339  
V
V
REF  
OUTPUT  
REF  
Waveform 3. Pulse duration  
V
OL  
SW00836  
Waveform 1. Propagation delay times  
V
IH  
TIMING INPUT  
V
REF  
V
IH  
V
IL  
RESET  
V
REF  
t
su  
t
h
V
V
IL  
V
IH  
t
PHL  
DATA INPUT  
V
V
REF  
REF  
OH  
V
REF  
OUTPUT  
V
IL  
V
OL  
SW00837  
SW00340  
Waveform 2. Propagation delay RESET to output.  
Waveform 4. Setup and hold times  
TEST CIRCUIT  
V
TT  
50 Ω  
TEST POINT  
C
= 30 pF  
L
NOTES:  
includes probe and jig capacitance  
C
L
All input pulses are supplied by generators having the following characteristics:  
PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1.25 ns/V, t 1.25 ns/V.  
O
r
f
The outputs are measured one at a time with one transition per measurement.  
= V = V x 0.5  
V
TT  
REF  
DDQ  
SW00838  
Figure 1. Load circuitry  
7
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm  
SOT362-1  
8
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
TSSOP48: plastic thin shrink small outline package; 48 leads;  
body width 4.4 mm; lead pitch 0.4 mm  
SOT480-1  
E
A
D
X
c
y
H
E
v
M
A
Z
25  
48  
Q
(A 3)  
A
A
2
A
1
pin 1 index  
θ
L
p
L
detail X  
1
24  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
θ
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
1
2
3
p
E
max.  
o
o
0.15  
0.05  
0.95  
0.85  
0.23  
0.13  
0.20  
0.09  
9.80  
9.60  
4.50  
4.30  
6.60  
6.20  
0.70  
0.50  
0.40  
0.30  
0.40  
0.10  
8
0
mm  
1.10  
0.40  
0.25  
1.00  
0.20  
0.07  
0.08  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEDEC  
EIAJ  
97–03–20  
99–12–27  
SOT480–1  
MO–153  
9
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls;  
body 4.5 x 7 x 0.65 mm  
SOT702-1  
10  
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
REVISION HISTORY  
Rev  
Date  
Description  
_6  
2002 Sep 27  
Product data (9397 750 10412); sixth version supersedes Product data fifth  
version, 2002 Jun 05.  
Engineering Change Notice: 853 2224 28989 (2002 Sep 26).  
Modifications:  
Package type changed from SSTV16857EC to SSTV16857EV.  
_5  
2002 Jun 05  
Product data (9397 750 09942); fifth version.  
11  
2002 Sep 27  
Philips Semiconductors  
Product data  
14-bit SSTL_2 registered driver  
with differential clock inputs  
SSTV16857  
Data sheet status  
Product  
status  
Definitions  
[1]  
Data sheet status  
[2]  
Objective data  
Development  
This data sheet contains data from the objective specification for product development.  
Philips Semiconductors reserves the right to change the specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
Production  
This data sheet contains data from the preliminary specification. Supplementary data will be  
published at a later date. Philips Semiconductors reserves the right to change the specification  
without notice, in order to improve the design and supply the best possible product.  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply.  
Changes will be communicated according to the Customer Product/Process Change Notification  
(CPCN) procedure SNW-SQ-650A.  
[1] Please consult the most recently issued data sheet before initiating or completing a design.  
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL  
http://www.semiconductors.philips.com.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Koninklijke Philips Electronics N.V. 2002  
Contact information  
All rights reserved. Printed in U.S.A.  
For additional information please visit  
http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
Date of release: 09-02  
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Semiconductors  

相关型号：

SSTV16857DGG-T

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SSTV16857DGV

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SSTV16857DGV,112

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SSTV16857DGV,118

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SSTV16857EV

 Bus Driver, PBGA56

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SSTV16857EV

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NXP

SSTV16857EV,157

 IC SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56, 4.50 X 7 X 0.65 MM, PLASTIC, SOT-702-1, VFBGA-56, FF/Latch

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SSTV16857MTD

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FAIRCHILD

SSTV16857MTDX

 Memory Driver

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ETC
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