SZA1000_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SZA1000

QIC digital equalizer

1998 Feb 16

Product speciﬁcation

File under Integrated Circuits, IC01

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

• Peak-to-peak amplitude detector with lowpass filter for

FEATURES

servo burst reading

• 3-wire serial interface for programming and status

• Fully digital PLL for clock and data recovery:

– Fully programmable behaviour

– No external components, no tolerance problems

– Programmable window shift

reading

• Suitable for MFM (Modified Frequency Modulation),

RLL 1,7 (Run Length Limited) and similar codes

• Transfer rates with MFM code from

250 kbits/s to 4 Mbits/s

– Fast run-in capability

• Transfer rates with RLL(1,7) code from

500 kbits/s to 12 Mbits/s

– Ideal zero phase restart.

• Parallel 8-bit input and output for product development

and production testing

• Programmable FIR (Finite Impulse-Response) filter

makes it possible to equalize complex and asymmetric

channel impulse responses

• Programmable WEQ (write equalization) circuit with

transfer rates of up to 2 Mbits/s for floppy tape drives

and up to 8 Mbits/s for drives with internal controllers.

• Programmable fixed and tracking qualification

thresholds provide reliable data recovery in read mode,

and reliable bad sector detection in verify mode

GENERAL DESCRIPTION

• Read pulse output for floppy tape drives

The SZA1000 is a single chip digital equalizer for single

channel QIC (Quarter Inch Cartridge) systems with

MR (Magneto Resistive) heads. It can be used with

QIC 3010, QIC 3020, QIC 3080, QIC 3095, Travan 2, 3, 4

and 5, and similar formats.

• Digital data synchronizer based on digital PLL with

maximum likelihood detector for a better error rate than

can be achieved with conventional analog circuits

• Data verification can be used (with the maximum

likelihood detector switched off) to find bad sectors on

drives with conventional read electronics

It replaces a pulse detector, programmable filter and data

synchronizer, and adds a FIR filter to the conventional

analog solution. This makes it possible to equalize

yoke-type MR heads as well as SIG (Sensor In Gap)

MR heads.

• Servo stripe detection for TR4, QIC3080 and similar

formats

• Gap detector

• 2 programmable current sources

QUICK REFERENCE DATA

SYMBOL

_DDD1; V_DDD2digital supply voltage

V_DDA1; V_DDA2analog supply voltage

PARAMETER

CONDITIONS

MIN.

4.5

TYP.

5.0

MAX.

5.5

UNIT

V

4.5

−

5.0

32

50

24

−

5.5

−

I

_DDD1; I_DDD2

_DDA1; I_DDA2

digital supply current

f_s= 24 MHz

mA

MHz

°C

I

analog supply current

−

f_clk(CLKIN)

f_clk(WEQCLK)

T_amb

read circuit clock frequency

WEQ circuit clock frequency

ambient operating temperature

−

24

36

70

−

0

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SZA1000H

QFP44

plastic quad ﬂat package; 44 leads (lead length 1.3 mm)

SOT307-2

body 10 × 10 × 1.75 mm

1998 Feb 16

2

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

PINNING

SYMBOL

DESCRIPTION

IO1

IO2

1

programmable current source

2

WEQEN

WGATE

V_DDD1

3

write equalization circuit enable input

write gate input; active LOW

digital supply voltage

4

5

CLKIN

6

external clock or crystal oscillator input

crystal oscillator output

CLKOUT

V_SSD1

7

8

digital ground

WEQCLK

WDIN

9

write equalization circuit clock input

write equalization circuit data input

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

AUXBUS0/WDOUT

AUXBUS1

AUXBUS2

AUXBUS3

AUXBUS4

AUXBUS5

AUXBUS6

AUXBUS7

LTD

bit 0 auxiliary I/O bus or write equalization output to write amplifier

bit 1 auxiliary I/O bus

bit 2 auxiliary I/O bus

bit 3 auxiliary I/O bus

bit 4 auxiliary I/O bus

bit 5 auxiliary I/O bus

bit 6 auxiliary I/O bus

bit 7 auxiliary I/O bus

fast lock to data input; active LOW

read gate input

RG

GAP/STRIPE

SDIO

gap or stripe detector output

serial interface data input and output

serial interface enable input

serial interface clock input

SDEN

SCLK

RRC

read reference clock output

digital supply voltage

V_DDD2

SRD/RD

V_SSD2

synchronized read data or read data output

digital ground

PACLK

RESET

TEST

pre-amp clock output

reset input; active LOW

test input; connect to ground

analog signal from read amplifier; positive input

analog signal from read amplifier; negative input

analog ground

INA

INB

V_SSA1

V_DDA1

analog supply voltage

WGX

extended write gate output for floppy tape drives; active LOW

positive A/D reference voltage input

connect external resistor

V_ref

R_ref

EYEA

differentiated signal; positive output

comparator for read pulse; positive input

CMPA

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

SYMBOL

V_SSA2

DESCRIPTION

41

42

43

44

analog ground

V_DDA2

CMPB

EYEB

analog supply voltage

comparator for read pulse; negative input

differentiated signal; negative output

handbook, full pagewidth

IO1

IO2

1

2

3

4

5

6

7

8

9

33 INB

32 INA

WEQEN

WGATE

31 TEST

30 RESET

29 PACLK

V

DDD1

SZA1000

CLKIN

28 V

SSD2

CLKOUT

27 SRD/RD

V

26 V

DDD2

SSD1

WEQCLK

25 RRC

24 SCLK

23 SDEN

WDIN 10

AUXBUS0/WDOUT 11

MGD794

Fig.2 Pin configuration.

5

1998 Feb 16

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

FUNCTIONAL DESCRIPTION

Clock oscillator and divider

Amplitude detector

This circuit has a separate rectifier and a positive and

negative peak detector.

The clock source for the SZA1000 can be a crystal

connected between pins 6 and 7, or an external clock

signal connected to pin 6. This clock frequency is divided

by a number programmable between 1 and 8

(see Tables 27 and 28). The resulting frequency, f_s, is

used as clock input to all on-chip circuits except the write

equalizer. The frequency of the PACLK output signal

(pin 29) is equal to f_s.

Typical rise time (0 to 70%) for a normal MFM or

1

RLL 1,7 code input signal is , typical decay time

---

f_s

500

f_s

400

---------

f_s

(100 to 30%) is programmable between

(see Tables 10 and 11).

and

---------

The output is an 8-bit number that can be polled via the

serial interface. In addition, the peak-to-peak value is

calculated and filtered by a first order low-pass filter with a

ADC

The 8-bit ADC has a differential input. The total ADC

conversion range is 1.6 V (p-p; differential). The ADC

sample rate is equal to f_s.

f _s

cut-off frequency of

------------

3217

High-pass ﬁlter after the ADC

Both the filtered and unfiltered amplitudes can be read via

the serial interface (see Table 44) or via the parallel output

bus.

f_s

This is a first order filter with a cut-off frequency of

It removes the DC component of the signal.

------------

1608

Amplitude qualiﬁer

Low-pass ﬁlter

A peak is considered valid if its amplitude is above a

qualification threshold. Separate qualification thresholds

are used for the positive and negative peaks. Each

threshold is the greater of:

This low-pass filter is an even symmetrical FIR (Finite

Impulse Response) filter. The number of taps depends on

the sample rate reduction factor R (see Tables 30 and 31).

The filter has 8 taps for R = 1 or 14 taps for R = 2 (see

Table 7). The middle taps have a fixed coefficient value of

+128, the coefficients of the other taps are programmable

in the range −128 to +127 (see Table 6).

• a programmable level (QUAL_FIX_ POS and

QUAL_FIX_NEG; control register addresses 24 and 25)

• a programmable fraction (¹⁄₂, ³⁄₈, ¹⁄₄, ¹⁄₈or 0;

see Tables 9 and 12) of the peak amplitude of the

incoming signal.

FIR

This transversal filter has 6 taps with the sample rate equal

to f_s(R = 1), or 11 taps with the sample rate equal to ¹⁄₂f_s

(R = 2). Tap 10 has a fixed coefficient value of +64, the

coefficients of the other taps are programmable between

−64 and +63 (see Table 2). The filter has 19 signal delay

sections. The position of each tap can be selected from a

subset of the 20 possible positions (see Tables 3 and 4).

Gap detector

When the peak-to-peak amplitude of the measured signal

is below a preset limit (GAP_THRESH; control register

address 28), the gap detector output is HIGH, otherwise

LOW (GAP output on pin 21 must be selected; see

Table 22).

Interpolator

If a sample rate of ¹⁄₂f_shas been selected for the FIR

(R = 2), it is increased once again to f_sat the interpolator.

1998 Feb 16

6

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Stripe detector

The maximum likelihood detector

This circuit is used to signal the stripes in QIC 3080,

QIC 3095 and TR4 servo formats (STRIPE output on

pin 21 must be selected; see Table 22). A frequency

detector counts the peaks above the qualification

threshold (see Table 29). An input signal containing

frequencies within ±25% of the programmable nominal

frequency will be detected as a stripe. The microcontroller

can then poll the amplitude of the following burst via the

serial interface.

This detector calculates the most likely position of the

peaks in the signal. It checks for (d,k) code constraints,

and for alternating peaks. If an error is detected, the ‘most

likely’ correction is implemented.

Separate corrections can be enabled or disabled.

The SRD output of the maximum likelihood detector is

valid during the rising edge of the RRC signal (see Fig.4).

The maximum likelihood detector is used only to generate

the SRD signal, and not to generate the time continuous

RD pulse.

Differentiator

This function is realized by subtracting samples. The delay

between samples is programmable between 1 and 6

periods of f_s, split into two parts to provide a balanced

delay between the differentiated and non-differentiated

signals (see Tables 24 to 26).

SRD

handbook, halfpage

The PLL

RRC

This is a fully digital PLL (Phase Lock Loop) with a

programmable nominal frequency (see Tables 35 and 36),

zero phase restart, programmable window shift

(WIN_SHIFT; control register address 42) and a loop filter

with two separate programmable settings.

MGG584

Fig.4 SRD/RRC timing.

The PLL output reference clock is the RRC signal (pin 25;

see Table 34). The frequency of this signal is rounded in

time to f_s. The PLL is switched to the nominal frequency if

RG (pin 20) is LOW, and makes a zero phase restart at the

first detected peak after RG goes HIGH.

The DAC

This is an internal differential 8-bit DAC operating at f_s.

The LPF after the DAC

The LTD input (pin 19) is used to select between the two

loop filter settings (see Tables 37 to 42). This allows for

fast lock-in during preamble, before switching to a lower

loop bandwidth for maximum data reliability (see Fig.3).

This analog LPF filters the time quantized signal from the

DAC to retain a time continuous signal. This provides more

accurate timing of the detected zero crossings in the RD

pulse output.

The LPF is a second order active filter with a cut-off

frequency of 8 MHz.

INPUT

SIGNALS

The read pulse circuit

handbook, halfpage

preamble

data

A peak in the equalized signal at the interpolator output

generates a read pulse. The peak is detected if a zero

crossing occurs in the filtered signal after the DAC while

the non-differentiated signal is above the qualification

threshold.

RG

LTD

zero phase restart

fast lock-in

nominal

frequency

PLL

MODE

normal read mode

Uncommitted current sources

MGG583

Two uncommitted 5-bit programmable current sink DACs

(0 to 2 mA) are available as IO1 and IO2 (see Table 20 for

programming). These could be used, for example, to drive

the tape hole detector circuit.

Fig.3 PLL timing diagram.

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

For QIC 3010 or 3020, the recording signal is typically

generated by a circuit that uses a separate crystal.

An input buffer with variable delay is used to prevent errors

occurring in the recorded signal. This buffer is set to its

nominal position when writing begins.

Parallel state bus

All internal digital signals can be monitored via an 8-bit

parallel bus. An external DAC or an evaluation tool such as

a phase error logger for TIA (Time Interval Analyzer),

drop-out and symmetry measurements can be connected

to this bus for evaluation purposes (see Table 34).

Signals longer than a data block can be recorded during

formatting. To avoid overloading the time buffer, the circuit

can resynchronize automatically during gaps in the

QIC 3010 or 3020 format.

Write equalization

This circuit has an independent clock input WEQCLK at

pin 9.

Serial interface

Write equalization can be programmed to conform to a

number of formats including QIC 3010, QIC 3020,

QIC 3080, QIC 3095, QIC 5010, Travan 2, Travan 3 and

Travan 4.

The serial interface uses 8-bit addresses and 8-bit data.

Its timing is shown in Fig.5. IC mode settings, filter

coefficients, scale factors and thresholds can be loaded

via the serial interface.

This is achieved by programming the circuit to divide a

channel bit-cell into 2, 3 or 6 time slots (see Tables 13

and 14). The external WEQ clock frequency should be

selected such that an integer number of between 1 and 8

clock periods fits in a time slot (see Tables 18 and 19).

Measured signal amplitude, for example Burst level

measurement at QIC 3095 or AGC control by the

microcontroller, and the actual PLL frequency can be read

via the serial interface. To read data from the status

registers, hex address FF must be transmitted along with

the required data code. The IC will then respond with the

contents of the appropriate 8-bit status register

(see Table 44).

The width and position of the inserted write pulse can be

programmed (see Tables 15 to 17).

The write equalization circuit input and output signals can

be independently programmed to be in either WD or WDI

format (see Table 15).

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

CONTROL REGISTER

Control register settings

The control register is accessible through the serial interface and contains 46 8-bit entries as shown in Table 1.

Table 1 Control register

ADDRESS

NAME

DESCRIPTION

0

FIR_VAL0

FIR_VAL1

FIR tap 0 coefficient value (see Table 2)

FIR tap 1 coefficient value

1

2

FIR_VAL2

FIR tap 2 coefficient value

3

FIR_VAL3

FIR tap 3 coefficient value

4

FIR_VAL4

FIR tap 4 coefficient value

5

FIR_VAL5

FIR tap 5 coefficient value

6

FIR_VAL6

FIR tap 6 coefficient value

7

FIR_VAL7

FIR tap 7 coefficient value

8

FIR_VAL8

FIR tap 8 coefficient value

9

FIR_VAL9

FIR tap 9 coefficient value

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

FIR_SEL05

FIR_SEL16

FIR_SEL27

FIR_SEL38

FIR_SEL49

FIR_SEL10

FIR_SHIFT

LPF_VAL1

LPF_VAL4

LPF_VAL2

LPF_VAL5

LPF_VAL3

LPF_VAL6

LPF_SHIFT

QUAL_FIX_POS

QUAL_FIX_NEG

QUAL_VAR_GAIN

QUAL_SLOPE_DEL

GAP_THRESH

WEQ_SET0

WEQ_SET1

WEQ_CLK_DIV

−

FIR tap positions (see Tables 3 and 4)

FIR tap positions

FIR output scaling (see Table 5)

LPF tap coefficient value (see Table 6)

LPF tap coefficient value

LPF output scaling (see Table 8)

Amplitude qualifier positive fixed qualification threshold

Amplitude qualifier negative fixed qualification threshold

Amplitude qualifier variable gain factors (see Tables 9 and 12)

Amplitude detector slope qualification delay (see Table 10)

Gap detector fixed threshold

WEQ settings (see Tables 13 and 14)

WEQ settings (see Tables 15, 16 and 17)

WEQ clock divider (see Tables 18 and 19)

not used

IDAC1

IO1 DAC current (see Table 20)

IO2 DAC current (see Table 20)

IDAC2

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

ADDRESS

NAME

DESCRIPTION

35

EQ MODE0

Mode setting for PACLK (pin 29) and GAP/STRIPE (pin 21)

(see Tables 21, 22 and 23)

36

37

38

39

40

41

42

43

44

45

DIFF

differentiator settings (see Tables 24, 25 and 26)

main clock divider (see Tables 27 and 28)

stripe detector nominal frequency (see Table 29)

equalizer mode settings

CLK_DIV

STRIPE_F

EQ_MODE1

PLL_FREQL

PLL_FREQH

WIN_SHIFT

PLL_NI

PLL nominal frequency bits 0 to 7

PLL nominal frequency bits 8 to 10

PLL window shift

PLL loop filter integrating gain and range

PLL loop filter proportional gain

PLL_NP

MLD_SET

maximum likelihood detector settings

Control register functions

Control register functions are detailed in Tables 2 to 43.

FIR FUNCTION

Addresses 0 to 9: FIR tap coefﬁcient values

Table 2 Coefﬁcient values: FIR_VAL0 to FIR_VAL9; note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

FIR_VALn.6

FIR_VALn.5 FIR_VALn.4 FIR_VALn.3 FIR_VALn.2 FIR_VALn.1 FIR_VALn.0

Note

1. These are 7-bit coefficient values in two’s complement notation; taps 5 to 9 are only used when R = 2; tap 10 has a

fixed coefficient value of +64.

Addresses 10 to 15: FIR tap position selection

Table 3 Tap position selection: FIR_SELnn; note 1

ADDR.

NAME

TAPS

D7

D6

D5

D4

D3

D2

D1

D0

10

11

12

13

14

15

FIR_SEL05

FIR_SEL16

FIR_SEL27

FIR_SEL38

FIR_SEL49

FIR_SEL10

0 and 5

1 and 6

2 and 7

3 and 8

4 and 9

10

−

FS0.2 FS0.1 FS0.0 FS5.2 FS5.1 FS5.0

FS1.2 FS1.1 FS1.0 FS6.2 FS6.1 FS6.0

FS2.2 FS2.1 FS2.0 FS7.2 FS7.1 FS7.0

FS3.2 FS3.1 FS3.0 FS8.2 FS8.1 FS8.0

FS4.2 FS4.1 FS4.0 FS9.2 FS9.1 FS9.0

−

FS10.3 FS10.2 FS10.1 FS10.0

Note

1. See Table 4 for the value of FSn.n.

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Table 4 Translation table: FS selection bits (FSn.n from Table 3) to tap position

FSn

TAP 0,5

TAP 1,6

TAP 2,7

TAP 3,8

TAP 4,9

TAP 10

0

1

12

13

14

15

16

17

18

19

−

9

10

11

12

13

14

15

16

−

6

7

3

4

0

1

2

3

4

5

6

7

−

2

3

2

8

5

4

3

9

6

5

4

10

11

12

13

−

7

6

5

8

7

6

9

8

7

10

−

9

8

10

11

12

13

14

15

16

17

9

−

10

11

12

13

14

15

−

Address 16: FIR output scaling

Table 5 Output scaling: FIR_SHIFT

FIR_SHIFT (BINARY)

FIR OUTPUT SCALING GAIN FACTOR

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

1

2

4

8

16

32

64

128

LOW-PASS FILTER FUNCTIONS

Addresses 17 to 22: LPF tap coefﬁcient values

Table 6 Coefﬁcient value: LPF_VAL1 to LPF_VAL6; notes 1 and 2

D7 D6 D5 D4 D3

D2

D1

D0

LPF_VALn.7 LPF_VALn.6 LPF_VALn.5 LPF_VALn.4 LPF_VALn.3 LPF_VALn.2 LPF_VALn.1 LPF_VALn.0

Notes

1. These are 8-bit coefficient values in two’s complement notation; taps 4 to 6 are only used when R = 2.

2. See Table 7 for the values of LPF_VALn.n

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Table 7 LPF tap positions

TAP POSITION

COEFFICIENT VALUES R = 1

COEFFICIENT VALUES R = 2

0

1

LPF_VAL3

LPF_VAL6

LPF_VAL5

LPF_VAL4

LPF_VAL3

LPF_VAL2

LPF_VAL1

+128

LPF_VAL2

2

LPF_VAL1

3

+128

4

+128

5

LPF_VAL1

6

LPF_VAL2

7

LPF_VAL3

+128

8

0

LPF_VAL1

LPF_VAL2

LPF_VAL3

LPF_VAL4

LPF_VAL5

LPF_VAL6

9

10

11

12

13

Address 23: LPF output scaling

Table 8 Output scaling: LPF_SHIFT

LPF_SHIFT (BINARY)

LPF OUTPUT SCALING GAIN FACTOR

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

1

2

4

8

16

32

64

128

AMPLITUDE QUALIFIER/DETECTOR FUNCTIONS

Address 24: QUAL_FIX_POS and Address 25: QUAL_FIX_NEG

QUAL_FIX_POS and QUAL_FIX_NEG contain the positive and negative fixed threshold (8-bit signed) values.

Address 26: Variable gain factors

Table 9 Gain factors: QUAL_VAR_GAIN; note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

GP.2

GP.1

GP.0

GN.2

GN.1

GN.0

Note

1. GP and GN set the factors of the measured amplitude that are to be used as variable qualifier thresholds: GP for the

positive peaks and GN for the negative peaks.

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Address 27: Amplitude detector slope qualiﬁcation delay

Table 10 Qualiﬁcation delay: QUAL_SLOPE_DEL; notes 1 and 2

D7

D6

D5

D4

D3

D2

D1

SL.1

D0

−

DEL.1

DEL.0

SL.0

Notes

1. DEL is the programmable compensation delay, in cycles of f_s, between the qualifier and the analog zero crossing of

the read pulse circuit; DEL is a 2-bit unsigned value

2. SL selects the decay time of the amplitude detectors.

500

Table 11 Amplitude detector decay time

---------

f_s

Table 12 Variable qualiﬁer threshold

SL

DECAY TIME

GP, GN

VARIABLE THRESHOLD

0

500

---------

f_s

1

⁄

8

⁄

4

⁄

8

⁄

2

1

3

1

2

3

1

2

3

1000

------------

f_s

4, 5, 6, 7

2000

------------

f_s

4000

------------

f_s

GAP DETECTOR FUNCTIONS

Address 28: Fixed threshold: GAP_THRESH

Fixed threshold for the gap detector; 8-bit signed value.

WRITE EQUALIZATION (WEQ) FUNCTIONS

Address 29: WEQ settings

Table 13 Time slots: WEQ_SET0; see Table 14

D7

D6

D5

D4

D3

D2

D1

D0

−

N6

N3

N2

Table 14 Time slots in channel bit cell

NUMBER OF TIME SLOTS

N6

N3

N2

2

3

6

0

1

0

1

0

1

0

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Address 30: WEQ settings

Table 15 WEQ_SET1; notes 1 to 4, see also Tables 16 and 17.

D7

D6

D5

D4

D3

D2

D1

TWS1

D0

WDI_O

WDI_I

RESYNC

TPS2

TPS1

TPS0

TWS0

Notes

1. If bit WDI_O is HIGH, the circuit output is a WD signal, else a WDI signal.

2. If bit WDI_I is HIGH, the circuit expects a WD signal at the input, else a WDI signal.

3. If the RESYNC bit is HIGH, the WEQ circuit resynchronizes its time buffer during a gap in the QIC 3010 or QIC 3020

format; this setting is only permitted if 6 time slots in a bit-cell are selected (N6 = 1; see Table 14).

4. TPS sets the position of the inserted write equalization pulse, TWS sets its width.

handbook, halfpage

WD

WDI

MGG586

Fig.6 WD/WDI signal timing.

1

0

1

handbook, halfpage

1 T

0

1

0

1.5 T

t

d

w

1

0

1

2 T, etc. to 4 T

MGG587

Fig.7 Position and width of write equalization pulse.

1998 Feb 16

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Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Table 16 Write equalization pulse position

Table 17 Write equalization pulse width

TPS

POSITION IN TIME SLOTS

TWS

WIDTH IN TIME SLOTS

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

0

1

2

3

WEQ off

1

2

3

Address 31: WEQ circuit clock divider

Table 18 Division factor: WEQ_CLK_DIV; note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

WCD.2

WCD.1

WCD.0

Note

1. WCD sets the division factor between WEQCLK and the frequency of the time slot.

Table 19 WEQ clock division

WCD

WEQ CLOCK DIVISION FACTOR

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

UNCOMMITTED CURRENT DAC FUNCTIONS

Addresses 33 and 34: Current DACs

Table 20 DAC current: IDAC1 and IDAC2; note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

IDn.4

IDn.3

IDn.2

IDn.1

IDn.0

Note

1. These are 5-bit unsigned numbers; the DAC current is

IDn

---------

16

mA.

1998 Feb 16

16

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

O/P SIGNAL FUNCTION: PINS 21 AND 29

Address 35: O/P Select pins 21 and 29

Table 21 Output signal select: EQ MODE 0; see Tables 22 and 23

D7

D6

D5

D4

D3

D2

D1

GAP.1

D0

−

PA.1

PA.0

GAP.0

Table 22 Output signal: pin 21

Table 23 Output signal: pin 29

GAP

OUTPUT SIGNAL ON PIN 21

PA

0

OUTPUT SIGNAL ON PIN 29

f_s- PACLK on

0

1

2

3

GAP⁽¹⁾

STRIPE

QUAL⁽²⁾

RD⁽³⁾

1

1 - PACLK off

2

0 - PACLK off

3

0 - PACLK off

Notes

1. GAP, STRIPE or QUAL may be selected to detect

gaps, stripes or valid signal peaks. All are active HIGH.

2. See also Table 34.

3. The RD output (read pulse): falling edge active.

DIFFERENTIATOR FUNCTIONS

Address 36: Differentiator settings

Table 24 DIFF; note 1

D7

D6

D5

D4

D3

DL2.1

D2

DL2.0

D1

D0

DL1.0

−

DS

DL1.1

Note

1. DL1 and DL2 are programmable delays for the differentiator; DS is the gain factor of the differentiated signal.

Table 25 Differentiator delay; notes 1 and 2

Table 26 Differentiator gain factor

DLn

DELAY IN f_sCYCLES

DS

0

OUTPUT SCALING GAIN FACTOR

0

1

2

3

0

1

2

3

4

2

1

Notes

1. DL1 and DL2 are added to provide a maximum delay

of 6 × f_scycles.

2. It is advisable to have DL1 and DL2 equal to avoid

adding unwanted delay in the differentiator.

1998 Feb 16

17

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

CLOCK FUNCTIONS

Address 37: Main clock divider

Table 27 Clock divider: CLK_DIV; note 1

D7

D6

D5

D4

D3

D2

D1

CD.1

D0

−

CD.2

CD.0

Note

1. CD selects the main clock division factor. The CLKIN frequency (pin 6) divided by this factor gives the IC’s operating

frequency f_s(apart from the WEQ circuit).

Table 28 Clock division factor

CD

0

CLOCK DIVISION

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

STRIPE DETECTOR FUNCTIONS

Address 38: Stripe detector nominal frequency

Table 29 Qualiﬁcation threshold: STRIPE_F; note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

SF.4

SF.3

SF.2

SF.1

SF.0

Note

1. SF is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. The nominal detection

f_s

frequency is

---------------------------------

3 × (SF + 1)

AUXBUS, PINS 25 AND 27, SAMPLE RATE REDUCTION AND STAND-BY FUNCTIONS

Address 39: Equalizer mode settings

Table 30 EQ_MODE 1; note 1, see also Tables 31 to 34

D7

D6

D5

D4

D3

D2

D1

D0

−

STBY2

ST.3

ST.2

ST.1

ST.0

STBY1

R1

Note

1. R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches;

ST selects output signal modes for pins 25 and 27.

1998 Feb 16

18

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Table 31 FIR/LPF Sample Rate

Table 33 ADC power

Table 32 DAC power

Reduction Factor: R

STBY2

A/D POWER

STBY1

D/A POWER

R1

0

R

2

0

1

on

off

0

1

on

off

1

Table 34 Mode settings: pins 25, 27 and AUXBUS

ST

IC MODE

PIN 27

PIN 25

AUXBUS

0

1

PLL off

RD

QUAL⁽¹⁾

COMP⁽²⁾

RRC

bit 0: WDOUT, bits 1 to 7 high-Z

ADC output

2

PLL on

SRD

RD

3

ADC test

RRC

4

DAC test

COMP

−

DAC output

5

one shot test

−

6

PLL off, AD bypass

PLL on, AD bypass

PLL on, LPF output

PLL on, FIR output

PLL on, PLL phase output

PLL on, PLL frequency output

PLL on, peak-to-peak level output

PLL on, ﬁltered level output

PLL on, differentiator output

RD

QUAL

COMP

RRC

8-bit input to HPF

7

RD

8-bit input to HPF

8

SRD

8-bit input to HPF

9

RRC

LPF output after scaling

FIR output after scaling and interpolator

PLL phase error output

PLL frequency output

10

11

12

13

14

15

RRC

bits 7 to 1: LEVEL_ABS; bit 0:WDOUT

bits 7 to 1: LEVEL_FIL; bit 0:WDOUT

differentiator output after scaling

RRC

Notes

1. QUAL is a test signal (active HIGH) used to detect valid signal peaks (see also Table 22).

2. When COMP is selected, pin 25 is switched to the output of the read pulse circuit comparator for test purposes.

PLL FUNCTIONS

Addresses 40 and 41: PLL nominal frequency

Table 35 PLL_FREQL (address 40)

D7

D6

D5

D4

D3

D2

D1

D0

PF.7

PF.6

PF.5

PF.4

PF.3

PF.2

PF.1

PF.0

Table 36 PLL_FREQH (address 41); note 1

D7

D6

D5

D4

D3

D2

D1

D0

−

PF.10

PF.9

PF.8

Note

PF

1. The nominal PLL frequency is f ×

------------

2048

s

1998 Feb 16

19

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Address 42: Phase comparator window shift

WIN_SHIFT is an 8-bit number in two’s complement format. The programmed phase shift is 180 × WIN_SHIFT degrees.

Address 43: PLL settings

Table 37 Address 43: PLL_NI; note 1

D7

D6

D5

D4

D3

D2

D1

D0

Q1

Q0

RNG.1

RNG.0

NI2.1

NI2.0

NI1.1

NI1.0

Note

1. If LTD (pin 19) is HIGH, NI2 is selected, else NI1.

Table 38 DL setting; note 1

DL SETTING

Q1

Q0

DL1 = DL2

DL1 < DL2

DL1 > DL2

1

0

1

0

1

Note

1. The Differentiator Delay (DL) settings (see Table 25) determine the values of Q1 and Q0 that should be entered.

Table 39 Integrating gain factor KI

Table 40 PLL range

NI

0

KI

RNG

PLL RANGE

1

⁄

0

1

2

3

±64

64

1

⁄

±128

±256

±512

128

256

512

2

3

Address 44: PLL loop ﬁlter proportional gain

Table 41 PLL_NP; note 1

D7

D6

D5

D4

D3

D2

NP1.2

D1

NP1. 1

D0

−

NP2.2

NP2.1

NP2.0

NP1. 0

Note

1. If LTD (pin 19) is HIGH, NP2 is selected, else NP1.

1998 Feb 16

20

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Table 42 Proportional gain factor KP

NP

KP

0

1

2

3

4

5

6

7

1

⁄

2

1

⁄

4

8

1

⁄

16

32

1

−

MAXIMUM LIKELIHOOD DETECTOR FUNCTIONS

Address 45: Settings

Table 43 Address 45: MLD_SET

D7

D6

D5

D4

D3

D2

D1

ks1⁽⁵⁾

D0

en_k⁽¹⁾

en_d⁽²⁾

PR1⁽³⁾

PR0⁽⁴⁾

ks3⁽⁵⁾

ks2⁽⁵⁾

ks0⁽⁵⁾

Notes

1. Check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. For MFM code:

k = 3 (ks = 4), for RLL(1,7) code: k = 7 (ks = 8).

2. Check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between

two bit cells with transitions. d = 1 for both MFM and RLL(1,7) codes

3. Check partial response constraints; delete incorrect peaks.

4. Check partial response constraints; add missing peaks.

5. ks = k + 1.

STATUS REGISTER

The status register contains 5 status bytes. The contents of the status bytes can be read via the serial interface.

Table 44 Status bytes; notes 1 to 4

ADDRESS

255

DATA

NAME

DESCRIPTION

0

1

2

3

4

FREQ

actual frequency of PLL

255

LEVEL_POS

LEVEL_NEG

LEVEL_ABS

LEVEL_FIL

positive peaks in measured level

negative peaks in measured level

measured peak-to-peak level

low-pass filtered LEVEL_ABS

255

Notes

1. The levels are measured behind the re-sampling block (interpolator) (see Fig.1).

FREQ

2. Actual PLL frequency is an 8-bit unsigned number: f ×

-----------------

256

s

3. LEVEL_FIL can be used for reading of the burst levels, or in an AGC loop (with the TZA1000 preamplifier).

4. LEVEL_POS, LEVEL_NEG, LEVEL_ABS and LEVEL_FIL are 8-bit numbers in two’s complement format.

1998 Feb 16

21

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

V_DDD1

PARAMETER

digital supply voltage

CONDITIONS

MIN.

−0.3

MAX.

+5.5

UNIT

V

V_DDD2

V_DDA1

V_DDA2

V_i

digital supply voltage

analog supply voltage

input voltage

−0.3

−50

−10

−

+5.5

V_DD+ 0.3 V

I_I

input current on supply pins

input current on remaining pins

maximum total power dissipation

ambient temperature

+50

mA

I_I(n)

+10

P_tot

+1100

+85

mW

°C

V

T_amb

T_j

−30

−50

−3000

−300

junction temperature

+125

+150

+3000

+300

T_stg

storage temperature

V_ES(HB)

V_ES(MM)

electrostatic handling: human body model note 1

electrostatic handling: machine model note 2

V

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistance.

2. Equivalent to discharging a 200 pF capacitor through a 25 Ω series resistance and a 2.5 µH series inductance.

THERMAL CHARACTERISTICS

SYMBOL

R_th(j-a)

PARAMETER

CONDITIONS

VALUE

UNIT

thermal resistance from junction to ambient in free air

70

K/W

QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-E”.

1998 Feb 16

22

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

CHARACTERISTICS

V

_DDD1= V_DDD2= V_DDA1= V_DDA2= 5 V ±5%; f_s= f_clk(CLKIN)= 24 MHz; V_ref= 2 V ±5%; R_ref= 10 kΩ, unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

5.0

MAX.

UNIT

V_DDD1

V_DDD2

V_DDA1

V_DDA2

digital supply voltage

analog supply voltage

digital supply current

analog supply current

4.5

−

5.5

80

V

5.0

32

V

I

_DDD1; I_DDD2

_DDA1; I_DDA2

r = 2, no WEQ

mA

I

STBY1 = 0;

STBY2 = 1;

see Table 30

−

50

65

STBY 1= 1;

STBY2 = 0

−

26

35

mA

f_clk(CLKIN)

read circuit clock frequency

−

24

36

MHz

f_clk(WEQCLK)

WEQ circuit clock frequency N6 = 0;

see Table 14;

−

(3080; 3095)

V_IL

V_IH

V_OL

V_OH

C_i

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

HIGH-level output voltage

input capacitance

−

0.3V_DD

V

0.7V_DD

−

V

I_o= −4 mA

−

0.5

−

V

I_o= +4 mA

V

_DD− 0.5

V

I/O pins high-Z;

note 1

−

5

pF

Analog section

V_ref

reference voltage (pin 37)

reference current (pin 37)

A/D conversion range

A/D common mode voltage

A/D input resistance

1.8

1.0

−

2.0

1.7

1.6

2.5

3.3

3

2.2

2.1

−

V

I_ref

mA

V

V_cnv(A/D)

V_CM(A/D)

R_i(A/D)

C_i(A/D)

I_I(32)

2

3

V

2.3

−

4.4

5

kΩ

pF

mA

V

A/D input capacitance

DC input current (INA)

DC input current (INB)

voltage on pin 38 (R_ref)

−

0.42

0.13

2.0

0.0

0.6

0.2

−

I_I(33)

−

V₃₈

−

I_O(1)

output current on pin 1 (IO1) IDAC1 = 0;

see Table 20

−

0.05

mA

IDAC1 = 31

1.40

1.95

0.0

2.60

0.05

mA

I_O(2)

output current on pin 2 (IO2) IDAC2 = 0;

see Table 20

−

IDAC2 = 31

1.40

1.5

1.95

1.72

2.60

1.8

mA

V

V_o(dif)

D/A differential output range note 2

(peak-to-peak)

V_CM(D/A)

D/A common mode voltage note 2

1.0

1.16

1.4

V

1998 Feb 16

23

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

f_{−3dB(cutoff)(LPF)}

−3dB cut-off frequency,

note 2

−

8

−

MHz

analog LPF (DAC ﬁlter)

V_CM(COMP)

comparator common mode

voltage

note 3

1.0

1.16

1.4

V

R_i(COMP)

comparator input resistance note 4

17

26

35

45

kΩ

V_IO(COMP)

comparator offset voltage

note 4

−

mV

Serial interface

f_clk(SIO)

t_su(D-CLK)

t_h(D-CLK)

t_d(1)

serial i/f clock

−

¹⁄₄f_s

−

MHz

ns

set-up time: data-to-clock

hold time: data-to-clock

delay clock: new data

delay clock: old data

10

note 5

t_s+ 10

−

ns

2t_s+ 10

ns

t_d(2)

t_s

−

ns

t_su(EN-CLK)

t_h(EN-CLK)

Digital read section

set-up time: enable-to-clock

t_s+ 10

ns

hold time: enable-to-clock

ns

t_CLKINH

t_CLKINL

t_RDL

CLKIN HIGH time

15

t_s

−

ns

CLKIN LOW time

RD LOW time

−

2t_s+ 10

t_su(SRD-RRC)

set-up time: SRD-to-RRC

note 6

t

_CLKINL− 5

− 0.2C_o(L)(SRD)

_CLKINH− 2

− 0.2C_o(L)(RRC)

_CLKINL− 5

t_CLKINL+ 2

− 0.2C_o(L)(RRC)

t_h(SRD-RRC)

t_RRCL

hold time: SRD-to-RRC

RRC LOW time

t

−

ns

t

t_CLKINL

−

− 0.2C_o(L)(RRC)

t_{su(AUX-CLKIN)}

t_h(AUX-CLKIN)

t_PACLKH

input set-up time:

AUXBUS-to-CLKIN (pin 6)

−

input hold time:

AUXBUS-to-CLKIN (pin 6)

−

PACLK HIGH time

note 7

t

_CLKINH− 2

− 0.2C_o(L)(PACLK)

_CLKINL− 5

t_CLKINH

t_CLKINL

t_PACLKL

PACLK LOW time

note 7

t

− 0.2C_o(L)(PACLK)

t_d(AUX-PACLK)

t_d(PACLK-AUX)

delay:

note 8

−

10 +

0.2C_o(L)(AUX)

AUXBUS-to-PACLK (pin 29)

delay: PACLK to AUXBUS

notes 7 and 8

−

5 +

0.2C_o(L)(PACLK)

1998 Feb 16

24

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Write equalization section

f_clk(WEQ)

WEQ clock frequency

N2 = 1 or N3 = 1;

see Table 14

−

36

24

MHz

N6 =1;

24

see Table 14

t_WEQL

WEQ LOW time

WEQ HIGH time

10

5

−

ns

t_WEQH

t_{su(WD-WEQCLK)}

setup time:

WDIN-to-WEQCLK

N2 = 1 or N3 = 1;

see Table 14

t_h(WD-WEQCLK)

t_IL(WDIN)

hold time: WD-to-WEQCLK N2 = 1 or N3 = 1; 10

see Table 14

−

ns

%

WDIN input LOW time (WDI WDI_I = 0;

10

mode)

see Table 15

t_OL(WDOUT)

WDOUT output LOW time

(WDI mode)

note 9

t

_WEQH− 2−0.2×

C_o(L)(WDOUT)

0.5

t_WEQH

∆f_{o(WDIN-WEQCLK)}frequency offset

N6 = 1;

−

WDIN-WEQCLK

see Table 14

Notes

1. Pins 3, 4, 6, 9 to 20, 22, 23, 24, 30 and 31.

2. Measured at pins 39 and 44 with a 10 MΩ/15 pF load.

3. Measured at pins 40 and 43.

4. Differential pins 40 and 43.

1

f_s

5. t_s

=

---

6. C_o(L)(SRD)is the external load (pF), at SRD (pin 27) for C_o(L)(SRD)< 50 pF.

C_o(L)(RRC)is the external load (pF), at RRC (pin 25) for C_o(L)(RRC)< 50 pF.

7. C_o(L)(PACLK)is the external load (pF), at PACLK (pin 29) for C_o(L)(PACLK)< 50 pF.

8. C_o(L)(AUX)is the external load (pF), at AUX0 to AUX7 (pins 11 to 18) for C_o(L)(AUX)< 50 pF.

9. C_o(L)(WDOUT)is the external load (pF), at WDOUT (pin 11) for C_o(L)(WDOUT)< 50 pF.

1998 Feb 16

25

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

Digital read section

t

handbook, full pagewidth

su(SRD-RRC)

t

h(SRD-RRC)

SRD

RRC

t

h(AUX-CLKIN)

t

su(AUX-CLKIN)

t

CLKINH

CLKINL

CLKIN

AUX0 to 7

INPUT

t

d(AUX-PACLK)

t

d(PACLK-AUX)

t

PACLKH

PACLKL

PACLK

AUX0 to 7

OUTPUT

MGG657

Fig.9 Digital read section showing set-up, hold and delay timing.

Write equalization section

t

handbook, full pagewidth

WEQH

t

WEQL

WEQCLK)

t

su(WD-WEQCLK)

t

h(WD-WEQCLK)

t

IL(WDIN)

WDIN

(WDI mode)

WDIN

(WD mode)

t

OL(WDOUT)

WDOUT

(WDI mode)

MGG658

Fig.10 WEQ section showing set-up and hold timing.

1998 Feb 16

27

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

y

X

A

33

23

34

22

Z

E

e

H

E

A

2

A

(A )

3

A

1

w

M

θ

b

p

L

p

pin 1 index

L

12

44

detail X

1

11

w

M

Z

v

M

A

D

b

p

e

D

B

H

v

M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

10^o

0^o

0.25 1.85

0.05 1.65

0.40 0.25 10.1 10.1

0.20 0.14 9.9 9.9

12.9 12.9

12.3 12.3

0.95

0.55

1.2

0.8

1.2

0.8

mm

2.10

0.25

0.8

1.3

0.15 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

97-08-01

SOT307-2

1998 Feb 16

28

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

If wave soldering cannot be avoided, for QFP

packages with a pitch (e) larger than 0.5 mm, the

following conditions must be observed:

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves

downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011).

Reﬂow soldering

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

Reflow soldering techniques are suitable for all QFP

packages.

6 seconds. Typical dwell time is 4 seconds at 250 °C.

The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or

vapour phase heating is used and the large packages are

not absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our “Quality

Reference Handbook” (order code 9397 750 00192).

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320 °C.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 50 and 300 seconds depending on heating

method. Typical reflow peak temperatures range from

215 to 250 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP

packages with a pitch (e) equal or less than 0.5 mm.

1998 Feb 16

29

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

1998 Feb 16

30

Philips Semiconductors

Product speciﬁcation

QIC digital equalizer

SZA1000

NOTES

1998 Feb 16

31

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,

Fax. +43 160 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Belgium: see The Netherlands

Brazil: see South America

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Colombia: see South America

Czech Republic: see Austria

Slovakia: see Austria

Slovenia: see Italy

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 0044

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615800, Fax. +358 9 61580920

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 488 3263

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Uruguay: see South America

Vietnam: see Singapore

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Middle East: see Italy

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA57

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545102/00/01/pp32

Date of release: 1998 Feb 16

Document order number: 9397 750 01122


型号：	SZA1000
厂家：	NXP
描述：	QIC digital equalizer QIC数字均衡器
文件：	总32页 (文件大小：168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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