TDA18211HDC2_技术文档

TDA18211HD

DVB-T Silicon Tuner IC

Rev. 05 — 2 June 2009

Product data sheet

1. General description

The TDA18211HD is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV

reception. The TDA18211HD integrates the overall tuning function, including selectivity,

and provides a low-IF output signal.

The TDA18211HD uses integrated IF ﬁlters to support 6/7/8 MHz channel bandwidths.

The TDA18211HD requires only one single 16 MHz crystal for clock generation. A clock

signal is available on crystal oscillator output pins (XTOUTP/XTOUTN) to synchronize the

channel decoder and slave front end in case of DVR conﬁguration.

This speciﬁcation is based on software version 3.4

2. Features

I Fully integrated RF tracking ﬁlters for unwanted signal suppression

I Fully integrated IF selectivity (no need for external SAW ﬁlters)

I Fully integrated oscillators with no external components

I Integrated wideband gain control

I Alignment free

I RF loop-through for easy implementation in the STB

I Input power level indicator

I Integrated die thermal sensor

I Single 3.3 V power supply

I Low power consumption (780 mW)

I Crystal oscillator output buffer (16 MHz) to allow single crystal applications

I I²C-bus interface compatible with 3.3 V and 5 V microcontrollers

I Three Standby modes

I RoHS packaging

3. Applications

3.1 Target applications

I DVB-T Set-Top-Box (STB) and TV receiver

I Application optimization is described in the application notes

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

3.2 Key beneﬁts

I The TDA18211HD is a low cost Silicon Tuner targeting digital terrestrial applications.

The TDA18211HD matches the performance of the conventional can tuners while

reducing the size of the tuner function drastically. Additionally, the following beneﬁts

can be stated:

N Allows easy on-board integration

N Allows easy dual-tuner conﬁguration

N Drastically reducing the size of the tuner function and power consumption

4. Quick reference data

Table 1.

Quick reference data

T_amb= 25 °C; V_CC= 3.3 V; IF output level option = 2 V (p-p); IF output load = 1 kΩ on each terminal.

Symbol Parameter

Conditions

Min

Typ

-

Max Unit

f_RF

RF frequency

center of channel

maximum gain

174

864

MHz

dB

NF_tun

ϕ_n

tuner noise ﬁgure

phase noise

-

5.5

−89

780

103

6

-

dBc/Hz

mW

P

power dissipation

-

V_i(max)

maximum input

voltage

1 dB gain compression, one

analog TV signal at RF input

(−5 dBm)

-

dBµV

α_image

image rejection

digital sensitivity

53

-

65

-

dB

[1]

S_dig

DVB-T (64 QAM ²⁄₃);

BER = 2.10⁻⁴

−82

dBm

[1] Measured with TDA10048HN channel decoder.

5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

SOT903-1

TDA18211HD/C2 HLQFN64R plastic thermal enhanced low proﬁle quad ﬂat

package; no leads; 64 terminals; resin based;

body 9 × 9 × 1.6 mm

TDA18211HD_5

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6. Block diagram

AGC CONTROL

DVB-T Silicon Tuner IC

DC-to-DC

DIGITAL

CONVERTER

CIRCUITRY

LC

tracking

filters

RF

polyphase

filter

IF

polyphase

filter

low-pass

filter

IF

AGC

LNA

10

mixer

45

IFOUTN

IFOUTP

RF_IN

ATTENUATORS

AGC2

46

47

RF

AGC

AGC1

V_IFAGC

FREEZE

15

13

STO

LT

28

DUAL TUNER

PROTOCOL

19

MASTERSYNC

TEST SIGNAL

GENERATOR

DIVIDER

TDA18211HD

crystal

oscillator

VCO

CONTROL

INTERFACE

CALIBRATION

SYNTHESIZER

MAIN

SYNTHESIZER

32

38

39

35

34

26

27

XTALN

24

22

21

VT_CAL

CP_CAL

XTALP

CP_LO

VT_COARSE

001aag932

AS SCL SDA

VT_FINE

Fig 1. Block diagram

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DVB-T Silicon Tuner IC

7. Pinning information

7.1 Pinning

terminal 1

index area

GND

n.c.

1

2

3

4

5

6

7

8

9

48 GND

47 V_IFAGC

46 IFOUTP

45 IFOUTN

44 VCC

43 GND

42 CAPREG28

41 GND

TDA18211HD

VCC

40 CAPREG18

39 SDA

RF_IN 10

GND 11

38 SCL

CAPRFAGC 12

LT 13

37 GND

36 GND

GND 14

35 VT_CAL

34 CP_CAL

33 VCC

STO 15

VCC 16

Transparent top view

001aaf832

Fig 2. Pin conﬁguration

7.2 Pin description

Table 3.

Pin description

Symbol

GND

1 to 7

8

Description

ground

n.c.

not connected

VCC

9

3.3 V supply voltage

unbalanced RF (TV) input

ground

RF_IN

GND

10

11

12

13

CAPRFAGC

LT

RF AGC ﬁltering

loop-through output

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Table 3.

Pin description …continued

Symbol

GND

14

15

16

17

18

19

Description

ground

STO

slave tuner output

3.3 V supply voltage

VCO supply decoupling

3.3 V supply voltage

VCC

CAPREGVCO

VCC

MASTERSYNC

synchronization signal for dual-tuner applications; leave open for

single-tuner applications

CAPFILTVCO

VT_COARSE

VT_FINE

GND

20

21

22

23

24

25

26

27

28

VCO reference decoupling

LO oscillator tuning voltage input

ground

CP_LO

charge pump of the local synthesizer

ground

GND

XTALP

crystal oscillator input

XTALN

FREEZE

synchronization signal for multi-tuner applications; leave open for

single-tuner applications

XTOUT_MS

XTOUTP

XTOUTN

AS

29

XTOUT mode and master/slave selection input

crystal oscillator output buffer

I²C-bus address selection input

3.3 V supply voltage

30

31

32

VCC

33

CP_CAL

VT_CAL

GND

34

charge pump of the calibration synthesizer

tuning voltage of the calibration synthesizer

ground

35

36, 37

38

SCL

I²C-bus clock input

SDA

39

I²C-bus data input/output

internal regulator decoupling

ground

CAPREG18

GND

40

41

CAPREG28

GND

42

internal regulator decoupling

ground

43

VCC

44

3.3 V supply voltage

IFOUTN

IFOUTP

V_IFAGC

GND

45

IF output

46

IF output

47

IF gain control input

48 to 50

51

ground

VSYNC

vertical synchronization input for analog applications; connect to

ground for digital applications

CAPREGFILTRF 52

internal regulator decoupling

GND

-

53 to 64

ground

exposed

die

TDA18211HD_5

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TDA18211HD

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DVB-T Silicon Tuner IC

8. Functional description

The RF input signal is driven to a low-noise ampliﬁer. It is then band-pass ﬁltered,

ampliﬁed and fed to the image rejection mixer. The mixer downconverts the RF signal to a

low IF, which depends on channel bandwidth (standard IF ﬁlters are implemented for

6/7/8 MHz channel bandwidths; see Table 41).

The gain between the antenna pin (pin RF_IN) and the loop-through pin (pin LT) is 0 dB.

The TDA18211HD requires a single 16 MHz crystal for clock generation.

When bit XTOUT_ON = 1, a differential sine wave clock reference is available on pins

XTOUTP and XTOUTN to drive a channel decoder.

8.1 Master and slave operation

The TDA18211HD allows easy dual-tuner conﬁguration.

Each individual tuner has to be set either in Master mode or Slave mode by applying a DC

voltage on the XTOUT_MS pin; see Table 4. This will decide whether the crystal oscillator

part is used as negative impedance connected to the crystal part or as a current buffer.

Table 4.

Master and slave selection

Voltage on pin XTOUT_MS

0 V to 0.1V_CC

Tuner type

master

Crystal oscillator

negative impedance presented to the crystal

current input buffer

0.4V_CCto 0.6V_CC

slave

In dual-tuner application:

• The ﬁrst tuner is set in Master mode

• The second tuner has to be set in Slave mode

In single-tuner application:

• The tuner must be set in Master mode.

8.2 Tuner outputs

The tuner provides a slave tuner output (pin STO) and a loop-through output (pin LT).

Those outputs are used to transmit the antenna signal to other tuners. Each output has its

own characteristics (see Table 56 and Table 57)

8.2.1 Loop-through output

The gain between the antenna connector and the loop-through pin (pin LT) equals 0 dB.

This pin can be connected to any consumer electronic equipment.

8.2.2 Slave tuner output

The slave tuner output (pin STO) must be connected to the RF input of the slave tuner

TDA18211HD in case of dual-tuner applications.

The gain between the antenna connector and the slave tuner output can change

according to the input level. The slave tuner will automatically compensate the gain

change, using the MASTERSYNC and FREEZE signals.

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8.3 Crystal input mode

The TDA18211HD requires a 16 MHz crystal reference. The chosen crystal must

withstand at least 100 µW drive level. An additional shunt capacitor as shown in Figure 1

is also needed. Its typical value is 5.6 pF. The quartz references for which performance is

guaranteed are:

• NDK NX5032

• Siward SX-5032

• TXC 9C series

• Chungho Elcom HC49/S proﬁle

Clock reference:

• In Master mode, the clock reference must be provided by a 16 MHz crystal connected

between pins XTALP and XTALN of the master tuner

• In Slave mode, the clock reference must be provided by pins XTOUTP and XTOUTN

of the tuner in Master mode to pins XTALP and XTALN of the tuner in Slave mode

8.4 Crystal output mode

Pins XTOUTP and XTOUTN deliver a symmetrical sine waveform to drive the channel

decoder and/or IF demodulator. The load on both outputs should be made similar to

ensure optimum performances. Hence, if only one crystal output is used, the unused

output should be loaded by an equivalent capacitance.

9. Control interface

9.1 I²C-bus format, write/read mode

Remark: In I²C-bus read mode, the TDA18211HD must read the entire I²C map with the

required subaddress 00h. The number of bytes to be read is 16, or 39 in extended register

mode; see Table 7. Reading write-only bits can return values that are different from the

programmed values.

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9.2 I²C-bus at power-on reset

Table 6.

Name

I²C-bus at power-on reset^[1]

Byte

Subaddress

Bit

7

1

X

1

X

1

0

1

0

1

0

1

0

X

1

0

1

0

1

0

1

6

1

X

0

X

1

0

1

0

1

0

1

0

1

0

X

0

1

0

5

4

3

0

2

1

0

Address byte 1

Address byte 2

ID byte

-

0

MA[1]

AD[2]

1

MA[0]

X

-

AD[5] AD[4]

AD[3]

0

AD[1] AD[0]

ID

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

0

X

0

1

0

1

0

1

0

X

0

X

0

1

0

1

0

1

0

1

0

X

0

X

0

X

0

X

1

0

1

0

X

1

0

X

0

X

0

X

0

X

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

X

0

X

Thermo byte

TM

PL

X

0

X

1

Power Level byte

Easy Prog byte 1

Easy Prog byte 2

Easy Prog byte 3

Easy Prog byte 4

Easy Prog byte 5

Cal Post-Divider byte

Cal Divider byte 1

Cal Divider byte 2

Cal Divider byte 3

EP1

EP2

EP3

EP4

EP5

CPD

CD1

CD2

CD3

1

0

Main Post-Divider byte MPD

0

Main Divider byte 1

Main Divider byte 2

Main Divider byte 3

Extended byte 1

Extended byte 2

Extended byte 3

Extended byte 4

Extended byte 5

Extended byte 6

Extended byte 7

Extended byte 8

Extended byte 9

Extended byte 10

Extended byte 11

Extended byte 12

Extended byte 13

Extended byte 14

Extended byte 15

Extended byte 16

Extended byte 17

Extended byte 18

Extended byte 19

Extended byte 20

MD1

MD2

MD3

EB1

0

1

EB2

0

EB3

0

1

EB4

0

EB5

0

EB6

0

1

EB7

1

0

EB8

X

0

1

EB9

0

EB10

EB11

EB12

EB13

EB14

EB15

EB16

EB17

EB18

EB19

EB20

X

0

X

1

0

1

0

X

0

X

0

X

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DVB-T Silicon Tuner IC

Table 6.

Name

I²C-bus at power-on reset^[1]…continued

Byte

Subaddress

Bit

7

0

1

6

0

1

0

5

1

0

1

4

1

0

1

3

0

1

0

2

0

1

0

1

0

Extended byte 21

Extended byte 22

Extended byte 23

EB21

EB22

EB23

24h

25h

26h

[1] X indicates a bit not changed on reset.

9.3 Description of symbols used in I²C-bus format table

Table 7.

I²C-bus registers bits explanation

Address Byte Symbol

MA[1:0]

Description

Reference

Table 8

programmable address bits

AD[5:0]

programmable address bits of the ﬁrst byte of the programming

Table 9

Data bytes

00h

01h

ID

ID[6:0]

POR

chip identiﬁcation number

Power-on reset bit

Table 10

Table 11

TM

LOCK

indicates that the main synthesizer is locked to the programmed

frequency

TM_RANGE

TM_ON

range selection bit for the internal die sensor

enables die temperature measurement

TM_D[3:0]

data from die temperature measurement (read only)

02h

03h

PL

POWER_LEVEL[7:0] Power level indicator value (read only)

Power level indicator value (read only

DIS_POWER_LEVEL disables the power-on level function

Table 12

Table 13

EP1 POWER_LEVEL[8]

RF_CAL_OK

indicates that the RF tracking ﬁlter calibration procedure has been

successful

IR_CAL_OK

indicates that the complete image rejection calibration procedure

has been successful

BP_FILTER[2:0]

EP2 RF_BAND[2:0]

GAIN_TAPER[4:0]

EP3 SM

RF band-pass ﬁlter selection

RF tracking ﬁlter band selection

gain taper value

04h

05h

Table 14

Table 15

Sleep mode, Standby modes

SM_LT

SM_XT

STD[4:0]

deﬁne the standard

06h

07h

EP4 FM_RFN

XTOUT_ON

selection which input is fed to RF ﬁlter

provides the 16 MHz on the XTOUTP and XTOUTN pins

IF output level selection

Table 17

IF_LEVEL[2:0]

CAL_MODE[1:0]

EP5 EXTENDED_REG

IR_GSTEP[2:0]

IR_MEAS[2:0]

calibration mode selection

enables the extended register addressing

gain step for image rejection calibration

image rejection measurement frequency range

Table 18

Table 19

08h

CPD CAL_POST_DIV[7:0] calibration synthesizer post-divider

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Table 7.

I²C-bus registers bits explanation …continued

Address Byte Symbol

Description

Reference

Table 20

09h

0Ah

0Bh

0Ch

CD1 CAL_DIV[22:16]

calibration synthesizer main divider bits

CD2 CAL_DIV[15:8]

CD3 CAL_DIV[7:0]

MPD IF_NOTCH

adds a DC notch in IF for a better adjacent channels rejection;

depends on standards

Table 21

MAIN_POST_DIV[6:0] LO synthesizer post-divider bits

0Dh

0Eh

0Fh

MD1 MAIN_DIV[22:16]

MD2 MAIN_DIV[15:8]

MD3 MAIN_DIV[7:0]

LO synthesizer main divider bits

Table 22

Extended bytes

10h

EB1 CALVCO_FORLON

determines which VCO is used during Normal mode operations

Table 23

AGC1_ALWAYS_

MASTERN

enables AGC1 normal operation whatever the tuner type (master or

slave)

AGC1_FIRSTN

EB4 LO_FORCESRCE

EB6 CAL_FORCESRCE

EB8 CID_ALARM

determines which AGC (1 or 2) will be detected when detectors 1

and 2 are up

13h

15h

17h

forces the main PLL charge pump to source current to the main PLL Table 23

loop ﬁlter

forces the calibration PLL charge pump to source current to the

calibration PLL loop ﬁlter

Table 23

indicates that signal sensed by the power detector used during

calibrations is out of range

Table 23

19h

1Bh

EB10 CID_GAIN[5:0]

EB12 PD_AGC1_DET

PD_AGC2_DET

calibration power detector output

power-down of AGC1 detector

Table 23

power-down of AGC2 detector

1Ch

EB13 RFC_K[2:0]

RFC_M[1:0]

parameter used during the RF tracking ﬁlters calibration

tuning word of the RF tracking ﬁlters

turns off the AGC1 loop

Table 23

1Dh

21h

EB14 RFC_CPROG[7:0]

EB18 AGC1_LOOP_OFF

AGC1_GAIN[1:0]

Table 23

AGC1 gain

23h

24h

EB20 FORCE_LOCK

EB21 AGC2_LOOP_OFF

AGC2_GAIN[1:0]

forces the internal lock indicator to logic 1

turns off the AGC2 loop

Table 23

AGC2 gain

25h

26h

EB22 RF_TOP[2:0]

IF_TOP[3:0]

Take Over Point (TOP) of the RF AGC, detection in RF

TOP of the RF AGC, detection in IF

1.5 MHz bandwidth ﬁlter selection

Table 23

EB23 FORCELP_FC2_EN

LP_FC[2]

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9.3.1 I²C-bus address selection

The module address contains programmable address bits (MA[1:0]), which offer the

possibility to have several synthesizers (up to 4) in one system by applying a speciﬁc

voltage on the AS input (V_AS).

Table 8.

Address byte 1 bit description

Legend: * power-on reset value

Bit

Symbol

-

Access

R/W

Value

Description

7 to 3

2 to 1

1 1000*

must be set to 1 1000

programmable address bits

V_AS= 0 V to 0.1 × V_CC

V_AS= 0.2 × V_CCto 0.3 × V_CC

V_AS= 0.4 × V_CCto 0.6 × V_CC

V_AS= 0.9 × V_CCto V_CC

write mode

MA[1:0]

R/W

00

01

10

11

0

R/W

1

read mode

Table 9.

Address byte 2 bit description

Legend: * power-on reset value

Bit

Symbol

-

Access

R/W

Value

Description

7 to 6

5 to 0

00

-

must be set to 00

AD[5:0]

R/W

programmable address bits of the ﬁrst byte

of the programming

9.3.2 Description of chip ID byte

Table 10. ID - Identiﬁcation byte (subaddress 00h) bit description

Legend: * power-on reset value

Bit

7

Symbol

-

Access

Value

1*

Description

R

must be logic 1

6 to 0

ID[6:0]

000 0100*

TDA18211HD/C2 identiﬁcation number

9.3.3 Description of temperature sensor byte

The temperature sensor is not available in Device-off mode as it requires a 16 MHz clock

to operate.

Table 11. TM - Thermo byte (subaddress 01h) bit description

Legend: * power-on reset value

Bit

Symbol

Access Value Description

7

POR

R

1*

power supply falls below the power-on reset level and is

reset after a read operation ending with a stop condition

0

power supply is above the power-on reset level

6

LOCK

1

main synthesizer is locked to the programmed frequency

0*

main synthesizer is not locked to the programmed

frequency

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Table 11. TM - Thermo byte (subaddress 01h) bit description …continued

Legend: * power-on reset value

Bit

Symbol

Access Value Description

5

TM_RANGE R/W

temperature range selection for the internal die sensor (see

Table 50)

1

92 °C to 122 °C

0*

1

60 °C to 90 °C

4

TM_ON

R/W

R

enables die temperature measurement (see Table 50)

disables die temperature measurement (see Table 50)

0*

3 to 0 TM_D[3:0]

XXXX data from die temperature measurement (see Table 50)

9.3.4 Description of power level byte (read mode)

There are 9 power level bits, dispatched in byte 2 and 3. They indicate the composite

voltage gain of the LNA, the loaded attenuator voltage gain, and the level at the input of

the RF AGC.

Table 12. PL - Power level (address 02h and 03h) bit description

Legend: * power-on reset value

Address Register Bit

Symbol

Access Value Description

03h

02h

EP1

PL

7

POWER_LEVEL[8]

POWER_LEVEL[7]

R

AGC2 gain, attenuator voltage gain included load, the

attenuator load is 50 Ω (explaining the maximum gain

of −6 dB)

00

01

10

11

−15 dB

−12 dB

−9 dB

−6 dB

6 to 5 POWER_LEVEL[6:5] R

AGC1 gain, LNA voltage gain, the LNA voltage gain

assumes a 75 Ω source impedance and a low output

impedance

00

01

10

11

6 dB

9 dB

12 dB

15 dB

4 to 0 POWER_LEVEL[4:0] R

sensed level at the input of the RF AGC, detector

slope is −1 dB/step

0 0000

0 0001

...

103 dBµV (RMS value)

102 dBµV (RMS value)

...

1 1110

1 1111

73 dBµV (RMS value)

72 dBµV (RMS value)

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9.3.5 Description of Easy Prog byte 1

Table 13. EP1 - Easy Prog byte 1 (subaddress 03h) bit description

Legend: * power-on reset value

Bit

7

Symbol

Access Value Description

POWER_LEVEL[8]

R

see Table 12

6

DIS_POWER_LEVEL R/W

1*

0

power level disabled

power level enabled

must be set to logic 0

5

4

-

R/W

0*

RF_CAL_OK

RF tracking ﬁlter calibration procedure (see

Section 9.4.9); updated each time the procedure

is started

1

successful

0*

not successful

3

IR_CAL_OK

R/W

complete image rejection calibration procedure

(see Section 9.4.4); can only be reset with POR

1

successful

0*

not successful

2 to 0 BP_FILTER[2:0]

110* RF band-pass ﬁlter selection (see Table 42)

9.3.6 Description of Easy Prog byte 2

Table 14. EP2 - Easy Prog byte 2 (subaddress 04h) bit description

Legend: * power-on reset value

Bit

7 to 5 RF_BAND[2:0]

4 to 0 GAIN_TAPER[4:0] R/W

Symbol

Access Value

Description

R/W

110*

RF tracking ﬁlter band selection (see Table 43)

gain taper value (see Table 47)

minimum attenuation

1 1111*

0 0000

maximum attenuation

9.3.7 Description of Easy Prog byte 3

The TDA18211HD has three different Standby modes. Two Standby modes are dedicated

to special application demands; the real Standby mode is called ‘device-off’. It represents

the smallest achievable power consumption.

Table 15. EP3 - Easy Prog byte 3 (subaddress 05h) bit description

Legend: * power-on reset value

Bit

Symbol

Access Value

Description

7

SM

R/W

1*

0

Sleep mode (see Table 16)

Normal mode (see Table 16)

see Table 16

6

5

SM_LT

SM_XT

R/W

0*

see Table 16

4 to 0 STD[4:0] R/W

1 0010* description of standards (see Table 41)

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Table 16. Standby modes^[1]

Bit

Circuit

Mode

SM

SM_LT SM_XT Loop-

Slave-

Crystal

through tuner

output

oscillator

0

1

0

on

Normal mode

Standby mode with crystal

oscillator, slave-tuner output and

loop-through output on

1

0

1

off

on

off

Standby mode with only crystal

oscillator and its output buffer on

Device-off mode

[1] In all modes, the I²C-bus interface remains active. All other codes are not valid.

9.3.8 Description of Easy Prog byte 4

Table 17. EP4 - Easy Prog byte 4 (subaddress 06h) bit description

Legend: * power-on reset value

Bit

Symbol

Access Value Description

7

FM_RFN

R/W

selection which input is fed to RF ﬁlter

1

FM input (RF LNA on; FM LNA on)

RF input (RF LNA on; FM LNA off)

16 MHz on pins XTOUTP and XTOUTN

not 16 MHz on pins XTOUTP and XTOUTN

must be set to logic 1

0*

1*

0

6

3

XTOUT_ON

-

R/W

1*

4 to 2 IF_LEVEL[2:0]

IF output level selection and attenuation with regard to

2 V (p-p)

000*

001

010

011

100

101

110

111

2 V (p-p); 0 dB

1.25 V (p-p); 4 dB

1 V (p-p); 6 dB

0.8 V (p-p); 8 dB

not used

0.5 V (p-p); 12 dB

1 to 0 CAL_MODE[1:0] R/W

calibration mode selection

no calibration (Normal mode)

Power detection mode

image rejection calibration (IRCAL) mode

RF tracking ﬁlters calibration (RFCAL) mode

00*

01

10

11

It is recommended to follow the ﬂowcharts described in Section 9.4 in order to perform

any calibration, as they require a precise set of sequential operations. The further

comments can only give an overview of what is typically done during the ﬂowchart.

The TDA18211HD has two calibration modes: one for the image rejection calibration, and

one for the RF tracking ﬁlters calibration.

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The image rejection calibration consists in optimizing some tunable parameters inside the

mixer throughout a set of internal measurements, leading to ensure a 65 dB typical value

of image rejection. The internal signal used during this phase is generated by the PLL

calibration (CAL PLL).

The RF tracking ﬁlters central frequency can be adjusted with the tuning word

RFC_CPROG. The RF tracking ﬁlters calibration (RFCAL) consists of an internal tone at

the input of the tracking ﬁlters (with the CAL PLL), and ﬁnding the RFC_CPROG

corresponding to the maximum transmitted power. The RFCAL is just a little part of a

more complex algorithm fully described in the ﬂowcharts in Section 9.4.

The Power detection mode is a Normal mode where the detector used for the calibrations

is switched ON. This special mode enables to sense the power at the input of the

TDA18211HD and makes the power scan algorithm possible (see Section 9.4.8

“Flowchart TDA18211PowerScan”).

9.3.9 Description of Easy Prog byte 5

Table 18. EP5 - Easy Prog byte 5 (subaddress 07h) bit description

Legend: * power-on reset value

Bit

Symbol

Access Value

Description

7

EXTENDED_REG R/W

enables the extended register addressing

extended register (00h to 26h)

1

0*

limited register (00h to 0Fh); only 1 byte can

be programmed after address 0Fh within 1

transmission

6 to 4 IR_GSTEP[2:0]

R/W

011*

0*

gain step for image rejection calibration

must be set to logic 0

3

-

2 to 0 IR_MEAS[2:0]

000*

image rejection measurement frequency range

(see Table 51)

9.3.10 Description of Cal Post-Divider byte

Table 19. CPD - Cal Post-Divider byte (subaddress 08h) bit description

Legend: * power-on reset value

Bit

Symbol

Access

Value Description

00h* calibration synthesizer post-divider (see

Table 46)

7 to 0 CAL_POST_DIV[7:0]

R/W

9.3.11 Description of Cal divider bytes 1, 2 and 3

Table 20. CD1, CD2 and CD3 - Cal divider bytes 1, 2 and 3 (address 09h, 0Ah and 0Bh) bit

description

Legend: * power-on reset value

Address Register Bit

Symbol

Access Value Description

R/W 0* must be set to logic 0

09h

CD1

7

-

6 to 0 CAL_DIV[22:16] R/W

00h* calibration synthesizer main

divider bits

0Ah

0Bh

CD2

CD3

7 to 0 CAL_DIV[15:8]

7 to 0 CAL_DIV[7:0]

R/W

00h*

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9.3.12 Description of Main Post-Divider byte

Table 21. MPD - Main Post-Divider byte (subaddress 0Ch) bit description

Legend: * power-on reset value

Bit

Symbol

Access

Value

Description

7

IF_NOTCH

R/W

0*

adds a DC notch in IF for a better

adjacent channels rejection; depends

on standards; see Table 41

6 to 4 MAIN_POST_DIV[6:4]

DCDC_CKSW

R/W

000*

LO synthesizer post-divider (see

Table 45)

3

allows switching between 16 MHz and

sub-harmonic LO for DC-to-DC

converter locking

1

16 MHz

0*

sub-harmonic LO

2 to 0 MAIN_POST_DIV[2:0]

R/W

000*

LO synthesizer post-divider (see

Table 45)

9.3.13 Description of Main divider bytes 1, 2 and 3

Table 22. MD1, MD2 and MD3 - Main divider bytes 1, 2 and 3 (address 0Dh, 0Eh and 0Fh) bit

description

Legend: * power-on reset value

Address Register Bit

Symbol

Access Value Description

R/W 0* must be set to logic 0

0Dh

MD1

7

-

6 to 0 MAIN_DIV[22:16] R/W

7 to 0 MAIN_DIV[15:8] R/W

00h* LO synthesizer main divider bits

0Eh

0Fh

MD2

MD3

00h*

7 to 0 MAIN_DIV[7:0]

R/W

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9.3.14 Description of Extended bytes 1 to 23

Table 23. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description

Legend: * power-on reset value

Address Register

Bit

7 to 3

2

Symbol

Access Value

Description

10h

EB1

EB1[7:3]

R

1 1111*

extended byte 1

CALVCO_FORLON

determines VCO used during Normal

mode operations

1*

0

LO VCO is used

CAL VCO is used

1

0

AGC1_ALWAYS_

MASTERN

R

enables AGC1 normal operation

whatever the tuner type, master or

slave.

1*

0

normal operation for the master;

6 dB ﬁxed for the slave

normal operation for both the master

and the slave

AGC1_FIRSTN

determines which AGC will be updated

when detectors 1 and 2 are up

1*

AGC1 and AGC2 both updated

AGC1 has priority on AGC2

extended byte 2

0

11h

12h

13h

EB2

EB3

EB4

7 to 0

7 to 6

5

EB2[7:0]

R/W

0000 0001*

EB3[7:0]

1000 0100*

extended byte 3

EB4[7:6]

01*

1

extended byte 4

LO_FORCESRCE

forces the main PLL charge pump to

source current to the main PLL loop

ﬁlter

0*

no force

4 to 0

EB4[4:0]

R/W

0 0001*

0000 0001*

1000 0100*

01*

extended byte 4

extended byte 5

extended byte 6

extended byte 7

14h

15h

16h

EB5

EB6

EB7

7 and 6 EB5[7:0]

7 to 0 EB6[7:0]

7 and 6 EB7[7:6]

5

CAL_FORCESRCE R/W

1

forces the main PLL charge pump to

source current to the main PLL loop

ﬁlter

0*

no force

4 to 0

7

EB7[4:0]

R/W

R

0 1000*

extended byte 7

17h

EB8

CID_ALARM

signal sensed by the power detector

used during calibrations

1

out of range

in range

0*

6 to 4

3

EB8[6:4]

EB8[3]

R/W

R

111*

extended byte 8

0*

2 to 0

7 to 0

EB8[2:0]

EB9[7:0]

R/W

W

101*

18h

19h

EB9

0000 0000*

XX

extended byte 9

EB10

7 and 6 EB10[7:6]

5 to 0 CID_GAIN[5:0]

R

extended byte 10

R

XX XXXX

calibration power detector output

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Table 23. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description …continued

Legend: * power-on reset value

Address Register

Bit

Symbol

Access Value

Description

1Ah

1Bh

EB11

EB12

7 to 0

EB11[7:0]

R/W

R

1000 0110*

extended byte 11

extended byte 12

AGC1 detector

power-down

7 and 6 EB12[7:6]

00*

5

4

PD_AGC1_DET

R/W

1

0*

no power-down

AGC2 detector

power-down

PD_AGC2_DET

R/W

1

0*

no power-down

extended byte 12

extended byte 13

3 to 0

7

EB12[3:0]

EB13[7]

R/W

0111*

1*

1Ch

EB13

6 to 4

RFC_K[2:0]

100*

00*

parameters used during the RF

tracking ﬁlters calibration (see

Table 44)

3 and 2 RFC_M[1:0]

1 to 0

7 to 0

7 to 4

3 to 0

7 to 0

7

EB13[1:0]

R/W

R

10*

extended byte 13

1Dh

1Eh

EB14

EB15

RFC_CPROG[7:0]

EB15[7:4]

0000 0000*

1000*

tuning word of the RF tracking ﬁlters

extended byte 15

EB15[3:0]

XXXX*

1Fh

20h

21h

EB16

EB17

EB18

EB16[7:0]

W

000X XX00*

000X XXXX*

extended byte 16

extended byte 17

turns the AGC1 loop

off

EB17[7:0]

W

AGC1_LOOP_OFF R/W

1

0*

on

6 to 2

EB18[6:2]

R/W

000 00*

extended byte 18

AGC1 gain

1 and 0 AGC1_GAIN[1:0]

00*

6 dB

01

9 dB

10

12 dB

11

15 dB

22h

23h

EB19

EB20

7 to 0

EB19[7:0]

W

000X XX00*

10*

extended byte 19

extended byte 20

forces the internal lock indicator

forced to logic 1

not forced

7 and 6 EB20[7:6]

5

FORCE_LOCK

1

0*

4 to 0

EB20[4:0]

W

X XXXX*

extended byte 20

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Table 23. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description …continued

Legend: * power-on reset value

Address Register

Bit

Symbol

Access Value

Description

turns the AGC2 loop

off

24h

EB21

7

AGC2_LOOP_OFF R/W

1

0*

on

6 to 2

EB21[6:2]

R/W

0 1100*

extended byte 21

AGC2 gain

−15 dB

1 and 0 AGC2_GAIN[1:0]

00

01

−12 dB

10

−9 dB

11*

0*

−6 dB

25h

26h

EB22

EB23

7

EB22[7]

R

extended byte 22

6 to 4

RFAGC_TOP[2:0]

R/W

100*

take over point of the RF AGC,

detection in RF

3 to 0

IFAGC_TOP[3:0]

EB23[7:3]

R/W

1000*

take over point of the RF AGC,

detection in IF

7 to 3

2

R/W

1 0110*

0*

extended byte 23

FORCELP_

FC2_EN

1.5 MHz bandwidth ﬁlter selection; see

Table 24

1

0

LP_FC[2]

EB23[0]

R/W

0*

extended byte 23

Table 24. Low pass cut-off frequency

FORCELP_FC2_EN LP_FC[2]

STD[1:0]

Cut-off frequency (MHz)

0

X

00

01

10

11

6

7

8

9

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9.4 I²C-bus programming ﬂowcharts

The following ﬂowcharts describe how to:

• Initialize the TDA18211HD

• Launch the calibrations

• Go to Normal mode

The image rejection calibration as well as RF tracking ﬁlters calibration must be launched

the way explicitly described in the ﬂowchart. If not done this way, it may result in bad

calibration or even blocking the TDA18211HD, which makes it impossible to communicate

via the I²C-bus.

For proper internal initialization, switching to Normal mode also requires a single I²C-bus

sequence from subaddresses 03h to 0Fh.

9.4.1 Flowchart explanation

This section provides instructions for reading the ﬂowcharts.

master or slave

2

MS

for I C-bus write

actions

registers to update

in the software

internal table

tuner registers

update

2

Internal table

I C-bus

IR_GSTEP = 2h

-

I2C_XTOUT_ASYM = 1 EP5

initialization phase

PD_AGC1_DET = 1

-

EB12

EB13

IR_GSTEP = 2h,

-

I2C_XTOUT_ASYM = 1,

PD_AGC1_DET = 1

-

EP5

EB12

EB13

-

EP1...CD2

EP1...EP2,

MD3

001aag935

Fig 3. Programming sequence

1. I²C-bus write:

– IR_GSTEP is updated, no immediate I²C-bus write

– I2C_XTOUT_ASYM is updated followed by an I²C-bus write of EP5

– PD_AGC1_DET is updated followed by an I²C-bus write of EB12

– I²C-bus write of EB13 with current value of the software internal table of EB13

I²C-bus read:

– Sub-addressing is not supported in read mode

– The only recommended I²C-bus read access procedures of the TDA18211HD are

described in Section 9.4.16 “Flowchart TDA18211Read” and Section 9.4.17

“Flowchart TDA18211ReadExtended”

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2. Update at the same moment is indicated by separation with commas:

IR_GSTEP, I2C_XTOUT_ASYM and PD_AGC1_DET are updated, no I²C-bus

registers update

3. I²C-bus registers update of the bytes EP5, EB12 and EB13

4. Bytes EP1 to CD2 are written in a single I²C-bus sequence

Example:

Start C0 03 EP1 EP2 EP3 EP4 EP5 CPD CD1 CD2 Stop

5. Bytes EP1, EP2 and MD3 are written in as many I²C-bus sequences as needed

Example:

Start C0 03 EP1 EP2 Stop

Start C0 0F MD3 Stop

X

stored or already calculated data

X

input variable

X

result of an operation

X

output variable

001aag722

Fig 4. Blocks used in the ﬂowcharts

2

I C initialization sequence

Call TDA18211FixedContentsI2Cupdate

Calibrate the RF tracking filters

MS_init

call TDA18211CalcRFFilterCurve

Back to POR

Call TDA18211MSPOR

001aag936

Master/slave variable MS_init is input for each of the three procedures.

Fig 5. Variable used in multiple procedures

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xx_in

XY_map

Find yy = f(xx) in XY_map

yy_out

001aag822

xx is a list of values stored in the ﬁrst column of the map XY_map.

yy is a list of values stored in column in XY_map.

yy_out is the particular value of yy to ﬁnd row n. xx(n − 1) < xx_in ≤ xx(n).

a. General description to ﬁnd a value in a table

650 MHz

KM_map

Find RFC_K = f

in

RF(max)

RFC_K

KM_map

001aag723

Finding the row of RFC_K: 350000 < 650000 ≤ 720000. Result n = 1. The value of RFC_K is then

3 (see Table 44).

b. Example to ﬁnd the value RFC_K corresponding to f_RF= 650 MHz in the KM_map.

Fig 6. Finding a value in a table

Units

• In the ﬂowcharts, hexadecimal values end with “h”, decimal values with “d”

• Frequency variables used in computations are expressed in kHz, for example 1 GHz

is written as 1000000.

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9.4.2 Flowchart TDA18211SetRf_dual

Table 25. TDA18211SetRf_dual

Function

Description

Input

Description

Reference

protocol top view for a dual-tuner application

RF_freq, Standard (from microcontroller), MS (from

microcontroller)

Table

-

Output

The initialization phase has to be launched before any SetRf.

MS = 1: master is selected for the channel conﬁguration.

MS = 0: slave is selected for the channel conﬁguration.

Start

TDA18211SetRf_dual

Yes

init_done = 1

No

Master and slave initialization

Call TDA18211InitCal

TMVALUE_RFCAL

init_done

Set the RF tracking filters

TMVALUE_RFCAL

Call TDA18211RFtrackingFiltersCorrection

RF_freq

MS

Standard

RF_freq

MS

Set the tuner to the wanted channel

Call TDA18211ChannelConfiguration

End

TDA18211SetRf_dual

001aag937

Fig 7. Flowchart TDA18211SetRf_dual

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9.4.3 Flowchart TDA18211InitCal

Table 26. TDA18211InitCal

Function

Description

Input

Description

Reference

systematic initialization for master and slave tuners

MS_init

Table

-

Output

TMVALUE_RFCAL, init_done

Start

TDA18211InitCal

MS_init = 1

MS_init

Master initialization

TMVALUE_RFCAL

2

I C initialization sequence

Call TDA18211FixedContentsI2Cupdate

MS_init

Calibrate the RF tracking filters

Call TDA18211CalcRFFilterCurve

Back to POR

Call TDA18211MSPOR

MS_init = 0

MS_init

Slave initialization

2

I C initialization sequence

Call TDA18211FixedContentsI2Cupdate

MS_init

Calibrate the RF tracking filters

Call TDA18211CalcRFFilterCurve

Back to POR

Call TDA18211MSPOR

init_done = true

init_done

End

TDA18211InitCal

001aag938

Fig 8. Flowchart TDA18211InitCal

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9.4.4 Flowchart TDA18211FixedContentsI2Cupdate

Table 27. TDA18211FixedContentsI2Cupdate

Function

Description

Reference

Description

update and write the TDA18211HD registers,

sequential update of AGC1 and AGC2,

image calibration algorithm

Input

MS

Table

Output

-

Start

MS

TDA18211FixedContentsI2Cupdate

2

Actions

Internal table

I

C-bus

Internal table update with TM = 08h

-

IRCAL low band

Initialization

EP3 = 1Fh

EP4 = 66h

EP5 = 81h

CPD = CCh

CD1 = 6Ch

CD2 = 00h

CD3 = 00h

MPD = CDh

MD1 = 77h

MD2 = 08h

MD3 = 00h

-

IRCAL high band

Initialization

EP5 = 83h

CPD = 98h

CD1 = 65h

CD2 = 00h

MPD = 99h

MD1 = 71h

MD2 = CDh

-

correct values

PL = 80h

EP1 = C6h

EP2 = DFh

EP3 = 16h

EP4 = 60h

EP5 = 80h

CPD = 80h

CD1 = 00h

CD2 = 00h

CD3 = 00h

MPD = 00h

MD1 = 00h

MD2 = 00h

MD3 = 00h

EB1 = FCh

EB2 = 01h

EB3 = 84h

EB4 = 41h

EB5 = 01h

EB6 = 84h

EB7 = 40h

EB8 = 07h

EB9 = 00h

EB10 = 00h

EB11 = 96h

EB12 = 33h

EB13 = C1h

EB14 = 00h

EB15 = 8Fh

EB16 = 00h

EB17 = 00h

EB18 = 8Ch

EB19 = 00h

EB20 = 20h

EB21 = B3h

EB22 = 48h

EB23 = B0h

Tuner registers update

Wait 5 ms - PLL locking

Launch detector

-

EP3...MD3

EP1

Tuner registers update

MAIN PLL CP source on

Wait 1 ms

-

EP3...MD3

EB4

EB4 = 61h

Wait 5 ms - measurement

CALPLL update

EP5 = 87h

CD1 = 65h

CD2 = 50h

-

MAIN PLL CP source off

Wait 5 ms - PLL locking

Launch detector

EB4 = 41h

EB4

EP1

Tuner registers update

Wait 5 ms - PLL locking

Launch optimization algorithm

Wait 30 ms - optimization

Back to normal mode

Synchronization

-

EP3...CD3

EP2

-

Wait 5 ms - measurement

CALPLL update

EP5 = 85h

CPD = CBh

CD1 = 66h

CD2 = 70h

-

EP4 = 64h

-

EP4

EP1

Tuner registers update

-

EP3...CD3

Wait 5 ms - PLL locking

Launch optimization algorithm

Wait 30 ms - optimization

-

EP2

End

TDA18211FixedContentsI2Cupdate

Tuner registers update

AGC1 gain setup

-

TM...EB23

IRCAL mid band

Initialization

EP5 = 82h

CPD = A8h

CD2 = 00h

MPD = A9h

MD1 = 73h

MD2 = 1Ah

-

EB17 = 00h

EB17 = 03h

EB17 = 43h

EB17

EB17 = 4Ch EB17

Tuner registers update

Wait 5 ms - PLL locking

Launch detector

-

EP3...MD3

-

EP1

Wait 5 ms - measurement

CALPLL update

EP5 = 86h

CPD = A8h

CD1 = 66h

CD2 = A0h

-

Tuner registers update

-

EP3...CD3

Wait 5 ms - PLL locking

Launch optimization algorithm

Wait 30 ms - optimization

-

EP2

001aag939

Fig 9. Flowchart TDA18211FixedContentsI2Cupdate

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9.4.5 Flowchart TDA18211CalcRFFilterCurve

Table 28. TDA18211CalcRFFilterCurve

Function

Description

Input

Description

Reference

calculate the RF ﬁlter curves coefﬁcients

RF1_default, RF2_default, RF3_default, MS

RF_BAND_map

Table

Table 43 “RF_BAND_map”

Output

TMVALUE_RFCAL

Start

TDA18211CalcRFFilterCurve

Wait 200 ms for die temperature stabilization

PowerScan Initialization

Call TDA18211PowerScanInit

f

= 203500

RF(max)

RF1_4, RF_A1_4,

RF_B1_4

RF_Band 4 filters calibration

Call TDA18211RFTrackingFiltersInit

f

RF(max)

f

= 457800

RF(max)

RF1_5, RF_B1_5, RF2_5, RF_A1_5,

RF3_5, RF_A2_5, RF_B2_5

RF_Band 5 filters calibration

Call TDA18211RFTrackingFiltersInit

MS

f

= 865000

RF(max)

RF1_6, RF_B1_6, RF2_6, RF_A1_6,

RF3_6, RF_A2_6, RF_B2_6

RF_Band 6 filters calibration

Call TDA18211RFTrackingFiltersInit

Read die current temperature

Call TDA18211ThermometerRead

TMVALUE_RFCAL

End

TDA18211CalcRFFilterCurve

001aag940

Fig 10. Flowchart TDA18211CalcRFFilterCurve

TDA18211HD_5

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DVB-T Silicon Tuner IC

9.4.6 Flowchart TDA18211RFTrackingFiltersInit

Table 29. TDA18211RFTrackingFiltersInit

Function

Description

Reference

Description

calculate the RF ﬁlter curve coefﬁcients used for

their approximation

Input

f_RF(max), MS

Table

Output

RF_CAL_map (Cprog_table = f(frequency))

RF1, RF2, RF3, RF_A1, RF_B1, RF_B2

Table 49 “RF_CAL_map”

bcal is a boolean output from TDA18211PowerScan:

bcal = 1 (true): enables the calibration of the RF tracking ﬁlters

bcal = 0 (false): no calibration is performed, default values for RFC_CPROG are used

TDA18211HD_5

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Start

TDA18211RFTrackingFiltersInit

RF1_default,

RF2_default,

RF3_default

RF_A1 = 0, RF_B1 = 0, RF_A2 = 0, RF_B2 = 0

RF1_default

MS

Find RF1_default, RF2_default, RF3_default = f

in RF_BAND_map

RF(max)

RF1

Look for optimized calibration frequency

Call TDA18211PowerScan

bcal

RF1

No

bcal = 1

Yes

MS

Find Cprog_cal1 to track RF1

Call TDA18211CalibrateRF

RF1

Cprog_cal1

RF1

RF_CAL_map

Find Cprog_table = f

RF(max)

in RF_CAL_map

Cprog_table1

No

bcal = 0

Yes

Cprog_table1

Cprog_cal1 = Cprog_table1

Cprog_cal1

RF1

Cprog_cal1

Cprog_table1

RF_B1

RF_A1

RF_B1 = Cprog_cal1 − Cprog_table1

Yes

End

RF2_default = 0

No

Look for optimized calibration frequency

TDA18211 RFTrackingFiltersInit

RF2_default

MS

bcal

RF2

Call TDA18211PowerScan

No

RF2

bcal = 1

Yes

MS

Find Cprog_cal2 to track RF2

Call TDA18211CalibrateRF

RF2

Cprog_cal2

Cprog_table2

RF2

RF_CAL_map

Find Cprog_table = f

RF(max)

in RF_CAL_map

No

bcal = 0

Yes

Cprog_table2

Cprog_cal2 = Cprog_table2

Cprog_cal2

RF_A1

RF1

RF2

Cprog_cal1

Cprog_cal2

Cprog_table1

Cprog_table2

RF_A1 = (Cprog_cal2 − Cprog_table2 − Cprog_cal1 + Cprog_table1)/

(RF2 − RF1)

Yes

End

RF3_default = 0

TDA18211 RFTrackingFiltersInit

RF3_default

MS

No

bcal

RF3

Look for optimized calibration frequency

Call TDA18211PowerScan

No

RF3

bcal = 1

MS

Yes

Find Cprog_cal3 to track RF3

Call TDA18211CalibrateRF

RF3

Cprog_cal3

Cprog_table3

RF3

RF_CAL_map

Find Cprog_table = f

RF(max)

in RF_CAL_map

No

bcal = 0

Yes

Cprog_table3

Cprog_cal3 = Cprog_table3

Cprog_cal3

RF_A2

RF2

RF3

Cprog_cal2

Cprog_cal3

Cprog_table2

Cprog_table3

RF_A2 = (Cprog_cal3 − Cprog_table3 − Cprog_cal2 + Cprog_table2)/(RF3 − RF2)

RF_B2 = Cprog_cal2 − Cprog_table2

RF_B2

End

TDA18211RFTrackingFiltersInit

001aag941

Fig 11. Flowchart TDA18211RFTrackingFiltersInit

Rev. 05 — 2 June 2009

TDA18211HD_5

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9.4.7 Flowchart TDA18211PowerScanInit

Table 30. TDA18211PowerScanInit

Function

Description

Input

Description

Reference

ﬁxed settings of the TDA18211PowerScan

MS

Table

Output

Start

MS

TDA18211PowerScanInit

2

Actions

Internal table

I C-bus

Set standard mode to digital mode

STD = 12,

-

IF_LEVEL = 0

CAL_MODE = 0

Tuner registers update

-

EP3...EP4

Set AGC1_GAIN to 6 dB

Set AGC2_GAIN to −15 dB

AGC1_GAIN = 0

AGC2_GAIN = 0

EB18

-

1.5 MHz low-pass filter

Tuner register update

FORCELP_FC2_EN = 1,

LP_FC[2] = 1

-

EB21...EB23

End

TDA18211PowerScanInit

001aag942

Fig 12. Flowchart TDA18211PowerScanInit

9.4.8 Flowchart TDA18211PowerScan

Table 31. TDA18211PowerScan

Function

Description

Input

Description

Reference

ﬁnd an interferer free calibration frequency

freq_input, MS

Table

RF_BAND_map,

Table 43 “RF_BAND_map”

Table 49 “RF_CAL_map”

Table 52 “CID_TARGET_map”

RF_CAL_map,

CID_TARGET_map

bcal, freq_output

Output

TDA18211HD_5

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Rev. 05 — 2 June 2009

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TDA18211HD

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DVB-T Silicon Tuner IC

Start

MS

TDA18211PowerScan

RF_BAND_map

RF_CAL_map

CID_TARGET_map

Actions

Find RF_BAND = f

Internal table

PC

in RF_BAND_map(MS)

in RF_CAL_map

RF_BAND = RF_BAND

-

RF(max)

Find Cprog_table = f

RFC_CPROG = CPROG_table

GAIN_TAPER = GAIN_TAPER

CID_Target = CID_Target

count_limit = count_limit

RF(max)

Find GAIN_TAPER = f

Find CID_TARGET count_limit = f

CID_TARGET_map

MS

CID_Target

count_limit

in GAIN_TAPER_map

RF(max)

in

RF(max)

freq_input

Tuner register update

-

EP2, EB14

freq_MAINPLL = freq_input + 1 MHz

freq_MAINPLL

Downconvert freq_input to 1 MHz

Call TDA18211CalcMAINPLL

freq_MAINPLL

Wait 5 ms - PLL locking

Detection mode

Launch power detection measurement

CAL_MODE = 1

-

EP4

EP2

Read power detection informations

Call TDA18211ReadExtended

CID_GAIN

Algorrithm Initialization

sgn =1

freq_output = freq_input

bcal = 0

count = 0

wait = false

sgn

freq_output

bcal

count

wait

freq_input

No

CID_GAIN < CID_Target

Yes

sgn count

freq_MAINPLL = freq_input + sgn × count + 1 MHz

freq_MAINPLL

Downconvert updated freq_input to 1 MHz

Call TDA18211CalcMAINPLL

freq_input

freq_MAINPLL

No

Yes

wait = true

Wait 5 ms - PLL locking

wait = false

Wait 100 µs - PLL locking

wait

Launch power detection measurement

-

EP2

Read power detection informations

Call TDA18211ReadExtended

CID_GAIN

count

count = count + 200d

No

count > count_limit

Yes

No

sgn > 0

Yes

sgn

count

wait

sgn = − sgn

count = 200d

wait = true

No

CID_GAIN ≥ CID_Target

Yes

bcal

freq_output

bcal

freq_output

bcal = 1

bcal = 0

freq_output = freq_input

freq_MAINPLL

freq_input

freq_output = freq_MAINPLL − 1 MHz

End

TDA18211PowerScan

001aag943

Fig 13. Flowchart TDA18211PowerScan

TDA18211HD_5

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TDA18211HD

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9.4.9 Flowchart TDA18211CalibrateRF

Table 32. TDA18211CalibrateRF

Function

Description

Reference

Description

ﬁnd the Cprog for which freq_input is

the central frequency of the RF tracking

ﬁlters

Input

Table

freq_input, MS

BP_FILTER_map,

KM_map,

Table 42 “BP_FILTER_map”

Table 44 “KM_map”

GAIN_TAPER_map

RFC_CPROG

Table 47 “GAIN_TAPER_map”

Output

TDA18211HD_5

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Start TDA18211CalibrateRF

MS

2

Actions

Internal table

I C-bus

Normal mode

Switch OFF AGC1

Set AGC1_GAIN to 15 dB

CAL_MODE = 0

SM_LT = 1

AGC1_GAIN = 3h

EP4

-

EB18

Frequency dependent parameters update

BP_FILTER = BP_FILTER

GAIN_TAPER = GAIN_TAPER

RF_BAND = RF_BAND

-

Find BP_FILTER = f

Find GAIN_TAPER = f

in BP_FILTER_map

RF(max)

BP_FILTER_map

KM_map

GAIN_TAPER_map

in GAIN_TAPER_map

RF(max)

Find RF_BAND = f

in RF_BAND_map

RF(max)

RFC_K = RFC_K, RFC_M = RFC_M

Find RFC_K, RFC_M = f

in KM_map

RF(max)

freq_input

MS

Tuner registers update

-

EP1 … EP2, EB13

MAIN PLL charge pump source

CAL PLL charge pump source

Force DCDC converter to 0 V

Disable PLLs lock

LO_FORCESRCE = 1

CAL_FORCESRCE = 1

RFC_CPROG = 0

FORCE_LOCK = 0

CAL_MODE = 3h

EB4

EB7

EB14

EB20

-

RF tracking filters calibration mode

Tuner registers update

-

EP4 … EP5

Set the internal calibration signal

Call TDA18211CalcCALPLL

freq_input

Downconvert the calibration signal to 1 MHz

Call TDA18211CalcMAINPLL

freq_input + 1 MHz

Wait 5 ms

Internal synchronization

EP2, EP1, EP2, EP1

Normal operation for the MAIN PLL charge pump

Normal operation for the CAL PLL charge pump

LO_FORCESRCE = 0

CAL_FORCESRCE = 0

EB4

EB7

Wait 10 ms - PLLs locking

Launch the RF Tracking filters calibration

Wait 60 ms - calibration on going

FORCE_LOCK = 1

EB20

Normal mode

Switch ON AGC1

Set AGC1_GAIN to 6 dB

CAL_MODE = 0

SM_LT = 0

AGC1_GAIN = 0

-

EB18

Tuner registers update

Synchronization

-

EP3 ... 4

EP1

Get the calibration result

Call TDA18211ReadExtended

RFC_CPROG

001aag944

End TDA18211CalibrateRF

Fig 14. Flowchart TDA18211CalibrateRF

TDA18211HD_5

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9.4.10 Flowchart TDA18211MSPOR

Table 33. TDA18211MSPOR

Function

Description

Reference

Description

master or slave tuner goes to Power-On Reset

(POR) mode

Input

MS

Table

Output

-

Start

TDA18211MSPOR

MS

2

Actions

Internal table

I C-bus

Power up Detector 1

Turn AGC1 loop ON

Set AGC1_GAIN to 6 dB

PD_AGC1_DET = 0

AGC1_LOOP_OFF = 0

AGC1_GAIN = 0

EB12

-

EB18

-

Set AGC2_GAIN to −6 dB

AGC2_GAIN = 3h

POR mode

SM = 1, SM_LT = 0,

SM_XT = 0

EP3

1.5 MHz low-pass filter disabled

FORCELP_FC2_EN = 0,

LP_FC[2] = 0

EB21 ... EB23

End

TDA18211MSPOR

001aag945

Fig 15. Flowchart TDA18211MSPOR

9.4.11 Flowchart TDA18211RFtrackingFiltersCorrection

Table 34. TDA18211RFtrackingFiltersCorrection

Function

Description

Reference

Description

ﬁnd the Cprog corresponding to the

programmed central frequency

freq_input

Input

Table

freq_input, TMVALUE_RFCAL, MS

RF_BAND_map,

Table 43 “RF_BAND_map”

RF_CAL_OVER_DT_map,

RF_CAL_map

Table 48 “RF_CAL_DC_OVER_DT_map”

Table 49 “RF_CAL_map”

Output

-

TDA18211HD_5

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MS

Start TDA18211RFTrackingFiltersCorrection

2

Action

Internal table

I C-bus

Power up TDA18211

SM = 0, SM_LT = 0, EP3

SM_XT = 0

Read die current temperature

Call TDA18211ThermometerRead

TMVALUE_CURRENT

Cprog_table

RF1

RF2

Frequency dependant parameters update

RF_CAL_map

RF_BAND_map

Find RFC_CPROG = f

in RF_CAL_map, Cprog_table = RFC_CPROG

RF(max)

Find RF1, RF2, RF3, RF_A1, RF_A2, RF_B1, RF_B2 = f

in RF_BAND_map(MS)

RF(max)

RF3

RF_A1

RF_A2

RF_B1

RF_B2

freq_input

MS

no

RF3 = 0 or

yes

freq_input < RF2

RF_A2

RF2

RF_B2

Cprog_table

RF_A1

RF1

RF_B1

Cprog_table

Capprox =

RF_A2 × (freq_input − RF2) +

RF_B2 + Cprog_table

Capprox =

RF_A1 × (freq_input − RF1) +

RF_B1 + Cprog_table

Capprox

freq_input

no

Capprox < 0

Capprox > 255

yes

Capprox = 0

Capprox = 255

RF_CAL_DC_OVER_DT_map

freq_input

Find dCoverdT = f

in RF_CAL_DC_OVER_DT_map

dCoverdT

RF(max)

Calculate temperature compensation

RFCAL_TCOMP = dCoverdT × (TMVALUE_CURRENT−TMVALUE_RFCAL) / 1000

dCoverdT

TMVALUE_CURRENT

RFCAL_TCOMP

TMVALUE_RFCAL

Capprox

RFCAL_TCOMP

Calculate final Cprog

Cprog = Capprox + RFCAL_TCOMP

RFC_CPROG = Cprog EB14

End TDA18211RFTrackingFiltersCorrection

001aag946

Fig 16. Flowchart TDA18211RFtrackingFiltersCorrection

TDA18211HD_5

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TDA18211HD

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9.4.12 Flowchart TDA18211ChannelConﬁguration

Table 35. TDA18211ChannelConﬁguration

Function Description

Reference

Description tune the tuner according to the

channel and broadcast conﬁguration

Input

Table

freq_input, MS, Standard

STANDARD_DESCRIPTION_map,

BP_FILTER_map,

RF_BAND_map,

CAL_PLL_map,

Table 41 “STANDARD_DESCRIPTION_map”

Table 42 “BP_FILTER_map”

Table 43 “RF_BAND_map”

Table 46 “CAL_PLL_map”

GAIN_TAPER_map,

IR_MEAS_map

Table 47 “GAIN_TAPER_map”

Table 51 “IR_MEAS_map”

Output

-

TDA18211HD_5

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9.4.13 Flowchart TDA18211CalcMAINPLL

Table 36. TDA18211CalcMAINPLL

Function

Description

Reference

Description

ﬁnd the correct values for the bytes

MPD, MD1, MD2, MD3 and update the

tuner registers

Input

freq_input, MS

Table

Output

MAIN_PLL_map

-

Table 45 “MAIN_PLL_map”

MPD, MD1, MD2 and MD3 are 8-bit registers. Arithmetical and logical operations

performed on those registers are considered binary operations. (Dividing is right shifting

and multiplying is left shifting, etc.)

Start TDA18211CalcMAINPLL

MAIN_PLL_map

freq_input

MAIN_POST_DIV

Div

Find MAIN_POST_DIV, Div = f

in MAIN_PLL_map

LO(max)

MS

2

Internal table

I C-bus

MAIN_POST_DIV

Div

Update MPD byte

MPD = MAIN_POST_DIV && 7Fh

-

7

MAIN_DIV = (Div × freq_input × 2 ) / 125d

MAIN_DIV

freq_input

16

Update MD1, MD2, MD3 bytes

Tuner registers update

MD1 = (MAIN_DIV / 2 ) && 7Fh

8

-

MAIN_DIV

MD2 = (MAIN_DIV / 2 )

MD3 = MAIN_DIV

-

MPD … MD3

End TDA18211CalcMAINPLL

001aag948

Fig 18. Flowchart TDA18211CalcMAINPLL

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9.4.14 Flowchart TDA18211CalcCALPLL

CPD, CD1, CD2 and CD3 are 8-bit registers. Arithmetical and logical operations

performed on those registers are considered binary operations. Dividing is right shifting

and multiplying is left shifting.

Table 37. TDA18211CalcCALPLL

Function

Description

Reference

Description

ﬁnd the correct values for the bytes

CPD, CD1, CD2, CD3 and update the

tuner registers

Input

freq_input, MS

CAL_PLL_map

Table

Output

Table 46 “CAL_PLL_map”

Start TDA18211CalcCALPLL

CAL_PLL_map

freq_input

CAL_POST_DIV

Div

Find CAL_POST_DIV, Div = f

in CAL_PLL_map

LO(max)

MS

2

Internal table

I C-bus

CAL_POST_DIV

Div

Update CPD byte

CPD = CAL_POST_DIV

-

7

CAL_DIV = (Div × freq_input × 2 ) / 125d

CAL_DIV

freq_input

16

Update CD1, CD2, CD3 bytes

Tuner registers update

CD1 = (CAL_DIV / 2 ) && 7Fh

8

-

CAL_DIV

CD2 = (CAL_DIV / 2 )

CD3 = CAL_DIV

-

CPD … CD3

End TDA18211CalcCALPLL

001aag949

Fig 19. Flowchart TDA18211CalcCALPLL

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9.4.15 Flowchart TDA18211ThermometerRead

Table 38. TDA18211ThermometerRead

Function

Description

Reference

Description

turns the on-chip thermometer ON,

reads the current temperature on the

die and then turns the thermometer

OFF

Input

MS

Table

Output

THERMOMETER_map

TMVALUE (temperature in °C)

Table 50 “THERMOMETER_map^[1]”

Start

MS

TDA18211ThermometerRead

2

Actions

Internal table

TM_ON = 1

I C-bus

Switch thermometer ON

TM

TM_RANGE

TM_D

Read thermometer information

Call TDA18211Read

(TM_D = 0) and (TM_RANGE = 1)

no

or

(TM_D = 8) and (TM_RANGE = 0)

yes

Switch TM_RANGE

TM_RANGE = not (TM_RANGE) TM

Wait 10 ms - temperature sensing

TM_RANGE

TM_D

Read thermometer information

Call TDA18211Read

TM_D

TM_RANGE

Find TMVALUE = f(TM_D, TM_RANGE) in

THERMOMETER_map

TMVALUE

Switch thermometer OFF

Normal mode

TM_ON = 0

CAL_MODE = 0

TM

EP4

End

TDA18211ThermometerRead

001aag950

Fig 20. Flowchart TDA18211ThermometerRead

TDA18211HD_5

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9.4.16 Flowchart TDA18211Read

Table 39. TDA18211Read

Function

Description

Input

Description

Reference

read the 16 ﬁrst bytes of the TDA18211HD

MS

Table

-

Output

an image of the tuner registers from TM to MD3

The software internal table registers are not updated throughout a read procedure. The

update is performed at the level of the call TDA18211Read.

Start TDA18211Read

(1)

MS

Choose Read address = f(MS)

AddRead

Read the 16d first bytes

Start Cx 00 zz … zz Stop

AddRead

TM ...MD3

16d bytes

End TDA18211Read

001aag951

AddRead = C1, C3, C5 or C7.

Fig 21. Flowchart TDA18211Read

TDA18211HD_5

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9.4.17 Flowchart TDA18211ReadExtended

Table 40. TDA18211ReadExtended

Function

Description

Input

Description

Reference

read the 39 ﬁrst bytes of the TDA18211HD

MS

Table

-

Output

an image of the tuner registers from TM to EB23

The software internal table registers are not updated throughout a read procedure. The

update is performed at the level of the call TDA18211ReadExtended.

Start TDA18211ReadExtended

(1)

MS

Choose Read address = f(MS)

AddRead

Read the 39d first bytes

Start Cx 00 zz … zz Stop

AddRead

TM ...EB23

39d bytes

End TDA18211ReadExtended

001aag952

AddRead = C1, C3, C5 or C7.

Fig 22. Flowchart TDA18211ReadExtended

9.5 Maps

Table 41. STANDARD_DESCRIPTION_map

Standard^[1]

Recommended value with a TDA10048HN channel decoder

STD[2:0]

100

IF_LEVEL[2:0]

IF_NOTCH

EB22[7:0]

0011 0111

f_IF(MHz)

3.25

3.30

3.50

4.00

4

ATSC 6 MHz

DVB-T 6 MHz

DVB-T 7 MHz

DVB-T 8 MHz

QAM 6 MHz

QAM 8 MHz

001

1

100

101

111

5

[1] Digital standard settings may vary, depending on channel decoder used.

Table 42. BP_FILTER_map

f_RF(max)(kHz)

180000

BP_FILTER[2:0]

101

110

865000

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Table 43. RF_BAND_map

f_RF(max)RF_BAND Used in ﬂowchart

RF1_

RF2_

RF3_

(kHz)

[2:0]

default default default

RF_A1

RF_B1

RF_A2

RF_B2

RF1

RF2

RF3

(kHz)

203500 100

457800 101

865000 110

RF_A1_4 RF_B1_4 RF_A2_4 RF_B2_4 RF1_4

0

186250

0

RF_A1_5 RF_B1_5 RF_A2_5 RF_B2_5 RF1_5 RF2_5 RF3_5 230000 345000 426000

RF_A1_6 RF_B1_6 RF_A2_6 RF_B2_6 RF1_6 RF2_6 RF3_6 489500 697500 842000

Table 44. KM_map

f_RF(max)(kHz)

350000

RFC_K[2:0]

011

RFC_M[1:0]

00

01

11

720000

010

865000

011

Table 45. MAIN_PLL_map

f_LO(max)(kHz)

180500

MAIN_POST_DIV[6:0]

Div^[1]

2Ch

28h

24h

20h

1Eh

1Ch

1Ah

18h

16h

14h

12h

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

33h

32h

31h

30h

27h

26h

25h

24h

23h

22h

21h

20h

17h

16h

15h

14h

13h

12h

11h

10h

198750

220750

248500

265000

284000

305500

331000

361000

397500

441500

497000

530000

568000

611000

662000

722000

795000

883000

994000

[1] Used in Section 9.4.13 “Flowchart TDA18211CalcMAINPLL”.

TDA18211HD_5

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Table 46. CAL_PLL_map

f_LO(max)(kHz)

175750

195250

219750

251250

270500

293000

319500

351500

390500

439500

502500

541000

586000

639000

703000

781000

879000

CAL_POST_DIV[7:0]

Div^[1]

28h

24h

20h

1Ch

1Ah

18h

16h

14h

12h

10h

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

BAh

B9h

B8h

B3h

ADh

ACh

ABh

AAh

A9h

A8h

A3h

9Dh

9Ch

9Bh

9Ah

99h

98h

[1] Used in Section 9.4.14 “Flowchart TDA18211CalcCALPLL”.

Table 47. GAIN_TAPER_map

f_RF(max)(kHz)

-

f_RF(max)(kHz)

476300

494800

513300

531800

550300

568900

587400

605900

624400

642900

661400

679900

698400

716900

735400

753900

772500

791000

809500

828000

GAIN_TAPER[4:0]^[1]

-

19h

18h

17h

16h

15h

14h

13h

12h

11h

10h

0Fh

0Eh

0Dh

0Ch

0Bh

0Ah

09h

08h

07h

06h

-

175800

-

181300

-

186900

216200

228900

241600

254400

267100

279800

292500

305200

317900

330700

343400

356100

368800

381500

394200

192400

198000

203500

-

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

45 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 47. GAIN_TAPER_map …continued

f_RF(max)(kHz)

406900

419700

432400

445100

457800

-

f_RF(max)(kHz)

GAIN_TAPER[4:0]^[1]

-

846500

05h

04h

03h

02h

01h

00h

865000

-

[1] The gain taper function compensates for any systematic RF gain ripple and makes it ﬂat versus frequency.

Table 48. RF_CAL_DC_OVER_DT_map

f_RF(max)(kHz) dCoverdT^[1]f_RF(max)(kHz) dCoverdT^[1]f_RF(max)(kHz) dCoverdT^[1]f_RF(max)(kHz) dCoverdT^[1]

203500

353000

356000

359000

363000

366000

369000

373000

376000

379000

383000

386000

389000

393000

396000

399000

402000

404000

407000

409000

412000

414000

32h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

417000

419000

422000

424000

427000

429000

432000

434000

437000

439000

442000

444000

447000

449000

457800

465000

477000

483000

502000

508000

519000

522000

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

0Fh

12h

14h

19h

1Bh

1Ch

1Dh

524000

534000

549000

554000

584000

589000

658000

664000

669000

699000

704000

709000

714000

724000

729000

739000

744000

749000

754000

759000

764000

769000

1Eh

1Fh

20h

22h

24h

26h

27h

2Ch

2Dh

2Eh

30h

31h

32h

33h

36h

38h

39h

3Bh

3Ch

3Dh

3Eh

3Fh

774000

779000

784000

789000

794000

799000

804000

809000

814000

819000

824000

829000

834000

839000

844000

849000

854000

859000

865000

-

40h

41h

43h

46h

48h

4Bh

4Fh

54h

59h

5Dh

61h

68h

6Eh

75h

7Eh

82h

84h

8Fh

9Ah

-

[1] Used in ﬂowcharts.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

46 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 49. RF_CAL_map

f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_

(kHz) table (kHz) table (kHz) table (kHz) table (kHz) table (kHz) table

174000 18h

175000 1Ah

176000 1Bh

178000 1Dh

179000 1Eh

180000 1Fh

181000 20h

182000 21h

183000 22h

184000 24h

185000 25h

186000 26h

187000 27h

188000 29h

189000 2Ah

190000 2Ch

191000 2Dh

192000 2Eh

193000 2Fh

194000 30h

195000 33h

196000 35h

198000 36h

200000 38h

201000 3Ch

202000 3Dh

203500 3Eh

206000 0Eh

208000 0Fh

212000 10h

216000 11h

217000 12h

218000 13h

220000 14h

222000 15h

225000 16h

228000 17h

231000 18h

234000 19h

235000 1Ah

267000 29h

269000 2Ah

271000 2Bh

273000 2Ch

275000 2Dh

277000 2Eh

279000 2Fh

282000 30h

284000 31h

286000 32h

287000 33h

290000 34h

293000 35h

295000 36h

297000 37h

300000 38h

303000 39h

305000 3Ah

306000 3Bh

307000 3Ch

310000 3Dh

312000 3Eh

315000 3Fh

318000 40h

320000 41h

323000 42h

324000 43h

325000 44h

327000 45h

331000 46h

334000 47h

337000 48h

339000 49h

340000 4Ah

341000 4Bh

343000 4Ch

345000 4Dh

349000 4Eh

352000 4Fh

353000 50h

384000 5Fh

385000 60h

386000 61h

388000 62h

390000 63h

393000 64h

394000 65h

396000 66h

397000 67h

398000 68h

400000 69h

402000 6Ah

403000 6Bh

407000 6Ch

408000 6Dh

409000 6Eh

410000 6Fh

411000 70h

412000 71h

413000 72h

414000 73h

417000 74h

418000 75h

420000 76h

422000 77h

423000 78h

424000 79h

427000 7Ah

428000 7Bh

429000 7Dh

432000 7Fh

434000 80h

435000 81h

436000 83h

437000 84h

438000 85h

439000 86h

440000 87h

441000 88h

442000 89h

473000 14h

474000 15h

481000 16h

486000 17h

491000 18h

498000 19h

499000 1Ah

501000 1Bh

506000 1Ch

511000 1Dh

516000 1Eh

520000 1Fh

521000 20h

525000 21h

529000 22h

533000 23h

539000 24h

541000 25h

547000 26h

549000 27h

551000 28

662000 4Ah

665000 4Bh

667000 4Ch

670000 4Dh

673000 4Eh

676000 4Fh

677000 50h

681000 51h

683000 52h

686000 53h

688000 54h

689000 55h

691000 56h

695000 57h

698000 58h

703000 59h

704000 5Ah

705000 5Bh

707000 5Ch

710000 5Dh

712000 5Eh

717000 5Fh

718000 60h

721000 61h

722000 62h

723000 63h

725000 64h

727000 65h

730000 66h

732000 67h

735000 68h

740000 69h

741000 6Ah

742000 6Bh

743000 6Ch

745000 6Dh

747000 6Eh

748000 6Fh

750000 70h

752000 71h

779000 80h

781000 81h

783000 82h

784000 83h

785000 84h

786000 85h

793000 86h

794000 87h

795000 88h

797000 89h

799000 8Ah

801000 8Bh

802000 8Ch

803000 8Dh

804000 8Eh

810000 90h

811000 91h

812000 92h

814000 93h

816000 94h

817000 96h

818000 97h

820000 98h

821000 99h

822000 9Ah

828000 9Bh

829000 9Dh

830000 9Fh

831000 A0h

833000 A1h

835000 A2h

836000 A3h

837000 A4h

838000 A6h

840000 A8h

842000 A9h

845000 AAh

846000 ABh

847000 ADh

848000 AEh

556000 29h

561000 2Ah

563000 2Bh

565000 2Ch

569000 2Dh

571000 2Eh

577000 2Fh

580000 30h

582000 31h

584000 32h

588000 33h

591000 34h

596000 35h

598000 36h

603000 37h

604000 38h

606000 39h

612000 3Ah

615000 3Bh

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

47 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 49. RF_CAL_map …continued

f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_ f_RF(max)Cprog_

(kHz) table (kHz) table (kHz) table (kHz) table (kHz) table (kHz) table

236000 1Bh

237000 1Ch

240000 1Dh

242000 1Eh

244000 1Fh

247000 20h

249000 21h

252000 22h

253000 23h

254000 24h

256000 25h

259000 26h

262000 27h

264000 28h

355000 51h

357000 52h

359000 53h

361000 54h

362000 55h

364000 56h

368000 57h

370000 58h

372000 59h

375000 5Ah

376000 5Bh

377000 5Ch

379000 5Dh

382000 5Eh

445000 8Ah

446000 8Bh

447000 8Ch

448000 8Eh

449000 8Fh

450000 90h

452000 91h

453000 93h

454000 94h

456000 96h

457800 98h

461000 11h

468000 12h

472000 13h

617000 3Ch

621000 3Dh

622000 3Eh

625000 3Fh

632000 40h

633000 41h

634000 42h

642000 43h

643000 44h

647000 45h

650000 46h

652000 47h

657000 48h

661000 49h

754000 72h

757000 73h

758000 74h

760000 75h

763000 76h

764000 77h

766000 78h

767000 79h

768000 7Ah

773000 7Bh

774000 7Ch

776000 7Dh

777000 7Eh

778000 7Fh

852000 AFh

853000 B0h

858000 B1h

860000 B2h

861000 B3h

862000 B4h

863000 B6h

864000 B8h

865000 B9h

-

Table 50. THERMOMETER_map^[1]

TM_D[3:0]

TMVALUE (die temperature)

TM_RANGE = 0

60 °C

TM_RANGE = 1

92 °C

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

62 °C

94 °C

66 °C

98 °C

64 °C

96 °C

74 °C

106 °C

104 °C

100 °C

102 °C

122 °C

120 °C

116 °C

118 °C

108 °C

110 °C

114 °C

112 °C

72 °C

68 °C

70 °C

90 °C

88 °C

84 °C

86 °C

76 °C

78 °C

82 °C

80 °C

[1] Bit TM_ON must be set to logic 1.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

48 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 51. IR_MEAS_map

f_RF(max)(kHz)

IR_MEAS[2:0]

200

600

865

101

110

111

Table 52. CID_TARGET_map

f_RF(max)

186250

230000

345000

426000

489500

697500

842000

CID_Target

count_limit

4000

10

24

14

30

50

58

4000

10. Internal circuitry

Table 53. Internal circuits

Symbol

Pin Description^[1]

Average DC voltage

RF_IN

10

0.8 V

10

001aaf837

CAPRFAGC

LT

12

13

2.8 V

12

001aaf838

0.85 V

13

001aaf839

TDA18211HD_5

Product data sheet

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TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 53. Internal circuits …continued

Symbol

Pin Description^[1]

Average DC voltage

STO

15

0.85 V

15

001aaf840

CAPREGVCO

17

2.8 V (Normal mode)

0 V (Standby mode)

17

001aaf841

MASTERSYNC

19

0.5 × V_CC

19

001aaf842

CAPFILTVCO

20

1.6 V (Normal mode)

0 V (Standby mode)

20

001aaf843

VT_COARSE

VT_FINE

CP_LO

21

22

24

0.5 × V_CC

21

22

001aaf844

001aaf845

24

001aaf846

TDA18211HD_5

Product data sheet

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Table 53. Internal circuits …continued

Symbol

Pin Description^[1]

Average DC voltage

XTALP

26

1.45 V

26

001aaf847

XTALN

27

28

1.45 V

27

001aaf848

FREEZE

3.3 V

28

001aaf849

XTOUT_MS

29

30

high-Z

29

001aaf850

XTOUTP

2.4 V

30

001aaf851

XTOUTN

31

2.4 V

31

001aaf852

TDA18211HD_5

Product data sheet

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TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 53. Internal circuits …continued

Symbol

Pin Description^[1]

Average DC voltage

AS

32

high-Z

32

001aaf853

CP_CAL

34

3.3 V (Normal mode)

0.5 × V_CC(Calibration

mode)

34

001aaf854

VT_CAL

SCL

35

3.3 V (Normal mode)

0.5 × V_CC(Calibration

mode)

35

001aaf855

001aaf856

001aaf857

38

high-Z

38

SDA

39

high-Z

39

CAPREG18

40

1.8 V (Normal mode)

2.0 V (Sleep mode)

40

001aaf858

CAPREG28

42

2.8 V (Normal mode)

2.4 V (Sleep mode)

42

001aaf859

TDA18211HD_5

Product data sheet

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TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 53. Internal circuits …continued

Symbol

Pin Description^[1]

Average DC voltage

IFOUTN

45

1.35 V

45

001aaf860

IFOUTP

46

47

1.35 V

46

001aaf861

V_IFAGC

VSYNC

high-Z

47

001aaf862

001aaf863

51

CAPREGFILTRF 52

2.8 V (Normal mode)

0 V (Sleep mode)

52

001aaf864

[1] ESD protection components are not shown.

11. Limiting values

Table 54. Limiting values^[1]

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

−0.3

Max

+3.6

+5.5

Unit

V

supply voltage

input voltage

V_I

pins SDA and SCL

all other pins

V_CC< 3.3 V

V

−0.3

−40

-

V_CC+ 0.3 V

V_CC> 3.3 V

+3.6

+150

110

-

V

T_stg

T_j

storage temperature

junction temperature

°C

V

V_esd

electrostatic

discharge voltage

EIA/JESD22-A114 (human

body model)

±2000

EIA/JESD22-A115(machine

model)

±200

-

V

[1] The TDA18211HD withstands the latch-up speciﬁcations of JEDEC (JESD78A), with the speciﬁc

recommendation using coupling capacitors on pins RF_IN, LT, STO, XTOUTP and XTOUTN.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

53 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

12. Thermal characteristics

Table 55. Thermal characteristics^[1]

Symbol

Parameter

Conditions

Typ

Unit

R_th(j-c)

thermal resistance

according to JEDEC

19.6

K/W

from junction to case speciﬁcation

[1] The junction temperature can be obtained with the formula T_j= T_amb+ R_th(j-a)× V_CC× I_CC, where R_th(j-a)is

the thermal resistance of the application. R_th(j-a)must be such that the resulting T_jdoes not exceed the

maximum value deﬁned in Table 54.

13. Characteristics

All data in this section refers to Master mode operation.

Table 56. Loop-through characteristics (RF input to loop-through output)

T_amb= 25 °C; V_CC= 3.3 V; for test circuit see Figure 26; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f_RF(lt)

loop-through RF

frequency

center of channel

45

-

864

MHz

VSWR

G_v(lt)

∆G_lt

voltage standing

wave ratio

loop-through output; 75 Ω

nominal impedance

-

3

-

loop-through voltage 75 Ω load

gain

1.5

3

dB

dBc

loop-through gain

variation

in the RF frequency range;

75 Ω load

-

NF_lt

loop-through noise

ﬁgure

Normal mode

5.5

−60

-

[1]

CSO

composite

second-order

distortion

-

CTB

composite triple beat

bypass isolation

-

−63

-

dBc

dB

α_isol(bp)

from loop-through output to

RF input

24

V_L(tun-lto)

leakage voltage

in RF TV band

-

10

-

dBµV

between tuner and

loop-through output

[1] Channel loading assumptions: 129 channels (NTSC 129 frequency plan) at 75 dBµV.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

54 of 66

TDA18211HD

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DVB-T Silicon Tuner IC

Table 57. Slave tuner output characteristics (pin STO)

T_amb= 25 °C; V_CC= 3.3 V; for test circuit see Figure 26; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f_RF(STO)

RF frequency on pin

STO

45

-

864

MHz

Z_o(STO)

G_v(STO)

output impedance on

pin STO

30

35

40

Ω

voltage gain on pin

STO

75 Ω source resistance on

RF input; Z_i= 35 Ω (75 Ω,

VSWR = 2)

POWER_LEVEL[6:5] = 00

POWER_LEVEL[6:5] = 01

POWER_LEVEL[6:5] = 10

POWER_LEVEL[6:5] = 11

-

6

-

dB

9

12

15

Table 58. General characteristics for TV reception (RF input to IF output)

T_amb= 25 °C; V_CC= 3.3 V; IF output level option = 2 V (p-p); IF output load = 1 kΩ on each terminal;

for test circuit see Figure 26; unless otherwise speciﬁed.

Symbol

Supply

V_CC

Parameter

Conditions

Min Typ

Max Unit

supply voltage

supply current

3.13 3.30 3.47 V

180 235 290 mA

I_CC

Normal mode

Standby mode with

40

51

65

mA

loop-through and crystal

oscillator on (default at POR)

Standby mode with only

crystal oscillator on

10

15

20

mA

Device off mode

1

-

2

5

mA

mW

°C

P

power dissipation

780

-

T_amb

ambient

0

70

temperature

Input

f_RF

RF frequency

center of channel

174

-

864 MHz

VSWR

voltage standing

wave ratio

RF input; 75 Ω nominal

impedance

2

3

-

NF_tun

tuner noise ﬁgure

maximum gain

-

5.5

83

6

dB

G_v(tun)maxmaximum tuner

voltage gain

2 V (p-p) IF output selection

71

90

∆G_AGC(tun)tuner AGC gain

68

-

71

80

-

dB

range

V_i(max)

maximum input

voltage

1 dB gain compression, one

analog TV signal at RF input

(−5 dBm)

103

dBµV

V_L(tun-RF)

leakage voltage

between tuner and

RF

at RF input; in RF band

-

0

-

dBµV

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

55 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 58. General characteristics for TV reception (RF input to IF output) …continued

T_amb= 25 °C; V_CC= 3.3 V; IF output level option = 2 V (p-p); IF output load = 1 kΩ on each terminal;

for test circuit see Figure 26; unless otherwise speciﬁed.

Symbol

Output

Parameter

Conditions

Min Typ

Max Unit

V_{o(IF)dif(p-p)}peak-to-peak

differential IF output

IF_LEVEL[2:0] = 000

IF_LEVEL[2:0] = 001

IF_LEVEL[2:0] = 010

IF_LEVEL[2:0] = 111

-

2

-

V

Ω

1.25

1

voltage

0.5

100

Z_o(IF)

IF output

differential mode; magnitude

value

impedance

∆G_AGC(IF)IF AGC GAIN range 2 V (p-p) IF output voltage

-

30

2

-

dB

selection

G_tlt

tilt gain

RF frequency range;

6/7/8 MHz channel

4

f_IF(stpb)lp

low-pass stop-band 60 dB attenuation

IF frequency

6 MHz IF ﬁlter

-

14

16

18

65

-

MHz

dB

7 MHz IF ﬁlter

8 MHz IF ﬁlter

-

α_image

image rejection

53

t_ripple

ripple time

digital TV; difference between

f₁and f₂in digital channel

ATSC 6 MHz;

f₁= 0.75 MHz;

f₂= 5.75 MHz

-

395

-

ns

DVB-T 6 MHz; f₁= 0.8 MHz

and f₂= 5.8 MHz

-

365

478

515

155

180

−89

-

ns

DVB-T 7 MHz; f₁= 0.5 MHz

and f₂= 6.5 MHz

ns

DVB-T 8 MHz; f₁= 0.5 MHz

and f₂= 7.5 MHz

ns

QAM 6 MHz; f₁= 1.5 MHz

and f₂= 6.5 MHz

ns

QAM 8 MHz; f₁= 1.5 MHz

and f₂= 8.5 MHz

ns

ϕ_n

phase noise

IF rejection

1 kHz and 10 kHz, details see

Figure 23

dBc/Hz

α_IF

9 MHz Low-pass ﬁlter

13.75 MHz

35

56

42

66

dB

18 MHz

Various

t_startup(tun)tuner start-up time at power-up

-

1.5

-

s

t_set

setting time

PLL setting time; channel

change

5

ms

[1]

S_dig

digital sensitivity

DVB-T (64 QAM ²⁄₃);

BER = 2.10⁻⁴

-

−82

-

dBm

[1] Measured with TDA10048HN channel decoder.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

56 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

Table 59. Characteristics of terminals

T_amb= 25 °C; V_CC= 3.3 V; 2.2 nF on input pin V_IFAGC; for test circuit see Figure 26; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

IF AGC input: pin V_IFAGC

V_AGC

Z_i

AGC voltage

0

-

V_CC

-

V

input impedance

high-Z

30

Ω

dG_AGC/dV rate of change of

AGC gain with

-

55

dB/V

voltage

Crystal oscillator

f_xtal

Z_i

crystal frequency

input impedance

15.99 16

16.01 MHz

magnitude value

-

500

-

Ω

Crystal oscillator output buffer; pins XTOUTP and XTOUTN

R_o

output resistance

16 MHz output frequency

-

460

0.4

-

Ω

V_o(p-p)

peak-to-peak

output voltage

10 kΩ//10 pF AC load

V

SR_r

SR_f

slew rate of rising

signal

10 kΩ//10 pF AC load

-

40

-

V/µs

slew rate of falling

signal

I²C-bus^[1]

Pin SCL

V_IL

LOW-level input

voltage

ﬁxed input levels

-

1.5

V

V_DDrelated input levels

ﬁxed input levels

-

0.3V_DD

V

V_IH

HIGH-level input

voltage

3

-

V

V_DDrelated input levels

0.7V_DD

-

V

f_SCL

SCL clock

frequency

400

kHz

Pin SDA

V_OH

HIGH-level output

voltage

I_SDA= 3 mA (sink current)

-

0.4

V

V_IL

V_IH

LOW-level input

voltage

ﬁxed input levels

-

1.5

V

V_DDrelated input levels

ﬁxed input levels

-

0.3V_DD

HIGH-level input

voltage

3

-

V_DDrelated input levels

0.7V_DD

[1] Devices that use non-standard supply voltages, which do not conform the intended I²C-bus system levels,

must relate their input levels to the supply voltage to which the pull-up resistors are connected.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

57 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

001aah543

−70

ϕ

n

(dBc/Hz)

(1)

(2)

−80

−90

−100

−110

−120

(3)

170

270

370

470

570

670

770

870

(MHz)

f

RF

(1) Offset is 1 kHz.

(2) Offset is 10 kHz.

(3) Offset is 100 kHz.

Fig 23. Typical phase noise curve

001aah544

0

Selectivity

(dB)

−10

−20

−30

−40

−50

−60

−70

(1)

(2)

(3)

(4)

−2

0

2

6

10

14

18

f

(MHz)

IF

(1) 6 MHz bandwidth ﬁlter.

(2) 7 MHz bandwidth ﬁlter.

(3) 8 MHz bandwidth ﬁlter.

(4) 9 MHz bandwidth ﬁlter.

Fig 24. Typical IF selectivity curves

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

58 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

14. Application information

14.1 Application example

XTAL

V_IFAGC

2

I C-bus (gated)

RF

RF_IN

SURGE

PROTECTION

IFOUTP

IFOUTN

SILICON TUNER

TDA18211

MASTER MODE

CHANNEL

RECEIVER

TDA10048

TS

LTO

SURGE

PROTECTION

TV

STO

1.2 V

2

3.3 V

I C-bus

V_IFAGC

2

I C-bus (gated)

CHANNEL

RECEIVER

TDA10048

SILICON TUNER

TDA18211

SLAVE MODE

TS

IFOUTP

IFOUTN

XTOUTP

XTOUTN

1.2 V

2

3.3 V

I C-bus

reference frequency

001aah541

Fig 25. Example for TDA18211HD of DVB-T dual-tuner reception

14.2 Application notes

Please contact the NXP sales ofﬁce for additional information on dual-tuner DVB-T

applications.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

59 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

16. Package outline

HLQFN64R; plastic thermal enhanced low profile quad flat package; no leads;

64 terminals; resin based; body 9 × 9 × 1.6 mm

SOT903-1

D

B

A

terminal 1

index area

E

A

detail X

C

y

e

1

y

C

1

M

v

C

A

B

e

b

1/2 e

L

1

L

M

w

17

32

33

16

e

E

m

E

h

j

E

l

e

2

E

k

E

1/2 e

n

1

48

terminal 1

index area

64

49

D

h

X

D

j

D

k

D

l

D

m

L

v

w

y

1

0

2.5

scale

5 mm

0.18

0.08

0.1

0.05 0.05

0.1

DIMENSIONS (mm are the original dimensions)

A

D

k

D

l

D

m

E

h

UNIT

b

D

h

D

E

e

2

L

E

l

E

m

E

n

j

1

k

max

2.16

2.06

3.32 1.79

3.22 1.69

9.1

8.9

0.31 0.69

0.21 0.59

0.3

0.2

9.1

8.9

2.92 0.86

2.82 0.76

0.45

0.40

1.79

1.69

0.79

0.69

2.63

2.53

2.02

1.92

mm

1.7

0.5

7.5

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

06-03-29

07-11-14

- - -

SOT903-1

Fig 27. Package outline SOT903-1 (HLQFN64R)

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

61 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

17. Printed-circuit board

17.1 Reﬂow proﬁle

See application note AN10366.

17.2 Desoldering recommendation

See application notes AN10366.

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

62 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

17.3 Footprint layout

H

x

D

P

1/2 P

C

0.065

V

d1

d

V

x

0.12

SL

y1

H

y

A

y

B

y

V

y3

y1

SP

V

SL

y

y1

y2

SP

y

SP

x

SP

x2

SP

SL

x1

SL

x

B

A

x

solder lands

solder paste

solder resist

SP

V

y3

y1

d

d1

x

y1

y2

occupied area

0.3

0.35

0.5

0.8

0.9

0.8

0.9

DIMENSIONS in mm

A

x

A

y

B

x

B

y

SL

y

SL

SP

y

P

C

D

H

x

H

y

x

x1

y1

x

x1

x2

0.500 9.000 9.000 7.880 7.880 0.555 0.250 9.500 9.500 4.610 1.740 3.220 0.640 0.800 2.065

0.3

0.7

Fig 28. Footprint HLQFN64R (SOT903-1)

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

63 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

18. Abbreviations

Table 60. Abbreviations

Acronym

AGC

DVB-T

DVR

ESD

IF

Description

Automatic Gain Control

Digital Video Broadcasting - Terrestrial

Digital Video Recorder

ElectroStatic Discharge

Intermediate Frequency

Low Noise Ampliﬁer

LNA

LO

Local Oscillator

PLL

Phase-Lock Loop

QAM

RoHS

SAW

STB

Quadrature Amplitude Modulation

Restriction of Hazardous Substances

Surface Acoustic Wave

Set-Top Box

VCO

Voltage-Controlled Oscillator

19. Revision history

Table 61. Revision history

Document ID

Release date

20090602

Data sheet status

Change notice

Supersedes

TDA18211HD_5

Modiﬁcations:

Product data sheet

-

TDA18211HD_4

• Figure 21 “Flowchart TDA18211Read” updated

TDA18211HD_4

TDA18211HD_3

TDA18211HD_2

TDA18211HD_1

20090505

20080304

20071121

20070802

Product data sheet

-

TDA18211HD_3

TDA18211HD_2

TDA18211HD_1

-

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

64 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Limiting values — Stress above one or more limiting values (as deﬁned in

20.2 Deﬁnitions

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

20.3 Disclaimers

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

20.4 Licenses

ICs with DVB-T functionality

Use of this product in any manner that complies with the DVB-T Standard

may require licenses under applicable patents in the DVB-T patent portfolio,

which license is available from Sisvel S.p.A., Via Sestriere 100, 10060 None

(TO), Italy, and under applicable patents of other parties.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

20.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

I²C-bus — logo is a trademark of NXP B.V.

Silicon Tuner — is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

65 of 66

TDA18211HD

NXP Semiconductors

DVB-T Silicon Tuner IC

22. Contents

1

2

General description . . . . . . . . . . . . . . . . . . . . . . 1

9.4.9

9.4.10

9.4.11

Flowchart TDA18211CalibrateRF . . . . . . . . . 33

Flowchart TDA18211MSPOR . . . . . . . . . . . . 35

Flowchart

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

3.1

3.2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Target applications . . . . . . . . . . . . . . . . . . . . . . 1

Key beneﬁts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

TDA18211RFtrackingFiltersCorrection . . . . . 35

Flowchart TDA18211ChannelConﬁguration. . 37

Flowchart TDA18211CalcMAINPLL. . . . . . . . 39

Flowchart TDA18211CalcCALPLL. . . . . . . . . 40

Flowchart TDA18211ThermometerRead . . . . 41

Flowchart TDA18211Read. . . . . . . . . . . . . . . 42

Flowchart TDA18211ReadExtended . . . . . . . 43

Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.4.12

9.4.13

9.4.14

9.4.15

9.4.16

9.4.17

9.5

4

5

6

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

10

11

12

13

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 49

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 53

Thermal characteristics . . . . . . . . . . . . . . . . . 54

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54

8

Functional description . . . . . . . . . . . . . . . . . . . 6

Master and slave operation. . . . . . . . . . . . . . . . 6

Tuner outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Loop-through output . . . . . . . . . . . . . . . . . . . . . 6

Slave tuner output. . . . . . . . . . . . . . . . . . . . . . . 6

Crystal input mode . . . . . . . . . . . . . . . . . . . . . . 7

Crystal output mode . . . . . . . . . . . . . . . . . . . . . 7

8.1

8.2

8.2.1

8.2.2

8.3

8.4

14

14.1

14.2

Application information . . . . . . . . . . . . . . . . . 59

Application example . . . . . . . . . . . . . . . . . . . . 59

Application notes . . . . . . . . . . . . . . . . . . . . . . 59

15

16

Test information. . . . . . . . . . . . . . . . . . . . . . . . 60

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 61

9

Control interface . . . . . . . . . . . . . . . . . . . . . . . . 7

I²C-bus format, write/read mode. . . . . . . . . . . . 7

I²C-bus at power-on reset. . . . . . . . . . . . . . . . 10

Description of symbols used in I²C-bus

9.1

9.2

9.3

17

Printed-circuit board . . . . . . . . . . . . . . . . . . . . 62

Reﬂow proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . 62

Desoldering recommendation . . . . . . . . . . . . 62

Footprint layout. . . . . . . . . . . . . . . . . . . . . . . . 63

17.1

17.2

17.3

format table. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I²C-bus address selection. . . . . . . . . . . . . . . . 13

Description of chip ID byte . . . . . . . . . . . . . . . 13

Description of temperature sensor byte . . . . . 13

Description of power level byte (read mode) . 14

Description of Easy Prog byte 1 . . . . . . . . . . . 15

Description of Easy Prog byte 2 . . . . . . . . . . . 15

Description of Easy Prog byte 3 . . . . . . . . . . . 15

Description of Easy Prog byte 4 . . . . . . . . . . . 16

Description of Easy Prog byte 5 . . . . . . . . . . . 17

Description of Cal Post-Divider byte . . . . . . . . 17

Description of Cal divider bytes 1, 2 and 3 . . . 17

Description of Main Post-Divider byte. . . . . . . 18

Description of Main divider bytes 1, 2 and 3. . 18

Description of Extended bytes 1 to 23 . . . . . . 19

I²C-bus programming ﬂowcharts . . . . . . . . . . 22

Flowchart explanation. . . . . . . . . . . . . . . . . . . 22

Flowchart TDA18211SetRf_dual . . . . . . . . . . 25

Flowchart TDA18211InitCal . . . . . . . . . . . . . . 26

Flowchart TDA18211FixedContentsI2Cupdate 27

Flowchart TDA18211CalcRFFilterCurve . . . . 28

Flowchart TDA18211RFTrackingFiltersInit . . . 29

Flowchart TDA18211PowerScanInit. . . . . . . . 31

Flowchart TDA18211PowerScan . . . . . . . . . . 31

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.3.7

9.3.8

9.3.9

9.3.10

9.3.11

9.3.12

9.3.13

9.3.14

9.4

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

18

19

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 64

Revision history . . . . . . . . . . . . . . . . . . . . . . . 64

20

Legal information . . . . . . . . . . . . . . . . . . . . . . 65

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 65

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20.1

20.2

20.3

20.4

20.5

21

22

Contact information . . . . . . . . . . . . . . . . . . . . 65

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 June 2009

Document identifier: TDA18211HD_5


型号：	TDA18211HDC2
厂家：	NXP
描述：	DVB-T Silicon Tuner IC DVB -T硅调谐器IC
文件：	总66页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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