TDA19977BHV15C1S1, [NXP]
SOT612-3 Package, Standard Marking, Tray Dry Pack, Bakeable, Single;
| 型号： | TDA19977BHV15C1S1, |
| 厂家： | 
NXP |
| 描述： | SOT612-3 Package, Standard Marking, Tray Dry Pack, Bakeable, Single |
| 文件： | 总40页 (文件大小：1160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA19977A; TDA19977B
Triple input HDMI 1.4a compliant receiver interface with
equalizer (up to 1080p for HDTV, and UXGA for PC formats
Rev. 3 — 19 November 2010
Product data sheet
1. General description
The TDA19977A; TDA19977B is a three input HDMI 1.4a compliant receiver with
embedded EDID memory. The built-in auto-adaptive equalizer, improves signal quality
and allows the use of cable lengths of up to 25 m which are laboratory tested with a
0.5 mm (24 AWG) cable at 2.05 gigasamples per second. The HDCP (TDA19977A only)
key set is stored in non-volatile OTP (One Time Programmable) memory for maximum
security. In addition, the TDA19977A; TDA19977B is delivered with software drivers to
ease configuration and use.
The TDA19977A; TDA19977B supports:
• TV resolutions:
– 480i (1440 × 480i at 60 Hz), 576i (1440 × 576i at 50 Hz) to HDTV (up to
1920 × 1080p at 50/60 Hz)
– WUXGA (1920 × 1200p at 60 Hz) reduced blanking format
• PC resolutions:
– VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz)
• Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock)
• Gamut boundary description
• IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR
(High Bit Rate) stream
The TDA19977A; TDA19977B includes:
• An enhanced PC and TV format recognition system
• Generation of a 128/256/512 × fs system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
• An embedded oscillator (an external crystal can also be used)
• Improved audio clock generation using an external reference clock
• OBA (as used in SACD), DST and HBR stream support
The TDA19977A; TDA19977B converts HDMI streams with or without HDCP
(TDA19977A only) into RGB or YCbCr digital signals. The YCbCr digital output signal can
be 4:4:4 or 4:2:2 semi-planar format based on the ITU-R BT.601 standard or 4:2:2 based
on the ITU-R BT.656 format. The device can adjust the output timing of the video port by
altering the values of tsu(Q) and th(Q). In addition, all settings are controllable using the
I2C-bus.
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
2. Features and benefits
Complies with the HDMI 1.4a, DVI 1.0, CEA-861-D and HDCP (TDA19977A only)
1.4 standards
Three independent HDMI inputs, up to the HDMI frequency of 205 MHz
Embedded auto-adaptive equalizer on all HDMI links
EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
Supports color depth processing (8-bit, 10-bit or 12-bit per color)
Color gamut metadata packet with interrupt on each update, readable via the I2C-bus
Up to four S/PDIF or I2S-bus outputs (eight channels) at a sampling rate up to 192 kHz
with IEC 60958/IEC 61937 stream
HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I2S-bus outputs
HBR streams (compatible with DTS-HD master audio and Dolby TrueHD up to eight
channels due to HBR packet for stream with a frame rate up to 768 kHz) support
DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
Channel status decoder supports multi-channel reception
Improved audio clock generation using an external reference clock
System/master clock output (128/256/512 × fs) enables the use of the UDA1334BTS
The HDMI interface supports:
All HDTV formats up to 1920 × 1080p at 50/60 Hz and WUXGA (1920 × 1200p at
60 Hz) with support for reduced blanking
3D formats including all primary formats up to 1920 × 1080p at 30 Hz Frame
Packing and 1920 × 1080p at 60 Hz Top-and-Bottom
PC formats up to UXGA (1600 × 1200p at 60 Hz)
Embedded oscillator (an external crystal can be used)
Frame and field detection for interlaced video signal
Sync timing measurements for format recognition
Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
HDCP (TDA19977A only) with repeater capability
Embedded non-volatile memory storage of HDCP (TDA19977A only) keys
Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
8-bit, 10-bit or 12-bit output formats selectable using the I2C-bus (8-bit and 10-bit only
in 4:4:4 format)
I2C-bus adjustable timing of video port (tsu(Q) and th(Q)
)
Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode
Internal video and audio pattern generator
Controllable using the I2C-bus; 5 V tolerant and bit rate up to 400 kbit/s
DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
LV-TTL outputs
Power-down mode
CMOS process
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
2 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
1.8 V and 3.3 V power supplies
Lead-free (Pb) HLQFP144 package
3. Applications
HDTV
High-end TV
YCbCr or RGB HI-Speed video digitizer
Projector, plasma and LCD TV
Rear projection TV
Home theater amplifier
DVD recorder
AVR and HDMI splitter
4. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Digital inputs: pins RXxC+, RXxC− [1]
fclk(max)
maximum clock frequency
205
-
-
MHz
Clock timing output: pins VCLK, ACLK and SYSCLK
fclk(max)
maximum clock frequency
pin VCLK
165
25
-
-
-
-
-
-
MHz
MHz
MHz
pin ACLK
pin SYSCLK
50
Supplies
VDDH(3V3) HDMI supply voltage (3.3 V)
VDDH(1V8) HDMI supply voltage (1.8 V)
VDDI(3V3) input supply voltage (3.3 V)
VDDC(1V8) core supply voltage (1.8 V)
VDDO(3V3) output supply voltage (3.3 V)
3.135
1.71
3.3
1.8
3.3
1.8
3.3
3.465
1.89
V
V
V
V
V
3.135
1.71
3.465
1.89
3.135
3.465
[2]
P
power dissipation
Active mode
720p at 60 Hz
-
-
-
0.75
1.13
1.63
-
-
-
W
W
W
1080p at 60 Hz
1080p at 60 Hz; Deep Color mode
Power-down mode
pin PD = HIGH
I2C-bus; EDID and HDCP[3] memory
power-up
Pcons
power consumption
-
-
1
4
-
-
mW
mW
I2C-bus; EDID; activity detection and
HDCP[3] memory power-up
-
150
-
mW
[1] x = A, B or C.
[2] At 30 % activity on video port output.
[3] HDCP decoding is only supported by the TDA19977A.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
3 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA19977AHV
TDA19977BHV
HLQFP144
HLQFP144
plastic thermal enhanced low profile quad flat package;
144 leads; body 20 × 20 × 1.4 mm; exposed die pad
SOT612-3
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
4 of 40
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
AP4/WS
AP0 to AP3
ACLK
AUDIO
PLL
AUDIO
FORMATTER
HDMI A (channels 0/1/2)
HDMI A (channel A)
RRX1
TERMINATION
RESISTANCE
CONTROL
SYSCLK/AP5
(1)
OTP
MEMORY
PACKET
EXTRACTION
AUDIO
FIFO
HDMI B (channels 0/1/2)
HDMI B (channel B)
TERMINATION
RESISTANCE
CONTROL
HDMI
RECEIVER
AND
VP[29:0]
VCLK
COLOR
DEPTH
UNPACKING
VIDEO
OUTPUT
FORMATTER
EQUALIZER
HDMI C (channels 0/1/2)
HDMI C (channel C)
TERMINATION
RESISTANCE
CONTROL
HDCP
RRX2
XTALIN/MCLK
POWER
MANAGEMENT
CRYSTAL
OSCILLATOR
EDID
MEMORY
XTALOUT
DE
SYNC
TIMING
MEASUREMENT
TDA19977
VHREF
TIMING
GENERATOR
HS/HREF
VS/VREF
CS/FREF
2
I C-BUS SLAVE
INTERFACE
SDA/SCL
HSDAA/
HSCLA
HSDAB/ HSDAC/
HSCLB HSCLC
001aai381
(1) only used by TDA19977A.
Fig 1. Block diagram of TDA19977A; TDA19977B
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
7. Pinning information
7.1 Pinning
1
108
TDA19977
36
73
001aai382
Fig 2. Pin configuration for TDA19977A; TDA19977B
7.2 Pin description
Table 3.
Pin description
Symbol
VSSC
Pin
1
Type[1] Description
G
I
ground for the digital core
power-down control input (active HIGH)
HDMI receiver supply voltage; 3.3 V
not connected
PD
2
VDDH(3V3)
n.c.
3
P
I
4
n.c.
5
I
not connected
VSSH
6
G
I
HDMI receiver ground
RXCC−
RXCC+
VDDH(3V3)
n.c.
7
HDMI input C negative clock channel
HDMI input C positive clock channel
HDMI receiver supply voltage; 3.3 V
not connected
8
I
9
P
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
n.c.
I
not connected
VSSH
G
I
HDMI receiver ground
RXC0−
RXC0+
VDDH(1V8)
n.c.
HDMI input C negative data channel 0
HDMI input C positive data channel 0
HDMI receiver supply voltage; 1.8 V
not connected
I
P
I
n.c.
I
not connected
VSSH
G
I
HDMI receiver ground
RXC1−
RXC1+
VDDH(3V3)
n.c.
HDMI input C negative data channel 1
HDMI input C positive data channel 1
HDMI receiver supply voltage; 3.3 V
not connected
I
P
I
n.c.
I
not connected
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
6 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 3.
Pin description …continued
Symbol
VSSH
Pin
24
25
26
27
28
29
30
31
32
Type[1] Description
G
I
HDMI receiver ground
RXC2−
RXC2+
VPP
HDMI input C negative data channel 2
HDMI input C positive data channel 2
OTP memory programming voltage[2]
digital core supply voltage; 1.8 V
video port output supply voltage; 3.3 V
video clock output
I
P
P
P
O
G
O
VDDC(1V8)
VDDO(3V3)
VCLK
VSSO
video port output ground
composite synchronization output
composite field output signal
vertical synchronization output
vertical reference output
horizontal synchronization output
reference output
CS/FREF
VS/VREF
HS/HREF
33
34
O
O
DE
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
O
O
G
O
O
O
P
data enable output
VP[0]
video port output bit 0
VSSC
digital core ground
VP[1]
video port output bit 1
VP[2]
video port output bit 2
VP[3]
video port output bit 3
VDDO(3V3)
VDDC(1V8)
VSSO
video port output supply voltage; 3.3 V
digital core supply voltage; 1.8 V
video port output ground
video port output bit 4
P
G
O
O
O
O
O
O
O
O
P
VP[4]
VP[5]
video port output bit 5
VP[6]
video port output bit 6
VP[7]
video port output bit 7
VP[8]
video port output bit 8
VP[9]
video port output bit 9
VP[10]
VP[11]
VDDO(3V3)
VP[12]
VSSO
video port output bit 10
video port output bit 11
video port output supply voltage; 3.3 V
video port output bit 12
O
G
O
O
O
O
O
O
O
video port output ground
video port output bit 13
VP[13]
VP[14]
VP[15]
VP[16]
VP[17]
VP[18]
VP[19]
video port output bit 14
video port output bit 15
video port output bit 16
video port output bit 17
video port output bit 18
video port output bit 19
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
7 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 3.
Pin description …continued
Type[1] Description
Symbol
VP[20]
VDDO(3V3)
VDDC(1V8)
VSSO
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
O
P
video port output bit 20
video port output supply voltage; 3.3 V
digital core supply voltage; 1.8 V
video port output ground
video port output bit 21
P
G
O
O
O
O
O
O
O
G
P
VP[21]
VP[22]
VP[23]
VP[24]
VP[25]
VP[26]
VP[27]
VSSC
video port output bit 22
video port output bit 23
video port output bit 24
video port output bit 25
video port output bit 26
video port output bit 27
digital core ground
VDDO(3V3)
VP[28]
VP[29]
VSSO
video port output supply voltage; 3.3 V
video port output bit 28
O
O
G
O
O
O
O
O
O
video port output bit 29
video port output ground
audio clock output
ACLK
AP0
audio port 0 output
AP1
audio port 1 output
AP2
audio port 2 output
AP3
audio port 3 output
AP4/WS
audio port 4 output
word select output
VDDO(3V3)
84
85
P
video port output supply voltage; 3.3 V
audio port 5 output
AP5/SYSCLK
O
system clock audio output
video port output ground
HDMI audio PLL supply voltage; 3.3 V
HDMI audio PLL supply voltage; 3.3 V
HDMI audio PLL ground
HDMI audio PLL supply voltage; 1.8 V
HDMI audio PLL ground
digital core supply voltage; 1.8 V
crystal oscillator output
VSSO
86
87
88
89
90
91
92
93
94
G
P
P
G
P
G
P
O
I
VDDH(3V3)
VDDH(3V3)
VSSH
VDDH(1V8)
VSSH
VDDC(1V8)
XTALOUT
XTALIN/MCLK
crystal oscillator input
test pattern clock input
VDDI(3V3)
VAI
95
96
P
digital inputs supply voltage; 3.3 V
O
video activity indication output (open-drain); warns the
external microprocessor that a special event has
occurred; must be connected to a pull-up resistor; 5 V
tolerant (active LOW)
SDA
97
I/O
I2C-bus serial data input/output
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
8 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 3.
Pin description …continued
Symbol
SCL
Pin
98
Type[1] Description
I
I2C-bus serial clock input
HSDAA
HSCLA
HSDAB
HSCLB
TEST0
VDDH(3V3)
VSSH
99
I/O
I
HDMI input/output A (HDCP[3]) DDC-bus serial data
HDMI input A (HDCP[3]) DDC-bus serial clock
HDMI input/output B (HDCP[3]) DDC-bus serial data
HDMI input B (HDCP[3]) DDC-bus serial clock
reserved for test; connect to digital inputs ground (VSSC
HDMI deep PLL supply voltage; 3.3 V
HDMI deep PLL ground
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
I/O
I
I
)
P
G
I
RRX1
HDMI inputs A and B termination resistance control
digital core supply voltage; 1.8 V
VDDC(1V8)
VDDH(1V8)
VSSC
P
P
G
I
HDMI receiver supply voltage; 1.8 V
digital core ground
I2C-bus address control input
A0
VDDH(3V3)
RXBC+
RXBC−
VSSH
P
I
HDMI receiver supply voltage; 3.3 V
HDMI input B positive clock channel
HDMI input B negative clock channel
HDMI receiver ground
I
G
I
RXAC−
RXAC+
VDDH(3V3)
RXB0+
RXB0−
VSSH
HDMI input A negative clock channel
HDMI input A positive clock channel
HDMI receiver supply voltage; 3.3 V
HDMI input B positive data channel 0
HDMI input B negative data channel 0
HDMI receiver ground
I
P
I
I
G
I
RXA0−
RXA0+
VDDH(1V8)
RXB1+
RXB1−
VSSH
HDMI input A negative data channel 0
HDMI input A positive data channel 0
HDMI receiver supply voltage; 1.8 V
HDMI input B positive data channel 1
HDMI input B negative data channel 1
HDMI receiver ground
I
P
I
I
G
I
RXA1−
RXA1+
VDDH(3V3)
RXB2+
RXB2−
VSSH
HDMI input A negative data channel 1
HDMI input A positive data channel 1
HDMI receiver supply voltage; 3.3 V
HDMI input B positive data channel 2
HDMI input B negative data channel 2
HDMI receiver ground
I
P
I
I
G
I
RXA2−
RXA2+
VSSH
HDMI input A negative data channel 2
HDMI input A positive data channel 2
HDMI receiver ground
I
G
P
P
I/O
VDDC(1V8)
VDDC(1V8)
HSDAC
digital core supply voltage; 1.8 V
digital core supply voltage; 1.8 V
HDMI input/output C (HDCP[3]) DDC-bus serial data
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
9 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 3.
Pin description …continued
Symbol
HSCLC
n.c.
Pin
139
140
141
142
143
144
-
Type[1] Description
I
HDMI input C (HDCP[3]) DDC-bus serial clock
I/O
I
not connected
n.c
not connected
VDDI(3V3)
RRX2
P
I
digital inputs supply voltage; 3.3 V
HDMI inputs C and D termination resistance control
HDMI receiver supply voltage; 1.8 V
exposed die pad; connect to digital core ground (VSSC
VDDH(1V8)
Exposed die pad
P
G
)
[1] P = power supply; G = ground; I = input; O = output and I/O = input/output.
[2] Connected to the ground of the HDMI receiver (VSSH) in normal operation.
[3] HDCP decoding is only supported by TDA19977A.
8. Functional description
The TDA19977A; TDA19977B converts digital data streams input by the HDMI sources
into parallel digital data for use by media and video signal processing integrated circuits in
devices for HDTV. Data streams can be decoded with or without HDCP protection.
Outputs from the TDA19977A; TDA19977B can be RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2
semi-planar format based on the ITU-R BT.601 standard or YCbCr 4:2:2 based on the
ITU-R BT.656 format. Inputs can be both progressive and interlaced formats. The
TDA19977A; TDA19977B comprises a color space conversion block, downsampling
filters and an embedded timing code function. In addition, the HDCP (TDA19977A only)
repeater function enables other HDMI devices to be connected to form an extended “total
application”.
8.1 Software drivers
Software drivers are provided for easy configuration and use of the TDA19977A;
TDA19977B. These drivers can be integrated with a large range of processors, with or
without an operating system. They control activity detection, input selection, video mode
identification, color conversion, Power-down modes, HDCP (TDA19977A only) and Info
Frame notification.
8.2 HDMI inputs
Control of the three HDMI inputs can be automatic using activity detection or using the
I2C-bus. The HDMI receiver inputs are defined by pins RXx0+, RXx0−, RXx1+, RXx1−,
RXx2+, RXx2−, RXxC+, RXxC−, RRXx, HSCLx and HSDAx. In the pin names, x equals A,
B or C (as applicable).
8.3 Termination resistance control
The HDMI receiver input contains a termination resistance control set by an external
resistor connected between pins RRXx and VDDH(3V3). In RRXx, x equals 1 for inputs A
and B or 2 for inputs C and D. Typically, the characteristic impedance is 50 Ω and the
default value of the external terminal control resistor is 12 kΩ ± 1 %.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
10 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
8.4 Equalizer
The auto-adaptive equalizer automatically measures and selects the settings which
provide the best signal quality for each cable. This improves signal quality and enables
the use of cable lengths up to 25 m (laboratory tested, contact NXP for detailed
information). The equalizer is fully automatic and consequently does not need any
external control.
8.5 Activity detection
The TDA19977A; TDA19977B uses activity detection to automatically select the active
HDMI input. An internal, fully programmable, frequency filter controls activity detection. It
sees only the activity on the HDMI inputs with a frequency range between fmin (22.5 MHz)
and fmax (205 MHz).
This activity detection can generate an interrupt enabling users to manage each HDMI
input.
8.6 High-bandwidth digital content protection (TDA19977A only)
The HDMI receiver also contains the HDCP decryption function. The keys provided by the
OTP non-volatile memory in encrypted format are decrypted and then stored in the HDCP
module. This is particularly suitable for repeater applications. The TDA19977A manages
all HDCP repeater functions based on the HDCP 1.4 specification.
Three DDC-buses HSCLA/HSDAA; HSCLB/HSDAB and HSCLC/HSDAC are integrated
into the HDCP function, one bus for each HDMI input. The DDC-bus connected to the
HDCP block is automatically selected based on the active HDMI input. The unused inputs
are disconnected from the DDC-bus (no acknowledge). No additional CPU processing is
required because the authentication phase and the re-key calculation are fully managed
by the TDA19977A.
8.7 Color depth unpacking
In Deep Color mode, the TDA19977A; TDA19977B receives several fragments of a pixel
group at the HDMI link frequency. This block translates the received pixel group into pixels
at the pixel frequency. This operation is fully automatic and does not need any external
control.
8.8 Derepeater
The HDMI source uses pixel repetition to increase the transmitted pixel clock for
transmitting video formats at native pixel rates below 25 Mpixel/s or to increase the
number of audio sample packets in each line. The derepeater function discards repeated
pixels and divides the clock to reproduce the native video format.
8.9 Upsample
The HDMI source can use YCbCr 4:2:2 pixel encoding which enables the number of bits
allocated per component to be increased up to 12. The upsample function transforms this
12-bit YCbCr 4:2:2 data stream into a 12-bit YCbCr 4:4:4 data stream by repeating or
linearly interpolating the chrominance pixels Cb and Cr.
Upsampling mode is selected using the I2C-bus.
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Triple input HDMI receiver interface with digital processing
8.10 Packet extraction
Information sent during the Data Island periods are extracted from the HDMI data stream.
Audio clock regeneration, general control and Info Frames can be read using the I2C-bus
while audio samples are sent to the audio FIFO.
The TDA19977A; TDA19977B can receive the new HDMI 1.4a packets, general control
and color gamut metadata information packets.
In audio applications, the TDA19977A; TDA19977B manages HBR packets for high bit
rate compressed audio streams (IEC 61937), OBA samples and DST packets for OBA
and SACD with DSD and DST audio streams.
The TDA19977A; TDA19977B includes a two channel status decoder supporting
multi-channel reception for audio sample packets. This enables the user to obtain channel
status information from the IEC 60958/IEC 61937 stream such as:
• The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)
• Copyright protection
• Sampling frequency
Refer to IEC 60958/IEC 61937 specifications for more details.
An update of each Info Frame or the channel status content is indicated by a register bit
and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
8.11 Audio PLL
The TDA19977A; TDA19977B generates a 128/256/512 × fs system clock enabling the
use of simple audio DACs without an integrated PLL, such as the UDA1334BTS. The
programming of the audio PLL can be either automatic, using the audio clock
regeneration parameters found in the Data Islands or set manually using the I2C-bus.
All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,
96 kHz and 192 kHz are accepted by the device.
8.12 Audio formatter
Audio samples can be output in either S/PDIF, I2S-bus formats or DSD (SACD). In I2S-bus
or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins
(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using
these pins. The audio port mapping depends on the channel allocation (see Table 4,
Table 5 and Table 6 for detailed information).
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Triple input HDMI receiver interface with digital processing
Table 4.
Audio port configuration (Layout 0)
All audio ports are LV-TTL compatible.
Audio port Pin
Layout 0
I2S-bus
SYSCLK[1]
S/PDIF
SYSCLK[1]
WS[1]
OBA
AP5
AP4
AP3
AP2
AP1
AP0
ACLK
85
83
82
81
80
79
78
WS (word select)
DSD channel 1
DSD channel 0
DSD clock
SD
S/PDIF
SCK (I2S-bus clock) master clock for S/PDIF[1]
64 × fs
32 × fs
64 × fs
64 × fs
[1] Can be activated with the I2C-bus (optional).
Table 5.
Audio port configuration (Layout 1)
All audio ports are LV-TTL compatible.
Audio port Pin
Layout 0
I2S-bus
SYSCLK[1]
WS (word select)
SD3
S/PDIF
OBA
AP5
AP4
AP3
AP2
AP1
AP0
ACLK
85
83
82
81
80
79
78
SYSCLK[1]
WS[1]
DSD channel 5
DSD channel 4
DSD channel 3
DSD channel 2
DSD channel 1
DSD channel 0
DSD clock
S/PDIF3
S/PDIF2
S/PDIF1
S/PDIF0
SD2
SD1
SD0
SCK (I2S-bus clock) master clock for S/PDIF[1]
64 × fs
32 × fs
64 × fs
64 × fs
[1] Can be activated with the I2C-bus (optional).
Table 6.
Audio port configuration for HBR and DST packets
All audio ports are LV-TTL compatible.
Audio port Pin HBR demultiplexed
DST
I2S-bus
S/PDIF
AP5
AP4
AP3
AP2
AP1
AP0
ACLK
85
83
82
81
80
79
78
SYSCLK[1]
WS (word select)
SDx + 3
SYSCLK[1]
WS[1]
frame_start
S/PDIFx + 3
S/PDIFx + 2
S/PDIFx + 1
S/PDIFx
SDx + 2
SDx + 1
SDx
DSD channel 0
DSD clock
64 × fs
SCK (I2S-bus clock) master clock for S/PDIF[1]
64 × fs (ACR)
32 × fs (ACR)
64 × fs
128 × fs
[1] Can be activated with the I2C-bus (optional).
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Triple input HDMI receiver interface with digital processing
8.13 Sync timing measurement
To assist input format recognition, the vertical/horizontal periods and the horizontal pulse
width are measured based on the externally generated MCLK frequency (27 MHz crystal).
This function has an accuracy of 1 LSB = 1 × MCLK period.
8.14 Format measurement timing
The TDA19977A; TDA19977B includes an improved system for accurate recognition of
PC and TV formats. This system measures the parameters of blanking and video active
area.
This function can be useful for example when the TDA19977A; TDA19977B receives PC
format data in HDMI or DVI modes.
8.15 Color space conversion
The color space conversion enables an RGB signal from the HDMI input to be converted
into a YCbCr signal or converting the YCbCr signal from the HDMI input into an RGB
signal. The color space conversion formula is:
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
C11 C12 C13
C21 C22 C23
C31 C32 C33
YG
VR
UB
CY
RV
BU
O11
O12
O13
OO1
OO2
OO3
=
×
+
+
(1)
Activation of the color space conversion function, programming of all coefficients and
offsets is done using the I2C-bus.
8.16 4:2:2 downsampling filters
These filters downsample the Cb and Cr signals by a factor of 2. A delay has been added
to the G/Y channel corresponding to the downsample filters pipeline delay to make sure
the Y channel is in phase with the Cb and Cr channels.
Four different filters, from simple cut to ITU-R BT.601 compliant digital, can be selected
using the I2C-bus.
8.17 Range control
The range control function truncates the range of data to remove super-white and
super-black pixels at specified ceiling and floor values.
8.18 Dithering function
The error dispersal rounding (dithering) function can convert the color depth from 30-bit or
36-bit to reduced 30-bit or 24-bit color depth. When dithering is triggered, the
TDA19977A; TDA19977B applies round, truncate or noise-shaping algorithms.
When the error dispersal rounding function is not used, the data coming from the filter is
directly sent to the 4:2:2 formatter. The error dispersal rounding function works only with
the active video signal.
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Triple input HDMI receiver interface with digital processing
8.19 4:2:2 formatter
The 4:2:2 formatter contains the YCbCr 4:2:2 semi-planar and the YCbCr 4:2:2
ITU-R BT.656 formatting functions. The selection of these functions is made using the
I2C-bus.
• In YCbCr 4:2:2 mode: the data frequency for the Y signal is equal to the pixel clock
frequency. While the data frequency for the Cb and Cr signals is equal to half the pixel
clock frequency
• In semi-planar mode: the output clock should be the same as the pixel clock
• In ITU-R BT.656 mode: the data frequency should be the same as the formatter clock
frequency (e.g. pixel clock × 2)
The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be
included in the data stream based on the HREF, VREF and FREF positions from the
VHREF timing generator.
Specific codes programmed using the I2C-bus can replace the data stream during the
blanking period to mask gain and clamp calibration.
8.20 Video port selection
Each channel can be allocated to a specified video port using the I2C-bus (see Section 13
“Output video port formats” on page 21) to optimize board layout at the interface with
video processing ICs. For example:
• R, G or B in RGB 4:4:4 mode on VP[29:20]
• Y, Cb or Cr in YUV 4:4:4 mode on VP[19:10]
• Y or Cb-Cr in 4:2:2 semi-planar mode on VP[9:0]
• Cb-Y-Cr-Y in 4:2:2 ITU-R BT.656 mode on VP[9:0]
Each video port can be set to high-impedance using the I2C-bus.
8.21 Output buffers
The levels of the output buffers are LV-TTL compatible. Switching the outputs between
active and high-impedance is set using the I2C-bus.
The outputs HREF, VREF and FREF can be set to high-impedance (Z) or forced LOW (L),
independently of the timing reference codes.
8.22 VHREF timing generator
The VHREF timing generator outputs all of the timing signals used by the device:
• VREF, HREF and FREF signals for SAV, EAV and active video area definition
• VS and HS to change width and position compared with the HDMI inputs
8.23 I2C-bus serial interface
The I2C-bus serial interface enables the internal registers of the device to be
programmed. The slave address of the device is selected by pin A0.
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Triple input HDMI receiver interface with digital processing
8.24 Power management
The TDA19977A; TDA19977B can use one of three Power-down modes:
• level 0: full Power-down mode
• level 1: internal EDID memory with I2C-bus serial interface active
• level 2: internal EDID memory with I2C-bus serial interface and activity detection
enabled
The user can activate these different modes with pin PD or using I2C-bus registers:
• level 0: PD pin is HIGH
• level 1: settings defined in the I2C-bus registers
• level 2: with settings defined in the I2C-bus registers
8.25 EDID memory management
The TDA19977A; TDA19977B embedded EDID memory can be shared with all HDMI
inputs. The embedded EDID memory shares 253 bytes with the three HDMI inputs. In
addition, three bytes are dedicated to the physical address and checksum for each HDMI
input (see Figure 3). This memory is accessible in parallel by all HDMI inputs. You can
share the EDID memory over zero, one, two or three HDMI input(s) as shown in Figure 4.
The content of embedded volatile EDID memory must be programmed using the I2C-bus
for each power-on of TDA19977A; TDA19977B. The embedded EDID memory remains
accessible on each HDMI input when the TDA19977A; TDA19977B uses a different
low-power mode.
The “physical address” of each HDMI input can be easily changed with the TDA19977A;
TDA19977B without corrupting the integrity of each DDC-bus.
8.25.1 EDID memory shared over all three HDMI inputs
EDID: 253 B
2
TDA19977
I C-bus
CPU
3 B
3 B
3 B
(1)
HDMI
HDMI
HDMI
FLASH
INPUT
INPUT
INPUT
EDID CONTENT
001aai383
(1) 253 bytes
+ 3 bytes input A
+ 3 bytes input B
+ 3 bytes input C
+ 1 byte address pointer (subPhys@): this indicates the address in each block where the data for
inputs A, B and C will be copied.
Fig 3. An example of an application with EDID memory shared over all three HDMI
inputs
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NXP Semiconductors
Triple input HDMI receiver interface with digital processing
8.25.2 EDID memory shared over two HDMI inputs
EDID: 253 B
2
I C-bus
CPU
TDA19977
3 B
3 B
EXTERNAL EDID:
256 B or 512 B
DVI or
HDMI
INPUT
(1)
HDMI
INPUT
HDMI
INPUT
FLASH
EDID CONTENT
001aai384
(1) 253 bytes
+ 3 bytes input B
+ 3 bytes input C
+ 1 byte address pointer (subPhys@): this indicates the address in each block where the data for
inputs B and C will be copied.
Fig 4. An example of an application with EDID memory shared over two HDMI inputs
9. I2C-bus protocol
The TDA19977A; TDA19977B is a slave I2C-bus device and the SCL pin is only an input
pin. The timing and protocol for I2C-bus are standard.
Bit A0 of the I2C-bus device address is externally selected by the A0 pin. The main device
I2C-bus address is given in Table 7.
Table 7.
I2C-bus slave address
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
1
1
0
A0
0/1
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDx(3V3)
VDDx(1V8)
ΔVDD
IO
Parameter
Conditions
Min
−0.5
−0.5
−0.5
-
Max
+4.6
+2.5
+0.5
35
Unit
supply voltage on all 3.3 V pins
supply voltage on all 1.8 V pins
supply voltage difference
output current
V
V
V
mA
°C
°C
°C
V
Tstg
storage temperature
ambient temperature
junction temperature
−55
0
+150
70
Tamb
Tj
-
125
VESD
electrostatic discharge voltage HBM
−2000
+2000
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
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Triple input HDMI receiver interface with digital processing
11. Thermal characteristics
Table 9.
Thermal characteristics
Symbol Parameter
Conditions
Typ
22.8
11.1
Unit
K/W
K/W
Rth(j-a)
Rth(j-c)
thermal resistance from junction to ambient in free air
thermal resistance from junction to case
12. Characteristics
Table 10. Characteristics
Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDH(3V3)
VDDH(1V8)
VDDI(3V3)
VDDC(1V8)
VDDO(3V3)
IDDH(3V3)
HDMI supply voltage (3.3 V)
HDMI supply voltage (1.8 V)
input supply voltage (3.3 V)
core supply voltage (1.8 V)
output supply voltage (3.3 V)
HDMI supply current (3.3 V)
3.135 3.3
1.71 1.8
3.135 3.3
1.71 1.8
3.135 3.3
3.465
V
1.89
V
3.465
V
1.89
V
3.465
V
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
720p at 60 Hz
-
103
106
110
48
68
85
1
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mV
1080p at 60 Hz
-
-
1080p at 60 Hz; Deep Color mode
720p at 60 Hz
-
-
IDDH(1V8)
IDDI(3V3)
IDDO(3V3)
IDDC(1V8)
HDMI supply current (1.8 V)
input supply current (3.3 V)
output supply current (3.3 V)
core supply current (1.8 V)
-
-
1080p at 60 Hz
-
-
1080p at 60 Hz; Deep Color mode
720p at 60 Hz
-
-
-
-
1080p at 60 Hz
-
1
-
1080p at 60 Hz; Deep Color mode
720p at 60 Hz
-
1
-
-
49
78
120
148
283
453
-
-
1080p at 60 Hz
-
-
1080p at 60 Hz; Deep Color mode
720p at 60 Hz
-
-
-
-
1080p at 60 Hz
-
-
1080p at 60 Hz; Deep Color mode
-
-
ΔVDD(3V3-3V3) supply voltage difference between start-up and established
two 3.3 V supplies conditions
−100
+100
ΔVDD(1V8-1V8) supply voltage difference between start-up and established
−100
-
+100
mV
two 1.8 V supplies
conditions
[1]
P
power dissipation
active mode
720p at 60 Hz
1080p at 60 Hz
-
-
-
0.75
1.13
1.63
-
-
-
W
W
W
1080p at 60 Hz; Deep Color
mode
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Triple input HDMI receiver interface with digital processing
Table 10. Characteristics …continued
Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pcons
power consumption
Power-down mode
pin PD = HIGH
I2C-bus; EDID and HDCP[2]
memory power-up
-
-
1
4
-
-
mW
mW
I2C-bus; EDID; activity detection
and HDCP[2] memory power-up
-
150
-
mW
Clock timing output: pins VCLK, ACLK and SYSCLK
fclk(max)
maximum clock frequency
pin VCLK
165
25
50
-
-
-
-
-
-
-
-
MHz
MHz
MHz
%
pin ACLK
-
pin SYSCLK
pin VCLK
-
δclk
clock duty cycle
50
50
50
pin ACLK
-
%
pin SYSCLK
-
%
Timing output: pins VP[29:0]; fs = 165 MHz; CL = 10 pF; see Figure 5
tsu(Q)
data output set-up time
data output hold time
pipeline delay time
CLKOUT_DEL = 0;
CLKOUT_TOG = 0
1.50
0.40
-
-
-
-
ns
ns
CLKOUT_DEL = 1;
CLKOUT_TOG = 1;
CLKOUT_DEL_SEL[2:0] = 4
th(Q)
CLKOUT_DEL = 0;
CLKOUT_TOG = 0
0.80
2.00
-
-
-
-
ns
ns
CLKOUT_DEL = 1;
CLKOUT_TOG = 1;
CLKOUT_DEL_SEL[2:0] = 4
td(pipe)
from inputs to outputs; all modes;
clock interval
-
80 × Tclk
-
Timing output: pins AP[5:0] with respect to ACLK; fclk = 12.288 MHz; CL = 10 pF; see Figure 6
tsu(Q)
th(Q)
data output set-up time
data output hold time
69
2
-
-
-
-
ns
ns
LV-TTL digital outputs: pins VP[29:0], VCLK, AP[5:0], ACLK, DE, HS, VS, HREF, VREF, FREF; CL = 10 pF
VOL
VOH
ILOZ
LOW-level output voltage
HIGH-level output voltage
IOL = 2 mA
-
-
0.4
V
IOH = −2 mA
2.4
-
-
V
[3]
OFF-state output leakage current high-impedance state; VO = 0 V
-
0
-
-
μA
μA
μA
μA
VO = VDDO(3V3) × 1∨3
VO = VDDO(3V3) × 2∨3
VO = VDDO(3V3)
10
−100
-
100
−10
-
-
0
Digital inputs: pins RXxC+, RXxC−[4]
VI(dif)
differential input voltage
RRRX1 = 12 kΩ ± 1 %;
RRRX2 = 12 kΩ ± 1 %
150
-
1200
mV
VI(cm)
common-mode input voltage
maximum clock frequency
2.735 -
205
3.475
-
V
fclk(max)
-
MHz
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Triple input HDMI receiver interface with digital processing
Table 10. Characteristics …continued
Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.
Symbol Parameter Conditions
Digital inputs: pins RXx0+, RXx0−, RXx1+, RXx1−, RXx2+, RXx2−[4]
Min
Typ
Max
Unit
VI(dif)
differential input voltage
RRRX1 = 12 kΩ ± 1 %;
RRRX2 = 12 kΩ ± 1 %
150
-
1200
mV
V
VI(cm)
common-mode input voltage
2.735 -
3.475
I2C-bus: pins SCL and SDA[5]
fSCL
Cb
SCL clock frequency
-
-
-
-
-
-
400
400
10
kHz
pF
capacitive load for each bus line
Ci
capacitance for each I/O pin
pF
DDC I2C-bus: pins HSCLx, HSDAx [4][6]
fSCL
SCL clock frequency
Standard-mode
Fast-mode
-
-
-
-
-
-
100
400
10
kHz
kHz
pF
Ci
capacitance for each I/O pin
[1] At 30 % activity on video port output.
[2] HDCP decoding is only supported by TDA19977A.
[3] In high-impedance state, the output buffer is set to repeater mode recopying the input logic state with a small current. The output current
changes from most negative to the most positive value at the triggering level which is internally set to VDDO(3V3) / 2 (e.g. the value of a
pull-up or pull-down resistor must be lower than 18 kΩ to have a stable output value of VDDO(3V3) or 0 V).
[4] x = A, B or C.
[5] Fast-mode, 5 V tolerant.
[6] 5 V tolerant.
VCLK
50 %
2.4 V
t
su(Q)
VP[29:0]
0.4 V
t
h(Q)
001aah368
Fig 5. Output timing diagram pin VCLK on pins VP[29:0]
ACLK
50 %
2.4 V
t
su(Q)
AP[5:0]
0.4 V
t
h(Q)
001aah369
Fig 6. Output timing diagram pin ACLK on pins AP[5:0]
TDA19977A_TDA19977B
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Triple input HDMI receiver interface with digital processing
13. Output video port formats
Table 11. Output in 12-bit video port format (register VP_CTRL address = 21h)
YCbCr 4:2:2 semi-planar[1] YCbCr 4:2:2 ITU-R BT.656[1]
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Z/L
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Z/L
VP[8]
VP[7]
VP[6]
VP[5]
VP[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
21 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 12. Output in 12-bit video port format (register VP_CTRL address = 09h)
YCbCr 4:2:2 semi-planar[1] YCbCr 4:2:2 ITU-R BT.656[1]
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Cb[1]
Cb[0]
Z/L
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[8]
Z/L
Z/L
Z/L
Z/L
VP[7]
Z/L
Z/L
Z/L
Z/L
VP[6]
Z/L
Z/L
Z/L
Z/L
VP[5]
Z/L
Z/L
Z/L
Z/L
VP[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
22 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 13. Output in 10-bit video port format (register VP_CTRL address = 61h)
RGB YCbCr 4:4:4
YCbCr 4:2:2 semi-planar[1] YCbCr 4:2:2 ITU-R BT.656[1]
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
G[11] Y[11]
G[10] Y[10]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
G[9]
G[8]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
R[11]
Y[9]
Y[8]
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Cr[11]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Z/L
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Z/L
R[10] Cr[10]
R[9]
R[8]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
B[11]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cb[11]
VP[8]
B[10] Cb[10]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[7]
B[9]
B[8]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[6]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[5]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
23 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 14. Output in 10-bit video port format (register VP_CTRL address = 58h)
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
RGB
B[11]
B[10]
B[9]
B[8]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
G[11]
YCbCr 4:4:4
Cb[11]
Cb[10]
Cb[9]
YCbCr 4:2:2 semi-planar[1]
YCbCr 4:2:2 ITU-R BT.656[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[8]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[7]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[6]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[5]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Y[11]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Z/L
Z/L
Z/L
Z/L
G[10] Y[10]
Z/L
Z/L
Z/L
Z/L
G[9]
G[8]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
R[11]
Y[9]
Y[8]
Y[7]
Y[6]
Y[5]
Y[4]
Y[3]
Y[2]
Cr[11]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Cb[3]
Cb[2]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
VP[8]
R[10] Cr[10]
VP[7]
R[9]
R[8]
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
VP[6]
VP[5]
VP[4]
VP[3]
VP[2]
VP[1]
VP[0]
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
24 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 15. Output in 8-bit video port format (register VP_CTRL address = A1h)
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
RGB[1] YCbCr 4:4:4[1]
YCbCr 4:2:2 semi-planar[1]
YCbCr 4:2:2 ITU-R BT.656[1]
G[11] Y[11]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Z/L
Z/L
Z/L
Z/L
Z/L
G[10] Y[10]
Z/L
Z/L
Z/L
Z/L
G[9]
G[8]
G[7]
G[6]
G[5]
G[4]
R[11]
Y[9]
Y[8]
Y[7]
Y[6]
Y[5]
Y[4]
Cr[11]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Z/L
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Z/L
R[10] Cr[10]
R[9]
R[8]
R[7]
R[6]
R[5]
R[4]
B[11]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cb[11]
B[10] Cb[10]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[9]
B[8]
B[7]
B[6]
B[5]
B[4]
Z/L
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[8]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[7]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[6]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[5]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
25 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 16. Output in 8-bit video port format (register VP_CTRL address = 98h)
RGB[1] YCbCr 4:4:4[1] YCbCr 4:2:2 semi-planar[1] YCbCr 4:2:2 ITU-R BT.656[1]
Signal
VP[29]
VP[28]
VP[27]
VP[26]
VP[25]
VP[24]
VP[23]
VP[22]
VP[21]
VP[20]
VP[19]
VP[18]
VP[17]
VP[16]
VP[15]
VP[14]
VP[13]
VP[12]
VP[11]
VP[10]
VP[9]
B[11]
B[10]
B[9]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Y[11]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[8]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[7]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[6]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[5]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
B[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
G[11]
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Z/L
Z/L
Z/L
Z/L
Z/L
G[10] Y[10]
Z/L
Z/L
Z/L
Z/L
G[9]
G[8]
G[7]
G[6]
G[5]
G[4]
R[11]
R[10]
R[9]
R[8]
R[7]
R[6]
R[5]
R[4]
Z/L
Y[9]
Y[8]
Y[7]
Y[6]
Y[5]
Y[4]
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Cb[11]
Cb[10]
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
Cb[4]
Z/L
Y0[11]
Y0[10]
Y0[9]
Y0[8]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Z/L
Cr[11]
Cr[10]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Z/L
Y1[11]
Y1[10]
Y1[9]
Y1[8]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Z/L
VP[8]
VP[7]
VP[6]
VP[5]
VP[4]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[3]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[2]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[1]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
VP[0]
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z = high-impedance; L = LOW-level; depending on bit VPL.
TDA19977A_TDA19977B
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Triple input HDMI receiver interface with digital processing
14. Example of supported video formats
Table 17. Example of supported video formats
Standard
Format
Total pixels ×
total lines
Horizontalrate Pixel clock
(kHz)
rate (MHz)[1]
27.000[3]
27.000[3]
27.027[3]
27.000
27.000
27.027
74.250
74.176
74.250
74.250
74.176
74.250
148.500
148.352
148.500
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
73.250
33.750
44.900
65.000
75.000
78.750
94.500
115.500
108.000
68.250
140.250
79.500
102.250
117.500
576i[2]
480i[4]
1440 × 576i 50 Hz
1440 × 480i 59.94 Hz
1440 × 480i 60 Hz
720 × 576p 50 Hz
1728 × 625
1716 × 525
1716 × 525
864 × 625
15.750
15.734
15.750
31.250
31.469
31.500
37.500
44.955
45.000
28.125
33.716
33.750
56.250
67.433
67.500
31.469
37.861
37.500
43.269
35.156
37.879
48.077
46.875
53.674
76.302
31.020
35.522
48.363
56.476
60.023
68.677
97.551
67.500
47.396
97.396
47.776
60.289
68.633
576p
480p
720 × 480p 59.94 Hz
720 × 480p 60 Hz
858 × 525
858 × 525
720p
1280 × 720p 50 Hz
1280 × 720p 59.94 Hz
1280 × 720p 60 Hz
1920 × 1080i 50 Hz
1920 × 1080i 59.94 Hz
1920 × 1080i 60 Hz
1920 × 1080p 50 Hz[5]
1980 × 750
1650 × 750
1650 × 750
2640 × 1125
2200 × 1125
2200 × 1125
2640 × 1125
1080i
1080p
1920 × 1080p 59.94 Hz[5] 2200 × 1125
1920 × 1080p 60 Hz[5]
640 × 480p 60 Hz
640 × 480p 72 Hz
640 × 480p 75 Hz
640 × 480p 85 Hz
800 × 600p 56 Hz
800 × 600p 60 Hz
800 × 600p 72 Hz
800 × 600p 75 Hz
800 × 600p 85 Hz
800 × 600p 120 Hz
848 × 480p 60 Hz
1024 × 768p 43 Hz
1024 × 768p 60 Hz
1024 × 768p 70 Hz
1024 × 768p 75 Hz
1024 × 768p 85 Hz
1024 × 768p 120 Hz
1152 × 864p 75 Hz
1280 × 768p 60 Hz
1280 × 768p 120 Hz[5]
1280 × 768p 60 Hz
1280 × 768p 75 Hz
1280 × 768p 85 Hz
2200 × 1125
800 × 525
0.31M3 VGA
832 × 520
840 × 500
832 × 509
0.48M3 SVGA
1024 × 625
1056 × 628
1040 × 666
1056 × 625
1048 × 631
960 × 636
0.48M3-R
0.41M9
1088 × 517
1264 × 817
1344 × 806
1328 × 806
1312 × 800
1376 × 808
1184 × 813
1600 × 900
1440 × 790
1440 × 813
1664 × 798
1696 × 805
1712 × 809
0.79M3 XGA
0.79M3-R XGA
1.00M3
0.98M9-R
0.98M9
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 17. Example of supported video formats …continued
Standard
Format
Total pixels ×
total lines
Horizontalrate Pixel clock
(kHz)
rate (MHz)[1]
1.02MA-R
1.02MA
1280 × 800p 60 Hz
1280 × 800p 120 Hz[5]
1280 × 800p 60 Hz
1280 × 800p 75 Hz
1280 × 800p 85 Hz
1280 × 960p 60 Hz
1280 × 960p 85 Hz[5]
1280 × 1024p 60 Hz
1280 × 1024p 75 Hz
1280 × 1024p 85 Hz[5]
1360 × 768p 60 Hz
1360 × 768p 120 Hz[5]
1400 × 1050p 60 Hz
1400 × 1050p 60 Hz
1400 × 1050p 75 Hz[5]
1440 × 900p 60 Hz
1440 × 900p 60 Hz
1440 × 900p 75 Hz[5]
1440 × 900p 85 Hz[5]
1600 × 1200p 60 Hz[5]
1680 × 1050p 60 Hz
1680 × 1050p 60 Hz[5]
1920 × 1200p 60 Hz[5]
1440 × 823
1440 × 847
1680 × 831
1696 × 838
1712 × 843
1800 × 1000
1728 × 1011
1688 × 1066
1688 × 1066
1728 × 1072
1792 × 795
1520 × 813
1560 × 1080
1864 × 1089
1896 × 1099
1600 × 926
1904 × 934
1936 × 942
1952 × 948
2160 × 1250
1840 × 1080
2240 × 1089
2080 × 1235
49.306
101.563
49.702
62.795
71.554
60.000
85.938
63.981
79.976
91.146
47.712
97.533
64.744
65.317
82.278
55.469
55.935
70.635
80.430
75.000
64.674
65.290
74.038
71.000
146.250
83.500
106.500
122.500
108.000
148.500
108.000
135.000
157.500
85.500
1.23M3
1.31M4 SXGA
1.04M9
1.04M9-R
1.47M3-R
1.47M3
148.250
101.000
121.750
156.000
88.750
1.29MA-R
1.29MA
106.500
136.750
157.000
162.000
119.000
146.250
154.000
1.92M3 UXGA
1.76MA-R
1.76MA
2.30MA-R[6]
[1] Pixel clock rate corresponds to VCLK output for 4:4:4 format and 4:2:2 semi-planar; VCLK / 2 for 4:2:2
ITU-R BT.656 format. The pixel clock rate can be determined by:
a) Total pixels × total lines × frame rate for the progressive format.
b) Total pixels × total lines × frame rate / 2 for the interlaced format.
[2] Also referred to as PAL (Phase Alternating Line).
[3] Pixel-doubling.
[4] Also referred to as NTSC (National Television Standards Committee).
[5] Only supports Deep Color mode 10-bit.
[6] Sometimes also referred to as WUXGA (Wide Ultra eXtended Graphics Array).
Table 18. Examples of 3D video formats timing supported
Resolution
3D transmission type
1280 × 720p at 23.98 Hz and 24 Hz
1280 × 720p at 25 Hz
Frame Packing, Side-by-Side (Half), Top-and-Bottom
Frame Packing, Side-by-Side (Half), Top-and-Bottom
Frame Packing, Side-by-Side (Half), Top-and-Bottom
Frame Packing, Side-by-Side (Half), Top-and-Bottom
Frame Packing, Side-by-Side (Half), Top-and-Bottom
Frame Packing[1], Side-by-Side (Half), Top-and-Bottom
1280 × 720p at 29.97 Hz and 30 Hz
1280 × 720p at 50 Hz
1280 × 720p at 59.94 Hz and 60 Hz
1920 × 1080i at 50 Hz
TDA19977A_TDA19977B
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NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Table 18. Examples of 3D video formats timing supported …continued
Resolution
3D transmission type
1920 × 1080i at 59.94 Hz and 60 Hz
1920 × 1080p at 23.98 Hz and 24 Hz
1920 × 1080p at 25 Hz
Frame Packing[1], Side-by-Side (Half), Top-and-Bottom
Frame Packing[1], Side-by-Side (Half), Top-and-Bottom
Frame Packing[1], Side-by-Side (Half), Top-and-Bottom
Frame Packing[1], Side-by-Side (Half), Top-and-Bottom
Side-by-Side (Half), Top-and-Bottom
1920 × 1080p at 29.97 Hz and 30 Hz
1920 × 1080p at 50 Hz
1920 × 1080p at 59.94 Hz and 60 Hz
Side-by-Side (Half), Top-and-Bottom
[1] Only available without timing code and blanking code.
TDA19977A; TDA19977B support other 3D video formats so software implementation can
be considered on request.
TDA19977A_TDA19977B
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NXP Semiconductors
Triple input HDMI receiver interface with digital processing
15. Application information
DDC C
HDMI inputs A and B
V
V
V
SSC
DDH(1V8)
1.8 V
1.8 V
GNDC
1
108
107
106
105
104
103
102
101
100
99
HDMI
PD
DDC(1V8)
2
DIG
12 kΩ 1%
V
V
V
V
RRX1
DDH(3V3)
3.3 V
3.3 V
HDMI
3
HDMI
HDMI
HDMI
HDMI
V
SSH
n.c.
4
V
n.c.
DDH(3V3)
3.3 V
HDMI
5
0 Ω
V
SSH
TEST0
HSCLB
HSDAB
HSCLA
HSDAA
SCL
6
GNDC
RXCC−
7
RXCC+
8
DDH(3V3)
n.c.
3.3 V
1.8 V
3.3 V
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
n.c.
98
V
SSH
SDA
97
RXC0−
VAI
96
V
RXC0+
DDI(3V3)
3.3 V
95
DIG_I
XTALIN/MCLK
DDH(1V8)
n.c.
94
XTALOUT
93
V
n.c.
DDC(1V8)
1.8 V
92
DIG
V
SSH
V
V
V
V
V
V
SSH
91
TDA19977
RXC1−
DDH(1V8)
SSH
1.8 V
90
HDMI
RXC1+
89
DDH(3V3)
n.c.
DDH(3V3)
DDH(3V3)
SSO
3.3 V
3.3 V
88
HDMI
87
HDMI
n.c.
86
V
SSH
AP5/SYSCLK
85
GNDC
V
RXC2−
DDO(3V3)
3.3 V
DIG
84
RXC2+
AP4/WS
AP3
83
V
PP
82
V
V
AP2
DDC(1V8)
1.8 V
81
DIG
AP1
DDO(3V3)
VCLK
3.3 V
80
DIG
AP0
79
V
SSO
ACLK
78
V
SSO
CS/FREF
VS/VREF
HS/HREF
DE
77
VP[29]
VP[28]
76
75
V
DDO(3V3)
3.3 V
DIG
74
V
SSC
VP[0]
73
GNDC
001aai385
control outputs and video port outputs
Fig 7. Application diagram of TDA19977A; TDA19977B
TDA19977A_TDA19977B
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Triple input HDMI receiver interface with digital processing
16. Package outline
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 x 20 x 1.4 mm; exposed die pad
SOT612-3
y
exposed die pad
X
A
D
h
108
109
73
72
Z
E
e
E
H
A
E
2
h
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v
M
A
Z
w M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
D
E
E
e
H
H
E
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
h
h
D
p
D
max.
7o
0o
0.12 1.45
0.05 1.35
0.27 0.20 20.1 5.7 20.1 5.7
0.17 0.09 19.9 5.5 19.9 5.5
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-07-12
04-07-05
SOT612-3
MS-026
Fig 8. Package outline SOT612-3 (HLQFP144)
TDA19977A_TDA19977B
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NXP Semiconductors
Triple input HDMI receiver interface with digital processing
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 19 and 20
Table 19. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 20. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 9.
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 9. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
18. Abbreviations
Table 21. Abbreviations
Acronym
ACR
Description
Audio Clock Regeneration
Audio Video Receiver
AVR
AWG
CMOS
DAC
American Wire Gauge
Complementary Metal-Oxide-Semiconductor
Digital-to-Analog Converter
Display Data Channel bus
Direct Stream Digital
DDC-bus
DSD
DST
Direct Stream Transfer
DTS-HD
DVD
Digital Theater Systems High-Definition
Digital Versatile Disc
DVI
Digital Video Interface
EDID
HBM
Extended Display Identification Data
Human Body Model
HBR
High Bit Rate
HD
High-Definition
HDCP
HDMI
HDTV
L-PCM
LSB
High-bandwidth Digital Content Protection
High-Definition Multimedia Interface
High-Definition TeleVision
Linear-Pulse Code Modulation
Least Significant Bit
LV-TTL
OBA
Low Voltage Transistor-Transistor Logic
One Bit Audio
OTP
One Time Programmable
Phase-Locked Loop
PLL
RGB
Red Green Blue
SACD
SVGA
SXGA
S/PDIF
TMDS
UXGA
VGA
Super Audio CD
Super Video Graphics Array
Super eXtended Graphics Array
Sony/Philips Digital Interface Format
Transition Minimized Differential Signaling
Ultra eXtended Graphics Array
Video Graphics Array
WUXGA
XGA
Wide Ultra eXtended Graphics Array
eXtended Graphics Array
Y = Luminance, Cb = Chroma blue, Cr = Chroma red
YCbCr
TDA19977A_TDA19977B
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Triple input HDMI receiver interface with digital processing
19. Revision history
Table 22. Revision history
Document ID
Release date
Data sheet status
Product data sheet
Change notice Supersedes
- TDA19977A_TDA19977B v.2
TDA19977A_TDA19977B v.3 20101119
Modifications:
• Replaced in all document HDMI 1.3a with HDMI 1.4a
• Replaced in all document HDCP 1.2 with HDCP 1.4
• Table 18: added
TDA19977A_TDA19977B v.2 20100511
Product data sheet
-
TDA19977A_TDA19977B v.1
-
TDA19977A_TDA19977B v.1 20080807
Product data sheet
-
TDA19977A_TDA19977B
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TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
20.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
37 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20.4 Licenses
Purchase of NXP ICs with HDMI technology
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
20.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
38 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .4
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Audio port configuration (Layout 0) . . . . . . . . .13
Table 5. Audio port configuration (Layout 1) . . . . . . . . .13
Table 6. Audio port configuration for HBR and DST
packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7. I2C-bus slave address . . . . . . . . . . . . . . . . . . .17
Table 8. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Thermal characteristics . . . . . . . . . . . . . . . . . .18
Table 10. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. Output in 12-bit video port format (register
VP_CTRL address = 21h) . . . . . . . . . . . . . . . .21
Table 13. Output in 10-bit video port format (register
VP_CTRL address = 61h) . . . . . . . . . . . . . . . . 23
Table 14. Output in 10-bit video port format (register
VP_CTRL address = 58h) . . . . . . . . . . . . . . . . 24
Table 15. Output in 8-bit video port format (register
VP_CTRL address = A1h) . . . . . . . . . . . . . . . 25
Table 16. Output in 8-bit video port format (register
VP_CTRL address = 98h) . . . . . . . . . . . . . . . . 26
Table 17. Example of supported video formats . . . . . . . 27
Table 18. Examples of 3D video formats timing
supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. SnPb eutectic process (from J-STD-020C) . . . 33
Table 20. Lead-free process (from J-STD-020C) . . . . . . 33
Table 21. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Output in 12-bit video port format (register
VP_CTRL address = 09h) . . . . . . . . . . . . . . . .22
23. Figures
Fig 1. Block diagram of TDA19977A; TDA19977B . . . . .5
Fig 2. Pin configuration for TDA19977A; TDA19977B. . .6
Fig 3. An example of an application with EDID
memory shared over all three HDMI inputs . . . . .16
Fig 4. An example of an application with EDID
memory shared over two HDMI inputs. . . . . . . . .17
Fig 5. Output timing diagram pin VCLK on pins
VP[29:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 6. Output timing diagram pin ACLK on pins
AP[5:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 7. Application diagram of
TDA19977A; TDA19977B . . . . . . . . . . . . . . . . . .30
Fig 8. Package outline SOT612-3 (HLQFP144) . . . . . .31
Fig 9. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
TDA19977A_TDA19977B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 19 November 2010
39 of 40
TDA19977A; TDA19977B
NXP Semiconductors
Triple input HDMI receiver interface with digital processing
24. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
14
15
16
Example of supported video formats . . . . . . 27
Application information . . . . . . . . . . . . . . . . . 30
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
17
Soldering of SMD packages. . . . . . . . . . . . . . 32
Introduction to soldering. . . . . . . . . . . . . . . . . 32
Wave and reflow soldering. . . . . . . . . . . . . . . 32
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 32
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 33
17.1
17.2
17.3
17.4
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . 36
8
Functional description . . . . . . . . . . . . . . . . . . 10
Software drivers . . . . . . . . . . . . . . . . . . . . . . . 10
HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Termination resistance control . . . . . . . . . . . . 10
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Activity detection. . . . . . . . . . . . . . . . . . . . . . . 11
High-bandwidth digital content protection
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 37
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1
8.2
8.3
8.4
8.5
8.6
20.1
20.2
20.3
20.4
20.5
(TDA19977A only) . . . . . . . . . . . . . . . . . . . . . 11
Color depth unpacking . . . . . . . . . . . . . . . . . . 11
Derepeater . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Upsample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Packet extraction . . . . . . . . . . . . . . . . . . . . . . 12
Audio PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Audio formatter. . . . . . . . . . . . . . . . . . . . . . . . 12
Sync timing measurement . . . . . . . . . . . . . . . 14
Format measurement timing. . . . . . . . . . . . . . 14
Color space conversion . . . . . . . . . . . . . . . . . 14
4:2:2 downsampling filters . . . . . . . . . . . . . . . 14
Range control . . . . . . . . . . . . . . . . . . . . . . . . . 14
Dithering function . . . . . . . . . . . . . . . . . . . . . . 14
4:2:2 formatter . . . . . . . . . . . . . . . . . . . . . . . . 15
Video port selection . . . . . . . . . . . . . . . . . . . . 15
Output buffers. . . . . . . . . . . . . . . . . . . . . . . . . 15
VHREF timing generator . . . . . . . . . . . . . . . . 15
I2C-bus serial interface . . . . . . . . . . . . . . . . . . 15
Power management . . . . . . . . . . . . . . . . . . . . 16
EDID memory management. . . . . . . . . . . . . . 16
EDID memory shared over all three
21
22
23
24
Contact information . . . . . . . . . . . . . . . . . . . . 38
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.25.1
HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 16
EDID memory shared over two
8.25.2
HDMI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . 18
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18
Output video port formats. . . . . . . . . . . . . . . . 21
10
11
12
13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 November 2010
Document identifier: TDA19977A_TDA19977B
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