TDA19988BHN/C1_技术文档

TDA19988

Low power, 150 MHz pixel rate HDMI 1.4a transmitter with

3  8-bit video inputs, HDCP and CEC support

Rev. 3 — 21 July 2011

Product data sheet

1. General description

TDA19988 is a very low power and very small size High-Definition Multimedia Interface

(HDMI) 1.4a transmitter. It is backward compatible DVI 1.0 and can be connected to any

DVI 1.0 or HDMI sink.

This device is primarily intended for mobile applications like Digital Video Camera (DVC),

Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and

Ultra-Mobile Personal Computer (UM PC), new PC tablet and MID where size and power

are key for battery autonomy.

This device is also targeting STB HDMI output applications. This part replaces previous

TDA9981 Transmitters with increased features and better performances.

It allows mixing 3  8-bit RGB or YCbCr video stream at pixel rate up to 165 MHz together

with S/PDIF or I²S-bus audio streams at audio sampling rate up to 192 kHz.

In order to be compatible with most applications, TDA19988 integrates a full

programmable input formatter and color space conversion block. The video input formats

accepted are YCbCr 4 : 4 : 4 (up to 3  8-bit), YCbCr 4 : 2 : 2 semi-planar (up to

2  12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1  12-bit). In case of

ITU656-like format, the input pixel clock can be made active on one (SDR mode) or both

edges (DDR mode).

TDA19988AHN and TDA19988AET only include a HDCP 1.4 compliant cipher block. The

HDCP keys are stored internally in a non-volatile OTP memory for maximum security.

This device provides additional embedded features like CEC (Consumer Electronic

Control). CEC is a single bidirectional bus that transmits CEC commands (like Standby

from remote control) over the home appliance network connected through this bus. This

eliminates the need of any additional device to handle this feature thus improving BOM

(Bill Of Materials) of the whole system and enabling the connected devices (CEC

enabled) to be controlled by only one remote control.

TDA19988 supports xvYCC HDMI 1.4a feature.

It can be switched to very low power Standby or Sleep modes to save power when HDMI

is not used.

TDA19988 embeds I²C-bus master interface for DDC-bus communication to read EDID

and to manage HDCP (TDA19988AHN and TDA19988AET only).

This device can be controlled or configured via I²C-bus interface.

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

PLL

2

I C-BUS

CEC

SERIALIZER

SLAVE

PIXEL, REPETITION

2

I S-bus

HDMI

ENCODER

SERIALIZER

HMDI

TMDS

link

HDCP

1.4 CIPHER

AUDIO

video

S/PDIF

RGB

COLOR

SPACE

CONVERTER

INPUT

FORMATTER

2

I C-BUS

YCbCr

MASTER DDC-BUS

001aal264

Fig 1. TDA19988 high-level block diagram

2. Features and benefits

 Compliance:

 DVI 1.0

 HDMI 1.4a

 EIA/CEA-861B

 CEC (HDMI 1.4a)

 HDCP 1.4 (TDA19988AHN and TDA19988AET only)

 Video:

 xvYCC HDMI 1.4a feature

 Video formats with a pixel rate up to 165 MHz:

RGB 4 : 4 : 4

YCbCr 4 : 4 : 4

YCbCr 4 : 2 : 2 semi-planar

YCbCr 4 : 2 : 2 ITU656

 3D:

Frame Packing: 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 24/30 Hz

Side-by-Side (Half): 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 50/60 Hz

Top-and-Bottom: 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 50/60 Hz

 Maximum resolution:

1080p at 50/60 Hz for TV

1600  1200 at 60 Hz for PC (UXGA60)

720p/1080i at 50/60 Hz in ITU656

 Programmable color space converter:

RGB to YCbCr

YCbCr to RGB

 Programmable input formatter and upsampler/interpolator allow input of any of the

4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656-like formats

 Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs

or VREF, HREF and FREF could be used for input data synchronization

 In ITU656, pixel clock input can be single or dual edges (selectable by I²C-bus)

 Repetition of video samples as required by HDMI specification

 Audio:

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

2 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

 4  I²S-bus or one S/PDIF; audio data rate up to 192 kHz (depending on video

format and on package)

 Deals with multiple levels of HDCP (TDA19988AHN and TDA19988AET only)

receivers and repeaters

 Internal SHA-1 calculation

 System operation:

 Master DDC-bus interface for EDID read

 Controllable via I²C-bus

 Hot Plug Detect (HPD) and receiver detection (RxSense)

 High performance power management:

 Standby mode: 18 W typical

 Operation mode: 55 mW 720p 24 Hz

 Package:

 TFBGA64, size 4.5 mm  4.5 mm  0.95 mm

 HVQFN64, size 9 mm  9 mm  0.85 mm

 Power management:

 External voltage supplies 1.8 V

 Low power

 Flexible power modes

 Miscellaneous:

 POR (Power-On Reset)

 Audio and video inputs LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant

 250 MHz to 1.5 GHz TMDS transmitter operation

3. Applications

 Digital Video Camera (DVC)

 AVR and HDMI splitter

 MID/tablet

 Digital Still Camera (DSC)

 Portable Multimedia Player (PMP)

 Media box

 Ultra-Mobile Personal Computer (UM PC)  Mobile Phone

 YCbCr or RGB high-speed video digitizer  Home theater amplifier

 Blu-ray disc player

 STB

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

TDA19988AET/C1 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT962-3

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

3 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 1.

Ordering information …continued

Type number

Package

Name

Description

Version

TDA19988BET/C1 TFBGA64 plastic thin fine-pitch ball grid array package;

64 balls; without HDCP

SOT962-3

TDA19988AHN/C1 HVQFN64 plastic thermal enhanced very thin quad flat package; SOT804-4

no leads; 64 terminals; body 9  9  0.85 mm

TDA19988BHN/C1 HVQFN64 plastic thermal enhanced very thin quad flat package; SOT804-4

no leads; 64 terminals; body 9  9  0.85 mm;

without HDCP

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

4 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

6. Pinning information

6.1 Pinning

TDA19988

ball A1

index area

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

H

001aan686

Transparent top view

Fig 3. Pin configuration (TFBGA64)

6.2 Pin description

Table 2.

Symbol

Pin description

H5

G5

F5

Type^[1]Description

ACLK

AP0

I

audio clock input

audio port 0 input

audio port 1 input

audio port 2 input

AP1

AP2

G6

H6

OSC_IN/AP3

input connected to the external oscillator circuit or external

clock source/audio port 3 input

HPD

E6

E7

I

hot plug detect; 5 V tolerant

EXT_SWING

O

TMDS output swing adjustment; place resistor

(R_{EXT_SWING}= 10 k  1 %) between this pin and analog

ground.

DSDA

DSCL

VCLK

F6

F7

D4

I/O

DDC-bus data input/output; 5 V tolerant

DDC-bus clock input; 5 V tolerant

I

input video pixel clock

HSYNC/HREF F4

VSYNC/VREF G4

I

input horizontal synchronization or reference input

input vertical synchronization or reference input

data enable or field reference input

I²C-bus clock input; 1.8 V to 3.3 V tolerant

I²C-bus data input/output; 1.8 V to 3.3 V tolerant

I

DE/FREF

CSCL

CSDA

INT

H4

B5

A5

B6

I

I/O

interrupt HDMI output (open-drain); this pin is used as Dual

function pin selectable through I²C-bus. In calibration mode

only this pin is used as input for 10 ms  1 % calibration pulse.

In operation mode this pin is used to warn the external

microprocessor that a special event has occurred for HDMI or

CEC

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

6 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 2.

Pin description …continued

Type^[1]Description

Symbol

TX0

E8

D8

C8

B8

A7

A6

G8

F8

H7

C1

B1

B2

A2

B3

A3

B4

A4

E3

E2

E1

D1

D2

D3

C2

C3

H3

H2

G3

G2

G1

F1

F2

F3

O

I/O

I

negative data channel 0 for TMDS output

positive data channel 0 for TMDS output

negative data channel 1 for TMDS output

positive data channel 1 for TMDS output

negative data channel 2 for TMDS output

positive data channel 2 for TMDS output

negative clock channel for TMDS output

positive clock channel for TMDS output

CEC connection (open-drain) to HDMI connector

video port A input bit 0 (LSB)

video port A input bit 1

TX0+

TX1

TX1+

TX2

TX2+

TXC

TXC+

CEC

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

I

video port A input bit 2

I

video port A input bit 3

I

video port A input bit 4

I

video port A input bit 5

I

video port A input bit 6

I

video port A input bit 7 (MSB)

video port B input bit 0 (LSB)

video port B input bit 1

I

video port B input bit 2

I

video port B input bit 3

I

video port B input bit 4

I

video port B input bit 5

I

video port B input bit 6

I

video port B input bit 7 (MSB)

video port C input bit 0 (LSB)

video port C input bit 1

I

video port C input bit 2

I

video port C input bit 3

I

video port C input bit 4

I

video port C input bit 5

I

video port C input bit 6

I

video port C input bit 7 (MSB)

TMDS analog supply voltage (1.8 V)

I/O digital supply voltage (1.8 V)

V_{DDA(TMDS)(1V8)}A8, C7

P

V_DDD(IO)(1V8)

V_{DDA(PLL)(1V8)}

E4

C6

PLL analog supply voltage (1.8 V), this PLL provides the clock

for the serializer

V_DDA(1V8)

V_DDDC

G7, H8

E5, D5

P

analog supply voltage (1.8 V), is used for the serializer and

miscellaneous blocks

core digital supply voltage (1.8 V)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

7 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 2.

Pin description …continued

Symbol

Type^[1]Description

V_SSD

B7,

G

digital ground supply voltage, is used for digital core and I/O

C4,

C5, H1

V_SSA

n.c.

D6, D7

A1

G

analog ground supply voltage, is used for PLL, serializer and

transmitter

not connected

[1] P = power supply, G = ground, I = input, O = output.

6.3 Pinning

terminal 1

index area

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VPB[6]

VPB[5]

VPB[4]

PCLK

V

DDA(PLL)(1V8)

DDA(Tx)(1V8)

3

4

TX2+

TX2-

TX1+

TX1-

5

V

DDDC

6

VPB[3]

VPB[2]

VPB[1]

VPB[0]

VPC[7]

VPC[6]

VPC[5]

VPC[4]

7

8

V

DDA(Tx)(1V8)

TDA19988

9

TX0+

TX0-

TXC+

TXC-

10

11

12

13

14

15

16

V

DDA(Tx)(1V8)

DDA(1V8)

V

DDD(IO)(1V8)

VPC[3]

EXT_SWING

DSCL

VPC[2]

001aan687

Transparent top view

Fig 4. Pin configuration (HVQFN64)

6.4 Pin description

Table 3.

Symbol

Pin description

Type^[1]Description

VPB[6]

VPB[5]

VPB[4]

1

2

3

I

video port B input bit 6

video port B input bit 5

video port B input bit 4

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

8 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 3.

Pin description …continued

Symbol

PCLK

4

Type^[1]Description

I

P

I

input video pixel clock

V_DDDC

5

core digital supply voltage (1.8 V)

video port B input bit 3

VPB[3]

VPB[2]

VPB[1]

VPB[0]

VPC[7]

VPC[6]

VPC[5]

VPC[4]

V_DDD(IO)(1V8)

VPC[3]

VPC[2]

VPC[1]

VPC[0]

VPP

6

7

I

video port B input bit 2

8

I

video port B input bit 1

9

I

video port B input bit 0 (LSB)

video port C input bit 7 (MSB)

video port C input bit 6

10

11

12

13

14

15

16

17

18

19

20

I

video port C input bit 5

I

video port C input bit 4

P

I

I/O digital supply voltage (1.8 V)

video port C input bit 3

I

video port C input bit 2

I

video port C input bit 1

I

video port C input bit 0 LSB)

to be connected to GND

data enable or field reference input

input vertical synchronization or reference input

input horizontal synchronization or reference input

audio clock input

DE/FREF

I

VSYNC/VREF 21

HSYNC/HREF 22

ACLK

AP0

23

24

25

26

27

audio port 0 input

AP1

audio port 1 input

AP2

audio port 2 input

OSC_IN/AP3

input connected to the external oscillator circuit or external

clock source/audio port 3 input

AP4

28

29

30

31

32

33

34

I

P

audio port 4 input

V_DDDC

CEC

core digital supply voltage (1.8 V)

CEC connection (open-drain) to HDMI connector

hot plug detect; 5 V tolerant

I/O

I

HPD

DSDA

DSCL

EXT_SWING

I/O

I

DDC-bus data input/output; 5 V tolerant

DDC-bus clock input; 5 V tolerant

O

TMDS output swing adjustment; place resistor

(R_{EXT_SWING}= 10 k  1 %) between this pin and analog

ground.

V_DDA(1V8)

35

P

analog supply voltage (1.8 V), is used for parallel-to-serial

shift register and miscellaneous blocks

V_DDA(Tx)(1V8)

TXC

36

37

38

39

40

41

P

O

P

Tx analog supply voltage (1.8 V)

negative clock channel for TMDS output

positive clock channel for TMDS output

negative data channel 0 for TMDS output

positive data channel 0 for TMDS output

Tx analog supply voltage (1.8 V)

TXC+

TX0

TX0+

V_DDA(Tx)(1V8)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

9 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 3.

Pin description …continued

Symbol

TX1

42

43

44

45

46

47

Type^[1]Description

O

P

negative data channel 1 for TMDS output

positive data channel 1 for TMDS output

negative data channel 2 for TMDS output

positive data channel 2 for TMDS output

Tx analog supply voltage (1.8 V)

TX1+

TX2

TX2+

V_DDA(Tx)(1V8)

V_{DDA(PLL)(1V8)}

P

PLL analog supply voltage (1.8 V), this PLL provides the clock

for the serializer

V_{DDA(PLL)(1V8)}

48

P

PLL analog supply voltage (1.8 V), this PLL provides the clock

for the serializer

TEST

INT

49

50

to be connected to GND

I/O

interrupt HDMI output (open-drain); this pin is used as Dual

function pin selectable through I²C-bus. In calibration mode

only this pin is used as input for 10 ms  1 % calibration pulse.

In operation mode this pin is used to warn the external

microprocessor that a special event has occurred for HDMI or

CEC

CSDA

51

52

53

54

55

56

57

58

59

60

61

62

63

64

-

I/O

I²C-bus data input/output; 1.8 V to 3.3 V tolerant

I²C-bus clock input; 1.8 V to 3.3 V tolerant

I²C-bus address LSB bit 0

CSCL

I

A0_I2C

A1_I2C

V_DDD(IO)(1V8)

VPA[7]

VPA[6]

VPA[5]

VPA[4]

VPA[3]

VPA[2]

VPA[1]

VPA[0]

VPB[7]

I

I²C-bus address LSB bit 1

P

I

I/O digital supply voltage (1.8 V)

video port A input bit 7 (MSB)

video port A input bit 6

I

video port A input bit 5

I

video port A input bit 4)

I

video port A input bit 3

I

video port A input bit 2

I

video port A input bit 1

I

video port A input bit 0 (LSB)

video port B input bit 7 (MSB)

exposed die pad; must be connected to ground

I

Exposed die

pad

G

[1] P = power supply, G = ground, I = input, O = output.

7. Functional description

TDA19988 is designed to convert digital data (video and audio) provided by Set-Top

Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable

Multimedia Player (PMP) or DVD into an HDMI output, connected to HDMI or DVI input of

a TV.

The video data input formats are:

• RGB 4 : 4 : 4

• YCbCr 4 : 4 : 4

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

10 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

• YCbCr 4 : 2 : 2 semi-planar

• YCbCr 4 : 2 : 2 ITU656-like

TDA19988 is able to output HDMI with the formats:

• RGB 4 : 4 : 4

• YCbCr 4 : 4 : 4

• YCbCr 4 : 2 : 2

It can also handle audio formats:

• four I²S-bus lanes

• one S/PDIF lane

TDA19988 is also designed to support CEC protocol. For more details about CEC, refer to

HDMI specification 1.4a.

7.1 System clock

The system clock section has a PLL serializer.

It is a system clock generator which enables the stream produced by the encoder to be

transmitted on the HDMI data channel at ten times, or above, the sampling rate.

7.2 Video input formatter

7.2.1 Description

TDA19988 has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and VPC[0] to

VPC[7].

TDA19988 can accept any of the following video input modes (see Table 7):

• RGB, with 8-bit for each component

• YCbCr 4 : 4 : 4, with 8-bit for each component

• YCbCr 4 : 2 : 2 semi-planar, with up to 12-bit for each component (YCbCr)

• YCbCr 4 : 2 : 2 ITU656, with up to 12-bit data depth

TDA19988 can be set to latch data at either rising or falling edge, or both.

7.2.2 Internal assignment

All video interfaces can be affected according to application requirements by swapping or

allocating the 24-input VP ports to internal 24-video bus by block of 4-bit.

VPA[0] to VPA[7]

VIDEO

VPB[0] to VPB[7]

VP[23:0]

INPUT

PROCESSOR

VPC[0] to VPC[7]

001aah028

Fig 5. Internal assignment of VP[23:0]

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

11 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 4.

Internal assignment

Internal port

RGB

YCbCr 4 : 4 : 4

YCbCr 4 : 2 : 2

semi-planar

YCbCr 4 : 2 : 2

ITU656

VP[23]

VP[22]

VP[21]

VP[20]

VP[19]

VP[18]

VP[17]

VP[16]

VP[15]

VP[14]

VP[13]

VP[12]

VP[11]

VP[10]

VP[9]

G[7]

G[6]

G[5]

G[4]

G[3]

G[2]

G[1]

G[0]

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

R[7]

R[6]

R[5]

R[4]

R[3]

R[2]

R[1]

R[0]

Y[7]

Y[11]

YCbCr[11]

YCbCr[10]

YCbCr[9]

YCbCr[8]

YCbCr[7]

YCbCr[6]

YCbCr[5]

YCbCr[4]

YCbCr[3]

YCbCr[2]

YCbCr[1]

YCbCr[0]

Y[6]

Y[10]

Y[5]

Y[9]

Y[4]

Y[8]

Y[3]

Y[7]

Y[2]

Y[6]

Y[1]

Y[5]

Y[0]

Y[4]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

Cb[3]

Cb[2]

Cb[1]

Cb[0]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Cr[2]

Cr[1]

Cr[0]

Y[3]

Y[2]

Y[1]

Y[0]

CbCr[11]

CbCr[10]

CbCr[9]

CbCr[8]

CbCr[7]

CbCr[6]

CbCr[5]

CbCr[4]

CbCr[3]

CbCr[2]

CbCr[1]

CbCr[0]

VP[8]

VP[7]

VP[6]

VP[5]

VP[4]

VP[3]

VP[2]

VP[1]

VP[0]

The device can swap and invert incoming video data using I²C-bus registers

VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 to match the expectation of the video

processing block.

Table 5 shows the behavior of SWAP_A[2:0] of VIP_CNTRL_0 register, whose function is

to map the 4 MSBs VP[23:20] to incoming video port

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

12 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 5.

Video input swap to VP[23:20]

External

assignment

SWAP_A[2:0] Internal assignment

selector

value

Internal RGB

port

YCbCr YCbCr 4 : 2 : 2 YCbCr 4 : 2 : 2

number^[1]name

4 : 4 : 4 semi-planar

ITU656

F3

F2

F1

G1

G2

G3

H2

H3

C3

C2

D3

D2

D1

E1

E2

E3

A4

B4

A3

B3

A2

B2

B1

C1

VPC[7] 000b

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

VP[23]

VP[22]

VP[21]

VP[20]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

G[7]

G[6]

G[5]

G[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y[7]

Y[6]

Y[5]

Y[4]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPC[6]

VPC[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPC[4]

VPC[3] 001b

VPC[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPC[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPC[0]

VPB[7] 010b

VPB[6]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPB[4]

VPB[3] 011b

VPB[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPB[0]

VPA[7] 100b

VPA[6]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPA[5]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPA[4]

VPA[3] 101b

VPA[2]

Y₀[11] Y₁[11]

Y₀[10] Y₁[10]

Cb[11] Y₀[11] Cr[11] Y₁[11]

Cb[10] Y₀[10] Cr[10] Y₁[10]

VPA[1]

Y₀[9]

Y₀[8]

Y₁[9]

Y₁[8]

Cb[9]

Cb[8]

Y₀[9]

Y₀[8]

Cr[9]

Cr[8]

Y₁[9]

Y₁[8]

VPA[0]

[1] Only for TFBGA package.

In the same way:

• SWAP_B[2:0] is used to map incoming video port to the internal port VP[19:16].

• SWAP_C[2:0] is used to map incoming video port to the internal port VP[15:12].

• SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8].

• SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4].

• SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0].

The device expects to receive big endian incoming data. However, in cases where the

input digital stream to the chip is little endian, the use of the mirror bit of the same register

can help to re-order the input bits as described in Table 6.

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

13 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 6.

TDA19988 input/output capability

Bit setting

Internal port

VP[23]

VP[22]

VP[21]

VP[20]

VP[19]

VP[18]

VP[17]

VP[16]

VP[15]

VP[14]

VP[13]

VP[12]

VP[11]

VP[10]

VP[9]

To be mapped to

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

MIRR_A = 1

SWAP_A[2:0] = 1

MIRR_B = 1

SWAP_B[2:0] = 0

MIRR_C = 1

SWAP_C[2:0] = 3

MIRR_D = 1

SWAP_D[2:0] = 2

VP[8]

MIRR_E = 1

SWAP_E[2:0] = 5

VP[7]

VP[6]

VP[5]

VP[4]

MIRR_F = 1

SWAP_F[2:0] = 4

VP[3]

VP[2]

VP[1]

VP[0]

Remark: Unused input port can be set in 3-state or grounded by using appropriate

configuration.

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

14 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

For all formats, active video windows can be selected using either external DE signal or

internal timing generator engine.

7.2.3.1 RGB 4 : 4 : 4 external synchronization (rising edge)

Table 8.

RGB (3  8-bit) external synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A

Video port B

RGB 4 : 4 : 4 Pin

Video port C

RGB 4 : 4 : 4 Pin

Control

RGB 4 : 4 : 4 Pin

RGB 4 : 4 : 4

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

HSYNC/HREF used

VSYNC/VREF used

DE/FREF

used

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

B [7:0]

...

B

[7:0]

B

[7:0]

xxx

0

1

2

3

xxx

G [7:0]

0

G [7:0]

1

G [7:0]

2

G [7:0]

3

G

R

G

R

[7:0]

xxx

R [7:0]

0

R [7:0]

1

R [7:0]

2

R [7:0]

3

xxx

001aag380

Fig 6. Pixel encoding RGB 4 : 4 : 4 external synchronization input (rising edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

16 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.2 YCbCr 4 : 4 : 4 external synchronization (rising edge)

YCbCr 4 : 4 : 4 (3  8-bit) external synchronization input (rising edge) mapping

Table 9.

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.

Video port A Video port B Video port C

Control

YCbCr 4 : 4 : 4

used

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

VPA[4] Cb[4]

VPA[5] Cb[5]

VPA[6] Cb[6]

VPA[7] Cb[7]

VPB[0] Y[0]

VPB[1] Y[1]

VPB[2] Y[2]

VPB[3] Y[3]

VPB[4] Y[4]

VPB[5] Y[5]

VPB[6] Y[6]

VPB[7] Y[7]

VPC[0] Cr[0]

VPC[1] Cr[1]

VPC[2] Cr[2]

VPC[3] Cr[3]

VPC[4] Cr[4]

VPC[5] Cr[5]

VPC[6] Cr[6]

VPC[7] Cr[7]

HSYNC/HREF

VSYNC/VREF

DE/FREF

used

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

Cb [7:0]

...

Cb [7:0]

xxx

0

1

2

3

xxx

Y [7:0]

0

Y [7:0]

1

Y [7:0]

2

Y [7:0]

3

Y

[7:0]

Y

[7:0]

xxx

Cr [7:0]

0

Cr [7:0]

1

Cr [7:0]

2

Cr [7:0]

3

Cr [7:0]

xxx

Cr [7:0]

xxx

001aai444

Fig 7. Pixel encoding YCbCr 4 : 4 : 4 external synchronization input (rising edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

17 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.3 YCbCr 4 : 2 : 2 ITU656-like external synchronization (rising edge)

Table 10. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

Y₀[0]

Cr[0]

Y₁[0]

VPB[0] Cb[4]

VPB[1] Cb[5]

VPB[2] Cb[6]

VPB[3] Cb[7]

VPB[4] Cb[8]

VPB[5] Cb[9]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF used

VSYNC/VREF used

Y₀[1]

Cr[1]

Y₁[1]

Y₀[2]

Cr[2]

Y₁[2]

DE/FREF

used

Y₀[3]

Cr[3]

Y₁[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai445

Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (rising edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

18 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.4 YCbCr 4 : 2 : 2 ITU656-like external synchronization (double edge)

Table 11. YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0]

VPA[1] Cb[1]

VPA[2] Cb[2]

VPA[3] Cb[3]

VPA[4] -

Y₀[0]

Cr[0]

Y₁[0]

VPB[0] Cb[4]

VPB[1] Cb[5]

VPB[2] Cb[6]

VPB[3] Cb[7]

VPB[4] Cb[8]

VPB[5] Cb[9]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF used

VSYNC/VREF used

Y₀[1]

Cr[1]

Y₁[1]

Y₀[2]

Cr[2]

Y₁[2]

DE/FREF

used

Y₀[3]

Cr[3]

Y₁[3]

-

VPA[5] -

VPA[6] -

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VPA[7] -

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai446

Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization input (double edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

19 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.5 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (rising edge)

Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge) mappings

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0] Y₀[0]

VPA[1] Cb[1] Y₀[1]

VPA[2] Cb[2] Y₀[2]

VPA[3] Cb[3] Y₀[3]

Cr[0]

Y₁[0]

VPB[0] Cb[4] Y₀[4]

VPB[1] Cb[5] Y₀[5]

VPB[2] Cb[6] Y₀[6]

VPB[3] Cb[7] Y₀[7]

VPB[4] Cb[8] Y₀[8]

VPB[5] Cb[9] Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF not used

VSYNC/VREF not used

Cr[1]

Y₁[1]

Cr[2]

Y₁[2]

DE/FREF

not used

Cr[3]

Y₁[3]

VPA[4] -

VPA[5] -

VPA[6] -

VPA[7] -

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai447

Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (rising edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

20 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.6 YCbCr 4 : 2 : 2 ITU656-like embedded synchronization (double edge)

Table 13. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.

Video port A

Video port B

Control

YCbCr 4 : 2 : 2 (ITU656-like)

YCbCr 4 : 2 : 2

VPA[0] Cb[0] Y₀[0]

VPA[1] Cb[1] Y₀[1]

VPA[2] Cb[2] Y₀[2]

VPA[3] Cb[3] Y₀[3]

Cr[0]

Y₁[0]

VPB[0] Cb[4] Y₀[4]

VPB[1] Cb[5] Y₀[5]

VPB[2] Cb[6] Y₀[6]

VPB[3] Cb[7] Y₀[7]

VPB[4] Cb[8] Y₀[8]

VPB[5] Cb[9] Y₀[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

HSYNC/HREF not used

VSYNC/VREF not used

Cr[1]

Y₁[1]

Cr[2]

Y₁[2]

DE/FREF

not used

Cr[3]

Y₁[3]

VPA[4] -

VPA[5] -

VPA[6] -

VPA[7] -

-

VPB[6] Cb[10] Y₀[10] Cr[10] Y₁[10]

VPB[7] Cb[11] Y₀[11] Cr[11] Y₁[11]

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Cb [11:0]

0

Y [11:0]

0

Cr [11:0]

0

Y [11:0]

1

...

Cr [11:0]

xxx

Y

[1:0]

xxx

001aai448

Fig 11. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization input (double edge)

TDA19988

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Product data sheet

Rev. 3 — 21 July 2011

21 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

7.2.3.7 YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge)

Table 14. YCbCr 4 : 2 : 2 semi-planar external synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.

Video port A

Pin YCbCr 4 : 2 : 2

semi-planar

Video port B

Pin YCbCr 4 : 2 : 2

semi-planar

Video port C

Pin YCbCr 4 : 2 : 2

semi-planar

Control

YCbCr 4 : 2 : 2

VPA[0] Y₀[0]

VPA[1] Y₀[1]

VPA[2] Y₀[2]

VPA[3] Y₀[3]

VPA[4] Cb[0]

VPA[5] Cb[1]

VPA[6] Cb[2]

VPA[7] Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

VPB[0] Y₀[4]

VPB[1] Y₀[5]

VPB[2] Y₀[6]

VPB[3] Y₀[7]

VPB[4] Y₀[8]

VPB[5] Y₀[9]

VPB[6] Y₀[10]

VPB[7] Y₀[11]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Y₁[10]

Y₁[11]

VPC[0] Cb[4]

VPC[1] Cb[5]

VPC[2] Cb[6]

VPC[3] Cb[7]

VPC[4] Cb[8]

VPC[5] Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

HSYNC/HREF used

VSYNC/VREF

DE/FREF

used

VPC[6] Cb[10] Cr[10]

VPC[7] Cb[11] Cr[11]

VCLK

HSYNC/HREF

VSYNC/VREF

DE/FREF

CONTROL

INPUTS

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Y [11:0]

0

Y [11:0]

1

Y [11:0]

2

Y [11:0]

3

Y [11:0]

4

Y [11:0]

5

...

VPC[0] to VPC[7];

VPA[4] to VPA[7]

Cb [11:0]

0

Cr [11:0]

0

Cb [11:0]

2

Cr [11:O]

2

Cb [11:0]

4

Cr [11:0]

4

...

001aai449

Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input synchronization (rising edge)

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7.2.3.8 YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge)

Table 15. YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge) mapping

Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h.

Video port A

Pin YCbCr 4 : 2 : 2

semi-planar

Video port B

Pin YCbCr 4 : 2 : 2

semi-planar

Video port C

Pin YCbCr 4 : 2 : 2

semi-planar

Control

YCbCr 4 : 2 : 2

VPA[0] Y₀[0]

VPA[1] Y₀[1]

VPA[2] Y₀[2]

VPA[3] Y₀[3]

VPA[4] Cb[0]

VPA[5] Cb[1]

VPA[6] Cb[2]

VPA[7] Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

VPB[0] Y₀[4]

VPB[1] Y₀[5]

VPB[2] Y₀[6]

VPB[3] Y₀[7]

VPB[4] Y₀[8]

VPB[5] Y₀[9]

VPB[6] Y₀[10]

VPB[7] Y₀[11]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Y₁[10]

Y₁[11]

VPC[0] Cb[4]

VPC[1] Cb[5]

VPC[2] Cb[6]

VPC[3] Cb[7]

VPC[4] Cb[8]

VPC[5] Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

HSYNC/HREF not used

VSYNC/VREF

DE/FREF

not used

VPC[6] Cb[10] Cr[10]

VPC[7] Cb[11] Cr[11]

VCLK

VPB[0] to VPB[7];

VPA[0] to VPA[3]

Y [11:0]

...

0

1

2

3

4

5

VPC[0] to VPC[7];

VPA[4] to VPA[7]

Cb [11:0]

0

Cr [11:0]

0

Cb [11:0]

2

Cr [11:0]

2

Cb [11:0]

4

Cr [11:0]

4

001aai450

Fig 13. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization input (rising edge)

7.2.4 Synchronization

TDA19988 can be synchronized with extraction of the sync information from embedded

sync (SAV/EAV) codes inside the video stream or with external HSYNC/VSYNC inputs.

7.2.4.1 Timing extraction generator

Synchronization signals can be extracted from Start Active Video (SAV) and End Active

Video (EAV) in case of embedded synchronization in the data stream.

Synchronization signals can be embedded or external.

7.2.4.2 Data enable generator

TDA19988 contains a Data Enable (DE) generator; this can generate an internal DE

signal for a system which does not provide one.

7.3 Input and output video format

Thanks to the flexible video input formatter, TDA19988 can accept a large range of input

formats. This flexibility allows TDA19988 to be compatible with the maximum possible

number of audio/video processors. Moreover, these input formats may be changed in

many ways (color space converter, upsampler, downsampler) before it is transmitted

across the HDMI link. Table 16 gives the possible inputs and outputs.

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Table 16. Use of color space converter, upsampler and downsampler

Input

Output

Color space

RGB

Color space

Format

Channels

Format

4 : 4 : 4

4 : 2 : 2

4 : 4 : 4

4 : 2 : 2

4 : 4 : 4

4 : 2 : 2

4 : 4 : 4

4 : 2 : 2

Channels

3  8-bit

2  12-bit

3  8-bit

2  12-bit

3  8-bit

2  12-bit

3  8-bit

2  12-bit

RGB

4 : 4 : 4

3  8-bit

YCbCr

RGB

YCbCr

4 : 4 : 4

4 : 2 : 2

3  8-bit

YCbCr

up to 2  12-bit RGB

semi-planar

YCbCr

up to 1  12-bit RGB

ITU656

YCbCr

7.4 Upsampler

The incoming YCbCr 4 : 2 : 2 (2  12-bit) data stream format may be upsampled into

YCbCr 4 : 4 : 4 (3  8-bit) data stream by repeating or linearly interpolating the

chrominance pixels.

7.5 Color space converter

The color space converter is used to convert input video data from one type to another

color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and

each coefficient is programmable via the I²C-bus register.













C₁₁C₁₂C₁₃

C₂₁C₂₂C₂₃

C₃₁C₃₂C₃₃

Oin_{G  Y}

Oin_{R  Cr}

Oin_{B  Cb}

Oout_Y\G

Oout_Cr\R

Oout_Cb\B

Y\G

Cr\R

Cb\B

Y

=



+

(1)

R  Cr

B  Cb

7.6 Gamut-related metadata

Gamut-related metadata is an enhanced colorimetry beyond the default standard with

higher definition colorimetries. Profile P0 is supported, which means that only one packet

per video field is sent.

Examples:

• xvYCC601 (IEC 61966-2-4 – SD) (using YCbCr)

• xvYCC709 (IEC 61966-2-4 – HD) (using YCbCr)

• AdobeYCC601 (IEC 61966-2-5) (using YCbCr)

• AdobeRGB (IEC 61966-2-5) (using RGB)

Remark: Gamut-related metadata is an HDMI 1.4a feature.

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7.7 Downsampler

This block works only with YCbCr input format; the filters downsample the Cb and Cr

signals by a factor of 2. A delay is added on the Y channel, which corresponds to the

pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel.

7.8 Audio input format

TDA19988 is compatible with the following audio features described in the “HDMI

specification 1.4a”:

• S/PDIF

• I²S-bus up to four stereo channels (depending on package)

TDA19988 can carry audio in I²S-bus format (one stereo to four stereo channels) or in

S/PDIF format through audio pins named AP1, AP2, AP3 and AP4 (depending on

package). S/PDIF or I²S-bus format can be selected via the I²C-bus. Only one audio

format can be used at a time: either S/PDIF or I²S-bus. Table 17 shows the audio port

allocation and Section 7.8.3 gives more details.

Table 17. Audio port configuration

Audio port

Input configuration

S/PDIF

I²S-bus

AP0

-

WS (word select)

I²S-bus channel 0

I²S-bus channel 1

I²S-bus channel 2

I²S-bus channel 3

SCK (I²S-bus clock)

AP1

S/PDIF input

AP2

AP3^[1]

AP4^[1]

ACLK

-

[1] Depending on package.

All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant. It is possible

to deactivate unused ports via I²C-bus with ENA_AP register on page 00h for both audio

and clock inputs.

7.8.1 S/PDIF

In this format TDA19988 supports 2-channel uncompressed PCM data (IEC 60958) layout

0, or compressed bit stream (Dolby Digital, DTS, AC3 etc.) layout 1.

Only one S/PDIF input can be used at the same time. The selection is done by register.

TDA19988 is able to recover the original clock from the S/PDIF signal (no need of external

clock). In addition, it can also use an external clock to decode the S/PDIF signal.

7.8.2 I²S-bus

There are 2  I²S-bus or 4  I²S-bus (depending on package) stereo input, which enables

4 or 8 (depending on package) PCM channels to be carried. The I²S-bus input interface

receives an I²S-bus signal including serial data, word select and serial clock.

Typical waveforms for the I²S-bus signals at 64f_sare given by Figure 14.

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LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

MSB

24-bit audio sample word

LSB

0

audio clock

64f

s

001aah029

a. Philips format.

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

MSB

24-bit audio sample word

LSB

0

audio clock

64f

s

001aah030

b. Left justified format.

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

(n−1)

(n)

(n+1)

word select

f

s

0

MSB

24-bit audio sample word

LSB

audio clock

64f

s

001aah031

c. Right justified format.

Fig 14. I²S-bus formats

The I²S-bus input interface can receive up to 24-bit wide audio samples via the serial data

input with a clock frequency of at least 32 times the input sample frequency f_s.

Audio samples with a precision better than 24-bit are truncated to 24-bit. If the input clock

has a frequency of 32f_s, only 16-bit audio-samples can be received. In this case, the 8

LSBs will be set to 0. If the input clock has a frequency of 64f_sand is left justified or

Philips, the audio word is truncated to 24-bit format and other bits padded with zeros. If

the input clock has a frequency of 64f_sand is right justified, audio sample size has to be

specified via software drivers.

The serial data signal carries the serial baseband audio data, sample by sample left/right

interleaved.

The word select signal indicates whether left or right channel information is transferred

over the serial data line.

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7.8.3 Audio port internal assignment

The aim of the internal audio input assignment is to internally map any of the incoming

data from the audio port AP1, AP2 to S/PDIF internal ports by setting the appropriate

I²C-bus register.

TDA19988

AUDIO

INTERNAL S/PDIF PORT

AP1

S/PDIF

AP2

2

I C-bus select

001aao144

Fig 15. Audio input swap to S/PDIF

7.9 Power management

TDA19988 HDMI and CEC cores can be independently powered down by the I²C-bus

register. In Standby mode all activities are reduced by switching off all PLLs, HDMI and

CEC cores and disconnecting the biasing structure of the output stage. TDA19988 has a

very low power consumption, which is suitable for portable applications.

Table 18 gives the typical power consumption of the device in different configurations.

Table 18. TDA19988 typical power consumption in different configurations

Typical power Configuration

Comment

18 W

Standby mode:

• I²C-bus ON

default configuration: after power-up; PLLs

HDMI and CEC cores are OFF; can be

switched ON via I²C-bus register

• HDMI interruption (HPD,

RxSense only)

0.9 mW

1.3 mW

Sleep mode without CEC:

no sink connected; CEC is OFF

no sink connected; CEC is ON

• HDMI interruption (HPD,

RxSense only)

Sleep mode with CEC:

• HDMI interruption (HPD,

RxSense only)

• CEC interruption

Operation mode:

60 mW

95 mW

sink connected; 30 % activity on video input

ports

• Video format 720p/1080i

• Video input RGB 24-bit

Full speed mode:

30 % activity on video input ports

• Video format 1080p

• Video input RGB 24-bit

In both Standby and Sleep modes, all video and audio pins are equivalent to

high-impedance.

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7.10 Interrupt controller

Pin INT is used to alert the system microcontroller that a critical event concerning the

HDMI or CEC has occurred. The software provided with the device read a status register

(I²C-bus) to determine which block between HDMI and CEC has caused the interruption

before processing it. Some of theses interrupts are maskable. The interrupt types are

described in Table 19.

Table 19. Interruptions

Interrupt domain

Interrupt name

Definition

Maskable feature

HDCP

r0

r0 = R’0 check done

pj = P’j check fails

V = V’ check success

bstatus available

bcaps available

maskable

pj

sha-1

bstatus

bcaps

t0

error in HDCP state

machine

HPD

hpd

transition on HPD input maskable

transition on RxSense maskable

RxSense

Interrupt

rx_sense

sw_intsoftware

test purpose (output an maskable

interrupt signal)

EDID

CEC

edid_block_rd

cec_int

EDID block read finished maskable

CEC message received not maskable

7.10.1 Hot plug/unplug detect

The Hot Plug Detect (HPD) pin is 5 V input tolerant. The HPD signal, when asserted, tells

the transmitter that the receiver is connected. When changing from LOW-to-HIGH,

TDA19988 has to read the EDID of the receiver in order to select video format that the

receiver can handle.

7.10.2 Receiver sensitivity

TDA19988 has the capability to sense the receiver connectivity and working behavior.

This feature (RxSense) detects the presence of the 50  pull-up resistor R_Ton the TMDS

clock channel of the downstream side.

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RECEIVER

V

CC

R

pu

HDMI cable

V

1.8 V

DD

pole τ =

80 ns

35 kΩ

Vinp_rxs

Vinn_rxs

power_down

35 kΩ

RXS_FIL

INTERNAL

BANDGAP

0.935 V 4ꢀ

I_transmit

TDA19988

001aan688

Fig 16. Receiver sensitivity detection

As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set

to logic 1.

As soon as the cable is unplugged or receiver side powered off (assuming in this case that

V_CCis switched off), the RxSense generates an interrupt inside TDA19988, changing the

value of bit RXS_FIL to logic 0 (See Table 20). This allows the application to stop sending

unnecessary video content.

This feature is very useful when the receiver recovers from an off-state and does not

generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will

generate an interrupt so that the chip restarts sending video.

Table 20. Receiver detection according to averaged terminal voltage

Average voltage

(Vinp_rxs + Vinn_rxs) / 2

bit RXS_FIL: receiver

powered on

bit RXS_FIL: receiver

powered off

V  1.2 V

1

0

0.7 V < V < 1.2 V

V  0.7 V

undefined

0

Remark: According to the HDMI specification, only the HPD interrupt allows the

application to read the EDID. The RxSense interrupt is not mandatory to initialize the

EDID reading procedure.

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7.11 HDCP processing (TDA19988AHN and TDA19988AET only)

7.11.1 High-bandwidth digital content protection

TDA19988AHN and TDA19988AET contain an HDCP function, which encrypts the

transmitted stream content (both video and audio). This function can be enabled and

disabled via the I²C-bus.

The keys are stored internally in OTP non-volatile memory for maximum security.

7.11.1.1 Repeater function

TDA19988AHN and TDA19988AET can be used in a repeater device according to the

HDCP specification, Rev 1.4. TDA19988AHN and TDA19988AET are able to store the

KSV list of a maximum of 127 devices in a register memory.

7.11.1.2 SHA-1

To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the

downstream repeater. For security purposes and in order to relieve the microcontroller,

the SHA-1 has been implemented within TDA19988.

This calculation is worked out after the transmitter has loaded the KSV list (see HDCP

specification, Rev 1.4). If SHA-1 calculated by transmitter equals the SHA-1 calculated by

repeater, then an interrupt is sent.

7.12 CEC

TDA19988 with its embedded CEC block provides a complete solution to enable

Consumer Electronic Control (CEC) in product (DSC, DVC, PMP, UM PC). This eliminates

the need of any additional device to handle this feature thus improving BOM (Bill Of

Materials). CEC capability allows AV products (CEC enable) to communicate together

over the home appliance network which could be controlled using only one remote

control.

The CEC block manages low level transactions (compliant to CEC timing specification)

over the one bidirectional line. It translates CEC protocol in I²C-bus for the host processor

and vice versa. It manages CEC message reception and transmission compliant to CEC

protocol and provides the message to the system microcontroller (host processor).

For power consumption optimization purpose CEC could be enabled or disabled through

I²C-bus register. The following sections describe CEC:

• Features

• Clocking scheme

7.12.1 Features

• Receive and transmit CEC messages to host processor

• Supports multiple CEC logical addresses

• Supports CEC messages up to 16 bytes long

• Programmable retry count

• Comprehensive arbitration and collision handling

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7.12.2 Clock

HDMI 1.4a transmitter with HDCP and CEC support

CEC clock must be running in Sleep mode (with CEC) to wake up TDA19988 using CEC

specific message as described in “HDMI specification 1.4a”.

CEC module can be clocked using:

• External clock:

– 12 MHz crystal  1 %.

• Internal clock:

– FRO (Free Running Oscillator). FRO frequency varies and in the range from

12.64 MHz to 12.9 MHz. See Figure 17.

CEC operates normally (i.e. matches the timing requested CEC specification) if and only if

its clock frequency is set to 12 MHz.

TDA19988

CEC clock calibration module

FRO

DIVIDER

CEC CLK

12 MHz

CEC

MODULE

2

I C-bus

2

INT

I C-bus

HOST PROCESSOR

001aan685

Fig 17. Modules involved in CEC clock calibration process

Calibration procedure is completely handled by the software delivered together with the

device, it has the following steps:

• Host processor set TDA19988 in calibration mode

• Host processor generates a negative pulse of 10 ms  1 % on INT pin

• Host processor deselects the calibration mode when it is completed, the chip is ready

to operate

CEC clock calibration must be performed at each power-up and each time TDA19988

moves from Standby or Sleep (without CEC) state to normal operating mode.

Non successful calibration will lead to CEC signal not matching timings specification; as a

consequence, CEC will not be functional.

7.12.3 CEC interrupt

Pin INT is used by TDA19988 to warn the host processor that HDMI or CEC events (CEC

message is available to read) have occurred.

Software interrupt status register reads determine which block between HDMI or CEC has

raised the interruption before processing it.

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7.13 HDMI core

7.13.1 Pixel repetition

To transmit video formats with pixel rates below 25 megasamples per second or to

increase the number of audio sample packets in each frame, TDA19988 allows pixel

repetition to increase the transmitted pixel clock. Pixel repetition factor can be adjusted

from 1 to 10.

7.13.2 DDC-bus channel

The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode

(100 kHz). The DDC-bus is used as a master interface when reading the EDID.

When the device is power-off, DSDA and DSCL ports:

• become in high-impedance

• can withstand 5 V from the sink

7.14 E-EDID

7.14.1 E-EDID reading

As a master interface for the EDID process, the DDC-bus is compliant with the I²C-bus

specification and has the possibility of repeat/start condition to enable quick access to the

EDID content, as well as the possibility of reading a large EDID (with the use of segment

pointer).

TDA19988 has a whole I²C-bus (page 09h) dedicated to the EDID where one block (128

bytes) can be stored. The block can be read by the system microcontroller to determine

the supported video and audio format of the downstream site.

Remark: When the block is read by TDA19988, it generates an interrupt to warn the main

processor that the chip is ready to transmit the content. Once the content is read out by

the main processor, it can allow other blocks to be read if required.

7.14.2 HDMI and DVI receiver discrimination

This information is located in the E-EDID receiver part, in the ‘vendor-specific data block’

within the first CEA EDID timing extension.

If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver

will support HDMI, otherwise the device will be treated as a DVI device.

However, even through TDA19988 have directly access to that information, it is the task of

the host processor to ask to switch from DVI to HDMI mode.

8. I²C-bus interface and register definitions

8.1 I²C-bus protocol

The I²C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast mode

(400 kHz) and Standard mode (100 kHz) are supported.

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The registers of TDA19988 can be accessed via the I²C-bus. All registers are R/W except

for those which are confidential.

HDMI and CEC cores I²C-bus addresses are given in Table 21 and Table 22.

Table 21. HDMI core I²C-bus address

HDMI core address

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

X^[1]

0/1

[1] X can be selected for HVQFN package. X is set to 0 for TFBGA package

Table 22. CEC core I²C-bus address

CEC core address

A6

A5

A4

A3

A2

A1

A0

R/W

0

1

0

1

X^[1]

0/1

[1] X can be selected for HVQFN package. X is set to 0 for TFBGA package

For read access, the master writes the address of TDA19988 HDMI or CEC core, and the

subaddress to access the specific register and then the data.

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

CSCL

CSDA

SLAVE ADDRESS

SUBADDRESS

DATA

STOP

001aal419

Fig 18. I²C-bus access

8.2 Memory page management

The I²C-bus memory is split into several pages for HDMI core only, and the selection

between pages is made with common register CURPAGE_ADR. It is only necessary to

write in this register once to change the current page. So multiple read or write operations

in the same page need a write register CURPAGE_ADR once at the beginning.

The following memory pages are available for TDA19988:

• Page 00h: general control

• Page 02h: PLL settings

• Page 09h: EDID control page

• Page 10h: information frames and packets

• Page 11h: audio settings and content info packets

• Page 12h: HDCP (TDA19988AHN and TDA19988AET only) and OTP

• Page 13h: gamut-related metadata packets

The CEC core does not need memory page mechanism due to its reduced number of

registers.

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8.3 ID version

The ID version readable via I²C-bus is defined by the concatenation of VERSION_MSB

and VERSION registers. The ID version value is 212h.

8.4 Clock stretching

Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction

cannot continue until the line is released HIGH again.

For example: on the byte level, a device may be able to receive bytes of data at a fast

rate, but needs more time to store a received byte or prepare another byte to be

transmitted. Slaves can then hold the CSCL line LOW after reception and

acknowledgment of a byte to force the master into a wait state until the slave is ready for

the next byte transfer; see Table 31.

Clock stretching must be supported by I²C-bus master especially when CEC feature of

TDA19988 is used. If CEC feature of TDA19988 is not used, I²C-bus master does not

need to support clock stretching.

9. Input format

In Table 23 the port VPA has been mapped to C_b(YCbCr space)/B (RGB space), VPB has

been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr

(YCbCr space)/R (RGB space).

Table 23. Input format

L: recommend tied to LOW voltage, e.g. ground

Input pins Signal

RGB

YCbCr

4 : 4 : 4

4 : 2 : 2 (semi-planar)

4 : 2 : 2 (ITU 656-like)

Video port A

VPA[0]

VPA[1]

VPA[2]

VPA[3]

VPA[4]

VPA[5]

VPA[6]

VPA[7]

Video port B

VPB[0]

VPB[1]

VPB[2]

VPB[3]

VPB[4]

VPB[5]

VPB[6]

VPB[7]

Cb[0]/B[0]

B[0]

B[1]

B[2]

B[3]

B[4]

B[5]

B[6]

B[7]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Y₀[0]

Y₀[1]

Y₀[2]

Y₀[3]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

Cb[0]

Cb[1]

Cb[2]

Cb[3]

L

Y₀[0]

Y₀[1]

Y₀[2]

Y₀[3]

L

Cr[0]

Cr[1]

Cr[2]

Cr[3]

L

Y₁[0]

Y₁[1]

Y₁[2]

Y₁[3]

L

Cb[1]/B[1]

Cb[2]/B[2]

Cb[3]/B[3]

Cb[4]/B[4]

Cb[5]/B[5]

Cb[6]/B[6]

Cb[7]/B[7]

L

Y[0]/G[0]

Y[1]/G[1]

Y[2]/G[2]

Y[3]/G[3]

Y[4]/G[4]

Y[5]/G[5]

Y[6]/G[6]

Y[7]/G[7]

G[0]

G[1]

G[2]

G[3]

G[4]

G[5]

G[6]

G[7]

Y[0]

Y[1]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Y₀[10]

Y₀[11]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Y₁[10]

Y₁[11]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Cb[8]

Cb[9]

Cb[10]

Cb[11]

Y₀[4]

Y₀[5]

Y₀[6]

Y₀[7]

Y₀[8]

Y₀[9]

Y₀[10]

Y₀[11]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

Y₁[4]

Y₁[5]

Y₁[6]

Y₁[7]

Y₁[8]

Y₁[9]

Cr[10] Y₁[10]

Cr[11] Y₁[11]

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 23. Input format …continued

L: recommend tied to LOW voltage, e.g. ground

Input pins Signal

RGB

YCbCr

4 : 4 : 4

4 : 2 : 2 (semi-planar)

4 : 2 : 2 (ITU 656-like)

Video port C

VPC[0]

VPC[1]

VPC[2]

VPC[3]

VPC[4]

VPC[5]

VPC[6]

VPC[7]

Cr[0]/R[0]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

R[6]

R[7]

Cr[0]

Cr[1]

Cr[2]

Cr[3]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cb[4]

Cb[5]

Cb[6]

Cb[7]

Cb[8]

Cb[9]

Cr[4]

Cr[5]

Cr[6]

Cr[7]

Cr[8]

Cr[9]

L

Cr[1]/R[1]

Cr[2]/R[2]

Cr[3]/R[3]

Cr[4]/R[4]

Cr[5]/R[5]

Cr[6]/R[6]

Cr[7]/R[7]

Cb[10] Cr[10]

Cb[11] Cr[11]

9.1 Timing parameters for video supported

TDA19988 supports all EIA/CEA-861B standards and ATSC video formats.

Table 24. Timing parameters for EIA/CEA-861B

EIA/CEA-861B

Video code

Format

V frequency H total

(Hz)

V total

H frequency Pixel

Pixel

repetition

(kHz)

frequency

(MHz)

59.94 Hz systems

1 (VGA)

640  480p

720  480p

1280  720p

1920  1080i

1440  480i

1920  1080p

59.9401

60.000

800

525

750

1125

525

1125

31.469

44.955

33.716

15.734

67.432

25.175

27.000

74.175

27.000

148.350

1

2

1

2, 3

858

4

1650

2200

1716

2200

5

6, 7 (NTSC)

16

60 Hz systems

1 (VGA)

640  480p

720  480p

1280  720p

1920  1080i

1440  480i

1920  1080p

60.000

800

525

750

1125

525

1125

31.500

45.000

33.750

15.750

67.500

25.200

27.027

74.250

27.027

148.50

1

2

1

2, 3

858

4

1650

2200

1716

2200

5

6, 7 (NTSC)

16

50 Hz systems

17, 18

720  576p

50.000

864

625

31.250

37.500

28.125

15.625

56.250

27.000

74.250

27.000

148.50

1

2

1

19

1280  720p

1920  1080i

1440  576i

1920  1080p

1980

2640

1728

2640

750

20

1125

625

21, 22 (PAL)

31

1125

Various systems

32

1920  1080p

23.976

24

2750

1125

26.973

27

74.175824

74.25

1

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 24. Timing parameters for EIA/CEA-861B …continued

EIA/CEA-861B

Video code

Format

V frequency H total

(Hz)

V total

H frequency Pixel

Pixel

repetition

(kHz)

frequency

(MHz)

33

34

1920  1080p

25

2640

2200

1125

28.125

33.716

33.75

74.25

1

29.97

30

74.175824

74.25

TDA19988 support other video formats, so software implementation can be considered on

request.

9.2 Timing parameters for PC standards supported

TDA19988 can support all major PC Standards up to 165 MHz.

Table 25. Timing parameters for PC standards below 165 MHz

Standard

Format

V frequency

(Hz)

H total

V total

H frequency

(kHz)

Pixel frequency Pixel

(MHz)

repetition

0.31M3

VGA

640  480p

800  600p

1024  768p

1280  1024p

59.940

72.809

75.000

85.008

60.317

72.188

75.000

85.061

60.004

70.069

75.029

60.020

800

525

520

500

509

628

666

625

631

806

800

1066

31.469

37.861

37.500

43.269

37.879

48.077

46.875

53.674

48.363

56.476

60.023

63.981

25.175

31.500

36.000

40.000

50.000

49.500

56.250

65.000

75.000

78.750

108.000

-

832

840

832

0.48M3

SVGA

1056

1040

1056

1048

1344

1328

1312

1688

0.79M3

XGA

1.31M4

SXGA

VDMTREV 1600  1200p

60.000

2160

1250

75.000

162.000

-

For other PC video formats in the range from VGA to 1600  1200 at 60 Hz

implementation can be considered on request.

9.3 Primary 3D video formats

Table 26. 3D video formats timing supported

Resolution

3D transmission type

1280  720p at 59.94 Hz and 60 Hz

1280  720p at 50 Hz

(Frame Packing, Side-by-Side (Half)), Top-and-Bottom

Frame Packing

1280  720p at 23.98 Hz and 24 Hz

1280  720p at 29.97 Hz and 30 Hz

1920  1080i at 59.94 Hz and 60 Hz

1920  1080i at 50 Hz

Frame Packing

Side-by-Side (Half)

1920  1080p at 23.98 Hz and 24 Hz

Side-by-Side (Half), Top-and-Bottom

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Product data sheet

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 26. 3D video formats timing supported …continued

Resolution

3D transmission type

1920  1080p at 29.97 Hz and 30 Hz

1920  1080p at 59.94 Hz and 60 Hz

1920  1080p at 50 Hz

Top-and-Bottom

TDA19988 support other 3D video formats, so software implementation can be

considered on request.

10. Limiting values

Table 27. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

0.5

2

Max

+2.5

+2

Unit

V

V_{DDA(TMDS)(1V8)}TMDS analog supply voltage (1.8 V)

V_{DDA(PLL)(1V8)}

V_DDA(1V8)

V_DDD(IO)(1V8)

V_DDDC

PLL analog supply voltage (1.8 V)

analog supply voltage (1.8 V)

I/O digital supply voltage (1.8 V)

core digital supply voltage

supply voltage difference

V

V_DD

V

V_IO

input/output voltage

3.3 V tolerant I/O

0.3

2.5

1

+3.6

+5.5

+2.5

+1

V

5 V tolerant I/O

V

[1]

[2]

V_ESD

electrostatic discharge voltage

EIA/JESD22-A114 (HBM)

EIA/JESD22-C101-C (FCDM)

kV

[1] On TMDS outputs.

[2] It withstands class III of JEDEC classification.

11. Thermal characteristics

Table 28. Thermal characteristics

Symbol

R_th(j-a)

R_th(j-c)

T_stg

Parameter

Conditions

Min Typ

Max

-

Unit

K/W

C

thermal resistance from junction to ambient

thermal resistance from junction to case

storage temperature

in free air; JEDEC 4L board

-

56.9

-

15.1

-

+150

+85

+125

T_amb

T_j

ambient temperature

20

C

junction temperature

-

C

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

12. Static characteristics

Table 29. Supplies

T_amb= 20 C to +85 C; without HDCP; unless otherwise specified.

Symbol

V_DDDC

Parameter

Conditions

Min

1.7

-

Typ

1.8

13

Max

1.9

16

Unit

V

[1]

core digital supply voltage

V_{DDA(TMDS)(1V8)}TMDS analog supply voltage (1.8 V)

V

V_{DDA(PLL)(1V8)}

V_DDA(1V8)

V_DDD(IO)(1V8)

I_{DDA(sum)(1V8)}

PLL analog supply voltage (1.8 V)

analog supply voltage (1.8 V)

V

I/O digital supply voltage (1.8 V)

sum analog supply current (1.8 V)

V

[2]

720p60

mA

1080p60

-

23

27

I_{DDA(PLL)(1V8)}

I_DDD(IO)(1V8)

PLL analog supply current (1.8 V)

-

6

8

input/output digital supply current

(1.8 V)

-

0.06

0.1

[2]

[3]

[4]

I_DDDC(1V8)

core digital supply current (1.8 V)

720p60

-

26

40

60

95

-

29

42

75

115

146

-

mA

1080p60

mA

P_cons

power consumption

720p60

mW

W

1080p60

Sleep mode with CEC

Sleep mode without CEC

Standby mode

1.3

0.9

18

172

207

-

[2]

P_tot

total power dissipation

-

mW

-

[1] See Table 7.

[2] Full RGB input 24-bit 30 % activity on video ports, HDMI RGB output, HDCP (TDA19988AHN and TDA19988AET only) enable.

[3] Full RGB input 24-bit 30 % activity on video ports, HDMI RGB output, HDCP (TDA19988AHN and TDA19988AET only) disable.

[4] Full YCbCr input 24-bit 30 % activity on video ports, HDMI RGB output, HDCP (TDA19988AHN and TDA19988AET only) enable.

Table 30. Digital inputs and outputs

T_amb= 20 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Not 5 V tolerant CMOS 1.8 V and CMOS 3.3 V tolerant digital input pins HSYNC, VSYNC, APn, ACLK, VPA[n],

VPB[n], VPC[n], VCLK, DE

V_IL

V_IH

I_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level input current

HIGH-level input current

input capacitance

-

0.75

-

V

1.4

2

-

V

-

+2

-

A

pF

I_IH

C_i

-

4.5

5 V tolerant input pin HPD

V_IL

V_IH

C_i

LOW-level input voltage

-

0.8

V

HIGH-level input voltage

input capacitance

2

-

V

4.5

pF

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NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 30. Digital inputs and outputs …continued

T_amb= 20 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

CMOS 1.8 V and CMOS 3.3 V tolerant digital input/output pin INT

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.85

-

V

V_IH

1.4

-

V_OL

LOW-level output voltage C_L= 10 pF; I_OL= 2 mA

0.4

5 V tolerant master bus: DDC-bus pins DSDA, DSCL^[1]

V_OL

V_IL

LOW-level output voltage

LOW-level input voltage

HIGH-level input voltage

-

0.4

1.5

-

V

-

V_IH

3.0

1.8 V to 3.3 V tolerant slave bus: I²C-bus input/output pins CSCL, CSDA^[1]

V_OL

V_IL

LOW-level output voltage

LOW-level input voltage

HIGH-level input voltage

-

0.4

0.85

-

V

-

V_IH

1.4

CEC input/output^[2]pin

V_OL

V_OH

V_IL

LOW-level output voltage

-

0.4

-

V

HIGH-level output voltage

LOW-level input voltage

HIGH-level input voltage

2.5

-

0.8

-

V_IH

2.0

TMDS output pins: TX0, TX0+, TX1, TX1+, TX2, TX2+, TXC and TXC+

V_O(dif)differential output voltage R_{EXT_SWING}= 10 k  1 %

420

500

580

mV

[1] See Section 7.1 and refer to the I²C-bus specification version 2.1 (document order number 9398 393 40011).

[2] For information, input hysteresis is normally supplied by the microprocessor input circuit: in this circumstance, external hysteresis

circuitry is not needed.

13. Dynamic characteristics

Table 31. Timing characteristics

T_amb= 20 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock input: pin VCLK

f_clk(max)

t_su(D)

t_h(D)

maximum clock frequency

-

165

1.5

0.7

30

-

MHz

ns

data input set-up time

data input hold time

clock duty cycle

see Figure 19 and 20

-

ns

[1]

_clk

50

12

70

-

%

f_clk

clock frequency

CEC

MHz

Clock input: pin ACLK

t_su(D)data input set-up time

t_h(D)data input hold time

DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus^[2]

3

-

ns

0.7

f_SCL

SCL frequency

Standard mode

-

100

-

kHz

pF

C_i

capacitance for each I/O pin

7

I²C-bus: pins CSCL, CSDA (5 V tolerant) slave bus^[2]

TDA19988

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

Table 31. Timing characteristics …continued

T_amb= 20 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Standard mode

Fast mode

CEC

Min

Typ

Max

100

400

-

Unit

kHz

s

f_SCL

SCL frequency

-

t_stretch

stretch time

80

CEC input/output^[3]

t_r

t_f

rise time

fall time

10 % to 90 %

-

50

2

s

TMDS output pins: TXC and TXC+

f_clk(max)maximum clock frequency

on the TMDS link

165

-

MHz

GHz

TMDS output pins: TX0, TX0+, TX1, TX1+, TX2 and TX2+

f_clk(max)maximum clock frequency

1.65

[1]

_clk= t_clk(H)/ (t_clk(H)+ t_clk(L)).

[2] See Section 7.1 and refer to the I²C-bus specification version 2.1 (document order number 9398 393 40011).

[3] For details about CEC electrical specification, see HDMI specification 1.4a.

EDGE = 0

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

EDGE = 1

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

data is not allowed to change in this period

data can change to meet the minimum set-up and hold time requirement

001aah035

Fig 19. Set-up and hold time definition diagram for single-edge clock mode

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

VCLK

VPA[0] to VPA[7]

VPB[0] to VPB[7]

VPC[0] to VPC[7]

DE, HSYNC, VSYNC

t

h(D)

su(D)

h(D)

su(D)

data is not allowed to change in this period

data can change to meet the minimum set-up and hold time requirement

001aah036

Fig 20. Set-up and hold time definition diagram for double-edge clock mode

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TDA19988

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HDMI 1.4a transmitter with HDCP and CEC support

14. Application information

14.1 Transmitter connection with external world

Figure 21 and Figure 22 refer to a simple receiver application. However, TDA19988 can

be part of a repeater application as described in “HDMI specification 1.4a”.

TRANSMITTER SIDE

DOWNSTREAM SIDE

2

I C-bus

TMDS channel 0

TMDS channel 1

TMDS channel 2

TMDS clock

video 24-bit

MASTER

MAIN

2

sync

I C-BUS

SLAVE

audio

PROCESSOR

HDMI

TDA19988

RECEIVER/

REPEATER

HPD

12 MHz

EXTERNAL

CLOCK

DDC-bus channel

DDC-BUS

MASTER

SLAVE

CEC

001aan689

Fig 21. Connecting TDA19988 transmitter using external clock source

TRANSMITTER SIDE

DOWNSTREAM SIDE

2

I C-bus

TMDS channel 0

TMDS channel 1

TMDS channel 2

TMDS clock

video 24-bit

MASTER

MAIN

PROCESSOR

2

sync

I C-BUS

SLAVE

audio

HDMI

RECEIVER/

REPEATER

TDA19988

HPD

DDC-bus channel

DDC-BUS

MASTER

SLAVE

CEC

001aan690

Fig 22. Connecting TDA19988 transmitter using internal FRO for CEC

TDA19988

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

15. Package outline

TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls

SOT962-3

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

1/2 e

C

M

∅ v

∅ w

C

A

B

e

b

y

1

y

C

H

e

G

F

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max 1.10 0.30 0.80 0.35

nom 0.95 0.25 0.70 0.30

4.6

4.5

4.4

4.6

4.5

4.4

mm

0.5

3.5

0.15 0.05 0.08

0.1

min

0.85 0.20 0.65 0.25

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

08-05-26

08-06-18

SOT962-3

- - -

Fig 23. Package outline SOT962-3 (TFBGA64)

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;

64 terminals; body 9 x 9 x 0.85 mm

SOT804-4

D

B

A

terminal 1

index area

E

A

1

c

detail X

e

1

C

e

v

C

A

B

1/2 e

b

L

y

1

y

w

C

L

1

17

32

16

33

E

t

e

E

s

E

e

2

h

1/2 e

1

48

X

terminal 1

index area

64

49

L

D

t

s

h

2

0

2.5

5 mm

scale

Dimensions

Unit

(1)

A

b

c

D

h

D

s

D

t

E

e

1

e

2

L

2

v

w

y

1

h

s

t

1

max 1.00 0.05 0.30

mm nom 0.85 0.02 0.21 0.2 9.0 5.10 0.14 0.45 9.0 5.10 0.14 0.45 0.5 7.5 7.5 0.4 0.25 0.25 0.1 0.05 0.05 0.1

min 0.80 0.00 0.18 8.9 4.95 0.09 0.40 8.9 4.95 0.09 0.40

0.3

9.1 5.25 0.19 0.50 9.1 5.25 0.19 0.50

0.5

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot804-4_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

10-05-26

10-05-27

SOT804-4

Fig 24. Package outline SOT804-4 (HVQFN64)

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16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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HDMI 1.4a transmitter with HDCP and CEC support

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 32 and 33

Table 32. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 33. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

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HDMI 1.4a transmitter with HDCP and CEC support

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Abbreviations

Table 34. Abbreviations

Acronym

AC3

Description

Active Coding-3

ACP

ACR

ATSC

AV

Audio Content Protection

Audio Clock Recovery

Advanced Television Systems Committee

Audio Video

AVR

BOM

CEA

CEC

CTS/N

DDC

DDR

DE

Audio Video Recorder

Bill Of Materials

Consumer Electronics Association

Consumer Electronics Control

Clock Time Stamp integer divider

Display Data Channel

Double Data Rate

Data Enable

DSC

DTS

DVC

DVD

DVI

Digital Still Camera

Digital Transmission System

Digital Video Camera

Digital Versatile Disc

Digital Visual Interface

End Active Video

EAV

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Table 34. Abbreviations …continued

Acronym Description

EDID

E-EDID

EIA

Extended Display Identification Data

Enhanced Extended Display Identification Data

Electronic Industries Alliance

Field Charged Device Model

First In, First Out

FCDM

FIFO

FREF

FRO

Field REFerence

Free Running Oscillator

HBM

Human Body Model

HDCP

HDMI

HPD

High-bandwidth Digital Content Protection

High-Definition Multimedia Interface

Hot Plug Detection

HREF

HSYNC

KSV

Horizontal REFerence

Horizontal SYNChronization

Key Selection Vector

LSB

Least Significant Bit

LV-CMOS

MID

Low Voltage Complementary Metal-Oxide Semiconductor

Mobile Internet Device

MSB

Most Significant Bit

OTP

One Time Programming

PC

Personal Computer

PCM

Pulse Code Modulation

PLL

Phase-Locked Loop

PMP

Portable Multimedia Player

Power-On Reset

POR

RGB

R = red, G = green, B = blue

Start Active Video

SAV

SDR

Single Data Rate

SHA-1

SMPTE

S/PDIF

STB

Secure Hash Algorithm

Society of Motion Picture and Television Engineers

Sony/Philips Digital Interface

Set-Top Box

TMDS

Tx

Transition Minimized Differential Signalling

Transmitter

UM PC

UXGA60

VHREF

VREF

VSYNC

YCbCr

WS

Ultra-Mobile Personal Computer

Ultra Extended Graphics Array

Vertical Horizontal REFerence

Vertical REFerence

Vertical SYNChronization

Y = luminance, Cb = Chroma component blue, Cr = Chroma component red

Word Select

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18. Revision history

Table 35. Revision history

Document ID

TDA19988 v.3

Modifications:

Release date

20110721

Data sheet status

Change notice

Supersedes

Product data sheet

-

TDA19988 v.2

• Section 1: updated

• Section 2: updated

• Section 3: updated

• Section 7.11: updated

• Figure 1: updated

• Table 27: updated

• Table 30: updated

• Table 31: updated

TDA19988 v.2

TDA19988 v.1

20110601

Product data sheet

-

TDA19988 v.1

-

20110304

Objective data sheet

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

19.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

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HDMI 1.4a transmitter with HDCP and CEC support

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Licenses

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that complies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

19.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

21. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 4. Internal assignment . . . . . . . . . . . . . . . . . . . . .12

Table 5. Video input swap to VP[23:20] . . . . . . . . . . . . .13

Table 6. TDA19988 input/output capability . . . . . . . . . .14

Table 7. Inputs of video input formatter . . . . . . . . . . . . .15

Table 8. RGB (3 ´ 8-bit) external synchronization input

(rising edge) mapping . . . . . . . . . . . . . . . . . . .16

Table 9. YCbCr 4 : 4 : 4 (3 ´ 8-bit) external

downsampler . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. Audio port configuration . . . . . . . . . . . . . . . . . 25

Table 18. TDA19988 typical power consumption in

different configurations . . . . . . . . . . . . . . . . . . 27

Table 19. Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Receiver detection according to averaged

terminal voltage . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. HDMI core I²C-bus address . . . . . . . . . . . . . . 33

Table 22. CEC core I²C-bus address . . . . . . . . . . . . . . . 33

Table 23. Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 24. Timing parameters for EIA/CEA-861B . . . . . . 35

Table 25. Timing parameters for PC standards below

165 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 26. 3D video formats timing supported . . . . . . . . . 36

Table 27. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 28. Thermal characteristics . . . . . . . . . . . . . . . . . . 37

Table 29. Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. Digital inputs and outputs . . . . . . . . . . . . . . . . 38

Table 31. Timing characteristics . . . . . . . . . . . . . . . . . . . 39

Table 32. SnPb eutectic process (from J-STD-020C) . . . 46

Table 33. Lead-free process (from J-STD-020C) . . . . . . 46

Table 34. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 35. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 49

synchronization input (rising edge) mapping . .17

Table 10. YCbCr 4 : 2 : 2 ITU656-like external

synchronization input (rising edge) mapping . .18

Table 11. YCbCr 4 : 2 : 2 ITU656-like external

synchronization input (double edge) mapping .19

Table 12. YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization input (rising edge) mappings .20

Table 13. YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization input (double edge) mapping .21

Table 14. YCbCr 4 : 2 : 2 semi-planar external

synchronization input (rising edge) mapping . .22

Table 15. YCbCr 4 : 2 : 2 semi-planar embedded

synchronization input (rising edge) mapping . .23

Table 16. Use of color space converter, upsampler and

22. Figures

Fig 1. TDA19988 high-level block diagram . . . . . . . . . . .2

Fig 2. TDA19988 Block diagram . . . . . . . . . . . . . . . . . . .5

Fig 3. Pin configuration (TFBGA64). . . . . . . . . . . . . . . . .6

Fig 4. Pin configuration (HVQFN64) . . . . . . . . . . . . . . . .8

Fig 5. Internal assignment of VP[23:0]. . . . . . . . . . . . . .11

Fig 6. Pixel encoding RGB 4 : 4 : 4 external

single-edge clock mode . . . . . . . . . . . . . . . . . . . 40

Fig 20. Set-up and hold time definition diagram for

double-edge clock mode. . . . . . . . . . . . . . . . . . . 41

Fig 21. Connecting TDA19988 transmitter using

external clock source . . . . . . . . . . . . . . . . . . . . . 42

Fig 22. Connecting TDA19988 transmitter using

internal FRO for CEC . . . . . . . . . . . . . . . . . . . . . 42

Fig 23. Package outline SOT962-3 (TFBGA64) . . . . . . . 43

Fig 24. Package outline SOT804-4 (HVQFN64). . . . . . . 44

Fig 25. Temperature profiles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

synchronization input (rising edge) . . . . . . . . . . .16

Fig 7. Pixel encoding YCbCr 4 : 4 : 4 external

synchronization input (rising edge) . . . . . . . . . . .17

Fig 8. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

external synchronization input (rising edge) . . . .18

Fig 9. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

external synchronization input (double edge) . . .19

Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

embedded synchronization input (rising edge) . .20

Fig 11. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like

embedded synchronization input (double edge) .21

Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar

external input synchronization (rising edge) . . . .22

Fig 13. Pixel encoding YCbCr 4 : 2 : 2 semi-planar

embedded synchronization input (rising edge) . .23

Fig 14. I²S-bus formats . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 15. Audio input swap to S/PDIF. . . . . . . . . . . . . . . . .27

Fig 16. Receiver sensitivity detection . . . . . . . . . . . . . . .29

Fig 17. Modules involved in CEC clock calibration

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 18. I²C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 19. Set-up and hold time definition diagram for

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TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

23. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.10.2

7.11

Receiver sensitivity . . . . . . . . . . . . . . . . . . . . 28

HDCP processing (TDA19988AHN and

TDA19988AET only) . . . . . . . . . . . . . . . . . . . 30

High-bandwidth digital content protection . . . 30

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.11.1

7.11.1.1 Repeater function. . . . . . . . . . . . . . . . . . . . . . 30

7.11.1.2 SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.12

CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CEC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 31

HDMI core . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 32

DDC-bus channel. . . . . . . . . . . . . . . . . . . . . . 32

E-EDID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . 32

HDMI and DVI receiver discrimination. . . . . . 32

I²C-bus interface and register definitions. . . 32

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 32

Memory page management. . . . . . . . . . . . . . 33

ID version. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Clock stretching . . . . . . . . . . . . . . . . . . . . . . . 34

6.1

6.2

6.3

6.4

7.12.1

7.12.2

7.12.3

7.13

7.13.1

7.13.2

7.14

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.3.1

Functional description . . . . . . . . . . . . . . . . . . 10

System clock . . . . . . . . . . . . . . . . . . . . . . . . . 11

Video input formatter . . . . . . . . . . . . . . . . . . . 11

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Internal assignment . . . . . . . . . . . . . . . . . . . . 11

Input format mappings . . . . . . . . . . . . . . . . . . 15

RGB 4 : 4 : 4 external synchronization

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 16

YCbCr 4 : 4 : 4 external synchronization

(rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

YCbCr 4 : 2 : 2 ITU656-like external

synchronization (rising edge) . . . . . . . . . . . . . 18

YCbCr 4 : 2 : 2 ITU656-like external

synchronization (double edge) . . . . . . . . . . . . 19

YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization (rising edge) . . . . . . . . . . . . . 20

YCbCr 4 : 2 : 2 ITU656-like embedded

synchronization (double edge) . . . . . . . . . . . . 21

YCbCr 4 : 2 : 2 semi-planar external

7.14.1

7.14.2

8

8.1

8.2

8.3

8.4

7.2.3.2

7.2.3.3

7.2.3.4

7.2.3.5

7.2.3.6

7.2.3.7

7.2.3.8

9

9.1

9.2

Input format . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Timing parameters for video supported . . . . . 35

Timing parameters for PC standards

supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Primary 3D video formats . . . . . . . . . . . . . . . 36

9.3

10

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37

Thermal characteristics . . . . . . . . . . . . . . . . . 37

Static characteristics . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics. . . . . . . . . . . . . . . . . 39

11

12

synchronization (rising edge) . . . . . . . . . . . . . 22

YCbCr 4 : 2 : 2 semi-planar embedded

13

14

14.1

Application information . . . . . . . . . . . . . . . . . 42

Transmitter connection with external

world . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

synchronization (rising edge) . . . . . . . . . . . . . 23

Synchronization . . . . . . . . . . . . . . . . . . . . . . . 23

Timing extraction generator . . . . . . . . . . . . . . 23

Data enable generator . . . . . . . . . . . . . . . . . . 23

Input and output video format. . . . . . . . . . . . . 23

Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Color space converter. . . . . . . . . . . . . . . . . . . 24

Gamut-related metadata. . . . . . . . . . . . . . . . . 24

Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 25

Audio input format . . . . . . . . . . . . . . . . . . . . . 25

S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I²S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Audio port internal assignment. . . . . . . . . . . . 27

Power management . . . . . . . . . . . . . . . . . . . . 27

Interrupt controller . . . . . . . . . . . . . . . . . . . . . 28

Hot plug/unplug detect . . . . . . . . . . . . . . . . . . 28

7.2.4

7.2.4.1

7.2.4.2

7.3

7.4

7.5

7.6

7.7

7.8

7.8.1

7.8.2

7.8.3

7.9

7.10

7.10.1

15

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 43

16

Soldering of SMD packages. . . . . . . . . . . . . . 45

Introduction to soldering. . . . . . . . . . . . . . . . . 45

Wave and reflow soldering. . . . . . . . . . . . . . . 45

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 45

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 46

16.1

16.2

16.3

16.4

17

18

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

19.1

19.2

19.3

continued >>

TDA19988

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 21 July 2011

53 of 54

TDA19988

NXP Semiconductors

HDMI 1.4a transmitter with HDCP and CEC support

19.4

19.5

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Contact information. . . . . . . . . . . . . . . . . . . . . 51

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

20

21

22

23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 July 2011

Document identifier: TDA19988


型号：	TDA19988BHN/C1
厂家：	NXP
描述：	Consumer Circuit, PQCC64
文件：	总54页 (文件大小：972K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA19988BHN/C1 [NXP]

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