TDA4662TD-T [NXP]
IC ACTIVE DELAY LINE, PDSO16, 3.90 MM WIDTH, PLASTIC, SOT109-1, SOP-16, Delay Line;
| 型号： | TDA4662TD-T |
| 厂家： | 
NXP |
| 描述： | IC ACTIVE DELAY LINE, PDSO16, 3.90 MM WIDTH, PLASTIC, SOT109-1, SOP-16, Delay Line 延迟线 |
| 文件： | 总12页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA4662
Baseband delay line
1996 Nov 14
Product specification
Supersedes data of 1995 Oct 30
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
FEATURES
GENERAL DESCRIPTION
• Two comb filters, using the switched-capacitor
technique, for one line delay time (64 µs)
The TDA4662 is an integrated baseband delay line circuit
with one line delay. It is suitable for PAL and NTSC
decoders with colour-difference signal outputs ±(R−Y) and
±(B−Y).
• For PAL and NTSC
• Adjustment-free application
• Handles negative or positive colour-difference input
signals
• Clamping of AC-coupled input signals [±(R−Y) and
±(B−Y)]
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 µs line)
• Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference
signals to suppress cross-colour.
QUICK REFERENCE DATA
SYMBOL
VP1
PARAMETER
analog supply voltage (pin 9)
MIN.
4.5
TYP.
MAX.
UNIT
5
5
6
6
V
V
VP2
digital supply voltage (pin 1)
total supply current
4.5
IP(tot)
Vi(p-p)
−
5.5
7.0
−
mA
mV
mV
±(R−Y) input signal PAL/NTSC (peak-to-peak value; pin 16) −
525
665
±(B−Y) input signal PAL/NTSC (peak-to-peak value; pin 14)
voltage gain VO/VI of colour-difference output signals
V11/V16 for PAL and NTSC
−
−
Gv
5.3
5.3
5.8
5.8
6.3
6.3
dB
dB
V12/V14 for PAL and NTSC
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA4662
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
TDA4662T
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Nov 14
2
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
BLOCK DIAGRAM
EM7D43
bnok,lfuapgedwith
1996 Nov 14
3
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
PINNING
SYMBOL PIN
DESCRIPTION
VP2
1
2
3
4
5
6
7
8
9
supply voltage for digital part (+5 V)
not connected
n.c.
GND2
i.c.
ground for digital part (0 V)
internally connected
handbook, halfpage
V
1
2
3
4
5
6
7
8
16
V
P2
i(R−Y)
n.c.
GND2
i.c.
15
14
13
12
11
10
9
n.c.
V
SAND
n.c.
sandcastle pulse input
not connected
i(B−Y)
i.c.
internally connected
n.c.
V
TDA4662
i.c.
internally connected
SAND
n.c.
o(B−Y)
VP1
supply voltage for analog part (+5 V)
V
o(R−Y)
GND1
Vo(R−Y)
Vo(B−Y)
n.c.
10 ground for analog part (0 V)
11 ±(R−Y) output signal
12 ±(B−Y) output signal
13 not connected
GND1
i.c.
V
i.c.
P1
MED744
Vi(B−Y)
n.c.
14 ±(B−Y) input signal
15 not connected
Fig.2 Pin configuration.
Vi(R−Y)
16 ±(R−Y) input signal
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP1 supply voltage (pin 9) −0.5 +7
V
VP2
V5
supply voltage (pin 1)
−0.5
−0.5
−0.5
−25
0
+7
V
input voltage on pin 5
VP + 1.0
VP
V
Vn
voltage on pins 11, 12, 14 and 16
storage temperature
V
Tstg
Tamb
VESD
+150
70
°C
°C
V
operating ambient temperature
electrostatic handling for all pins
note 1
−
±500
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
SOT38-4
75
K/W
K/W
SOT109-1
220
1996 Nov 14
4
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
CHARACTERISTICS
VP = 5 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz;
Tamb = 25 °C; measurements taken in Fig.3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
4.5
TYP.
MAX.
UNIT
VP1
VP2
IP1
analog supply voltage (pin 9)
digital supply voltage (pin 1)
analog supply current (pin 9)
digital supply current (pin 1)
5
5
6
6
V
4.5
−
V
4.8
0.7
6.0
1.0
mA
mA
IP2
−
Colour-difference input signals
Vi(p-p) input signal (peak-to-peak value)
±(R−Y) PAL and NTSC (pin 16)
±(B−Y) PAL and NTSC (pin 14)
−
−
525
665
−
−
mV
mV
Vi(max; p-p) maximum symmetrical input signal
(peak-to-peak value)
±(R−Y) for PAL and NTSC
±(B−Y) for PAL and NTSC
before clipping
660
840
−
−
−
mV
mV
kΩ
pF
V
before clipping
−
−
R14,16
C14,16
V14,16
input resistance during clamping
input capacitance
−
40
10
1.7
−
−
input clamping voltage
proportional to VP
1.3
1.5
Colour-difference output signals
Vo(p-p)
output signal (peak-to-peak value)
±(R−Y) on pin 11
±(B−Y) on pin 12
−
−
1.05
1.33
0
−
V
−
V
V11/V12
ratio of output amplitudes at equal input
signals
Vi14,16 = 665 mV (p-p) −0.4
+0.4
dB
V11,12
R11,12
Gv
DC output voltage
output resistance
proportional to VP
2.5
−
2.9
330
5.8
−
3.3
400
6.3
1.2
V
Ω
gain for PAL and NTSC
ratio Vo/Vi
5.3
−
dB
mV
VN(rms)
noise voltage
Vi14,16 = 0 V; note 1
(RMS value; pins 11 and 12)
V11,12(p-p) unwanted signals (line-locked)
(peak-to-peak value)
Vi14,16 = 0 V; active
video; RS = 300 Ω
meander
spikes
−
−
−
−
5
mV
mV
dB
−
10
−
S/N(W)
td
weighted signal-to-noise ratio
(pins 11 and 12)
Vo = 1 V (p-p); note 1
54
time difference between undelayed and
delayed output signals (pins 11 and 12)
63.94
40
64
60
64.06
80
µs
delay of undelayed signals
ns
1996 Nov 14
5
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Sandcastle pulse input (pin 5)
fBK
V5
burst-key frequency/sandcastle frequency
14.2
15.625 17.0
kHz
top pulse voltage
internal slicing level
input current
note 2
4.0
−
−
−
−
VP + 1.0 V
V5 − 0.5 V
Vslice
I5
V5 − 1.0
−
−
10
10
µA
C5
input capacitance
pF
Notes
1. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 Ω.
2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.
APPLICATION INFORMATION
TDA4662
±(R−Y) comb filtering
V
V
V
i(R−Y)
o(R−Y)
o(B−Y)
16
14
11
12
colour
difference
input
colour
difference
output
LINE DELAY
1 nF
1 nF
V
signals
signals
LINE DELAY
i(B−Y)
4
8
7
±(B−Y) comb filtering
i.c.
VCO
n.c.
n.c.
n.c.
n.c.
2
6
sandcastle
input
5
LINE-LOCKED PLL /
PULSE PROCESSING
13
15
(+5 V)
+5.1 V
+5.1 V
1
9
3
10
(1)
(1)
100
nF
100
nF
10 Ω
10 Ω
560 Ω
+12 V
5.1 V
22 µF
MED745
(1) Positioned close to pins.
Fig.3 Application circuit.
6
1996 Nov 14
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.030
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT38-4
1996 Nov 14
7
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.0098 0.057
0.0039 0.049
0.019 0.0098 0.39
0.014 0.0075 0.38
0.16
0.15
0.24
0.23
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
91-08-13
95-01-23
SOT109-1
076E07S
MS-012AC
1996 Nov 14
8
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
DIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1996 Nov 14
9
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Nov 14
10
Philips Semiconductors
Product specification
Baseband delay line
TDA4662
NOTES
1996 Nov 14
11
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© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/03/pp12
Date of release: 1996 Nov 14
Document order number: 9397 750 01156
相关型号：
TDA4663
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-
NXP
TDA4663T
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-
NXP
TDA4663T-T
IC SPECIALTY CONSUMER CIRCUIT, PDSO16, PLASTIC, SOT-109-1, SO-16, Consumer IC:OtherWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665
Baseband delay lineWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NXP
TDA4665/V5,112
TDA4665Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665N
IC SPECIALTY CONSUMER CIRCUIT, PDIP16, Consumer IC:OtherWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665T
Baseband delay lineWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665T-T
IC SPECIALTY CONSUMER CIRCUIT, PDSO16, Consumer IC:OtherWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665T/V5,118
TDA4665TWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4665TD-T
Consumer Circuit, Bipolar, PDSO16,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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PHILIPS
TDA4670
Picture Signal Improvement PSI circuitWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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NXP
TDA4670P
Consumer Circuit, PDIP18Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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YAGEO
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