TDA4663T [NXP]
Baseband delay line; 基带延迟线
| 型号： | TDA4663T |
| 厂家： | 
NXP |
| 描述： | Baseband delay line |
| 文件： | 总12页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA4663T
Baseband delay line
1996 Nov 22
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
FEATURES
GENERAL DESCRIPTION
• Two delay lines, using the switched-capacitor
technique, for a delay time of one horizontal line (1H)
minus 55 ns (64 µs − 55 ns)
The TDA4663T is an integrated baseband delay line circuit
with a delay time of one horizontal line (1H) minus 55 ns
(64 µs − 55 ns).
• Adjustment-free application
• Handles negative or positive colour-difference input
signals
• Clamping of AC-coupled input signals [mostly
colour-difference signals ±(R−Y) and ±(B−Y)]
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 µs line)
• Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
• Output buffer amplifiers.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
analog supply voltage (pin 9)
MIN.
4.75
TYP.
MAX.
5.25
UNIT
VP1
5
5
V
V
VP2
digital supply voltage (pin 1)
total supply current
4.75
5.25
7.0
IP(tot)
Vi(p-p)
−
5.9
mA
input signal PAL/NTSC (peak-to-peak value)
±(R−Y); pin 16
−
−
1.3
1.3
−
−
V
V
±(B−Y); pin 14
Gv
Vo
gain
of colour-difference output signals for PAL and NTSC
------
Vi
−1
−1
0
0
+1
+1
dB
dB
V 11
--------
V16
V 12
--------
V14
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA4663T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Nov 22
2
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
BLOCK DIAGRAM
EM8D0
bnok,lfuapgedwith
1996 Nov 22
3
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
PINNING
SYMBOL PIN
DESCRIPTION
VP2
1
2
supply voltage for digital part (+5 V)
not connected
n.c.
handbook, halfpage
GND2
i.c.
3
ground for digital part (0 V)
internally connected
sandcastle pulse input
not connected
V
1
2
3
4
5
6
7
8
16
V
P2
i(R−Y)
4
n.c.
GND2
i.c.
15
14
13
12
11
10
9
n.c.
V
SAND
n.c.
5
i(B−Y)
6
n.c.
V
VCL
7
clamping pulse input
internally connected
supply voltage for analog part (+5 V)
ground for analog part (0 V)
±(R−Y) output signal
±(B−Y) output signal
not connected
TDA4663T
SAND
n.c.
o(B−Y)
i.c.
8
V
VP1
9
o(R−Y)
GND1
Vo(R−Y)
Vo(B−Y)
n.c.
10
11
12
13
14
15
16
GND1
V
CL
V
i.c.
P1
MED801
Vi(B−Y)
n.c.
±(B−Y) input signal
not connected
Fig.2 Pin configuration.
Vi(R−Y)
±(R−Y) input signal
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together.
SYMBOL
PARAMETER
supply voltage (pin 9)
CONDITIONS
MIN.
−0.5
MAX.
UNIT
VP1
VP2
V5
+7
+7
V
V
V
V
supply voltage (pin 1)
−0.5
−0.5
−0.5
−
voltage on pin 5
VP + 1.0
VP
Vn
voltage on pins 7, 11, 12, 14 and 16
current on pins 7, 11 and 12
storage temperature
In
20
mA
°C
Tstg
Tamb
Ptot
Ves
−25
−20
−
+150
+70
operating ambient temperature
total power dissipation
°C
100
mW
V
electrostatic handling for all pins
note 1
−
±500
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
K/W
Rth j-a
thermal resistance from junction to ambient in free air
220
1996 Nov 22
4
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
CHARACTERISTICS
VP = 5.0 V; input signals as specified in characteristics with 75% colour bars;
super-sandcastle frequency of 15.625 kHz; Tamb = 25 °C; measurements taken in Fig.3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
4.75
TYP.
MAX.
5.25
UNIT
VP1
VP2
IP1
analog supply voltage (pin 9)
digital supply voltage (pin 1)
supply current
5
V
4.75
−
5
5.25
5.9
V
5.1
0.8
mA
mA
IP2
supply current
−
1.1
Colour-difference input signals
Vi(p-p) input signal (peak-to-peak value)
pin 16
pin 14
−
−
1.3
1.3
−
−
V
V
Vi(max)(p-p) maximum symmetrical input signal
(peak-to-peak value)
pin 16
pin 14
before clipping
1.6
−
−
−
V
before clipping
1.6
−
V
I14, 16
input leakage current
0.06
0.085
0.1
µA
(during picture content)
R14, 16
C14, 16
V14, 16
input resistance during clamping
input capacitance
−
−
40
10
1.7
kΩ
pF
V
−
−
input clamping voltage
proportional to VP
1.3
1.5
Colour-difference output signals
Vo(p-p)
output signal (peak-to-peak value)
pin 11
pin 12
−
−
1.3
1.3
0
−
V
−
V
V11/V12
ratio of output amplitudes at equal Vi14, 16 = 665 mV (p-p) −0.4
+0.4
dB
input signals
V11, 12
R11, 12
Gv
DC output voltage
output resistance
proportional to VP
2.5
−
2.9
300
0
3.3
400
+1
V
Ω
−1
dB
Vo
voltage gain
------
Vi
Vn(rms)
S/N(W)
tj
noise voltage
(RMS value; pins 11 and 12)
Vi14, 16 = 0 V; note 1
Vo = 1 V (p-p); note 1
−
−
−
−
1.2
−
mV
dB
ns
weighted signal-to-noise ratio
(pins 11 and 12)
54
−
jitter of output signal to external
sandcastle reference V5
20
−
αct(11, 12)
αct(12, 11)
αct(14, 12)
crosstalk between channels
V14 = 0 V;RS = 300 Ω; 30
V11 = 1.35 V (p-p)
−
dB
dB
dB
crosstalk between channels
V16 = 0 V;RS = 300 Ω; 30
V12 = 1.35 V (p-p)
−
−
crosstalk direct from input to output V16 = 0 V;RS = 300 Ω; 30
signal V14 = 1.35 V (p-p)
−
−
1996 Nov 22
5
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
αct(16, 11)
crosstalk direct from input to output V14 = 0 V;RS = 300 Ω; 30
−
−
−
−
dB
signal
V16 = 1.35 V (p-p)
SVRR
supply voltage ripple rejection
∆V11, 12/VR
VR = 100 mV (p-p);
fR = 10 Hz to 1 kHz;
V11, 12 = 1.35 V (p-p)
34
dB
V11, 12(p-p) clamping offset during H-clamp
(peak-to-peak value)
V14 = V16 = 0 V;
RS = 300 Ω
−
−
5
mV
V11, 12(p-p) unwanted signals (line-locked)
(peak-to-peak value)
V14 = V16 = 0 V;
active video;
RS = 300 Ω
residual clock (3 MHz)
meander
−
−
−
−
−
−
6.25
1.5
mV
mV
mV
needles
2.5
td
line delay time
for PAL signals
64 − 0.125 64 − 0.055 64 + 0.015 µs
for NTSC signals
63.555 −
0.125
63.555 −
0.055
63.555 +
0.015
µs
Sandcastle pulse input (pin 5)
fBK
burst-key frequency/sandcastle
14.2
15.625
17.0
kHz
frequency
V5
tBK
Vslice
Ii
top pulse voltage
top pulse duration
internal slicing level
input current
note 2
4.0
−
VP + 1.0
V
−
2.5
−
−
µs
V
V5 − 1.0
V5 − 0.5
−
−
−
−
10
10
1
µA
pF
ms
Ci
input capacitance
lock-in time for PLL
−
tli
−
Clamping pulse input (pin 7)
Vclamp
clamping pulse ON
clamping pulse OFF
input current
3.5
−0.5
−
VP − 0.1
VP
+1.5
10
10
3
V
+0.1
V
Ii
−
−
2
−
−
µA
pF
µs
ns
ns
Ci
input capacitance
clamping pulse duration
rise time
−
tclamp
0.1
10
10
tr
tf
−
fall time
−
Notes
1. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 Ω.
2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.
1996 Nov 22
6
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
APPLICATION INFORMATION
colour-
difference
signals
TDA4663T
V
i(R−Y)
16
14
11
12
V
V
LINE DELAY
LINE DELAY
o(R−Y)
o(B−Y)
1 nF
V
i(B−Y)
1 nF
4
8
clamping pulse
(CMOS)
7
VCO
n.c.
n.c.
n.c.
n.c.
2
6
5
SSC
(5 V)
LINE-LOCKED PLL /
PULSE PROCESSING
13
15
+5.1 V
+5.1 V
1
3
10
(1)
9
(1)
100
nF
100
nF
10 Ω
10 Ω
560 Ω
+12 V
5.1 V
22 µF
MED802
(1) Positioned close to pins.
Fig.3 Application circuit.
1996 Nov 22
7
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
PACKAGE OUTLINE
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.0098 0.057
0.0039 0.049
0.019 0.0098 0.39
0.014 0.0075 0.38
0.16
0.15
0.24
0.23
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
91-08-13
95-01-23
SOT109-1
076E07S
MS-012AC
1996 Nov 22
8
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1996 Nov 22
9
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Nov 22
10
Philips Semiconductors
Product specification
Baseband delay line
TDA4663T
NOTES
1996 Nov 22
11
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© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
537021/1200/02/pp12
Date of release: 1996 Nov 22
Document order number: 9397 750 01375
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