TDA6651 [NXP]
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog); 5 V混频器/振荡器和低噪声的PLL合成器，用于混合动力地面调谐器（数字和模拟）
| 型号： | TDA6651 |
| 厂家： | 
NXP |
| 描述： | 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| 文件： | 总55页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA6650TT; TDA6651TT
5 V mixer/oscillator and low noise
PLL synthesizer for hybrid
terrestrial tuner (digital and analog)
Product specification
2004 Mar 22
Supersedes data of 2003 Sep 11
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
CONTENTS
10
11
12
13
14
HANDLING
THERMAL CHARACTERISTICS
CHARACTERISTICS
1
2
3
4
5
6
7
FEATURES
APPLICATIONS
INTERNAL PIN CONFIGURATION
APPLICATION AND TEST INFORMATION
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
14.1
14.2
14.3
Tuning amplifier
Crystal oscillator
Examples of I2C-bus program sequences
PINNING
FUNCTIONAL DESCRIPTION
15
PACKAGE OUTLINE
SOLDERING
7.1
7.2
7.3
Mixer, Oscillator and PLL (MOPLL) functions
I2C-bus voltage
Phase noise, I2C-bus traffic and crosstalk
16
16.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
8
I2C-BUS PROTOCOL
16.2
16.3
16.4
16.5
8.1
Write mode; R/W = 0
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
I2C-bus address selection
XTOUT output buffer and mode setting
Step frequency setting
Suitability of surface mount IC packages for
wave and reflow soldering methods
AGC detector setting
17
18
19
20
DATA SHEET STATUS
DEFINITIONS
Charge pump current setting
Automatic Loop Bandwidth Control (ALBC)
Read mode; R/W = 1
DISCLAIMERS
PURCHASE OF PHILIPS I2C COMPONENTS
8.3
Status at Power-on reset
9
LIMITING VALUES
2004 Mar 22
2
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
1
FEATURES
• Single-chip 5 V mixer/oscillator and low phase noise
PLL synthesizer for TV and VCR tuners, dedicated to
hybrid (digital and analog) as well as pure digital
applications (DVB-T)
• Five possible step frequencies to cope with different
digital terrestrial TV and analog TV standards
2
APPLICATIONS
• Eight charge pump currents between 40 and 600 µA to
reach the optimum phase noise performance over the
bands
• Digital and analog terrestrial tuners (OFDM, PAL, etc.)
• Cable tuners (QAM)
• Automatic Loop Bandwidth Control (ALBC) sets the
• Digital TV sets
optimum phase noise performance for DVB-T channels
• I2C-bus protocol compatible with 2.5, 3.3 and 5 V
• Digital set-top boxes.
microcontrollers:
– Address + 5 data bytes transmission (I2C-bus write
mode)
– Address + 1 status byte (I2C-bus read mode)
– Four independent I2C-bus addresses
• Five PMOS open-drain ports with 15 mA source
capability for band switching and general purpose; one
of these ports is combined with a 5-step ADC
• Wide band AGC detector for internal tuner AGC:
– Six programmable take-over points
– Two programmable time constants
– AGC flag
• In-lock flag
• Crystal frequency output buffer
• 33 V tuning voltage output
• Fractional-N programmable divider
• Balanced mixers with a common emitter input for the low
band and for the mid band (each single input)
• Balanced mixer with a common base input for the high
band (balanced input)
• 2-pin asymmetrical oscillator for the low band
• 2-pin symmetrical oscillator for the mid band
• 4-pin symmetrical oscillator for the high band
• Switched concept IF amplifier with both asymmetrical
and symmetrical outputs to drive low impedance or
SAW filters i.e. 500 Ω//40 pF.
2004 Mar 22
3
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
3
GENERAL DESCRIPTION
The AGC detector provides a control that can be used in a
tuner to set the gain of the RF stage. Six AGC take-over
points are available by software. Two programmable AGC
time constants are available for search tuning and normal
tuner operation.
The TDA6650TT; TDA6651TT is a programmable 3-band
mixer/oscillator and low phase noise PLL synthesizer
intended for pure 3-band tuner concepts applied to hybrid
(digital and analog) terrestrial and cable TV reception.
The local oscillator signal is fed to the fractional-N divider.
The divided frequency is compared to the comparison
frequency into the fast phase detector which drives the
charge pump. The loop amplifier is also on-chip, including
the high-voltage transistor to drive directly the 33 V tuning
voltage without the need to add an external transistor.
The device includes three double balanced mixers for low,
mid and high bands, three oscillators for the corresponding
bands, a switchable IF amplifier, a wide band AGC
detector and a low noise PLL synthesizer. The frequencies
of the three bands are shown in Table 1. Two pins are
available between the mixer output and the IF amplifier
input to enable IF filtering for improved signal handling and
to improve the adjacent channel rejection.
The comparison frequency is obtained from an on-chip
crystal oscillator. The crystal frequency can be output to
the XTOUT pin to drive the clock input of a digital
demodulation IC.
Table 1 Recommended band limits in MHz for PAL and
DVB-T tuners; note 1
Control data is entered via the I2C-bus; six serial bytes are
required to address the device, select the local
oscillator (LO) frequency, select the step frequency,
program the output ports and set the charge pump current
or select the ALBC mode, enable or disable the crystal
output buffer, select the AGC take-over point and time
constant and/or select a specific test mode. A status byte
concerning the AGC level detector and the ADC voltage
can be read out on the SDA line during a read operation.
During a read operation, the loop ‘in-lock’ flag, the
Power-on reset flag and the automatic loop bandwidth
control flag are read.
RF INPUT
MIN. MAX.
44.25
OSCILLATOR
BAND
Low
MIN.
83.15
MAX.
196.15
482.15
902.15
157.25
443.25
863.25
Mid
157.25
443.25
196.15
482.15
High
Note
1. RF input frequency is the frequency of the
corresponding picture carrier for analog standard.
The device has 4 programmable addresses. Each address
can be selected by applying a specific voltage to pin AS,
enabling the use of multiple devices in the same system.
The IF amplifier is switchable in order to drive both
symmetrical and asymmetrical outputs. When it is used as
an asymmetrical amplifier, the IFOUTB pin needs to be
The I2C-bus is fast mode compatible, except for the timing
as described in the functional description and is
compatible with 5, 3.3 and 2.5 V microcontrollers
depending on the voltage applied to pin BVS.
connected to the supply voltage VCCA
.
Five open-drain PMOS ports are included on the IC. Two
of them, BS1 and BS2, are also dedicated to the selection
of the low, mid and high bands. PMOS port BS5 pin is
shared with the ADC.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA6650TT
TDA6651TT
TSSOP38 plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
SOT510-1
2004 Mar 22
4
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
5
BLOCK DIAGRAM
IFFIL1
IFFIL2
IFOUTA
IFOUTB
V
n.c.
21 (18)
CCA
26 (13)
6 (33)
7 (32) 28 (11)
27 (12)
(30) 9
AGC
IF
AGC
AMP
DETECTOR
TDA6650TT
AGC
flag
(TDA6651TT)
AL0, AL1, AL2 ATC
(10) 29
IFGND
(1) 38
(2) 37
LOSCIN
4 (35)
LOW
INPUT
LOW
MIXER
LOW
OSCILLATOR
LBIN
BS1
BS1
LOSCOUT
(5) 34
(4) 35
MOSCIN1
MOSCIN2
3 (36)
MID
INPUT
MID
MIXER
MID
OSCILLATOR
MBIN
BS2
BS2
(9) 30
(8) 31
(7) 32
(6) 33
1 (38)
2 (37)
HOSCIN1
HBIN1
HBIN2
HIGH
INPUT
HIGH
MIXER
HOSCOUT1
HOSCOUT2
HOSCIN2
HIGH
OSCILLATOR
BS1 . BS2
BS1 . BS2
5 (34)
(3) 36
RFGND
OSCGND
XTOUT
(21) 18
OUTPUT
BUFFER
R0, R1,
R2
24 (15)
[ ]
N 14:0
V
CCD
T0, T1, T2
PHASE
COMPARATOR
FRACTIONAL
DIVIDER
FRACTIONAL
CALCULATOR
(17) 22
(16) 23
LOOP
AMP
VT
CP
19 (20)
20 (19)
XTAL1
XTAL2
CHARGE
PUMP
CRYSTAL
OSCILLATOR
REFERENCE
DIVIDER
15 (24)
16 (23)
17 (22)
13 (26)
T0, T1, CP0, CP1,
SCL
SDA
AS
LOCK
DETECTOR
T2
CP2
2
I C-BUS
TRANSCEIVER
FRACTIONAL
SPURIOUS
COMPENSATION
BAND SWITCH
BS5-
BVS
AGC
OUTPUT PORTS
BS1
(14) 25
POR
ADC
14
8
10
11
12
PLLGND
(25) (31) (29) (28) (27)
FCE723
ADC/
BS5
BS3
BS1
BS4
BS2
The pin numbers in parenthesis represent the TDA6651TT.
Fig.1 Block diagram.
5
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
6
PINNING
SYMBOL
PIN
DESCRIPTION
TDA6650TT TDA6651TT
HBIN1
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
high band RF input 1
high band RF input 2
mid band RF input
low band RF input
RF ground
HBIN2
MBIN
LBIN
2
3
4
RFGND
IFFIL1
IFFIL2
BS4
5
6
IF filter output 1
IF filter output 2
7
8
PMOS open-drain output port 4 for general purpose
AGC output
AGC
9
BS3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PMOS open-drain output port 3 for general purpose
PMOS open-drain output port 2 to select the mid band
PMOS open-drain output port 1 to select the low band
bus voltage selection input
BS2
BS1
BVS
ADC/BS5
SCL
ADC input or PMOS open-drain output port 5 for general purpose
I2C-bus serial clock input
I2C-bus serial data input and output
I2C-bus address selection input
crystal frequency buffer output
crystal oscillator input 1
SDA
AS
XTOUT
XTAL1
XTAL2
n.c
crystal oscillator input 2
not connected
VT
tuning voltage output
CP
charge pump output
VCCD
PLLGND
VCCA
IFOUTB
supply voltage for the PLL part
PLL ground
supply voltage for the analog part
IF output B for symmetrical amplifier and asymmetrical IF amplifier
switch input
IFOUTA
28
29
30
31
32
33
34
35
36
37
38
11
10
9
IF output A
IFGND
IF ground
HOSCIN1
HOSCOUT1
HOSCOUT2
HOSCIN2
MOSCIN1
MOSCIN2
OSCGND
LOSCOUT
LOSCIN
high band oscillator input 1
high band oscillator output 1
high band oscillator output 2
high band oscillator input 2
mid band oscillator input 1
mid band oscillator input 2
oscillators ground
8
7
6
5
4
3
2
low band oscillator output
low band oscillator input
1
2004 Mar 22
6
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
handbook, halfpage
handbook, halfpage
HBIN1
HBIN2
MBIN
LBIN
1
2
3
4
5
6
7
8
9
38 LOSCIN
1
2
38
37
36
35
34
HBIN1
HBIN2
MBIN
LOSCIN
37 LOSCOUT
36 OSCGND
35 MOSCIN2
34 MOSCIN1
33 HOSCIN2
32 HOSCOUT2
31 HOSCOUT1
30 HOSCIN1
29 IFGND
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
3
4
LBIN
RFGND
IFFIL1
IFFIL2
BS4
5
RFGND
6
33 IFFIL1
32 IFFIL2
7
8
31
30
29
28
27
26
25
24
23
22
21
20
BS4
TDA6650TT
TDA6651TT
AGC
9
AGC
BS3
BS3 10
BS2 11
BS1 12
BVS 13
10
11
12
13
14
15
16
17
18
19
28 IFOUTA
IFOUTA
BS2
27 IFOUTB
IFOUTB
BS1
26
V
V
BVS
CCA
CCA
ADC/BS5 14
SCL 15
25 PLLGND
PLLGND
ADC/BS5
SCL
24
V
V
CCD
CCD
SDA 16
23 CP
CP
VT
SDA
AS 17
22 VT
AS
XTOUT 18
21 n.c.
20 XTAL2
n.c.
XTOUT
XTAL1
19
XTAL1
XTAL2
FCE724
FCE874
Fig.2 Pin configuration TDA6650TT.
Fig.3 Pin configuration TDA6651TT.
7
FUNCTIONAL DESCRIPTION
a fractional calculator on the chip that generates the data
for the fractional divider as well as the reference divider
ratio, depending on the step frequency selected. The
crystal oscillator requires a 4 MHz crystal in series with an
18 pF capacitor between pins XTAL1 and XTAL2.
7.1
Mixer, Oscillator and PLL (MOPLL) functions
Bit BS1 enables the BS1 port, the low band mixer and the
low band oscillator. Bit BS2 enables the BS2 port, the mid
band mixer and the mid band oscillator. When both BS1
and BS2 bits are logic 0, the high band mixer and the high
band oscillator are enabled.
The output of the phase comparator drives the charge
pump and the loop amplifier section. This amplifier has an
on-chip high voltage drive transistor. Pin CP is the output
of the charge pump, and pin VT is the pin to drive the
tuning voltage to the varicap diodes of the oscillators and
the tracking filters. The loop filter has to be connected
between pins CP and VT. The spurious signals introduced
by the fractional divider are automatically compensated by
the spurious compensation block.
The oscillator signal is applied to the fractional-N
programmable divider. The divided signal fdiv is fed to the
phase comparator where it is compared in both phase and
frequency with the comparison frequency fcomp. This
frequency is derived from the signal present on the crystal
oscillator fxtal and divided in the reference divider. There is
2004 Mar 22
7
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Phase noise, I2C-bus traffic and crosstalk
It is possible to drive the clock input of a digital
demodulation IC from pin XTOUT with the 4 MHz signal
from the crystal oscillator. This output is also used to
output 1/2fdiv and fcomp signals in a specific test mode (see
Table 6). It is possible to switch off this output, which is
recommended when it is not used.
7.3
While the TDA6650TT; TDA6651TT is dedicated for hybrid
terrestrial applications, the low noise PLL will clean up the
noise spectrum of the VCOs close to the carrier to reach
noise levels at 1 kHz offset from the carrier compatible with
e.g. DVB-T reception.
For test and alignment purposes, it is also possible to
release the tuning voltage output by selecting the sinking
mode (see Table 6), and by applying an external voltage
on pin VT.
Linked to this noise improvement, some disturbances may
become visible while they were not visible because they
were hidden into the noise in analog dedicated
applications and circuits.
In addition to the BS1 and BS2 output ports that are used
for the band selection, there are three general purpose
ports BS3, BS4 and BS5. All five ports are PMOS
open-drain type, each with 15 mA drive capability. The
connection for port BS5 and the ADC input is combined on
one pin. It is not possible to use the ADC if port BS5 is
used.
This is especially true for disturbances coming from the
I2C-bus traffic, whatever this traffic is intended for the
MOPLL or for another slave on the bus.
To avoid this I2C-bus crosstalk and be able to have a clean
noise spectrum, it is necessary to use a bus gate that
enables the signal on the bus to drive the MOPLL only
when the communication is intended for the tuner part
(such a kind of I2C-bus gate is included into the Philips
terrestrial channel decoders), and to avoid unnecessary
repeated sending of the same information.
The AGC detector compares the level at the IF amplifier
output to a reference level which is selected from
6 different levels via the I2C-bus. The time constant of the
AGC can be selected via the I2C-bus to cope with normal
operation as well as with search operation.
8
I2C-BUS PROTOCOL
When the output level on pin AGC is higher than the
threshold VRMH, then bit AGC = 1. When the output level
on pin AGC is lower than the threshold VRML, then
bit AGC = 0. Between these two thresholds, bit AGC is not
defined. The status of the AGC bit can be read via the
I2C-bus according to the read mode as described in
Table 12.
The TDA6650TT; TDA6651TT is controlled via the
two-wire I2C-bus. For programming, there is one device
address (7 bits) and the R/W bit for selecting read or write
mode. To be able to have more than one MOPLL in an
I2C-bus system, one of four possible addresses is selected
depending on the voltage applied to address selection
pin AS (see Table 5).
7.2
I2C-bus voltage
The TDA6650TT; TDA6651TT fulfils the fast mode
I2C-bus, according to the Philips I2C-bus specification (see
Chapter 20), except for the timing as described in Fig.4.
The I2C-bus interface is designed in such a way that the
pins SCL and SDA can be connected to 5, 3.3 or to 2.5 V
pulled-up I2C-bus lines, depending on the voltage applied
to pin BVS (see Table 2).
The I2C-bus lines SCL and SDA can be connected to an
I2C-bus system tied to 2.5, 3.3 or 5 V. The choice of the
bus input threshold voltages is made with pin BVS that can
be left open-circuit, connected to the supply voltage or to
ground (see Table 2).
Table 2 I2C-bus voltage selection
LOGIC LEVEL
PIN BVS
BUS
CONNECTION VOLTAGE
LOW
HIGH
To ground
Open-circuit
To VCC
2.5 V
3.3 V
5 V
0 to 0.75 V 1.75 to 5.5 V
0 to 1.0 V 2.3 to 5.5 V
0 to 1.5 V 3.0 to 5.5 V
2004 Mar 22
8
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
8.1
Write mode; R/W = 0
sent by the controller, additional data bytes can be entered
without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission
(STOP condition). Each control byte is loaded after the
8th clock pulse of the corresponding control byte. Main
divider data are valid only if no new I2C-bus transmission
is started (START condition) during the computation
period of 50 µs.
After the address transmission (first byte), data bytes can
be sent to the device (see Table 3). Five data bytes are
needed to fully program the TDA6650TT; TDA6651TT.
The I2C-bus transceiver has an auto-increment facility that
permits programming the device within one single
transmission (address + 5 data bytes).
The TDA6650TT; TDA6651TT can also be partly
programmed on the condition that the first data byte
following the address is byte 2 (divider byte 1) or byte 4
(control byte 1). The first bit of the first data byte
transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I2C-bus STOP condition is
Both DB1 and DB2 need to be sent to change the main
divider ratio. If the value of the ratio selection bits R2, R1
and R0 are changed, the bytes DB1 and DB2 have to be
sent in the same transmission.
50 µs
ADDRESS
ADDRESS
BYTE
DIVIDER DIVIDER CONTROL CONTROL CONTROL CONTROL
STOP
START
START
2
BYTE
BYTE 1
BYTE 2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
2
I C transmission dedicated to
the MOPLL
I C transmission
dedicated to
another IC
FCE921
Fig.4 Example of I2C-bus transmission frame.
Table 3 I2C-bus write data format
BIT
NAME
BYTE
ACK
MSB(1)
LSB
Address byte
1
2
3
4
1
1
0
N13
N5
T2
0
N12
N4
T1
0
MA1
N10
N2
MA0
N9
R/W = 0
N8
A
A
A
A
A
A
Divider byte 1 (DB1)
Divider byte 2 (DB2)
0
N7
1
N14
N11
N3
N6
N1
N0
Control byte 1
(CB1); see Table 4
T/A = 1
T/A = 0
CP1
T0
R2
R1
R0
1
0
0
ATC
BS4
AL2
BS3
AL1
BS2
AL0
BS1
Control byte 2 (CB2)
5
CP2
CP0
BS5
Note
1. MSB is transmitted first.
2004 Mar 22
9
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Table 4 Description of write data format bits
BIT
DESCRIPTION
A
acknowledge
MA1 and MA0
R/W
programmable address bits; see Table 5
logic 0 for write mode
N14 to N0
T/A
programmable LO frequency; N = N14 × 214 + N13 × 213 + N12 × 212 + ... + N1 × 21 + N0
test/AGC bit
T/A = 0: the next six bits sent are AGC settings
T/A = 1: the next six bits sent are test and reference divider ratio settings
test bits; see Table 6
T2, T1 and T0
R2, R1, and R0
ATC
reference divider ratio and programmable frequency step; see Table 7
AGC current setting and time constant; capacitor on pin AGC = 150 nF
ATC = 0: AGC current = 220 nA; AGC time constant = 2 s
ATC = 1: AGC current = 9 µA; AGC time constant = 50 ms
AGC take-over point bits; see Table 8
AL2, AL1 and AL0
CP2, CP1 and CP0 charge pump current; see Table 9
BS5, BS4, BS3,
BS2 and BS1
PMOS ports control bits
BSn = 0: corresponding port is off, high-impedance state (status at Power-on reset)
BSn = 1: corresponding port is on; VO = VCC − VDS(sat)
8.1.1
I2C-BUS ADDRESS SELECTION
The device address contains programmable address bits MA1 and MA0, which offer the possibility of having up to four
MOPLL ICs in one system. Table 5 gives the relationship between the voltage applied to the AS input and the MA1 and
MA0 bits.
Table 5 Address selection
VOLTAGE APPLIED TO PIN AS
MA1
MA0
0 V to 0.1VCC
0
0
1
1
0
1
0
1
0.2VCC to 0.3VCC or open-circuit
0.4VCC to 0.6VCC
0.9VCC to VCC
2004 Mar 22
10
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
8.1.2
XTOUT OUTPUT BUFFER AND MODE SETTING
recommended to disable it, by setting T[2:0] to 000. This
pin is also used to output 1/2fdiv and fcomp in a test mode.
At Power-on, the XTOUT output buffer is set to on,
supplying the fxtal signal. The relation between the signal
on pin XTOUT and the setting of theT[2:0] bits is given in
Table 6.
The crystal frequency can be sent to pin XTOUT and used
in the application, for example to drive the clock input of a
digital demodulator, saving a quartz crystal in the bill of
material. To output fxtal, it is necessary to set T[2:0] to 001.
If the output signal on this pin is not used, it is
Table 6 XTOUT buffer status and test modes
T2
T1
T0
PIN XTOUT
MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
disabled
fxtal (4 MHz)
1/2fdiv
normal mode with XTOUT buffer off
normal mode with XTOUT buffer on
charge pump off
fxtal (4 MHz)
switch ALBC on or off (note 1)
test mode
fcomp
1/2fdiv
test mode
fxtal (4 MHz)
disabled
charge pump sinking current (note 2)
charge pump sourcing current
Notes
1. Automatic Loop Bandwidth Control (ALBC) is disabled at Power-on reset. After Power-on reset this feature is
enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts like a toggle
switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC, two consecutive Control
byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will be switched on or off and one byte
programming the test mode to be selected (see Table 23, example of I2C-bus sequence).
2. This is the default mode at Power-on reset. This mode disables the tuning voltage.
8.1.3
STEP FREQUENCY SETTING
The step frequency is set by three bits, giving five steps to cope with different application requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The phase detector works at either
4, 2 or 1 MHz.
Table 7 shows the step frequencies and corresponding reference divider ratios. When the value of bits R2, R1 and R0
are changed, it is necessary to re-send the data bytes DB1 and DB2.
Table 7 Reference divider ratio select bits
REFERENCE
DIVIDER RATIO
FREQUENCY
COMPARISON
R2
R1
R0
FREQUENCY STEP
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
1
1
4
1
−
−
−
2 MHz
4 MHz
4 MHz
1 MHz
4 MHz
−
62.5 kHz
142.86 kHz
166.67 kHz
50 kHz
125 kHz
reserved
reserved
reserved
−
−
2004 Mar 22
11
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
8.1.4
AGC DETECTOR SETTING
The AGC take-over point can be selected out of 6 levels according to Table 8.
Table 8 AGC programming
AL2
AL1
AL0
TYPICAL TAKE-OVER POINT LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
124 dBµV (p-p)
121 dBµV (p-p)
118 dBµV (p-p)
115 dBµV (p-p)
112 dBµV (p-p)
109 dBµV (p-p)
IAGC = 0; note 1
VAGC = 3.5 V; note 2
Notes
1. The AGC current sources are disabled. The AGC output goes into a high-impedance state and an external AGC
source can be connected in parallel and will not be influenced.
2. The AGC detector is disabled and IAGC = 9 µA.
8.1.5
CHARGE PUMP CURRENT SETTING
The charge pump current can be chosen from 8 values depending on the value of bits CP2, CP1 and CP0 bits; see
Table 9. The programming of the CP bits are not taken into account when ALBC mode is in use.
Table 9 Charge pump current
CHARGE PUMP CURRENT
NUMBER
TYPICAL CURRENT
(ABSOLUTE VALUE IN µA)
CP2
CP1
CP0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
38
54
83
122
163
254
400
580
8.1.6
AUTOMATIC LOOP BANDWIDTH CONTROL (ALBC)
tuner, to set the charge pump current to different values
depending on the band and frequency used. This is to
cope with the variations of the different parameters that set
the bandwidth. The selection can be done in the
application and requires for each frequency to program not
only the divider ratios, but also the band and the best
charge pump current.
In a PLL controlled VCO in which the PLL reduces phase
noise close to the carrier, there is an optimum loop
bandwidth corresponding to the minimum integrated
phase jitter. This loop bandwidth depends on different
parameters like the VCO slope, the loop filter components,
the dividing ratio and the gain of the phase detector and
charge pump.
The TDA6650TT; TDA6651TT includes the ALBC feature
that automatically sets the band and the charge pump
current, provided the IC is used in the DVB-T standard
In order to reach the best phase noise performance it is
necessary, especially in a wide band system like a digital
2004 Mar 22
12
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
application shown in Figs 27 and 28. This feature is
activated by setting bits T[2:0] = 011 after Power-on reset.
This feature is disabled when the same bits are set again.
When ALBC is activated, the output ports BS1, BS2
and BS3 are not programmed by the corresponding
BS bits, but are set according to Tables 10 and 11. When
ALBC is active, bit ALBC = 1. Table 11 summarizes the
programming of the band selection and the charge pump
current when ALBC is active.
Table 10 ALBC settings
BIT
CHARGE
PUMP
CURRENT
PORT
BS2
BAND
SELECTED
ALBC
BS3
BS2
BS1
BS3
BS1
0
0
0
0
1
X
X
X
X
X
0
0
1
1
X
0
1
0
1
X
high
low
see
Table 11
follows
bit BS3
off
off
on
off
on
off
mid
forbidden
depends on LO program, shown in Table 11
Table 11 ALBC band selection and charge current setting
CHARGE PUMP CURRENT
NUMBER
LO FREQUENCY
BAND
80 to 92 MHz
92 to 144 MHz
144 to 156 MHz
156 to 176 MHz
176 to 184 MHz
184 to 196 MHz
196 to 224 MHz
224 to 296 MHz
296 to 380 MHz
380 to 404 MHz
404 to 448 MHz
448 to 472 MHz
472 to 484 MHz
484 to 604 MHz
604 to 676 MHz
676 to 752 MHz
752 to 868 MHz
868 to 904 MHz
low
mid
2
3
4
5
6
7
2
3
4
5
6
7
8
4
5
6
7
8
high
2004 Mar 22
13
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
8.2
Read mode; R/W = 1
A second data byte can be read from the device if the
microcontroller generates an acknowledge on the SDA
line (master acknowledge). End of transmission will occur
if no master acknowledge occurs. The device will then
release the data line to allow the microcontroller to
generate a STOP condition.
Data can be read from the device by setting the R/W bit
to 1 (see Table 12). After the device address has been
recognized, the device generates an acknowledge pulse
and the first data byte (status byte) is transferred on the
SDA line (MSB first). Data is valid on the SDA line during
a HIGH level of the SCL clock signal.
Table 12 I2C-bus read data format
BIT
NAME
BYTE
ACK
LSB
MSB(1)
Address byte
Status byte
1
2
1
1
0
0
1
0
MA1
A2
MA0
A1
R/W = 1
A0
A
POR
FL
ALBC
AGC
−
Note
1. MSB is transmitted first.
Table 13 Description of read data format bits
BIT
DESCRIPTION
A
acknowledge bit
POR
Power-on reset flag
POR = 0, normal operation
POR = 1, Power-on reset
in-lock flag
FL
FL = 0, not locked
FL = 1, the PLL is locked
ALBC
AGC
automatic loop bandwidth control flag
ALBC = 0, no automatic loop bandwidth control
ALBC = 1, automatic loop bandwidth control selected
internal AGC flag
AGC = 0 when internal AGC is active (VAGC < VRML
)
AGC = 1 when internal AGC is not active (VAGC > VRMH
)
A2, A1, A0
digital outputs of the 5-level ADC; see Table 14
2004 Mar 22
14
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Table 14 ADC levels
VOLTAGE APPLIED TO PIN ADC(1)
0.6VCC to VCC
A2
1
A1
0
A0
0
0.45VCC to 0.6VCC
0.3VCC to 0.45VCC
0.15VCC to 0.3VCC
0 to 0.15VCC
0
1
1
0
1
0
0
0
1
0
0
0
Note
1. Accuracy is ±0.03VCC. Bit BS5 must be set to logic 0 to disable the BS5 output port. The BS5 output port uses the
same pin as the ADC and can not be used when the ADC is in use.
8.3
Status at Power-on reset
At power on or when the supply voltage drops below approximately 2.85 V (at Tamb = 25 °C), internal registers are set
according to Table 15.
At power on, the charge pump current is set to 580 µA, the test bits T[2:0] are set to 110 which means that the charge
pump is sinking current, the tuning voltage output is disabled and the ALBC function is disabled. The XTOUT buffer is
on, driving the 4 MHz signal from the crystal oscillator and all the ports are off. As a consequence, the high band is
selected by default.
Table 15 Default setting at Power-on reset
BIT(1)
NAME
BYTE
MSB
LSB
X
Address byte
1
2
3
4
1
1
0
0
0
MA1
MA0
Divider byte 1 (DB1)
Divider byte 2 (DB2)
Control byte 1 (CB1)
0
N7 = X
1
N14 = X N13 = X N12 = X N11 = X N10 = X N9 = X
N8 = X
N0 = X
R0 = X
N6 = X
N5 = X
T2 = 1
N4 = X
T1 = 1
N3 = X
T0 = 0
N2 = X
R2 = X
N1 = X
R1 = X
T/A = X;
note 2
1
T/A = X;
note 3
0
0
ATC = 0 AL2 = 0 AL1 = 1 AL0 = 0
Control byte 2 (CB2)
5
CP2 = 1 CP1 = 1 CP0 = 1 BS5 = 0 BS4 = 0 BS3 = 0 BS2 = 0 BS1 = 0
Notes
1. X means that this bit is not set or reset at Power-on reset.
2. The next six bits are written, when bit T/A = 1 in a write sequence.
3. The next six bits are written, when bit T/A = 0 in a write sequence.
2004 Mar 22
15
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); positive currents are entering the IC and
negative currents are going out of the IC; all voltages are referenced to ground (GND); note 1
SYMBOL
VCCA
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.3
MAX.
UNIT
,
+6
V
VCCD
VVT
tuning voltage output
−0.3
−0.3
0
+35
V
V
VSDA
ISDA
VSCL
VAS
Vn
serial data input and output voltage
serial data output current
serial clock input voltage
+6
during acknowledge
4.5 V< VCC < 5.5 V
10
mA
V
−0.3
−0.3
−0.3
+6
address selection input voltage
+6
V
voltage on all other inputs, outputs and
combined inputs and outputs, except
GNDs
VCC + 0.3
V
IBSn
PMOS port output current
corresponding port on;
open-drain
−20
0
mA
IBS(tot)
tsc(max)
Tstg
sum of all PMOS port output currents
maximum short-circuit time
storage temperature
open-drain
−50
−
0
mA
s
each pin to VCC or to GND
10
−40
−20
−
+150
°C
°C
°C
(2)
Tamb
Tj
ambient temperature
Tamb(max)
+150
junction temperature
Notes
1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings cannot be accumulated.
2. The maximum allowed ambient temperature Tamb(max) depends on the assembly conditions of the package and
especially on the design of the PCB. The application mounting must be done in such a way that the maximum junction
temperature Tj is never exceeded. An estimation of the junction temperature can be obtained through measurement
of the temperature of the top centre of the package (Tpackage). The temperature difference junction to case (∆Tj-c) is
estimated at about 13 °C on the demoboard (PCB 827-3).
The junction temperature is: Tj = Tpackage + ∆Tj-c
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it
is desirable to take normal precautions appropriate to handling integrated circuits.
2004 Mar 22
16
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
notes 1, 2 and 3
VALUE
UNIT
thermal resistance from
junction to ambient
TDA6650TT
TDA6651TT
82
74
K/W
K/W
Notes
1. Measured in free air as defined by JEDEC standard JESD51-2
2. These values are given for information only. The thermal resistance depends strongly on the nature and design of
the PCB used in the application.The thermal resistance given corresponds to the value that can be measured on a
multilayer PCB (4 layers) as defined by JEDEC standard.
3. The junction temperature influences strongly the reliability of an IC. The PCB used in the application contributes in a
large part to the overall thermal characteristic. It must therefore be insured that the junction temperature of the IC
never exceeds Tj(max) = 150 °C at the maximum ambient temperature.
12 CHARACTERISTICS
VCCA = VCCD = 5 V, Tamb = 25 °C; values are given for an asymmetrical IF output loaded with a 75 Ω load or with a
symmetrical IF output loaded with 1.25 kΩ; positive currents are entering the IC and negative currents are going out of
the IC; the performances of the circuits are measured in the measurement circuits Figs 27 and 28 for digital application
or in the measurement circuits Figs 29 and 30 for hybrid application; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
ICC
supply voltage
supply current
4.5
80
one PMOS port on: sourcing 15 mA 96
5.0
5.5
V
PMOS ports off
96
115
131
136
mA
mA
mA
112
117
two PMOS ports on: one port
sourcing 15 mA and one other port
sourcing 5 mA
101
General functions
VPOR
Power-on reset supply
Power-on reset active if VCC < VPOR
−
2.85
3.5
V
voltage
∆flock
frequency range the PLL is
able to synthesize
64
−
1024
MHz
Crystal oscillator; note 1
fxtal crystal frequency
Zxtal
−
4.0
−
−
MHz
input impedance (absolute fxtal = 4 MHz; VCC = 4.5 V to 5.5 V; 350
430
Ω
value)
Tamb = −20 °C to + 85 °C
Pxtal
crystal drive level
fxtal = 4 MHz; note 2
−
70
−
−
µW
µA
PMOS ports: pins BS1, BS2, BS3, BS4 and BS5
ILO(off)
output leakage current in
off state
VCC = 5.5 V; VBS = 0 V
−10
−
2004 Mar 22
17
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
VDS(sat)
PARAMETER
CONDITIONS
MIN.
TYP.
0.2
MAX.
UNIT
output saturation voltage
only corresponding buffer is on,
sourcing 15 mA;
−
0.4
V
VDS(sat) = VCC − VBS
ADC input: pin ADC
Vi
ADC input voltage
see Table 14
VADC = VCC
VADC = 0 V
0
−
−
−
5.5
10
−
V
IIH
IIL
HIGH-level input current
LOW-level input current
−
µA
µA
−10
Address selection input: pin AS
IIH
IIL
HIGH-level input current
LOW-level input current
VAS = 5.5 V
VAS = 0 V
−
−
−
10
µA
µA
−10
−
Bus voltage selection input: pin BVS
IIH
IIL
HIGH-level input current
LOW-level input current
VBVS = 5.5 V
VBVS = 0 V
−
−
−
100
µA
µA
−100
−
Buffered output: pin XTOUT
Vo(p-p)
square wave AC output
voltage (peak-to peak
value)
note 3
−
−
400
175
−
−
mV
Zo
output impedance
Ω
I2C-bus
INPUTS: PINS SCL AND SDA
fclk
VIL
clock frequency
frequency on SCL
VBVS = 0 V
−
−
−
−
−
−
−
−
−
−
−
−
400
0.75
1.0
1.5
5.5
5.5
5.5
10
kHz
V
LOW-level input voltage
0
VBVS = 2.5 V or open-circuit
VBVS = 5 V
0
V
0
V
VIH
HIGH-level input voltage
VBVS = 0 V
1.75
2.3
3.0
−
V
VBVS = 2.5 V or open-circuit
VBVS = 5 V
V
V
IIH
HIGH-level input current
LOW-level input current
VCC = 0 V; VBUS = 5.5 V
VCC = 5.5 V; VBUS = 5.5 V
VCC = 0 V; VBUS = 1.5 V
VCC = 5.5 V; VBUS = 0 V
µA
µA
µA
µA
−
10
IIL
−
10
−10
−
OUTPUT: PIN SDA
ILH
leakage current
VSDA = 5.5 V
ISDA = 3 mA
−
−
−
−
10
µA
VO(ack)
output voltage during
acknowledge
0.4
V
Charge pump output: pin CP
Io
output current (absolute
see Table 9
−
−
−
µA
value)
IL(off)
off-state leakage current
charge pump off (T[2:0] = 010)
−15
0
+15
nA
2004 Mar 22
18
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
Tuning voltage output: pin VT
IL(off) leakage current when
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tuning supply voltage = 33 V
−
−
10
µA
switched-off
Vo(cl)
output voltage when the
loop is closed
charge pump off (T[2:0] = 010);
tuning supply voltage = 33 V;
RL = 15 kΩ
0.3
−
32.7
V
Noise performance
Jφ(rms)
phase jitter (RMS value)
integrated between 1 kHz and
1 MHz offset from the carrier
digital application
hybrid application
−
−
0.5
0.6
−
−
deg
deg
Low band mixer, including IF amplifier
fRF
Gv
RF frequency
voltage gain
picture carrier; note 4
43.25
−
157.25 MHz
asymmetrical IF output; RL = 75 Ω;
see Fig.14
f
RF = 44.25 MHz
21
21
24
24
27
27
dB
dB
fRF = 157.25 MHz
symmetrical IF output;
RL = 1.25 kΩ; see Fig.15
fRF = 44.25 MHz
fRF = 157.25 MHz
see Figs 16 and 17
fRF = 50 MHz
25
25
28
28
31
31
dB
dB
NF
Vo
noise figure
−
−
8.0
8.0
10.0
10.0
dB
dB
fRF = 150 MHz
output voltage causing 1% asymmetrical application;
cross modulation in
channel
see Fig.18; note 5
fRF = 44.25 MHz
107
107
110
110
−
−
dBµV
dBµV
fRF = 157.25 MHz
symmetrical application;
see Fig.19; note 5
fRF = 44.25 MHz
fRF = 157.25 MHz
117
117
−
120
120
90
−
−
−
dBµV
dBµV
dBµV
Vi
input voltage causing
750 Hz frequency
asymmetrical IF output
deviation pulling in channel
INTSO2
Vi(lock)
Gi
channel SO2 beat
VRFpix = 80 dBµV; note 6
57
−
60
−
dBc
dBµV
mS
input level without lock-out see Fig.25; note 7
−
120
−
input conductance
fRF = 44.25 MHz; see Fig.5
−
0.13
0.11
1.36
fRF = 157.25 MHz; see Fig.5
−
−
mS
Ci
input capacitance
fRF = 44.25 to 157.25 MHz;
see Fig.5
−
−
pF
2004 Mar 22
19
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Mid band mixer, including IF amplifier
fRF
Gv
RF frequency
voltage gain
picture carrier; note 4
157.25 −
443.25 MHz
asymmetrical IF output;
load = 75 Ω; see Fig.14
fRF = 157.25 MHz
fRF = 443.25 MHz
21
21
24
24
27
27
dB
dB
symmetrical IF output;
load = 1.25 kΩ; see Fig.15
fRF = 157.25 MHz
fRF = 443.25 MHz
see Figs 16 and 17
fRF = 150 MHz
25
25
28
28
31
31
dB
dB
NF
Vo
noise figure
−
−
8.0
9.0
10.0
11.0
dB
dB
fRF = 300 MHz
output voltage causing 1% asymmetrical application;
cross modulation in
channel
see Fig.18; note 5
fRF = 157.25 MHz
fRF = 443.25 MHz
107
107
110
110
−
−
dBµV
dBµV
symmetrical application;
see Fig.19; note 5
f
RF = 157.25 MHz
117
117
−
120
120
80
−
−
−
dBµV
dBµV
dBµV
fRF = 443.25 MHz
Vf(N+5)-1
(N + 5) − 1 MHz pulling
fRF(wanted) = 443.25 MHz;
fosc = 482.15 MHz;
fRF(unwanted) = 482.25 MHz; note 8
Vi
input voltage causing
750 Hz frequency
asymmetrical IF output
−
89
−
dBµV
deviation pulling in channel
Vi(lock)
Gi
input level without lock-out see Fig.25; note 7
−
−
−
−
120
−
dBµV
mS
input conductance
input capacitance
see Fig.6
see Fig.6
0.3
1.1
Ci
−
pF
High band mixer, including IF amplifier
fRF
Gv
RF frequency
voltage gain
picture carrier; note 4
443.25 −
863.25 MHz
asymmetrical IF output;
load = 75 Ω; see Fig.20
fRF = 443.25 MHz
fRF = 863.25 MHz
31.5
31.5
34.5
37.5
37.5
dB
dB
34.5
symmetrical IF output;
load = 1.25 kΩ; see Fig.21
fRF = 443.25 MHz
fRF = 863.25 MHz
35.5
35.5
38.5
38.5
41.5
41.5
dB
dB
2004 Mar 22
20
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
NF
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
noise figure, not corrected see Fig.22
for image
fRF = 443.25 MHz
−
6.0
8.0
9.0
dB
fRF = 863.25 MHz
−
7.0
dB
Vo
output voltage causing 1% asymmetrical application;
cross modulation in
channel
see Fig.23; note 5
fRF = 443.25 MHz
fRF = 863.25 MHz
107
107
110
110
−
−
dBµV
dBµV
symmetrical application;
see Fig.24; note 5
f
RF = 443.25 MHz
fRF = 863.25 MHz
input level without lock-out see Fig.26; note 7
117
117
−
120
120
−
−
dBµV
dBµV
dBµV
dBµV
−
Vi(lock)
120
−
Vf(N+5)-1
(N + 5) − 1 MHz pulling
fRF(wanted) = 815.25 MHz;
−
80
fosc = 854.15 MHz;
fRF(unwanted) = 854.25 MHz; note 8
Vi
Zi
input voltage causing
750 Hz frequency
deviation pulling in channel
asymmetrical IF output
−
79
−
dBµV
input impedance
fRF = 443.25 MHz; see Fig.7
(RS + jLSω)
RS
−
−
35
8
−
−
Ω
LS
nH
fRF = 863.25 MHz; see Fig.7
RS
LS
−
−
36
8
−
−
Ω
nH
Low band oscillator
fosc
oscillator frequency
note 9
83.15
−
196.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
110
−
−
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V with
compensation; note 11
−
900
95
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 8, 27 and 28
82
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
104
−
100
110
117
−
−
−
dBc/Hz
dBc/Hz
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 10, 27 and 28
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
2004 Mar 22
21
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
Φosc(hyb)
PARAMETER
CONDITIONS
MIN.
80
TYP.
95
MAX.
UNIT
phase noise, carrier to
sideband noise in hybrid
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29, and 30
−
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29, and 30
85
104
−
96
−
−
−
−
dBc/Hz
dBc/Hz
dBc/Hz
mV
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29, and 30
110
117
200
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
RSCp-p
ripple susceptibility of VCC VCC = 5 V ±5%; worst case in the
15
(peak-to-peak value)
frequency range; ripple frequency
500 kHz; note 12
Mid band oscillator
fosc
oscillator frequency
note 9
196.15 −
482.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
110
−
−
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V with
compensation; note 11
−
1500
90
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 8, 27 and 28
85
dBc/Hz
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
104
−
95
−
−
−
−
−
−
−
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 10, 27 and 28
110
115
88
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
Φosc(hyb)
phase noise, carrier to
sideband noise in hybrid
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29 and 30
82
85
104
−
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29 and 30
90
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29 and 30
110
115
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
2004 Mar 22
22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
RSCp-p
PARAMETER
CONDITIONS
MIN.
15
TYP.
MAX.
UNIT
mV
ripple susceptibility of VCC VCC = 5 V ±5%; worst case in the
140
−
(peak-to-peak value)
frequency range; ripple frequency
500 kHz; note 12
High band oscillator
fosc
oscillator frequency
note 9
482.15 −
902.15 MHz
∆fosc(V)
oscillator frequency shift
with supply voltage
note 10
−
300
−
−
−
kHz
∆fosc(T)
oscillator frequency drift
with temperature
∆T = 25 °C; VCC = 5 V; with
compensation; note 11
−
1100
89
kHz
Φosc(dig)
phase noise, carrier to
sideband noise in digital
application
±1 kHz frequency offset;
85
dBc/Hz
fcomp = 4 MHz; see
Figs 8, 27 and 28
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 9, 27 and 28
87
104
−
93
−
−
−
−
−
−
−
−
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
mV
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 11, 27 and 28
107
117
85
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 27 and 28
Φosc(hyb)
phase noise, carrier to
sideband noise in hybrid
application
±1 kHz frequency offset;
fcomp = 4 MHz; see
Figs 11, 29 and 30
80
82
104
−
±10 kHz frequency offset; worst
case in the frequency range; see
Figs 12, 29 and 30
86
±100 kHz frequency offset; worst
case in the frequency range; see
Figs 13, 29 and 30
107
117
40
±1.4 MHz frequency offset; worst
case in the frequency range; see
Figs 29 and 30
RSCp-p
ripple susceptibility of VCC VCC = 5 V ±5%; worst case in the
15
(peak-to-peak value)
frequency range; ripple frequency
500 kHz; note 12
IF amplifier
Zo
output impedance
asymmetrical IF output
RS at 38.9 MHz
−
−
50
−
−
Ω
LS at 38.9 MHz
5.4
nH
symmetrical IF output
RS at 38.9 MHz
−
−
100
−
−
Ω
LS at 38.9 MHz
10.4
nH
2004 Mar 22
23
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Rejection at the IF output (IF amplifier in asymmetrical mode)
INTdiv
divider interferences in
IF level
worst case; note 13
−
−
20
dBµV
dBc
INTxtal
INTf(step)
crystal oscillator
interferences rejection
VIF = 100 dBµV; worst case in the
frequency range; note 14
−
−
−
−
−50
−50
step frequency rejection
measured in digital application for
DVB-T; fstep = 166.67 kHz;
IF = 36.125 MHz; note 15
dBc
measured in hybrid application for
DVB-T; fstep = 166.67 kHz;
IF = 36.125 MHz; note 15
−
−
−
−
−
−
−
−
−57
−57
−57
45
dBc
measured in hybrid application for
PAL; fstep = 62.5 kHz;
IF = 38.9 MHz; note 15
dBc
measured in hybrid application for
FM; fstep = 50 kHz; IF = 38.9 MHz;
note 15
dBc
INTXTH
crystal oscillator
harmonics in the
IF frequency
note 16
dBµV
AGC output (IF amplifier in asymmetrical mode): pin AGC
AGCTOP(p-p)
AGC take-over point
(peak-to-peak level)
bits AL[2:0] = 000
122.5 124
125.5 dBµV
Isource(fast)
Isource(slow)
Vo
source current fast
source current slow
output voltage
7.5
185
3.45
0
9.0
220
3.55
−
11.6
280
3.8
µA
nA
V
maximum level
minimum level
bits AL[2:0] = 111
0.1
V
Vo(dis)
output voltage with AGC
disabled
3.45
3.55
3.8
V
VRF(slip)
RF voltage range to switch
the AGC from active to not
active mode
−
−
0.5
dB
VRML
VRMH
ILO
low threshold AGC output AGC bit = 0 or AGC not active
voltage
0
−
2.8
3.8
+50
V
high threshold AGC output AGC bit = 1 or AGC active
voltage
3.2
3.55
−
V
leakage current
bits AL[2:0] = 110; 0 < VAGC < VCC −50
nA
2004 Mar 22
24
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Notes
1. Important recommendation: to obtain the performances mentioned in this specification, the serial resistance of the
crystal used with this oscillator must never exceed 120 Ω. The crystal oscillator is guaranteed to operate for any
supply voltage between 4.5 V and 5.5 V and at any temperature between −20 °C and +85 °C
2. The drive level is expected with a 50 Ω series resistance of the crystal at series resonance. The drive level will be
different with other series resistance values.
3. The VXTOUT level is measured when the pin XTOUT is loaded with 5 kΩ in parallel with 10 pF.
4. The RF frequency range is defined by the oscillator frequency range and the intermediate frequency (IF).
5. The 1% cross modulation performance is measured with AGC detector turned off (AGC bits set to 110).
6. Channel SO2 beat is the interfering product of fRFpix, fIF and fosc of channel SO2; fbeat = 37.35 MHz. The possible
mechanisms are: fosc − 2 × fIFpix or 2 × fRFpix − fosc
.
7. The IF output signal stays stable within the range of the step frequency for any RF input level up to 120 dBµV.
8. (N + 5) − 1 MHz pulling is the input level of channel N + 5, at frequency 1 MHz lower, causing 100 kHz FM sidebands
30 dB below the wanted carrier.
9. Limits are related to the tank circuits used in Figs 27 and 28 for digital application or Figs 29 and 30 for hybrid
application. Frequency bands may be adjusted by the choice of external components.
10. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from
VCC = 5 to 4.5 V or from VCC = 5 to 5.25 V. The oscillator is free running during this measurement.
11. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from
Tamb = 25 to 50 °C or from Tamb = 25 to 0 °C. The oscillator is free running during this measurement.
12. The supply ripple susceptibility is measured in the measurement circuit according to Figs 27, 28, 29 and 30 using a
spectrum analyser connected to the IF output. An unmodulated RF signal is applied to the test board RF input. A
sinewave signal with a frequency of 500 kHz is superimposed onto the supply voltage. The amplitude of this ripple
signal is adjusted to bring the 500 kHz sidebands around the IF carrier to a level of −53.5 dB with respect to the
carrier.
13. This is the level of divider interferences close to the IF frequency. For example channel S3: fosc = 158.15 MHz,
1⁄4 fosc = 39.5375 MHz. The low and mid band inputs must be left open (i.e. not connected to any load or cable); the
high band inputs are connected to an hybrid.
14. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator.
15. The step frequency rejection is the level of step frequency sidebands (e.g. 166.67 kHz) related to the carrier.
16. This is the level of the 9th and 11th harmonics of the 4 MHz crystal oscillator into the IF output.
2004 Mar 22
25
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
1
2
0.5
0.2
5
10
∞
10
− j
+ j
10
5
2
1
0.5
0.2
40 MHz
0
200 MHz
5
0.2
2
0.5
MCE160
1
Fig.5 Input admittance (S11) of the low band mixer (40 to 200 MHz); Yo = 20 mS.
1
2
0.5
0.2
5
10
∞
10
− j
+ j
10
5
2
1
0.5
0.2
100 MHz
0
500 MHz
5
0.2
2
0.5
MCE161
1
Fig.6 Input admittance (S11) of the mid band mixer (100 to 500 MHz); Yo = 20 mS.
2004 Mar 22
26
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
1
0.5
2
900 MHz
0.2
5
400 MHz
0.5
10
+ j
− j
0.2
1
2
5
10
0
∞
10
5
0.2
2
0.5
MCE165
1
Fig.7 Input impedance (S11) of the high band mixer (400 to 900 MHz); Zo = 100 Ω.
FCE915
−80
Φ
osc
(dBc/Hz)
−85
−90
−95
−100
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.8 1 kHz phase noise typical performance in digital application (Figs 27 and 28).
27
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE916
−80
Φ
osc
(dBc/Hz)
−85
−90
−95
−100
−105
−110
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.9 10 kHz phase noise typical performance in digital application (Figs 27 and 28).
FCE917
−100
Φ
osc
(dBc/Hz)
−105
−110
−115
−120
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.10 100 kHz phase noise typical performance in digital application (Figs 27 and 28).
28
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE918
−80
Φ
osc
(dBc/Hz)
−85
−90
−95
−100
−105
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.11 1 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
FCE919
−80
Φ
osc
(dBc/Hz)
−85
−90
−95
−100
−105
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.12 10 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
29
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FCE920
−100
Φ
osc
(dBc/Hz)
−105
−110
−115
−120
40
140
240
340
440
540
640
740
840
940
(MHz)
f
RF
Fig.13 100 kHz phase noise typical performance in hybrid application (Figs 29 and 30).
signal
LBIN
or
MBIN
source
50 Ω
27 Ω
IFOUTA
spectrum
analyzer
DUT
50
Ω
V
e
V
V'
meas
50 Ω
meas
V
o
V
i
IFOUTB
RMS
voltmeter
V
FCE747
CCA
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 3.75 dB.
Vo
Gv = 20 log
.
------
DVB-T and PAL.
IF = 38.9 MHz.
Vi
Fig.14 Gain (GV) measurement in low and mid band with asymmetrical IF output.
30
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
signal
50 Ω source
LBIN
or
transformer
IFOUTA
spectrum
MBIN
analyzer
V
DUT
50
Ω
N1
N2
V'
C
meas
e
50 Ω
V
V
i
V
o
meas
IFOUTB
RMS
voltmeter
FCE748
Zi >> 50 Ω → Vi = 2 × Vmeas = 70 dBµV.
Vi = Vmeas + 6 dB = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N2/N1 = 5 and transformer loss).
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
Vo
DVB-T and PAL.
IF = 38.9 MHz.
Gv = 20 log
.
------
Vi
Fig.15 Gain (GV) measurement in low and mid band with symmetrical IF output.
NOISE
FIGURE
METER
LBIN
or
MBIN
27 Ω
NOISE
SOURCE
BNC
RIM
IFOUTA
INPUT
CIRCUIT
DUT
IFOUTB
V
FCE750
CCA
NF = NFmeas − loss of input circuit (dB).
Fig.16 Noise figure (NF) measurement in low and mid band with asymmetrical IF output.
31
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
BNC
connector
BNC
connector
Cs
TL
TL
Cc
Cp
Cc
Cp
Ls
to the IC
mixer input
to the IC
mixer input
Lp
Lp
MCE452
Schematic A.
Schematic B.
For fRF = 50 MHz (Schematic A)
For fRF = 300 MHz (Schematic B)
Loss = 0 dB.
Loss = 0.5 dB.
Cs = 12 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cp = 18 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cc = 4.7 nF.
Cp = 8.2 pF in parallel with a 0.8 pF to 8 pF trimmer.
Cc = 4.7 nF.
Ls = 2 turns, 1.5 mm, wire = 0.4 mm air coil.
Lp = 2 turns, 1.5 mm, wire = 0.4 mm air coil.
TL = 50 Ω semi rigid cable, length = 75 mm.
Lp = 8 turns, 5 mm, wire = 0.4 mm air coil
TL = 50 Ω semi rigid cable, length = 75 mm.
For fRF = 150 MHz (Schematic A)
Loss = 0 dB.
Cs = 0.8 pF to 8 pF trimmer.
Cp = 0.4 pF to 2.5 pF trimmer.
Cc = 4.7 nF.
Lp = 4 turns, 4.5 mm, wire = 0.4 mm air coil
TL = 50 Ω semi rigid cable, length = 75 mm.
Fig.17 Input circuit for optimum noise figure in low and mid band.
FILTER
AM = 30%
10 dB
1 kHz
LBIN
or
MBIN
attenuator
50 Ω
27 Ω
A
C
IFOUTA
modulation
analyzer
unwanted
signal
source
e
u
38.9 MHz
V
o
HYBRID
DUT
V
meas
50 Ω
V
50 Ω
IFOUTB
B
D
wanted
signal
source
50
Ω
e
w
RMS
voltmeter
V
CCA
fce749
Vo = Vmeas + 3.75 dB.
Wanted signal source at fRFpix is 80 dBµV.
Unwanted output signal at fsnd
.
The level of unwanted signal is measured by causing 1% AM modulation in
the wanted signal.
Fig.18 Cross modulation measurement in low and mid band with asymmetrical IF output.
32
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FILTER
6 dB
AM = 30%
attenuator
1 kHz
LBIN
or
MBIN
50 Ω
transformer
A
IFOUTA
C
modulation
analyzer
unwanted
signal
e
u
38.9 MHz
source
HYBRID
C
N2
DUT
N1
o
V
V'
meas
50 Ω
V
50 Ω
B
D
IFOUTB
wanted
signal
source
50
Ω
e
w
RMS
voltmeter
fce793
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Wanted signal source at fRFpix is 80 dBµV.
N1 = 10 turns.
N2 = 2 turns.
N1/N2 = 5.
The level of unwanted signal Vo at fsnd is measured by causing 1%
AM modulation in the wanted output signal.
Fig.19 Cross modulation measurement in low and mid band with symmetrical IF output.
signal
source
50 Ω
27 Ω
A
HBIN1
HBIN2
C
IFOUTA
spectrum
analyzer
DUT
50
Ω
HYBRID
V
V
V
e
50 Ω
meas
i
V
o
IFOUTB
B
D
50
Ω
RMS
voltmeter
V
CCA
FCE751
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 3.75 dB.
Vo
G = 20 log
v
.
------
DVB-T and PAL.
IF = 38.9 MHz.
Vi
Fig.20 Gain (GVa) measurement in high band with asymmetrical IF output.
33
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
signal
source
50 Ω
transformer
C
D
HBIN1
HBIN2
IFOUTA
A
spectrum
analyzer
50
Ω
DUT
HYBRID
V
C
N1
N2
V'
V
e
V
meas
50 Ω
i
V
o
meas
B
IFOUTB
50
Ω
RMS
voltmeter
FCE752
Loss in hybrid = 1 dB.
Vi = Vmeas − loss = 70 dBµV.
Vo = V’meas + 15 dB (transformer ratio N2/N1 = 5 and transformer
loss).
Vo
DVB-T and PAL.
IF = 38.9 MHz.
G = 20 log
v
.
------
Vi
Fig.21 Gain (GVs) measurement in high band with symmetrical IF output.
NOISE
FIGURE
METER
27 Ω
NOISE
SOURCE
A
HBIN1 IFOUTA
C
HYBRID
DUT
B
D
IFOUTB
HBIN2
50
Ω
V
FCE753
CCA
Loss in hybrid = 1 dB.
NF = NFmeas − loss.
Fig.22 Noise figure (NF) measurement in high band with asymmetrical IF output.
34
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
FILTER
AM = 30%
10 dB
1 kHz
attenuator
50 Ω
27 Ω
A
A
C
C
HBIN1
IFOUTA
IFOUTB
modulation
analyzer
unwanted
signal
source
e
u
38.9 MHz
HYBRID
HYBRID
DUT
V
o
V
50 Ω
V
meas
50 Ω
B
D
B
D
HBIN2
wanted
signal
source
50
Ω
50
Ω
e
w
RMS
voltmeter
V
CCA
fce754
Wanted signal source at fRFpix is 70 dBµV.
Unwanted output signal at fsnd
.
The level of unwanted signal is measured by causing 1% AM modulation
in the wanted signal.
Fig.23 Cross modulation measurement in high band with asymmetrical IF output.
FILTER
6 dB
attenuator
AM = 30%
1 kHz
transformer
50 Ω
A
C
A
C
HBIN1 IFOUTA
DUT
modulation
unwanted
signal
source
analyzer
e
u
38.9 MHz
HYBRID
HYBRID
V'
meas
N1
N2
C
V
50 Ω
V
o
50 Ω
B
D
D
HBIN2 IFOUTB
B
wanted
signal
source
50
Ω
50
Ω
e
w
RMS
voltmeter
fce794
N1 = 10 turns.
N2 = 2 turns.
N1 / N2 = 5.
V’meas = Vo − (transformer ratio N1/N2 = 5 and loss).
Fig.24 Cross modulation measurement in high band with symmetrical IF output.
35
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
signal
source
LBIN
or
27 Ω
50 Ω
IFOUTA
spectrum
analyzer
MBIN
50
Ω
DUT
e
V
V
50 Ω
meas
IFOUTB
RMS
voltmeter
V
CCA
FCE755
Zi >> 50 Ω → Vi = 2 × Vmeas
.
Vi = Vmeas + 6 dB.
Fig.25 Maximum RF input level without lock-out in low and mid band with asymmetrical IF output.
signal
source
27 Ω
50 Ω
A
HBIN1
HBIN2
IFOUTA
IFOUTB
C
spectrum
analyzer
DUT
HYBRID
50
Ω
V
V
V
50 Ω
e
i
meas
B
D
50
Ω
RMS
voltmeter
V
FCE756
CCA
Loss in hybrid = 1 dB.
Vi = Vmeas − loss.
Fig.26 Maximum RF input level without lock-out in high band with asymmetrical IF output.
36
2004 Mar 22
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
The TDA6650TT, TDA6651TT PLL loop stability is
guaranteed in the configuration of Figs. 27, 28, 29 and 30.
In this configuration, the external supply source is 30 V
minimum, the pull-up resistor R19, is 15 kΩ and all of the
local oscillators are aligned to operate at a maximum
tuning voltage of 26 V. If the configuration is changed,
there might be an impact on the loop stability.
V
DC – VT
Idelivered
Where
=
> ICP
-----------------------
Rpu
I
delivered is the delivered current
VDC is the supply source voltage or DC-to-DC converter
output voltage
For any other configurations, a stability analysis must be
performed. The conventional PLL AC model (cf. SIMPATA
Philips software) used for the stability analysis, is valid
provided the external source (DC supply source or
DC-to-DC converter) is able to deliver a minimum current
that is equal to the charge pump current in use.
VT is the tuning voltage
Rpu is the pull-up resistor between the DC supply source
(or the DC-to-DC converter output) and the tuning line
(R19 in Figs. 27 to 30)
ICP is the charge pump current in use.
The delivered current can be simply calculated with the
following formula:
2004 Mar 22
37
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
The pin numbers in parenthesis
represent the TDA6651TT.
J4
J1
J2
J3
LOW
HIGH1 HIGH2
MID
C7
L3
R1
140 nH
R08304
12 Ω
1.8 pF
N750
C6
C5
D1
C4
4.7
nF
C3
4.7
nF
C1
4.7
nF
C2
4.7
nF
47 pF
N750
1.5 pF BB182
N750
R2
6
4
1 kΩ
2
6t
2
L4
T0K0;
500 nF
*
C34
R3
HBIN1
LOSCIN
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
9 (30)
(1) 38
(2) 37
5.6 kΩ
120 pF
N750
HBIN2
MBIN
LBIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
1
3
D2
BB178
R4
L1
25 nH
(3) 36
C27
C26
(4) 35
C33
RFGND
IFFIL1
IFFIL2
BS4
(5) 34
12 pF
12 pF
5.6 kΩ
120 pF
N750
(6) 33
(7) 32
C11 1 pF
TDA6650TT
(TDA6651TT)
(8) 31
AGC
AGC
TP1
(9) 30
N750
D3
BB179
BS3
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C28
150 nF
C12 1 pF
BS2
IFOUTA
L2
13 nH
R01255
R5
BS1
IFOUTB
N750
C13 1 pF
V
BVS
D4
CCA
R20
5.6 kΩ
C17
ADC/BS5
SCL
PLLGND
15 pF
N470
R8
1 kΩ
C18
V
N750
CCD
V
CC
2.7 nF
D5
D6
D7
D8
SDA
CP
C14 1 pF
R21
R6
AS
VT
1 kΩ
27 Ω
5.6 kΩ
N750
XTOUT
XTAL1
n.c.
XTAL2
R22
1 kΩ
V
CC
Y1
C19
18 pF
R9
330
Ω
R10
330
Ω
R11
330
Ω
V
CC
C23
4.7 nF
R7
1 kΩ
R23
C21
100 nF
4 MHz
1 kΩ
C16
4.7 nF
C15
4.7 nF
5 V bus
ST2
V
R24
ADC
5 V bus
C20
330 pF
R13
6.8 kΩ
1 kΩ
R27
3.3
kΩ
R28
3.3
kΩ
V
CC
CC
30 V
R14
SCL
1
SDA AS
C29
4.7 nF
ST1
1 kΩ
R19
15 kΩ
R26
27 Ω
C31
10
µF
C32
10
µF
C30
10
µF
1
2 3 4
J5
J8
2
3
4
5
6
J6
J7
IF out
test
30 V
5 V bus
MCE162
Fig.27 Measurement circuit for digital application, with asymmetrical IF output and DVB-T compliant loop filter.
ahdnbok,uflapegwidt
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
J4
LOW
J3
J1
J2
C7
L3
R1
MID HIGH1 HIGH2
140 nH
R08304
12 Ω
1.8 pF
N750
C6
C5
D1
C4
4.7
nF
C3
4.7
nF
C1
4.7
nF
C2
4.7
nF
47 pF
N750
1.5 pF BB182
N750
R2
6
4
1 kΩ
2
6t
2
L4
T0K0;
500 nF
*
C34
R3
HBIN1
LOSCIN
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
9 (30)
(1) 38
(2) 37
5.6 kΩ
120 pF
N750
HBIN2
MBIN
LBIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
1
3
D2
BB178
R4
L1
25 nH
(3) 36
C27
C26
(4) 35
C33
RFGND
IFFIL1
IFFIL2
BS4
(5) 34
12 pF
12 pF
5.6 kΩ
120 pF
N750
(6) 33
(7) 32
C11 1 pF
TDA6650TT
(TDA6651TT)
(8) 31
AGC
AGC
TP1
(9) 30
N750
D3
BB179
BS3
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C28
150 nF
C12 1 pF
BS2
IFOUTA
L2
13 nH
R01255
R5
BS1
IFOUTB
N750
C13 1 pF
V
BVS
D4
CCA
R20
5.6 kΩ
C17
ADC/BS5
SCL
PLLGND
15 pF
N470
R8
1 kΩ
C18
V
N750
CCD
V
CC
2.7 nF
D5
D6
D7
D8
SDA
CP
C14 1 pF
R21
R6
AS
VT
1 kΩ
27 Ω
5.6 kΩ
N750
XTOUT
XTAL1
n.c.
XTAL2
R22
C24
4.7 nF
C23
4.7 nF
R7
1 kΩ
1 kΩ
C21
100 nF
Y1
C19
18 pF
R9
330
Ω
R10
330
Ω
R11
330
Ω
V
CC
R23
C25
4 MHz
C20
330 pF
1 kΩ
R13
6.8 kΩ
C16
4.7 nF
C15
4.7 nF
5 V bus
12 pF
ST2
V
R24
ADC
5 V bus
1 kΩ
R27
3.3
kΩ
R28
3.3
kΩ
1
2
3
4
V
CC
CC
30 V
R14
SCL
1
SDA AS
C29
4.7 nF
ST1
1 kΩ
6
C31
10
C32
10
C30
10
1
2 3 4
J5
J8
4 5
R19
15 kΩ
R26
0 Ω
2
3
6
µF
µF
µF
J7
J6
test
IF out
30 V
fce875
5 V bus
The pin numbers in parenthesis represent
the TDA6651TT.
Fig.28 Measurement circuit for digital application, with symmetrical IF output and DVB-T compliant loop filter.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
The pin numbers in parenthesis
represent the TDA6651TT.
J4
LOW
J3
J1
J2
C7
L3
R1
MID HIGH1 HIGH2
140 nH
R08304
12 Ω
1.8 pF
N750
C6
C5
D1
C4
4.7
nF
C3
4.7
nF
C1
4.7
nF
C2
4.7
nF
47 pF
N750
1.5 pF BB182
N750
R2
6
4
1 kΩ
2
6t
2
L4
T0K0;
500 nF
*
C34
R3
HBIN1
LOSCIN
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
9 (30)
(1) 38
(2) 37
5.6 kΩ
120 pF
N750
HBIN2
MBIN
LBIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
1
3
D2
BB178
R4
L1
25 nH
(3) 36
C27
C26
(4) 35
C33
RFGND
IFFIL1
IFFIL2
BS4
(5) 34
12 pF
12 pF
5.6 kΩ
120 pF
N750
(6) 33
(7) 32
C11 1 pF
TDA6650TT
(TDA6651TT)
(8) 31
AGC
AGC
TP1
(9) 30
N750
D3
BB179
BS3
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C28
150 nF
C12 1 pF
BS2
IFOUTA
L2
13 nH
R01255
R5
BS1
IFOUTB
N750
C13 1 pF
V
BVS
D4
CCA
R20
5.6 kΩ
C17
ADC/BS5
SCL
PLLGND
15 pF
N470
R8
1 kΩ
C18
V
N750
CCD
V
CC
4.7 nF
D5
D6
D7
D8
SDA
CP
C14 1 pF
R21
R6
AS
VT
1 kΩ
27 Ω
5.6 kΩ
N750
XTOUT
XTAL1
n.c.
XTAL2
R22
1 kΩ
V
CC
Y1
C19
18 pF
R9
330
Ω
R10
330
Ω
R11
330
Ω
V
CC
C23
4.7 nF
R7
1 kΩ
R23
C21
100 nF
4 MHz
1 kΩ
C16
4.7 nF
C15
4.7 nF
5 V bus
ST2
V
R24
ADC
5 V bus
C20
2.7 nF
R13
1.8 kΩ
1 kΩ
R27
3.3
kΩ
R28
3.3
kΩ
V
CC
CC
30 V
R14
SCL
1
SDA AS
C29
4.7 nF
ST1
1 kΩ
R19
15 kΩ
R26
27 Ω
C31
10
µF
C32
10
µF
C30
10
µF
1
2 3 4
J5
J8
2
3
4
5
6
J6
J7
IF out
test
30 V
FCE909
5 V bus
Fig.29 Measurement circuit for hybrid application, with asymmetrical IF output and loop filter for PAL and DVB-T standards.
ahdnbok,uflapegwidt
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
J4
LOW
J3
J1
J2
C7
L3
R1
MID HIGH1 HIGH2
140 nH
R08304
12 Ω
1.8 pF
N750
C6
C5
D1
C4
4.7
nF
C3
4.7
nF
C1
4.7
nF
C2
4.7
nF
47 pF
N750
1.5 pF BB182
N750
R2
6
4
1 kΩ
2
6t
2
L4
T0K0;
500 nF
*
C34
R3
HBIN1
LOSCIN
1 (38)
2 (37)
3 (36)
4 (35)
5 (34)
6 (33)
7 (32)
8 (31)
9 (30)
(1) 38
(2) 37
5.6 kΩ
120 pF
N750
HBIN2
MBIN
LBIN
LOSCOUT
OSCGND
MOSCIN2
MOSCIN1
HOSCIN2
HOSCOUT2
HOSCOUT1
HOSCIN1
IFGND
1
3
D2
BB178
R4
L1
25 nH
(3) 36
C27
C26
(4) 35
C33
RFGND
IFFIL1
IFFIL2
BS4
(5) 34
12 pF
12 pF
5.6 kΩ
120 pF
N750
(6) 33
(7) 32
C11 1 pF
TDA6650TT
(TDA6651TT)
(8) 31
AGC
AGC
TP1
(9) 30
N750
D3
BB179
BS3
10 (29)
11 (28)
12 (27)
13 (26)
14 (25)
15 (24)
16 (23)
17 (22)
18 (21)
19 (20)
(10) 29
(11) 28
(12) 27
(13) 26
(14) 25
(15) 24
(16) 23
(17) 22
(18) 21
(19) 20
C28
150 nF
C12 1 pF
BS2
IFOUTA
L2
13 nH
R01255
R5
BS1
IFOUTB
N750
C13 1 pF
V
BVS
D4
CCA
R20
5.6 kΩ
C17
ADC/BS5
SCL
PLLGND
15 pF
N470
R8
1 kΩ
C18
V
N750
CCD
V
CC
2.7 nF
D5
D6
D7
D8
SDA
CP
C14 1 pF
R21
R6
AS
VT
1 kΩ
27 Ω
5.6 kΩ
N750
XTOUT
XTAL1
n.c.
XTAL2
R22
C24
4.7 nF
C23
4.7 nF
R7
1 kΩ
1 kΩ
C21
100 nF
Y1
C19
18 pF
R9
330
Ω
R10
330
Ω
R11
330
Ω
V
CC
R23
C25
4 MHz
C20
2.7 nF
1 kΩ
R13
6.8 kΩ
C16
4.7 nF
C15
4.7 nF
5 V bus
12 pF
ST2
V
R24
ADC
5 V bus
1 kΩ
R27
3.3
kΩ
R28
3.3
kΩ
1
2
3
4
V
CC
CC
30 V
R14
SCL
1
SDA AS
C29
4.7 nF
ST1
1 kΩ
6
C31
10
C32
10
C30
10
1
2 3 4
J5
J8
4 5
R19
15 kΩ
R26
0 Ω
2
3
6
µF
µF
µF
J7
J6
test
IF out
30 V
fce910
5 V bus
The pin numbers in parenthesis represent
the TDA6651TT.
Fig.30 Measurement circuit for hybrid application, with symmetrical IF output and loop filter for PAL and DVB-T standards.
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
13 INTERNAL PIN CONFIGURATION
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID HIGH
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
n.a.
HBIN1
HBIN2
1
2
38
37
n.a
n.a
1.0 V
1.0 V
n.a.
n.a.
(38)
1
2 (37)
FCE899
MBIN
3
4
5
36
35
34
1.8 V
n.a.
−
n.a.
n.a
−
(36)
3
FCE901
LBIN
1.8 V
(35)
4
FCE898
RFGND
−
5
(34)
FCE897
IFFIL1
IFFIL2
6
7
33
32
3.7 V
3.7 V
3.7 V
3.7 V
3.7 V
3.7 V
7
(32)
(33)
6
FCE896
2004 Mar 22
42
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
high Z or
CC − VDS
HIGH
BS4
8
31
high Z or
CC − VDS
high Z or
VCC − VDS
V
V
8
(31)
FCE895
AGC
9
30
0 V or
3.5 V
0 V or
3.5 V
0 V or
3.5 V
9
(30)
FCE907
BS3
BS2
10
11
29
28
high Z or
high Z or
high Z or
VCC − VDS
VCC − VDS
VCC − VDS
10 (29)
FCE893
high Z
VCC − VDS high Z
11 (28)
FCE892
BS1
12
27
VCC − VDS high Z
high Z
12 (27)
FCE891
2004 Mar 22
43
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
2.5 V
HIGH
BVS
13
26
2.5 V
2.5 V
(26) 13
MCE163
ADC/BS5
14
25
VCEsat or
high Z
VCEsat or
high Z
VCEsat or
high Z
(25) 14
FCE887
SCL
15
24
high Z
high Z
high Z
(24) 15
FCE889
SDA
16
23
high Z
high Z
high Z
(23) 16
FCE888
AS
17
22
1.25 V
1.25 V
1.25 V
(22) 17
FCE890
2004 Mar 22
44
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID HIGH
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
3.45 V
XTOUT
18
21
3.45 V
3.45 V
18 (21)
MCE164
XTAL1
XTAL2
19
20
20
19
2.2 V
2.2 V
2.2 V
2.2 V
2.2 V
2.2 V
20 (19)
19 (20)
FCE883
n.c.
VT
21
22
18
17
n.a.
VVT
not connected
VVT
VVT
22 (17)
FCE884
CP
23
16
1.8 V
1.8 V
1.8 V
23 (16)
FCE885
VCCD
24
15
5 V
5 V
5 V
2004 Mar 22
45
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID HIGH
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
PLLGND
25
14
−
−
−
(14)
25
FCE882
VCCA
26
27
28
13
12
11
5 V
5 V
5 V
IFOUTB
IFOUTA
2.1 V
2.1 V
2.1 V
2.1 V
2.1 V
2.1 V
28 (11)
FCE886
IFGND
29
10
−
−
−
(10)
29
FCE880
HOSCIN1
30
31
32
33
9
8
7
6
2.2 V
5 V
2.2 V
5 V
1.8 V
2.5 V
2.5 V
1.8 V
HOSCOUT1
HOSCOUT2
HOSCIN2
5 V
5 V
(7)
32
31
33
(8)
(6)
2.2 V
2.2 V
30 (9)
FCE879
MOSCIN1
MOSCIN2
34
35
5
4
2.3 V
2.3 V
1.3 V
1.3 V
2.3 V
2.3 V
35 (4)
34 (5)
FCE878
2004 Mar 22
46
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
AVERAGE DC VOLTAGE VERSUS
PIN
BAND SELECTION
MID HIGH
SYMBOL
DESCRIPTION(1)
TDA6650TT TDA6651TT
LOW
OSCGND
36
3
−
−
−
36 (3)
FCE908
LOSCOUT
LOSCIN
37
38
2
1
1.7 V
2.9 V
1.4 V
3.5 V
1.4 V
3.5 V
(2)
37
(1) 38
FCE877
Note
1. The pin numbers in parenthesis refer to the TDA6651TT.
2004 Mar 22
47
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
14 APPLICATION AND TEST INFORMATION
14.1 Tuning amplifier
Do not use the signal on pins XTAL1 or XTAL2, or the
signal present on the crystal, to drive an external IC or for
any other use as this may dramatically degrade the phase
noise performance of the TDA6650TT; TDA6651TT.
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 15 kΩ
which is connected to the tuning voltage supply rail. The
loop filter design depends on the oscillator characteristics
and the selected reference frequency as well as the
required PLL loop bandwidth.
14.3 Examples of I2C-bus program sequences
Tables 16 to 23 show various sequences where:
S = START
A = acknowledge
P = STOP.
Applications with the TDA6650TT; TDA6651TT have a
large loop bandwidth, in the order of a few tens of kHz. The
calculation of the loop filter elements has to be done for
each application, it depends on the reference frequency
and charge pump current. A simulation of the loop can
easily be done using the SIMPATA software from Philips.
The following conditions apply:
LO frequency is 800 MHz
fcomp = 166.666 kHz
N = 4800
BS3 output port is on and all other ports are off: thus the
high band is selected
14.2 Crystal oscillator
The TDA6650TT; TDA6651TT needs to be used with a
4 MHz crystal in series with a capacitor with a typical value
of 18 pF, connected between pin XTAL1 and pin XTAL2.
Philips crystal 4322 143 04093 is recommended. When
choosing a crystal, take care to select a crystal able to
withstand the drive level of the TDA6650TT; TDA6651TT
without suffering from accelerated ageing. For optimum
performances, it is highly recommended to connect the
4 MHz crystal without any serial resistance.
Charge pump current ICP = 280 µA
Normal mode, with XTOUT buffer on
IAGC = 220 nA
AGC take-over point is set to 112 dBµV (p-p)
Address selection is adjusted to make address C2 valid.
To fully program the device, either sequence of Table 16
or 17 can be used, while other arrangements of the bytes
are also possible.
The crystal oscillator of the TDA6650TT; TDA6651TT
should not be driven (forced) from an external signal.
Table 16 Complete sequence 1
ADDRESS
BYTE
DIVIDER
BYTE 1
DIVIDER
BYTE 2
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
CONTROL
BYTE 1(2)
START
S
STOP
C2
A
12
A
C0
A
CA
A
A4
A
84
A
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 17 Complete sequence 2
ADDRESS
BYTE
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
DIVIDER
BYTE 1
DIVIDER
BYTE 2
CONTROL
BYTE 1(2)
START
S
STOP
C2
A
CA
A
A4
A
12
A
C0
A
84
A
P
Notes
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
2004 Mar 22
48
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
Table 18 Sequence to program only the main divider ratio
START
ADDRESS BYTE
C2
DIVIDER BYTE 1
12
DIVIDER BYTE 2
C0
STOP
S
A
A
A
P
Table 19 Sequence to change the charge pump current, the ports and the test mode. If the reference divider ratio is
changed, it is necessary to send the DB1 and DB2 bytes
START
ADDRESS BYTE
C2
CONTROL BYTE 1(1)
CA
CONTROL BYTE 2
A4
STOP
S
A
A
A
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 20 Sequence to change the test mode. If the reference divider ratio is changed, it is necessary to send the DB1
and DB2 bytes
START
ADDRESS BYTE
C2
CONTROL BYTE 1(1)
CA
STOP
S
A
A
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
Table 21 Sequence to change the charge pump current, the ports and the AGC data
START
ADDRESS BYTE
C2
CONTROL BYTE 1(1)
82
CONTROL BYTE 2
A4
STOP
S
A
A
A
P
Note
1. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 22 Sequence to change only the AGC data
START
ADDRESS BYTE
C2
CONTROL BYTE 1(1)
84
STOP
S
A
A
P
Note
1. Control byte 1 with bit T/A = 0, to program AGC time constant bit ATC and AGC take-over point bits AL2, AL1
and AL0.
Table 23 Sequence to program the main divider, the ALBC on and the test modes in normal mode with XTOUT buffer
off.
STAR
T
ADDRESS
BYTE
DIVIDER
BYTE 1
DIVIDER
BYTE 2
CONTROL
BYTE 1(1)
CONTROL
BYTE 2
CONTROL
BYTE 1
STOP
S
C2
A
12
A
C0
A
DA
A
00
A
C2
A
P
Note
1. Control byte 1 with bit T/A = 1, to program test bits T2, T1 and T0 and reference divider ratio bits R2, R1 and R0.
2004 Mar 22
49
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
15 PACKAGE OUTLINE
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;
lead pitch 0.5 mm
SOT510-1
E
H
D
A
X
c
v
M
A
y
E
Z
20
38
A
(A )
3
2
A
A
1
pin 1 index
θ
L
p
L
1
19
detail X
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
(1)
Z
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
v
w
y
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.85
0.27
0.17
0.20
0.09
9.8
9.6
4.5
4.3
0.7
0.5
0.49
0.21
mm
1.1
0.5
1
0.2
0.25
6.4
0.08
0.08
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
98-09-16
03-02-18
SOT510-1
2004 Mar 22
50
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
16 SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
16.1 Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
16.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
16.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Mar 22
51
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
PLCC(5), SO, SOJ
not suitable(4)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not recommended(7)
suitable
not suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 Mar 22
52
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
17 DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18 DEFINITIONS
19 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Mar 22
53
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2004 Mar 22
54
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R25/03/pp55
Date of release: 2004 Mar 22
Document order number: 9397 750 13025
相关型号：
TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651ATT/C3
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651ATT/C3/S2
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651ATT/C3/S3
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651TT
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651TT/C3
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651TT/C3/S2
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
TDA6651TT/C3/S3
5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
NXP
©2020 ICPDF网 联系我们和版权申明