TDA8006H [NXP]
Multiprotocol IC Card coupler; 多协议IC卡连接器
| 型号： | TDA8006H |
| 厂家： | 
NXP |
| 描述： | Multiprotocol IC Card coupler |
| 文件： | 总40页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8006
Multiprotocol IC Card coupler
Product specification
2000 Feb 21
Supersedes data of 1998 Aug 18
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
FEATURES
APPLICATIONS
• 80C52 core with 16 kbyte ROM and 256 byte RAM
• Extra 1 kbyte RAM outside the core for data storage
• Smart card readers for multiprotocol applications
(EMV banking, digital pay TV, access control, etc.).
• Control and communication through a standard RS232
GENERAL DESCRIPTION
full duplex interface or a parallel interface
• Specific ISO 7816 UART with parallel access on I/O for
automatic convention processing, variable baud rate
through frequency or division ratio programming, error
management at character level for T = 0, extra guard
time register
It is assumed that the reader of this data sheet is familiar
with ISO 7816.
The TDA8006 is controlled either through a standard serial
interface or a parallel bus, it takes care of all ISO 7816,
EMV and GSM11.11 requirements. It gives the card and
the set a very high level of security due to its special
hardware against ESD, short circuit, power failure, etc.
Its integrated step-up converter allows operation within a
supply voltage range of 4.2 to 6 V.
• VCC generation (5 V ±5% or 3 V ±5%, 65 mA maximum
with controlled rise and fall times)
• Card clock generation (up to 10 MHz) with two times
synchronous frequency doubling
• Card clock STOP HIGH, clock STOP LOW or 1.25 MHz
(from internal oscillator) for card power-down mode
A special version of the TDA8006 is available which has its
internal connections to the controller accessible through
external pins. This allows easy development and
evaluation when used with a 80CL580 microcontroller or a
development tool. An emulation board is available.
• CLKOUT output for clocking external devices with either
f
xtal, 1⁄2fxtal or 1⁄4fxtal
• Automatic activation and deactivation sequence through
an independent sequencer
A software library has been developed, taking care of all
actions required for T = 0, T = 1 and synchronous
protocols. This library may be either linked with the
application software before masking, or masked in the
internal ROM (see “Application Note AN98106”).
• Supports the asynchronous protocols T = 0 and T = 1 in
accordance with ISO 7816, Europay, Mastercard and
Visa (EMV)
• Supports synchronous cards
• Short circuit current limiting
• Special circuitry for killing spikes during power-on or off
• Supply supervisor for power-on/off reset
• Step-up converter (supply voltage from 4.2 to 6 V)
• Power-down and sleep mode for low power
consumption
• Enhanced ESD protection on card side (6 kV minimum)
• Software library for easy integration within the
application.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA8006H/C1
TDA8006H/C2
TDA8006H/C3
TDA8006AH/C1
TDA8006AH/C2
TDA8006AH/C3
QFP64
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
SOT319-2
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2
2000 Feb 21
2
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage
supply current in power-down mode VDD = 5 V; card inactive; note 1
CONDITIONS
MIN.
4.2
TYP. MAX. UNIT
VDD
−
−
−
6
V
IDD(pd)
IDD(sm)
−
−
250
µA
supply current in sleep mode
card powered but clock stopped;
note 1
1500 µA
VCC
card supply voltage
including static loads (5 V card)
4.75
4.6
5.0
5.25
5.4
V
V
with 40 nAs dynamic loads on
100 nF capacitor (5 V card)
−
including static loads (3 V card)
2.80
2.75
−
−
3.20
3.25
V
V
with 24 nAs dynamic loads on
100 nF capacitor (3 V card)
ICC
SR
card supply current
operating
−
−
−
65
−
mA
overload detection
80
0.16
mA
slew rate (rise and fall)
maximum load capacitor pin VCC 0.10
400 nF (including typical 100 nF
decoupling)
0.22
V/µs
tde
deactivation cycle duration
activation cycle duration
crystal frequency
−
−
4
−
−
−
−
100
225
25
µs
tact
fxtal
foper
µs
MHz
MHz
operating frequency
external frequency applied on
pin XTAL1
0
25
Tamb
operating ambient temperature
−25
−
+85
°C
Note
1.
IDD in all configurations include the current at pins VDD, VDDA and VDDRAM.
2000 Feb 21
3
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
BLOCK DIAGRAM
V
V
DD
100 nF
DDA
30
100 nF
S2
GND
S1
AGND
28 (18)
41(28) 40 (27)
29 (19)
31
(21)
TDA8006H
(TDA8006AH)
(20)
45 (32)
ALARM
SUPPLY
AND
SUPERVISOR
STEP-UP
CONVERTER
(22) 32 VUP
44 (31)
CDELAY
100 nF
52 (34)
7 (3)
RESET
PSEN
ALE
(25) 38
(26) 39
8 (4)
P34
P35
C4
C4
11 (7)
61 (41)
62 (42)
EA
C8
P36/WR
P37/RD
C8
MICROCONTROLLER
80C52
19 to 12
(11 to 8)
ANALOG
DRIVERS
(1)
(17) 27
(16) 26
(23) 36
P00 to P07
CLK
RST
AND
63, 64, 1 to 6
(43, 44, 1, 2)
16-kbyte ROM
256-byte RAM
(2)
SEQUENCER
P20 to P27
58 (38)
59 (39)
60 (40)
53 (35)
54 (36)
P30/RXD
P31/TXD
P33/INT1
P10/T2
V
CC
P11/T2EX
(24) 37
(29) 42
I/O
P40
to P47
INT0
6
8
INTERNAL
OSCILLATOR
PERIPHERALS
PRES
23 (14)
24 (15)
V
I/O
OFF
3 V/5 V
1024
AUX
RAM
T = 0,1
ISO
UART
DDRAM
GNDRAM
CMDVCC
43 (30)
CLKOUT
CLOCK CIRCUITRY
PORT EXTENSION
(3)
10 (6)
9 (5)
XTAL2
48 to 51
MGR225
XTAL1
K0 to K3
Minimum value for capacitor between VDDA and AGND is 2.2 µF.
Pin numbers in parenthesis represent the TDA8006AH.
(1) Ports P04 to P07 not applicable for QFP44 package.
(2) Ports P24 to P27 not applicable for QFP44 package.
(3) Ports K0 to K3 not applicable for QFP44 package.
Fig.1 Block diagram.
4
2000 Feb 21
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
PINNING
PIN
SYMBOL
DESCRIPTION
address 10/general purpose I/O port
QFP64
QFP44
P22
1
1
2
P23
2
address 11/general purpose I/O port
address 12/general purpose I/O port
address 13/general purpose I/O port
address 14/general purpose I/O port
address 15/general purpose I/O port
program store enable output
P24
3
−
P25
4
−
P26
5
−
P27
6
−
PSEN
ALE
XTAL2
XTAL1
EA
7
3
8
4
address latch enable
9
5
crystal connection
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
6
crystal connection or external clock input
external access
7
P07
−
address/data 7/general purpose I/O port
address/data 6/general purpose I/O port
address/data 5/general purpose I/O port
address/data 4/general purpose I/O port
address/data 3/general purpose I/O port
address/data 2/general purpose I/O port
address/data 1/general purpose I/O port
address/data 0/general purpose I/O port
not connected
P06
−
P05
−
P04
−
P03
8
P02
9
P01
10
11
12
13
−
P00
n.c.
n.c.
not connected
n.c.
not connected
VDDRAM
GNDRAM
n.c.
14
15
−
supply voltage for the auxiliary RAM
ground for the auxiliary RAM
not connected
RST
CLK
AGND
S1
16
17
18
19
card reset output (ISO contact C2)
clock output to the card (ISO contact C3)
ground for the analog part
contact 1 for the step-up converter (a ceramic capacitor of 100 nF must be
connected between S1 and S2)
VDDA
S2
30
31
20
21
analog supply voltage for the voltage doubler
contact 2 for the step-up converter (a ceramic capacitor of 100 nF must be
connected between S1 and S2)
VUP
32
22
output of the step-up converter; must be decoupled with a 100 nF ceramic
capacitor
n.c.
n.c.
n.c.
VCC
33
34
35
36
−
−
not connected
not connected
−
not connected
23
card supply output voltage (ISO contact C1)
2000 Feb 21
5
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
PIN
SYMBOL
DESCRIPTION
data line to/from the card (ISO contact C7)
QFP64
QFP44
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
24
25
26
27
28
29
30
31
32
33
−
C4
auxiliary I/O for ISO contact C4 (synchronous cards for example)
auxiliary I/O for ISO contact C8 (synchronous cards for example)
ground
C8
GND
VDD
supply voltage
PRES
CLKOUT
CDELAY
ALARM
TEST
INHIB
K0
card presence contact input (active HIGH or LOW by mask option); see Table 12
output for clocking external devices
external capacitor connection for delayed reset signal
open drain reset output (active HIGH or LOW by mask option); see Table 12
test pin (must be left open-circuit in the application)
test pin (must be left open-circuit in the application)
output port from port extension (±2 mA push-pull)
output port from port extension (±2 mA push-pull)
output port from port extension (±2 mA push-pull)
output port from port extension (±2 mA push-pull)
input for resetting the microcontroller (active HIGH)
general purpose I/O port (connected to P10)
general purpose I/O port (connected to P11)
not connected
−
K1
−
K2
−
K3
−
RESET
P10/T2
P11/T2EX
n.c.
34
35
36
37
−
n.c.
not connected
n.c.
−
not connected
P30/RXD
P31/TXD
P33/INT1
P36/WR
P37/RD
P20
38
39
40
41
42
43
44
general purpose I/O port or serial interface receive line
general purpose I/O port or serial interface transmit line
general purpose I/O port or interrupt (connected to P33)
general purpose I/O port or external data memory write strobe
general purpose I/O port or external data memory read strobe
address 8/general purpose I/O port
P21
address 9/general purpose I/O port
2000 Feb 21
6
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
P22
P23
P24
P25
P26
P27
1
2
3
4
5
6
7
8
9
51
50
49
48
K3
K2
K1
K0
47 INHIB
46 TEST
45 ALARM
44 CDELAY
PSEN
ALE
XTAL2
CLKOUT
43
XTAL1 10
EA 11
TDA8006H
42 PRES
V
41
DD
P07 12
P06 13
P05 14
P04 15
P03 16
P02 17
P01 18
P00 19
40 GND
39 C8
38 C4
37 I/O
V
36
CC
35 n.c.
34 n.c.
33 n.c.
MGR226
Fig.2 Pin configuration (QFP64).
7
2000 Feb 21
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
1
2
3
4
5
6
7
8
9
33 TEST
P22
P23
ALARM
32
31 CDELAY
30 CLKOUT
PSEN
ALE
XTAL2
XTAL1
29 PRES
V
28
DD
TDA8006AH
27 GND
26 C8
25 C4
24 I/O
EA
P03
P02
P01 10
P00 11
V
23
CC
MGR227
Fig.3 Pin configuration (QFP44).
2000 Feb 21
8
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
FUNCTIONAL DESCRIPTION
Microcontroller
Register PCON has an added feature: PCON.5 = RFI
(reduced Radio Frequency Interference bit). When set to
logic 1, pin ALE cannot be toggled. ALE clears on RESET.
The microcontroller is an 80C52 with 16 kbytes of ROM,
256 byte RAM, timers 0, 1, 2 , and 5 I/O ports (port P0:
open-drain; ports P1 to P3: weak pull-up). Port P4 is
identical to 83CE560, except that precharge circuits
ensure fast rise times at end of read mode (transition times
<0.5 µs). The ROM code content can be tested by
signature to avoid reading it out after masking; for security
bit option, see Table 12. The CPU, timers 0 and 1, serial
UART, parallel I/O ports, 256 byte RAM, 16 kbyte ROM
and external bus are conventional C51 family library
elements. Timer 2 is a conventional C52 element
(interrupt enable bit ET2: bit 3 in register IEN1 at byte
address E8H and interrupt priority bit PT2: bit 3 in register
IP1 at byte address F8H.
If access is required to the external data memory via
MOVX instructions (see Table 1), set bit PCON.6 = ARD in
the PCON register to logic 1.
For further information, please refer to the published
specification of the 83CE560 in “Data Handbook IC20;
80C51-Based 8-Bit Microcontrollers”.
Ports P40 to P47, INT0 and P12 to P17 are used internally
for controlling the smart card interface and the other
peripherals. Ports P34 and P35 are used to control the
auxiliary contacts C4 and C8.
The list of differences given in Table 1 may help the
software developer of the dedicated emulation board for
the TDA8006 or other devices.
Table 1 List of differences between TDA8006, CE560, CL580 and C52
FEATURES TDA8006 83CE560
P4 address
CL580
INTEL C52
C0
C0
C1
no
Timer 2
Intel
Philips
64 kbytes
0003H
highest (1st)
000BH
2nd
Intel
Intel
ROM size
16 kbytes
6 kbytes
0003H
highest (1st)
000BH
4th
8 kbytes
0003H
highest (1st)
000BH
2nd
External 0 interrupt vector 0003H
External 0 interrupt priority highest (1st)
Timer 0 interrupt vector
Timer 0 interrupt priority
000BH
2nd
External 1 interrupt vector 0013H
External 1 interrupt priority 3th
0013H
3th
0013H
7th
0013H
3th
Timer 1 interrupt vector
Timer 1 interrupt priority
Serial 0 interrupt vector
Serial 0 interrupt priority
Timer 2 interrupt vector
Timer 2 interrupt priority
I2C-bus
001BH
001BH
4th
001BH
10th
001BH
4th
4th
0023H
0023H
5th
0023H
13th
0023H
5th
5th
004BH
0033H, etc. (8)
miscellaneous
yes
0033H
5th
002BH
lowest (6th)
no
lowest (6th)
no
yes
ADC
no
yes
yes
no
32 kHz oscillator
PWM
no
yes
no
no
no
yes
yes
no
Watchdog
no
yes
yes
no
Interrupts on P1
Additional RAM
no
no
yes
no
1 kbyte peripheral
reset, INT0, INT1
2 kbyte MOVX
no
no
Wake-up from
power-down mode
reset, INT0,
INT1 + other
reset, INT2 to INT8 reset
2000 Feb 21
9
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Table 2 Special function register bit addresses
X = don’t care.
BIT ADDRESS [HEX]
BIT FUNCTION
BYTE
BIT RESET
VALUE
REGISTER ADDRESS
(HEX)
MSB
LSB
IP1
F8
F0
E8
E0
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
[FF]
−
[FE]
−
[FD]
−
[FC]
−
[FB]
PT2
[F3]
−
[FA]
−
[F9]
−
[F8]
−
XXXX 0XXX
0000 0000
0000 0000
0000 0000
0000 0000
B
[F7]
−
[F6]
−
[F5]
−
[F4]
−
[F2]
−
[F1]
−
[F0]
−
IEN1
ACC
PSW
T2CON
P4
[EF]
−
[EE]
−
[ED]
−
[EC]
−
[EB]
ET2
[E3]
−
[EA]
−
[E9]
−
[E8]
−
[E7]
−
[E6]
−
[E5]
−
[E4]
−
[E2]
−
[E1]
−
[E0]
−
[D7]
CY
[CF]
TF2
[C7]
−
[D6]
AC
[CE]
EXF2
[C6]
−
[D5]
F0
[D4]
RS1
[CC]
[D3]
RS0
[CB]
[D2]
OV
[CA]
[D1]
F1
[C9]
[D0]
P
[CD]
[C8]
RCLK TCLK
EXEN2 TR2
C/T2N CP/RL2N 0000 0000
[C5]
−
[C4]
−
[C3]
−
[C2]
−
[C1]
−
[C0]
−
1111 1111
XXX0 0000
1111 1111
0XX0 0000
1111 1111
0000 0000
1111 1111
0000 0000
1111 1111
IP0
[BF]
−
[BE]
−
[BD]
−
[BC]
PS0
[B4]
−
[BB]
PT1
[B3]
−
[BA]
PX1
[B2]
−
[B9]
PT0
[B1]
−
[B8]
PX0
[B0]
−
P3
[B7]
−
[B6]
−
[B5]
−
IEN0
P2
[AF]
EA
[A7]
−
[AE]
−
[AD]
−
[AC]
ES0
[A4]
−
[AB]
ET1
[A3]
−
[AA]
EX1
[A2]
−
[A9]
ET0
[A1]
−
[A8]
EX0
[A0]
−
[A6]
−
[A5]
−
SCON
P1
[9F]
SM0
[97]
−
[9E]
SM1
[96]
−
[9D]
SM2
[95]
−
[9C]
REN
[94]
−
[9B]
TB8
[93]
−
[9A]
RB8
[92]
−
[99]
TI
[98]
RI
[91]
−
[90]
−
TCON
P0
[8F]
TF1
[87]
−
[8E]
TR1
[86]
−
[8D]
TF0
[85]
−
[8C]
TR0
[84]
−
[8B]
IE1
[83]
−
[8A]
IT1
[82]
−
[89]
IE0
[81]
−
[88]
IT0
[80]
−
2000 Feb 21
10
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Table 3 Other register byte addresses
An integrated spike killer ensures the contacts to the card
remain inactive during power-up or power-down.
An internally generated voltage reference is used by the
step-up converter, the voltage supervisor and the VCC
generator.
BYTE
BIT RESET
VALUE
REGISTER
SP
ADDRESS
(HEX)
81
0000 0111
If VDD is too low to ensure proper operation, the voltage
supervisor generates an alarm pulse, whose length is
defined by an external capacitor tied to the CDELAY pin,
(1 ms per 1 nF typical). This pulse is used to reset the
controller and is used in parallel with an external reset
input which can come from the system controller. It is also
used to either block any spurious on-card contacts during
a controller reset or to force an automatic deactivation of
the contacts in the event of supply drop-out (see
Sections “Activation sequence” and “Deactivation
sequence”). It is also fed to an external open-drain output
(called ALARM) which can be chosen active HIGH or LOW
by mask option (see Table 12).
DPL
82
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
XXXX XXXX
0000 0000
0000 0000
0000 0000
0000 0000
DPH
83
PCON
TMOD
TL0
87
89
8A
8B
8C
8D
99
TL1
TH0
TH1
S0BUF
RCAP2L
RCAP2H
TL2
CA
CB
CC
CD
Step-up converter
Except for the VCC generator and the other card contact
buffers, the whole circuit is powered by VDD, VDDA and
TH2
VDDRAM. If the supply voltage is 4.2 V, then a higher
Supply
voltage is needed for the supply to the ISO contacts. When
a card session is requested by the controller, the
sequencer first starts the step-up converter. This uses
switched capacitors which are clocked at a frequency of
approximately 2.5 MHz by an internal oscillator.
The output voltage VUP is regulated at approximately 6 V
and then fed to the VCC generator. VCC and GND are used
as a reference for all other card contacts.
The circuit operates within a supply voltage range of
4.2 to 6 V. The supply pins are VDD, VDDA, GND, AGND,
VDDRAM and GNDRAM. Pins VDDA and AGND supply the
card analog drivers and have to be externally decoupled
because of the large current spikes that the card and the
step-up converter can create. VDDRAM and GNDRAM
supply the auxiliary RAM and should be decoupled
separately. VDD and GND supply the rest of the chip.
V
th(VDD)
V
DD
V
th(CDELAY)
CDELAY
ALARM
MGR228
t
W
Fig.4 Voltage supervisor.
2000 Feb 21
11
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
ISO 7816 security
After resetting EN HIGH, the controller must release the
bus by setting port P4 HIGH again (the transition times on
port P4 are less than 500 ns).
The correct sequence during activation and deactivation of
the card is ensured by a specific sequencer clocked at a
frequency which is a division ratio of the internal oscillator. The interrupt line is reset HIGH when reading out the
status register.
Activation (bit CMDVCC within the ports extension register
HIGH) is only possible if the card is present (pin PRES
HIGH or LOW according to the mask option) and if the
READ OPERATION
supply voltage is correct (ALARM signal inactive).
• Set port P4 to FFH
• Select the register with AD0, AD1, AD2, AD3
• Assert R/W HIGH
The presence of the card is signalled to the controller by
the OFF bit (within the UART status register), generating
an interrupt, if enabled, when toggling.
• Assert EN LOW; the data is available on data bus P4
• Read the data on port P4
During a session, the sequencer performs an automatic
emergency deactivation in the event of card take-off,
supply voltage drop or short circuit. The OFF bit goes
LOW, thereby warning the controller through the interrupt
line INT0 and the status register.
• Set EN HIGH; the bus is set to high impedance.
WRITE OPERATION
• Select the correct register with AD0, AD1, AD2, AD3
• Assert R/W LOW
Peripheral interface (see Figs 5 and 6)
This block allows parallel communication with the four
peripherals (ISO 7816 UART, clock generator, on/off
sequencer and auxiliary RAM) through an 8-bit data bus,
6-bit address and control bus and one interrupt line to the
controller. The data bus consists of ports P40 (data bit 0)
to P47 (data bit 7). The address bus consists of ports AD0
(P12), AD1 (P13), AD2 (P14) and AD3 (P15). The control
lines are R/W (P16) and EN (P17). The interrupt line is
INT0.
• Write data to the data bus port P4
• Assert EN LOW; the data is written to the register
• Set EN HIGH
• Set port P4 to FFH; the bus is set to high impedance.
Integrated precharges allow fast rising edges on port P4
when changing from read mode to write mode, thus
avoiding the need to trigger the active pull-ups on port P4.
During a read operation, EN goes LOW allowing the
controller to read data on the bus. During a write operation,
the data should be present on the bus before asserting EN
LOW which allows the data to be written to the registers.
P4
XX
FF
DATA
FF
DATA
FF
R/W
AD0 to AD3
EN
X
AD
AD
read data cycle
write data cycle
MGR229
Fig.5 Use of peripheral interface.
12
2000 Feb 21
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8
8
P00/P07
P20/P27
PSEN
ALE
EA
P37/RD P36/WR
P30/RXD P31/TXD
P10/T2 P11/T2EX
P33/INT1
RESET
OSC
P32/INT0
80C52 CORE
P17 P34 P35 P16
P40 to P47
P15 P14 P13 P12
databus
8
control bus
TRANSMIT REGISTER
RECEIVE REGISTER
PERIPHERAL EXTENSION REGISTER
CLOCK CONFIGURATION REGISTER
PROGRAMMABLE DIVIDER
CLOCK GENERATOR
LOW ADDRESS REGISTER
ON/OFF SEQUENCER
HIGH ADDRESS REGISTER
MEMORY READ REGISTER
MEMORY WRITE REGISTER
AUXILIARY RAM
STATUS REGISTER
MICRO CLOCK
SYNCHRONOUS IN REGISTER
SYNCHRONOUS OUT REGISTER
GUARD TIME REGISTER
CONFIGURATION REGISTER
ISO 7816 UART
UART CARD EXTERNAL
CLOCK CLOCK CLOCK
XTAL
MGR230
I/O
C4
C8
K0 K1 K2 K3
RST DET ERR POR
CLK
CLKOUT OSCINT XTAL1
CMDVCC
INTERFACE, SECURITY AND POWER CONTROL
Fig.6 Peripheral interface.
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Table 4 Register addresses
X = don’t care.
AD3
AD2
AD1
AD0
R/W
REGISTER
PERIPHERAL
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
X
X
X
X
0
0
0
1
0
1
1
0
0
0
0
0
0
1
CCR (Clock Configuration Register)
PDR (Programmable Divider Register)
SOR (Synchronous Output Register)
SIR (Synchronous Input Register)
UTR (UART Transmit Register)
URR (UART Receive Register)
USR (UART Status Register)
clock generator
ISO 7816 UART
UCR (UART Configuration Register)
GTR (Guard Time Register)
PER (Ports Extension Register)
MAR0 (Memory Address LOW)
MAR1 (Memory Address HIGH)
MWR (Memory Write Register)
MRR (Memory Read Register)
on/off sequencer
auxiliary RAM
Clock circuit
To achieve the different I/O baud rates as defined by
values F and D (see Table 7), the clock signal is counted
by an auto-reload 8-bit programmable counter and then
divided by a 31 or 32 prescaler.
The microcontroller clock (OSC), the card clock (CLK), the
ISO 7816 UART clock, and the clock to the external world
(CLKOUT), are derived from the main clock signals (XTAL
from 4 to 20 MHz, or an external clock signal applied to
XTAL1), or the internal oscillator (fINT).
All these configurations are controlled by the clock
configuration register and by the programmable divider
register.
• Microcontroller clock (OSC): after power-on or reset, the
microcontroller is clocked at 1⁄8fINT. Then, the application
may decide to clock it at 1⁄2fINT, 1⁄2fxtal or fxtal
.
All frequency changes are synchronous, thereby
ensuring no hang-up due to short spikes etc.
• Card clock (CLK): the application may send a clock
frequency of 1⁄2fxtal, 1⁄4fxtal, 1⁄8fxtal or 1⁄2fINT (≈1.25 MHz),
or may stop the clock at HIGH or LOW. All transitions
are synchronous, ensuring correct pulse length during
start or change, in accordance with ISO 7816. After
power-on or reset, CLK is held LOW.
• External clock output (CLKOUT): CLKOUT is a
permanent clock output for external use. The following
frequencies are possible: fxtal, 1⁄2fxtal and 1⁄4fxtal
.
All transitions are synchronous. After power-on or reset,
CLKOUT is fixed at 1⁄4fxtal
.
• ISO 7816 UART clock: the clock to the ISO 7816 UART
is identical to the clock to the card (CLK).
2000 Feb 21
14
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Table 5 Clock Configuration Register (CCR; address 0; write only; all bits cleared after reset)
X = don’t care.
UART
PRESCALER
D7 D6 D5 D4 D3 D2 D1 D0
CLK
CLKOUT
OSC
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
0
X
X
0
X
X
0
0
1
÷31
÷32
X
X
X
X
X
X
X
X
X
X
X
X
X
STOP LOW
1⁄2fxtal
1⁄4fxtal
1⁄8fxtal
1⁄2fINT
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
STOP HIGH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1⁄4fxtal
0
1
fxtal
1⁄2fxtal
1
0
X
X
X
X
X
X
X
X
1⁄8fINT
fxtal
1⁄2fxtal
1⁄2fINT
0
1
1
0
1
1
The hexadecimal value stored in the Programmable
Divider Register (PDR) is the auto-reload value of an 8-bit
counter clocked by the card clock (CLK); when the value is
loaded in the counter, it counts from this value till overflow;
then it is reloaded with the same value and the count
restarts. The output of the counter is then divided by
31 or 32 depending on the programmed value of the
UART prescaler. The result is the ISO 7816 UART CLK
which is used for shifting the data in or out on the I/O line.
The example shown in Fig.7 shows how to program a
division factor of 372. With these registers, the baud rates
given in Table 7 are achieved according to ISO 7816.
The division ratio of 31 or 32 depends on which prescaler
is selected, and the hexadecimal value is the value
programmed within the PDR.
Table 6 Programmable Divider Register (PDR; address 1; write only; all bits cleared after reset)
D7 D6 D5 D4 D3 D2 D1 D0
DIVISION FACTOR
n7
n6
n5
n4
n3
n2
n1
n0
n7n6n5n4 n3n2n1n0(1)
Note
1. A division factor of F4H, for example, would be 1111 0100 reading from D7 to D0.
2000 Feb 21
15
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
÷31
÷32
ISO 7816
UART CLK
8-BIT AUTO-RELOAD COUNTER
WITH PDR = F4H
CLK
MGR231
Fig.7 Baud rate selection on I/O.
Table 7 Selecting baud rate using F and D values
Baud rate is selected by values D and F shown in parenthesis. The PDR is loaded with a value shown in Hexadecimal,
and either prescaler 31 or 32 is selected.
PDR VALUE
PRESCALER ÷31
PRESCALER ÷32
[VALUE D]
[VALUE F]
[VALUE F]
[0000] [0001] [0010] [0011] [0100] [0101] [0110] [1001] [1010] [1011] [1100] [1101]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[1000]
[1001]
F4
FA
FD
−
F4
FA
FD
−
EE
F7
−
E8
F4
FA
FD
−
DC
EE
F7
−
D0
E8
F4
FA
FD
−
C4
E2
F1
−
F0
F8
FC
FE
FF
−
E8
F4
FA
FD
−
E0
F0
F8
FC
FE
FF
−
D0
E8
F4
FA
FD
−
C0
E0
F0
F8
FC
FE
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FF
−
FF
−
−
FE
−
FD
−
FC
−
FB
FD
−
FE
−
FC
−
−
−
−
−
2000 Feb 21
16
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
On/off controller
Table 8 On/off controller bits (PER; address 7; write only; all bits cleared after reset)
BIT
D0
NAME
DESCRIPTION
CMDVCC; set and reset by software
set to 1 for starting activation sequence of the card, and reset
to 0 for starting deactivation
D1
D2
RSTIN; set and reset by software
control line RST for card contact C2 in manual mode (active
HIGH)
Force Inverse Parity (FIP); set and reset by when LOW, the UART processes the parity according to
software
ISO 7816; when HIGH, the UART processes the inverse parity
(which causes parity errors during transmission and ‘not
acknowledge’ signals during reception)
D3
automatic ATR processing enabling
(ATREN); set by software, reset by
hardware
when HIGH, the UART automatically counts the clock pulses
during ATR and controls the RST contact; this bit is
automatically reset by hardware when a start bit is detected
on I/O or when the card is declared as mute; when LOW, this
automatic processing is disabled (manual mode)
D4
D5
D6
D7
K0; set and reset by software
K1; set and reset by software
K2; set and reset by software
K3; set and reset by software
auxiliary ±2 mA push-pull output control (inverted output)
auxiliary ±2 mA push-pull output control (inverted output)
auxiliary ±2 mA push-pull output control (inverted output)
auxiliary ±2 mA push-pull output control (inverted output)
The on/off controller is used for activating or deactivating
the card, for controlling contact C2 (RST) manually
through RSTIN or automatically, for forcing inverse parity
(for flow control or test purposes), and for controlling four
independent push-pull output lines K0 to K3.
ISO 7816 UART
The ISO 7816 UART handles all specific requirements
defined in ISO 7816 T = 0 and T = 1 protocol types. It is
also able to deal with synchronous cards (in conjunction
with contacts C4 and C8). In addition, there is a possibility
to force parity errors for test purposes or flow control.
The counting of CLK cycles during ATR is possible by
either hardware or software.
After having cleared the ISO 7816 UART reset bit (see
UART configuration register) and checking the card
presence within the status register, the software may
initiate an activation sequence by setting bit CMDVCC
HIGH. It may also initiate a deactivation sequence by
resetting this bit (see activation and deactivation
sequences).
The ISO 7816 UART is configured with 2 registers: UART
Configuration Register (UCR) and Guard Time Register
(GTR).
When timings are given in terms of ETU (Elementary Time
Unit as defined by ISO 7816), then the reference is the
negative edge of the start bit of the character being
received or transmitted, unless otherwise specified.
The timings during the ATR may be checked either
manually (using RSTIN and t3/t5 for counting clock pulses)
or automatically by setting bit ATREN HIGH (see Section
“Activation sequence”). In this case, hardware controls
both RST and the counting of CLK pulses. Bit ATREN is
reset by hardware when a start bit has been detected
before 2 × 40100 CLK pulses for versions C2 and C3
(2 × 45000 CLK pulses for version C1), or when the card
is declared as ‘mute’. Setting this bit HIGH again during a
session initiates a warm reset.
A warm reset may also be done manually by using RSTIN
and t3/t5 again.
2000 Feb 21
17
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Table 9 UART Configuration Register (UCR; address 5; write only; all bits cleared after reset)
BIT
NAME
DESCRIPTION
D0 Reset ISO 7816 UART (RIUN); set by
software, reset by software
when LOW, this bit resets the UART; must be set by software
before any use of the UART
D1 Start Session (SS); set by software, reset by
software
when HIGH, this bit allows the detection of the convention
during the initial character of the card; must be reset by
software after correct reception of the first character and before
complete reception of the next character
D2 Last Character to Transmit (LCT); set by
software, reset by hardware or software
when HIGH, this bit allows automatic toggling from transmission
to reception mode after successful transmission of the last
character; in this case, TRN is also reset by hardware
D3 Transmit/Receive-N (TRN); set by software,
reset by software or hardware
when LOW, the UART is in reception mode; when HIGH, it is in
transmission mode; INT goes LOW when TRN is set
D4 not used
D5 Protocol Selection (PS); set by software, reset when LOW, the UART is in T = 0 mode; when HIGH, the UART
by software
is in T = 1 mode
D6 3 V/5 V-N (TFN); set by software, reset by
software
when LOW, the card supply voltage VCC = 5 V; when HIGH,
VCC = 3 V
D7 Synchrone/asynchrone-N (SAN); set by
software, reset by software
when HIGH, this bit allows direct monitoring of I/O by bit D0 of
SIR or SOR; when LOW, I/O is fed to the ISO 7816 UART
RECEPTION
For the next characters, bit RBF is set at 10.5 ETU and an
interrupt is generated, if enabled, to indicate that a
character has been received, with or without parity error,
and that this character may be read within the reception
register. The interrupt is cleared on the falling edge of EN
during the read operation of the received character.
In order to start a session with the card, bit RIUN (which
resets the ISO 7816 UART when LOW) must be set HIGH.
The UART recognizes the convention (direct or inverse) of
the characters received while bit SS (Start Session) is
HIGH. Then the UART automatically converts any
transmitted or received character according to this
convention, so the software only has to deal with
characters written in direct convention. Indeed, bit SS
must be reset by software after correct receipt of the first
character of the ATR (TS) and before complete receipt of
the next character.
In protocol type T = 0 (bit PS LOW), the I/O line is
automatically pulled LOW between 10.5 and 11.75 ETU if
a character parity error is detected (parity error handling at
character level).
In protocol type T = 1 (bit PS HIGH), if a parity error is
detected, bit PE is set in the status register, but the I/O line
is not pulled LOW.
Reception mode is selected when TRN is LOW. Bit FSD is
set within the UART Status Register (USR), and an
interrupt is generated, if enabled, at the start bit of the
received character when SS is HIGH, allowing the manual
CLK count during ATR. The interrupt will be cleared on the
rising edge of EN during the status read operation.
2000 Feb 21
18
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
RIU
SS
CMDVCC
R/W
P4
FF
FF
FF
FF
FF
EN
I/O
INT
FSD
RBF
10.5 ETU
release reset
set CMDVCC
first start
read status
int cleared
buffer full
anything
read status
set start session
read character
and int cleared
reset start session
MGR232
Fig.8 First character reception.
TRANSMISSION
character (see Section “Extra guard time”). If the parity is
not correct, then assuming that a character has been
written to the UTR, the transmission starts at 13 ETU (the
guard time GT must be programmed before transmitting).
Transmission mode is selected when TRN is HIGH.
If enabled, an interrupt occurs on the rising edge of TRN,
indicating that the transmission buffer is empty and ready
to accept a character for transmission. The interrupt is
cleared during the read status operation. The character is
written to the UTR on the falling edge of EN during the
write operation, and starts to be transmitted on the rising
edge of EN.
Bit LCT can be used for cards that are required to change
from transmission to reception mode very fast. If LCT is set
HIGH, then the UART automatically resets
bits TRN and LCT at 10.85 ETU if no parity error has
occurred; the UART is ready to receive a character from
the card at 12 ETU (T = 0) or 11 ETU (T = 1) after the
previous start bit. If a parity error has occurred during
transmission of the last character, then the UART stays in
transmission mode with LCT set, waiting for the software
to rewrite the corrupted character.
The I/O line is read at 10.84 ETU to check if the card has
detected a parity error. At the same time, bit TBE is set in
the USR, and, if enabled, an interrupt occurs to indicate
that the transmission buffer is empty, and that a new
character may be written. If the parity is correct, the
transmission of the next character will start at
12 ETU + GT + 0.5 ETU after the start bit of the previous
2000 Feb 21
19
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
R/W
P4
FF
FF
FF
FF
FF
EN
TRN
LCT
TBE
INT
I/O
anything
start transmit
buffer empty
set LCT
anything
buffer empty
read status
read status
int cleared
start transmit
start receive
TRN/LCT reset
int cleared
write character
transmission
write character
MGR233
Fig.9 Character transmission with or without LCT.
SYNCHRONOUS CARDS
Synchronous Input Register (SIR; address 3; read only)
If bit SAN (Synchronous/Asynchronous-N) is set, the
software can operate with synchronous cards; the
information available on the I/O line is copied on data bit 0
of the data bus without entering the UART when either
registers SIR or SOR are selected. At the end of a
transmission in synchronous mode, it is necessary to
switch back to synchronous reception mode by reading
register SIR.
When this register is selected, I/O is copied on data bit 0
(P40) and may be read by the controller.
Synchronous Output Register (SOR; address 3; write
only)
When this register is selected, I/O is copied on data bit 0
(P40) on the falling edge of EN.
The synchronous clock may be controlled by selecting
CLK STOP HIGH or STOP LOW. Contacts C4 and C8
may be controlled by ports P34 and P35 (operation
depends on synchronous card type).
2000 Feb 21
20
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
R/W
P4
P40
CLK
FF
FF
EN
I/O
read
write
MGR234
Fig.10 Using synchronous cards.
EXTRA GUARD TIME
A GT of FFH has a special status which means 0 ETU
when the protocol is T = 0 and −1 ETU when the protocol
is T = 1 (reception and transmission is possible at
11 ETU).
Between the transmission of two characters to the card,
the ISO 7816 UART automatically inserts a number of
guard ETUs equal to the value, called GT, stored in the
GTR, see Table 10. For a GT of FAH, for example, the
value would be 1111 1010 reading from D7 to D0.
Table 10 Guard Time Register (GTR; address 6; write only; all bits cleared after reset)
D7
D6
D5
D4
D3
D2
D1
D0
GUARD TIME VALUE (GT)
n7
n6
n5
n4
n3
n2
n1
n0
n7n6n5n4 n3n2n1n0
UART receive and transmit registers
start bit. This overwrites the previous character which
should have been read by the controller.
UART Receive Register (URR; address 4; read only; all
bits cleared after reset)
• The UART checks the parity of the received characters;
if the parity is wrong, then bit PE is set in the status
register at the same time as bit RBF (Receive Buffer
Full).
D7 to D0 are the data bits received from the card.
Because the UART automatically converts the characters
according to the convention recognized during TS, all
characters in the URR are in direct convention.
• In protocol T = 0, I/O is pulled LOW between
10.5 and 11.75 ETU in case of error. Characters may be
received from the card every 12 ETU, even after a
transmission (see LCT; Table 9). In protocol T = 1,
reception is possible at 11 ETU.
• The received character is loaded in the URR 0.5 ETU
after the parity shift, i.e. 10.5 ETU after the edge of the
2000 Feb 21
21
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
UART Transmit Register (UTR; address 4; write only;
all bits cleared after reset)
STATUS REGISTER AND INTERRUPTS
The ISO 7816 UART reports its activity to the
microcontroller through the UART status register, which
acts upon the interrupt line INT.
Bits D7 to D0 are the data bits to be transmitted to the
card. Due to the automatic conversion performed by the
UART according to the convention detected during TS, the
controller must write the characters to send to the card in
direct convention. The character to be sent may be written
to the UTR as soon as bit TBE (Transmit Buffer Empty) is
set in the status register.
All bits except for D5 generate an interrupt on INT, if
enabled, when they are set. D0, D2, D3, D4, D6 and D7
are cleared on the rising edge of EN after a read operation
of the USR. D1 is cleared when the data in the reception
buffer has been read-out. D5 may be used to check the
card’s presence and also to determine the reason for an
emergency deactivation during a card’s session. In case of
Early Answer (EA) or Mute Card (MC) during automatic
ATR processing, the card is not automatically deactivated.
If enabled, an interrupt is generated, and the controller
then decides to deactivate or not.
If writing to the UCR occurs after 12.5 ETU + GT after the
previous start bit, then the transmission starts on the rising
edge of EN during the write operation. If writing to the UCR
occurs before 12.5 ETU + GT after the previous start bit,
the UART waits until 12.5 ETU + GT after the previous
start bit before starting the transmission.
In protocol T = 0, if a parity error is signalled by the card,
the previous character must be rewritten to the UTR.
The UART will then wait 13 ETU after the start bit of the
previous character before restarting the transmission.
Table 11 UART Status Register (USR; address 5; read only; all bits cleared after reset except for D5)
BIT
NAME
DESCRIPTION
D0 TX Buffer Empty (TBE)
this bit is set when the UART has finished transmitting the data written in
the UTR (at 10.8 ETU) or on the rising edge of TRN; it is reset on the rising
edge of EN during a read status operation
D1 RX Buffer Full (RBF)
this bit is set when the UART has finished receiving a character from the card
(at 10.5 ETU); it is reset on the falling edge of EN during the read status
operation
D2 First Start Detect (FSD)
D3 Parity Error (PE)
this bit is set on the falling edge of the first start bit if SS = 1; it is reset on the
rising edge of EN during a read status operation
this bit is set when a parity error has been detected by the UART in
transmission or in reception mode at the same time as TBE and RBF; it is
reset on the rising edge of EN during a read status operation
D4 Early Answer (EA)
D5 OFF
this bit is set if a start bit has been detected on I/O between the 200 and 400
first CLK pulses when the UART is configured in automatic ATR processing; it
is reset on the rising edge of EN during a read status operation
this bit is set if the card is present and reset if the card is not present;
if CMDVCC is set HIGH, it may also be reset if a hardware problem causing
an emergency deactivation sequence has occurred
D6 Off Interrupt (OFFI)
D7 Mute Card (MC)
this bit is set when OFF state has changed; it is reset on the rising edge of EN
during a read status operation
this bit is set if a card has not answered after 80200 CLK pulses for versions
C2 and C3 (90000 for version C1), when the ISO 7816 UART is configured in
automatic ATR processing; it is reset on the rising edge of EN during a read
status operation
2000 Feb 21
22
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Auxiliary RAM (MAR0, address C or D, write only;
MAR1, address E or F, write only; MRR, MWR,
address 8 or 9, read/write; all bits cleared after reset)
Activation sequence
When the card is inactive, pins VCC, CLK, RST and I/O are
LOW, having low impedance with respect to GND.
The step-up converter is stopped. The I/O is configured in
reception mode with a high impedance path to the
ISO 7816 UART. Any spurious pulses from the card during
power-up will have no effect until I/O is enabled. When
requirements are fulfilled (correct voltage supply, card
present, no hardware problems), the microcontroller may
initiate an activation sequence by setting bit CMDVCC
HIGH (t0).
In order to store data, 1 kbyte of auxiliary RAM may be
accessed through the peripheral interface. The content of
the RAM is undefined after reset. Note that only AD3,
AD2 and AD1 must be programmed for addressing the
RAM register, allowing faster operations if needed.
There are two methods to address this memory:
• Random method: the low order address is written in
MAR0, and the high order address is written in MAR1.
A write operation to MWR will write the data at the
preselected address on the falling edge of EN, and a
read operation to MRR will load to port P4 the data that
is stored at the preselected address on the falling edge
of EN.
• The step-up converter starts (t1)
• VCC starts rising from 0 to 5 V or to 3 V with a controlled
rise time of typically 0.16 V/µs (t2)
• I/O, contacts C4 and C8 buffers are enabled (t3);
integrated pull-up resistors of 10 kΩ are connected to
VCC
• Sequential method: once low order and high order
addresses are written in MAR0 and MAR1, every read
or write operation to MRR or MWR will increment the
address that is stored in MAR0 and MAR1. Thus it is
possible to read or write data strings within the auxiliary
RAM without rewriting the addresses between 2 data
bytes. The auto-increment feature is operational on the
whole length of the RAM. In case of overflow, the count
starts again at address 00H.
• CLK is sent to the card (t4)
• RST buffer is enabled (t5).
In order to allow a precise count of clock pulses during
ATR in manual mode, a defined time window (t3/t5) is
opened where the clock may be sent to the card using
RSTIN. Beyond this window, RSTIN does not respond to a
clock pulse, and only monitors the card’s RST contact.
In automatic mode (ATREN set HIGH), RST is monitored
by the TDA8006, RSTIN is inactive and CLK is output by
the TDA8006 at t3. RST is LOW. If the card has not
responded within the period of 40100 CLK pulses for
versions C2 and C3 (45000 for version C1), RST is set
HIGH for a maximum of 40100 CLK pulses for versions
C2 and C3 (45000 for version C1).
Output Ports Extension Register (PER, address 7,
write only; all bits cleared after reset)
In this register, the four low order bits control the activation
of the card. The four high order bits D4, D5, D6 and D7
each control auxiliary ±2 mA push-pull output ports, which
can be used for any purpose (LEDs, control signals, etc.).
The electrical state of a port is HIGH if the bit is LOW, and
LOW if the bit is HIGH. The bits are cleared after reset
making the ports HIGH.
It is also possible to customize the activation sequence by
keeping CLK STOP LOW with RSTIN LOW beyond t5, and
then output CLK using the CLK configuration.
The sequencer is clocked by 1⁄64fINT which gives a time
interval T of typically 25 µs. Thus t1 = 0 to 1⁄64T, t2 = t1 + T,
t3 = t1 + 4T, t4 = t3 to t5 and t5 = t1 + 7T.
2000 Feb 21
23
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
CMDVCC
VUP
V
CC
I/O
RSTIN
CLK
RST
t
t
t
t
t
t
(= t
)
act
ATR
0 1
2
3
4
5
MGR235
Fig.11 Manual activation sequence using t3/t5.
CMDVCC
ATREN
VUP
V
CC
I/O
CLK
RST
t
t
t
t
t
(= t
)
act
note1
ATR
0
1
2
3
5
MGR236
(1) CLK = 45000 for version C1 or 40100 for versions C2 and C3.
Fig.12 Automatic activation sequence.
2000 Feb 21
24
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Deactivation sequence
t11 = t10 + 1⁄64T, t12 = t11 + 1⁄2T, t13 = t11 + T,
t14 = t11 + 3⁄2T, t15 = t11 + 5T.
When the session has completed, the microcontroller sets
CMDVCC LOW (t10). The circuit then executes an
automatic deactivation sequence:
tde is the time that VCC requires to fall to less than 0.3 V.
• Card reset (RST goes LOW) (t11)
• Clock is stopped (t12)
• I/O goes LOW (t13)
• VCC falls to 0 V with typically 0.16 V/µs slew rate (t14)
• The step-up converter is stopped and CLK, RST, VCC
and I/O become low impedance to GND (t15).
CMDVCC
RST
CLK
I/O
V
CC
VUP
MGR237
t
t
t
t
t
t
10
11
12
13
14
15
t
de
Fig.13 Deactivation sequence.
Protection
When one of these problems is detected, the security logic
block sets the OFF bit LOW which generates an interrupt
warning the microcontroller and initiates an automatic
deactivation of the contacts.
The main hardware fault conditions monitored by the
circuit are:
• Overcurrent on VCC
When the deactivation has completed and CMDVCC has
been set LOW, the OFF bit goes HIGH, unless the problem
was caused by a card extraction, in which case it remains
LOW until a card is inserted.
• Short circuits between VCC and other contacts
• Card take-off during transaction.
2000 Feb 21
25
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
CMDVCC
OFF
RST
CLK
I/O
V
CC
MGR238
Fig.14 Emergency deactivation sequence after VCC short circuited to ground.
Auxiliary contacts C4 and C8
After a delay of approximately 200 ns (td), the N transistor
on the slave side is turned on which transmits the ‘0’
present on the master side. When the master side goes
back to logic 1, the P transistor on the slave side is turned
on during td, and then both sides return to their idle states.
The auxiliary contacts C4 and C8 are controlled by ports
P34 and P35 through two identical pseudo-bidirectional
I/O lines.
In the Idle state, port P34 is pulled HIGH to VDD by an
integrated 20 kΩ resistor and C4 is pulled HIGH to VCC by
an integrated 10 kΩ resistor. This allows operation with a
VCC value of 3 V and a VDD value of 5 V. The first side on
which a falling edge occurs becomes the master.
An anti-latch circuit disables the detection of a falling edge
on the other side, which becomes the slave.
The maximum frequency on the I/O lines is 1 MHz.
2000 Feb 21
26
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
+6.5
UNIT
VDDA
VDDD
Vn1
V
V
digital supply voltage
−0.5
−0.5
−0.5
−5
all input voltages except S1, S2 and VUP
voltage on pins S1, S2 and VUP
VDD + 0.5 V
Vn2
+7.5
+5
V
In1
DC current into XTAL1, XTAL2, P30/RXD,
P31/TXD, RESET, P33/INT1, P36/WR,
P37/RD, P00 to P07, P20 to P27, P10/T2,
P11/T2EX, EA, ALE, PSEN, CDELAY, PRES,
INHIB, CLKOUT and TEST
mA
In3
In6
In7
DC current from or to pins S1, S2 and VUP
DC current from or to K0 to K3
−200
−5
+200
+5
mA
mA
mA
DC current from or into pin ALARM
(according to option choice)
see Table 12
−5
+5
Ptot
total power dissipation
QFP44
Tamb = −20 to +85 °C
−
400
500
+150
140
+6
mW
mW
°C
QFP64
−
Tstg
Tj
storage temperature
junction temperature
electrostatic discharge
−55
−
°C
Vesd
on pins I/O, VCC
RST, CLK, C4, C8
and PRES
−6
kV
on other pins
−2
+2
kV
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
QFP64
QFP44
51
64
K/W
K/W
2000 Feb 21
27
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
CHARACTERISTICS
VDD = 5 V; VSS = 0 V; Tamb = 25 °C; for general purpose I/O ports refer to 80CE560 data sheet; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
digital supply voltage
4.2
−
−
−
6.0
V
VDDD
4.2
6.0
V
IDD(pd)
supply current in power-down VDD = 5 V; card inactive; note 1
mode
−
250
µA
IDD(sm)
supply current in sleep mode
card powered, microcontroller in
power-down mode but with clock
stopped; note 1
−
−
−
1500
180
µA
IDD(om)
supply current operating mode ICC = 65 mA; fxtal = 20 MHz;
fclk = 10 MHz; fosc = 20 MHz;
130
mA
fCLKOUT = 20 MHz; 5 V card;
notes 1 and 2
ICC = 65 mA; fxtal = 20 MHz;
65
1
−
−
−
−
90
6
mA
mA
mA
V
fclk = 10 MHz; fosc = 20 MHz;
fCLKOUT = 20 MHz; 3 V card;
notes 1 and 2
unloaded; fxtal = 20 MHz;
fclk = 5 MHz; fosc = 10 MHz;
fCLKOUT = 5 MHz; 5 V card;
notes 1 and 2
unloaded; fxtal = 20 MHz;
fclk = 5 MHz; fosc = 10 MHz;
fCLKOUT = 5 MHz; 3 V card;
notes 1 and 2
0.5
3.6
4
Vth(VDD)
threshold voltage on VDD
(falling)
3.95
Vhys(VthVDD) hysteresis on Vth(VDD)
50
−
250
mV
V
Vth(CDELAY) threshold voltage on
pin CDELAY
−
1.38
−
VCDELAY
ICDELAY
voltage on pin CDELAY
output current at pin CDELAY pin grounded (charge)
CDELAY = VDD (discharge)
CCDELAY = 10 nF
−
−
−
−
−
VDD
−
V
−1
2
µA
mA
ms
V
−
tW
ALARM pulse width
10
−
ALARM (open drain active HIGH or LOW output)
IOH
VOL
IOL
HIGH-level output current
LOW-level output voltage
LOW-level output current
HIGH-level output voltage
active LOW option; VOH = 5 V
active LOW option; IOL = 2 mA
active HIGH option; VOL = 0 V
active HIGH option; IOH = −2 mA
−
−
−
−
−
10
µA
V
−0.3
−
+0.4
−10
µA
V
VOH
V
DD − 0.8
VDD + 0.3
2000 Feb 21
28
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal oscillator
fxtal
fext
crystal frequency
4
0
−
−
25
25
MHz
MHz
frequency of external signal
applied on pin XTAL1
CLKOUT
fCLKOUT
VOL
VOH
to(r)
frequency on pin CLKOUT
LOW-level output voltage
HIGH-level output voltage
output rise time
0
−
V
−
−
−
−
−
−
−
−
25
MHz
V
IOL = 5 mA
0.8
−
IOH = −5 mA
CL = 60 pF
CL = 60 pF
CL = 60 pF
DD − 1
V
10
10
60
ns
ns
%
to(f)
output fall time
δ
duty factor
40
Step-up converter
fINT
internal oscillation frequency
voltage on pin VUP
2
2.5
6.5
3
MHz
V
VVUP
−
−
Reset output to the card (pin RST)
Vo(RST)
output voltage
inactive mode; no load
inactive mode; Io(RST) = 1 mA
when inactive and pin grounded
IOL = 200 µA
0
0
0
0
−
−
−
−
−
−
−
0.1
0.3
−1
V
V
Io(RST)
VOL
VOH
tr
output current
mA
V
LOW-level output voltage
HIGH-level output voltage
rise time
0.3
VCC
0.1
0.1
IOH = −200 µA
V
−
−
CC − 0.7
V
CL = 30 pF
µs
µs
tf
fall time
CL = 30 pF
Clock output to the card (pin CLK)
Vo(CLK)
output voltage
inactive mode; no load
inactive mode; Io(CLK) = 1 mA
when inactive and pin grounded
IOL = 200 µA
0
0
0
0
V
−
−
1
0
−
−
−
−
−
−
−
0.1
0.3
−1
0.3
VCC
8
V
V
Io(CLK)
VOL
VOH
tr
output current
mA
V
LOW-level output voltage
HIGH-level output voltage
rise time
IOH = −200 µA
CC − 0.5
V
CL = 30 pF
ns
tf
fall time
CL = 30 pF
8
ns
fCLK
clock frequency
1.25 MHz idle configuration
operational
1.25 1.5
MHz
MHz
%
−
−
−
10
55
−
δ
duty factor
CL = 30 pF
45
SR
slew rate (rise and fall)
CL = 30 pF
0.2
V/ns
2000 Feb 21
29
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
SYMBOL
Card supply voltage (pin VCC); note 3
VO(VCC) card supply output voltage
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
inactive
no load
O(VCC) = 1 mA
pin grounded
active
CC < 65 mA; 5 V card
CC < 65 mA; 3 V card
0
0
0
−
−
−
0.1
V
I
0.3
V
−1
mA
I
4.75
2.8
5
3
−
5.25
3.2
V
V
V
I
current pulses of 40 nAs with 4.6
CC < 200 mA; t < 400 ns;
5.4
I
f < 20 MHz; 5 V card
current pulses of 24 nAs with 2.75
−
3.25
V
ICC < 200 mA; t < 400 ns;
f < 20 MHz; 3 V card
IO(VCC)
card supply output current
from 0 to 3 or 5 V
−
−
65
250
−
mA
mA
mA
V/µs
VCC short circuited to GND
−
−
ICC(sd)
SR
shutdown current at pin VCC
slew rate
−
−80
up or down
0.10
0.16 0.22
(capacitor = 100 to 300 nF)
Data line (pin I/O); note 4
Vo(I/O)
output voltage
inactive
no load
0
−
0
0
−
−
−
−
0.1
0.3
−1
V
I
o(I/O) = 1 mA
V
Io(I/O)
VOL
output current
inactive and pin grounded
I/O configured as output;
mA
V
LOW-level output voltage
0.3
IOL = 1 mA
VOH
HIGH-level output voltage
I/O configured as output;
0.8VCC
−
VCC + 0.25 V
IOH < −50 µA
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
I/O configured as input
I/O configured as input
VIL = 0 V
−0.3
1.5
−
−
−
−
−
+0.8
VCC
−600
20
V
V
µA
µA
ILIH
HIGH-level input leakage
current
VIH = VCC
−
ti(r)
input rise time
input fall time
output rise time
output fall time
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
−
−
−
−
8
−
1
µs
µs
µs
µs
kΩ
ti(f)
−
1
to(r)
−
0.1
0.1
13
to(f)
−
Rpu(int)
internal pull-up resistance
between I/O and VCC
10
2000 Feb 21
30
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Auxiliary card contacts (C4 and C8); note 5
Vo(C4,C8)
output voltage
inactive
no load
o(C4,C8) = 1 mA
0
−
−
0
−
−
−
−
0.1
V
I
0.3
−1
V
Io(C4,C8)
VOL
output current
inactive and pin grounded
mA
V
LOW-level output voltage
C4 or C8 configured as output;
IOL = 1 mA
0.3
VOH
HIGH-level output voltage
C4 or C8 and I/O configured as 0.8VCC
−
VCC + 0.25 V
output; IOH < −50 µA
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
C4 or C8 configured as input
C4 or C8 configured as input
VIL = 0 V
−0.3
1.5
−
−
−
−
−
+0.8
VCC
−600
20
V
V
µA
µA
ILIH
HIGH-level input leakage
current
VIH = VCC
−
ti(r)
ti(f)
to(r)
to(f)
td
input rise time
input fall time
output rise time
output fall time
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
−
−
−
−
−
−
−
−
−
−
1
µs
µs
µs
µs
ns
1
0.1
0.1
200
delay between falling edge on
P34 and C4 (or C4 and P34)
Rpu(int)
internal pull-up resistance
between C4 and VCC and
C8 and VCC
8
10
13
1
kΩ
f(max)
maximum frequency on
C4 or C8
−
−
MHz
Timing
tact
tde
activation sequence duration
−
−
−
−
225
100
µs
µs
deactivation sequence
duration
t3(start)
t5(end)
start of the window for sending
clock to the card
−
−
−
130
µs
µs
end of the window for sending
clock to the card
145
−
Output ports from extension (K0 to K3)
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 2 mA
−
−
−
0.4
V
V
IOH = −2 mA
V
DD − 1
−
2000 Feb 21
31
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Card presence input (pin PRES)
VIL
VIH
ILIL
LOW-level input voltage
HIGH-level input voltage
−
−
−
−
0.3VDD
V
0.7VDD
−
V
LOW-level input leakage
current
Vi = 0 V
Vi = VDD
−
20
µA
ILIH
HIGH-level input leakage
current
−
−
20
µA
Notes
1. IDD in all configurations include the current at pins VDD, VDDA and VDDRAM
.
2. Values given for program executed from internal ROM. Current consumption may be higher if program is executed
from external ROM or if charges are present on I/O ports.
3. A ceramic multilayer capacitor having a minimum value of 100 nF with a low ESR should be used to obtain these
specifications.
4. The I/O line has an integrated 10 kΩ pull-up resistor at pin VCC
5. Pins C4 and C8 have integrated 10 kΩ pull-up resistors at pin VCC; ports P34 and P35 have integrated 20 kΩ pull-up
resistors at pin VDD
.
.
OPTIONS
Table 12 Options
FEATURES
OPTIONS
active LOW
Alarm
active HIGH
active HIGH
on
Presence
active LOW
off
MOVEC protection
2000 Feb 21
32
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V
V
V
DD
DD
DD
C9
2
+5 V
R2
100 kΩ
J1
C14
100 nF
100 nF
C20
C21
100 nF
33 µF
C7
4.7
nF
1
GND
J1
R1
0 Ω
C4
100
nF
C5
100 nF
33 32 31 30 29 28 27 26 25 24 23
V
DD
VUP
S2
RESET
P10/T2
P11/T2EX
n.c.
C1
100 nF
C8
C4
C3
reset
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
C7
V
C6
C2
DDA
C2
100
nF
C3
10 µF
C5
C1
S1
C1I
C2I
C3I
C4I
C5I
C6I
C7I
C8I
AGND
CLK
RST
P30/RXD
P31/TXD
P33/INT1
P36/WR
P37/RD
P20
RX
TX
TDA8006AH
GNDRAM
C10
47 pF
V
DDRAM
C6
100 nF
CARD READ UNIT
n.c.
n.c.
P21
K1
K2
1
2
3
4
5
6
7
8
9
10 11
V
DD
Y2
14.745 MHz
MGR239
C21
33 pF
C20
33 pF
Fig.15 Application diagram.
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
PACKAGE OUTLINES
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-08-01
99-12-27
SOT319-2
MO-112
2000 Feb 21
34
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
2000 Feb 21
35
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
SOLDERING
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
2000 Feb 21
36
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 21
37
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
NOTES
2000 Feb 21
38
Philips Semiconductors
Product specification
Multiprotocol IC Card coupler
TDA8006
NOTES
2000 Feb 21
39
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/03/pp40
Date of release: 2000 Feb 21
Document order number: 9397 750 06361
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