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TDA8007B [NXP]

Double multiprotocol IC card interface; 双多协议IC卡接口
TDA8007B
型号： TDA8007B
厂家： NXP    NXP
描述：

Double multiprotocol IC card interface
双多协议IC卡接口
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INTEGRATED CIRCUITS  
DATA SHEET  
TDA8007B  
Double multiprotocol IC card  
interface  
Product specification  
2000 Nov 09  
Supersedes data of 2000 Aug 29  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
FEATURES  
• Fast and efficient swapping between the 3 cards due to  
separate buffering of parameters for each card  
• Control and communication through an 8-bit parallel  
interface, compatible with multiplexed or  
non-multiplexed memory access  
• Chip select input allowing use of several devices in  
parallel and memory space paging  
• Enhanced ESD protections on card side [6 kV (min.)]  
• Specific ISO UART with parallel access on I/O for  
automatic convention processing, variable baud rate  
through frequency or division ratio programming, error  
management at character level for T = 0, extra guard  
time register  
• Software library for easy integration within the  
application  
• Power-down mode for reducing current consumption  
when no activity.  
• 1 to 8 characters FIFO in reception mode  
• Parity error counter in reception mode  
APPLICATIONS  
• Dual VCC generation (5 V ±5%, 65 mA (max.) or 3 V  
±8%, 50 mA (max.) with controlled rise and fall times)  
• Multiple smart card readers for multiprotocol  
applications (EMV banking, digital pay TV, access  
control, etc.).  
• Dual cards clock generation (up to 10 MHz), with two  
times synchronous frequency doubling  
• Cards clock STOP HIGH, clock STOP LOW or  
1.25 MHz (from internal oscillator) for cards  
Power-down mode  
GENERAL DESCRIPTION  
The TDA8007B is a low cost card interface for dual smart  
card readers. Controlled through a parallel bus, it takes  
care of all ISO 7816, EMV and GSM11-11 requirements.  
It may be interfaced to the P0/P2 ports of a 80C51 family  
microcontroller, and be addressed as a memory through  
MOVX instructions. It may also be addressed on a  
non-multiplexed 8-bit data bus, by means of address  
registers AD0, AD1, AD2 and AD3. The integrated ISO  
UART and the time-out counters allow easy use even at  
high baud rates with no real time constraints. Due to its  
chip select and external I/O and INT features, it greatly  
simplifies the realization of any number of cards readers.  
It gives the cards and the reader a very high level of  
security, due to its special hardware against ESD,  
short-circuiting, power failure, etc. Its integrated step-up  
converter allows operation within a supply voltage range of  
2.7 to 6 V.  
• Automatic activation and deactivation sequence through  
an independent sequencer  
• Supports the asynchronous protocols T = 0 and T = 1 in  
accordance with ISO 7816 and EMV  
• Versatile 24-bit time-out counter for Answer To Reset  
(ATR) and waiting times processing  
• 22 Elementary Time Unit (ETU) counter for Block Guard  
Time (BGT)  
• Supports synchronous cards  
• Current limitations in the event of short-circuit  
• Special circuitry for killing spikes during power-on/-off  
• Supply supervisor for power-on/-off reset  
• Step-up converter (supply voltage from 2.7 to 6 V),  
doubler, tripler or follower according to VCC and VDD  
A software library has been developed, taking care of all  
actions required for T = 0, T = 1 and synchronous  
protocols (see application reports).  
• Additional I/O pin allowing use of the ISO UART for  
another analog interface (pin I/OAUX)  
• Additional interrupt pin allowing detection of level  
toggling on an external signal (pin INTAUX)  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TDA8007BHL  
2000 Nov 09  
LQFP48  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
SOT313-2  
2
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
QUICK REFERENCE DATA  
SYMBOL  
VDD  
PARAMETER  
supply voltage  
CONDITIONS  
MIN.  
2.7  
TYP. MAX. UNIT  
−
−
6
V
IDD(pd)  
supply current in power-down  
mode  
VDD = 3.3 V; cards inactive; XTAL  
oscillator stopped  
−
350  
µA  
VDD = 3.3 V; cards active at  
VCC = 5 V; CLK stopped; XTAL  
oscillator stopped  
−
−
3
mA  
IDD(sm)  
IDD(om)  
supply current in sleep mode  
cards powered at 5 V but clock  
stopped  
−
−
−
−
5.5  
mA  
mA  
supply current in operating mode VDD = 3.3 V; fXTAL = 20 MHz;  
CC1 = VCC2 = 5 V;  
315  
V
ICC1 + ICC2 = 80 mA  
VCC  
output card supply voltage  
including static loads (5 V card)  
4.75  
4.6  
5.0  
5.25  
5.4  
V
V
with 40 nC dynamic loads on  
200 nF capacitor (5 V card)  
−
including static loads (3 V card)  
2.78  
2.75  
−
−
3.22  
3.25  
V
V
with 24 nC dynamic loads on  
200 nF capacitor (3 V card)  
ICC  
output card supply current  
operating; 5 V card  
operating; 3 V card  
overload detection  
−
−
65  
mA  
mA  
mA  
mA  
V/µs  
µs  
−
−
50  
−
100  
−
−
ICC1 + ICC2 sum of both cards currents  
−
80  
SR  
tdeact  
tact  
fxtal  
fop  
slew rate on VCC (rise and fall)  
deactivation cycle duration  
activation cycle duration  
crystal frequency  
CL(max) = 300 nF  
0.05  
−
0.16  
−
0.22  
150  
225  
27  
−
−
µs  
4
−
MHz  
MHz  
operating frequency  
external frequency applied to pin  
XTAL1  
0
−
25  
Tamb  
ambient temperature  
−25  
−
+85  
°C  
2000 Nov 09  
3
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
BLOCK DIAGRAM  
V
V
DD  
DDA  
100 nF  
220 nF  
220 nF  
GND  
19  
SAP SAM  
SBP SBM  
AGND  
27  
23 21  
26  
22  
24 25  
1
RSTOUT  
DELAY  
SUPPLY  
AND  
SUPERVISOR  
STEP-UP  
CONVERTER  
V
48  
20 UP  
220 nF  
22 nF  
40  
39  
45  
44  
43  
42  
36  
37  
28  
29  
30  
31  
32  
33  
34  
35  
38  
2
6
4
INT  
ALE  
AD0  
AD1  
AD2  
AD3  
RD  
C41  
C81  
8
CLK1  
RST1  
10  
9
ISO7816  
UART  
V
CC1  
3
I/O1  
5
WR  
D0  
PRES1  
GNDC1  
C42  
ANALOG  
DRIVERS  
AND  
7
D1  
14  
12  
16  
18  
17  
11  
13  
15  
SEQUENCERS  
D2  
TIME-OUT  
COUNTER  
C82  
D3  
CLK2  
RST2  
D4  
D5  
D6  
V
CC2  
CLOCK  
CIRCUIT  
D7  
I/O2  
CS  
PRES2  
GNDC2  
I/OAUX  
INTAUX  
41  
INT OSC  
TDA8007B  
XTAL OSC  
47  
46  
XTAL2  
FCE534  
XTAL1  
Fig.1 Block diagram.  
4
2000 Nov 09  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
PINNING  
SYMBOL  
PIN  
DESCRIPTION  
open-drain output for resetting external chips  
RSTOUT  
I/OAUX  
I/O1  
1
2
input or output for an I/O line issued of an auxiliary smart card interface  
data line to/from card 1 (ISO C7 contact)  
3
C81  
4
auxiliary I/O for ISO C8 contact (synchronous cards for instance) for card 1  
card 1 presence contact input (active HIGH or LOW by mask option)  
auxiliary I/O for ISO C4 contact (synchronous cards for instance) for card 1  
ground for card 1  
PRES1  
C41  
5
6
GNDC1  
CLK1  
VCC1  
7
8
clock output to card 1 (ISO C3 contact)  
9
card 1 supply output voltage (ISO C1 contact)  
card 1 reset output (ISO C2 contact)  
RST1  
I/O2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
data line to/from card 2 (ISO C7 contact)  
C82  
auxiliary I/O for ISO C8 contact (synchronous cards for instance) for card 2  
card 2 presence contact input (active HIGH or LOW by mask option)  
auxiliary I/O for ISO C4 contact (synchronous cards for instance) for card 2  
ground for card 2  
PRES2  
C42  
GNDC2  
CLK2  
VCC2  
clock output to card 2 (ISO C3 contact)  
card 2 supply output voltage (ISO C1 contact)  
card 2 reset output (ISO C2 contact)  
RST2  
GND  
ground connection  
VUP  
output of the step-up converter  
SAP  
contact 1 for the step-up converter (connect a low ESR 220 nF capacitor between pins SAP  
and SAM)  
SBP  
22  
contact 3 for the step-up converter (connect a low ESR 220 nF capacitor between pins SBP  
and SBM)  
VDDA  
SBM  
23  
24  
positive analog supply voltage for the step-up converter  
contact 4 for the step-up converter (connect a low ESR 220 nF capacitor between pins SBP  
and SBM)  
AGND  
SAM  
25  
26  
ground connection for the step-up converter  
contact 2 for the step-up converter (connect a low ESR 220 nF capacitor between pins SAP  
and SAM)  
VDD  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
RD  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
positive supply voltage  
data 0 or add 0  
data 1 or add 1  
data 2 or add 2  
data 3 or add 3  
data 4 or add 4  
data 5 or add 5  
data 6 or add 6  
data 7 or add 7  
read selection signal (read or write in non-multiplexed configuration)  
2000 Nov 09  
5
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
WR  
PIN  
DESCRIPTION  
37  
38  
39  
write selection signal (enable in case of non-multiplexed configuration)  
chip select input (active HIGH or LOW)  
CS  
ALE  
address latch enable in case of multiplexed configuration (connect to VDD in non-multiplexed  
configuration)  
INT  
40  
41  
42  
43  
44  
45  
46  
47  
48  
interrupt output (active LOW)  
INTAUX  
AD3  
auxiliary interrupt input  
register selection address 3  
AD2  
register selection address 2  
AD1  
register selection address 1  
AD0  
register selection address 0  
XTAL2  
XTAL1  
DELAY  
connection pin for an external crystal  
connection pin for an external crystal or input for an external clock signal  
connection pin for an external delay capacitor  
RSTOUT  
I/OAUX  
I/O1  
1
2
3
4
5
6
7
8
9
36 RD  
35 D7  
34 D6  
33 D5  
32 D4  
31 D3  
30 D2  
29 D1  
28 D0  
C81  
PRES1  
C41  
TDA8007BHL  
GNDC1  
CLK1  
V
CC1  
RST1 10  
I/O2 11  
C82 12  
27  
V
DD  
26 SAM  
25 AGND  
FCE678  
Fig.2 Pin configuration.  
6
2000 Nov 09  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
FUNCTIONAL DESCRIPTION  
If ALE is tied to VDD or GND, then the TDA8007B will be in  
the non-multiplexed configuration. In this case, the  
address bits are external pins AD0 to AD3, RD is the  
read/write control signal, and WR is a data write or read  
active LOW enable signal.  
Throughout this specification, it is assumed that the reader  
is aware of ISO 7816 norm terminology.  
Interface control  
In both configurations, the TDA8007B is selected only  
when CS is LOW. INT is an active LOW interrupt signal.  
The TDA8007B can be controlled via an 8-bit parallel bus  
(bits D0 to D7).  
In non-multiplexed bus configuration, CS and EN play the  
same role.  
If a microcontroller with a multiplexed address/data bus  
(such as the 80C51) is used, then D0 to D7 may be directly  
connected to P0 to P7. When CS is LOW, the  
demultiplexing of address and data is performed internally  
using the ALE signal, a LOW pulse on pin RD allows the  
selected register to be read, a LOW pulse on pin WR  
allows the selected register to be written to. The  
TDA8007B automatically switches to the multiplexed bus  
configuration if a rising edge is detected on pin ALE. In this  
event, AD0 to AD3 play no role and may be tied to VDD or  
GND. Using a 80C51 microcontroller, the TDA8007B is  
simply controlled with MOVX instructions.  
In read operations (RD/WR is HIGH), the data  
corresponding to the chosen address is available on the  
bus when both CS and EN are LOW.  
In write operations, the data present on the bus is written  
when signals RD/WR, CS and EN become LOW.  
AD0 to AD3  
CS  
D0 to D7  
ALE  
WR  
RD  
LATCH  
REC  
MUX  
MUX  
addresses  
RD  
REGISTERS  
WR  
FCE679  
Fig.3 Multiplexed bus recognition.  
2000 Nov 09  
7
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
ALE  
t
t
AVLL  
t
W(RD)  
t
t
(RWH-AH)  
W(ALE)  
t
t
(RWH-AH)  
AVLL  
t
(AL-RWL)  
CS  
(AL-RWL)  
DATA  
READ  
ADDRESS  
DATA WRITE  
ADDRESS  
D0 to D7  
t
(DV-WL)  
RD  
t
t
(RL-DV)  
W(WR)  
WR  
FCE680  
Fig.4 Control with multiplexed bus.  
AD0 to AD3  
Write (data written on  
falling edge of CS)  
Read  
Read  
Read  
RD  
t
(CEL-DV)  
t
(REH-CL)  
CS  
EN  
t
t
(RL-CEL)  
(CEH-DZ)  
DATA OUT  
t
t
t
(CEH-DZ)  
(CREL-DZ)  
(CEL-DV)  
t
(AD-DV)  
t
(REH-CL)  
DATA OUT  
DATA OUT  
DATA IN  
D0 to D7  
FCE681  
Fig.5 Control with non-multiplexed bus.  
8
2000 Nov 09  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Control registers  
The Hardware Status Register (HSR) gives the status of  
the supply voltage, of the hardware protections and of the  
card movements.  
The TDA8007B has 2 complete analog interfaces which  
can drive card 1 and card 2. The data to and from these  
2 cards share the same ISO UART. The data to and from  
a third card (card 3), externally interfaced (with a TDA8002  
or TDA8003 for example), may also share the same  
ISO UART.  
HSR and USR give interrupts on pin INT when some of  
their bits have been changed.  
The MSR does not give interrupts and may be used in the  
polling mode for some operations; for this use, some of the  
interrupt sources within the USR and HSR may be  
masked.  
Cards 1, 2 and 3 have dedicated registers for setting the  
parameters of the ISO UART; Programmable Divider  
Register (PDR), Guard Time Register (GTR), UART  
Configuration Register 1 (UCR1), UART Configuration  
Register 2 (UCR2) and Clock Configuration Register  
(CCR).  
A 24-bit time-out counter may be started to give an  
interrupt after a number of ETUs programmed into  
registers TOR1, TOR2 and TOR3. This will help the  
microcontroller in processing different real-time tasks  
(ATR, WWT, BWT, etc.) mainly if the microcontrollers and  
cards clock are asynchronous.  
Cards 1 and 2 also have dedicated registers for controlling  
their power and clock configuration. The Power Control  
Register (PCR) for card 3, is controlled externally. The  
PCR is also used for writing or reading on the auxiliary  
card contacts C4 and C8.  
This counter is configured with a register Time-Out counter  
Configuration (TOC). It may be used as a 24-bit or as a  
16 + 8 bits. Each counter can be set to start counting once  
data has been written, or on detection of a start bit on the  
I/O, or as auto-reload.  
Card 1, 2 or 3 can be selected via the Card Select Register  
(CSR). When one card is selected, the corresponding  
parameters are used by the ISO UART. The CSR also  
contains one bit for resetting the ISO UART (active LOW).  
This bit is reset after Power-on, and must be set to HIGH  
before starting with any one of the cards. It may be reset  
by software when necessary.  
When the specific parameters of the cards have been  
programmed, the UART may be used with the following  
registers: UART Receive Register (URR), UART Transmit  
Register (UTR), UART Status Register (USR) and Mixed  
Status Register (MSR). In reception mode, a FIFO of 1 to 8  
characters may be used, and is configured with the FIFO  
Control Register (FCR).  
2000 Nov 09  
9
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GENERAL  
ISO UART  
CARD SELECT REGISTER  
HARD STATUS REGISTER  
TIME-OUT REGISTER 1  
TIME-OUT REGISTER 2  
TIME-OUT REGISTER 3  
TIME-OUT CONFIGURATION  
UART STATUS REGISTER  
UART TRANSMIT REGISTER  
UART RECEIVE REGISTER  
FIFO CONTROL REGISTER  
MIXED STATUS REGISTER  
CARD1  
CARD2  
CARD3  
PROGRAM DIVIDER REGISTER 1  
PROGRAM DIVIDER REGISTER 2  
PROGRAM DIVIDER REGISTER 3  
GUARD TIME REGISTER 1  
GUARD TIME REGISTER 2  
GUARD TIME REGISTER 3  
UART CONFIGURATION REGISTER 11  
UART CONFIGURATION REGISTER 12  
CLOCK CONFIGURATION REGISTER 1  
POWER CONTROL REGISTER 1  
UART CONFIGURATION REGISTER 21  
UART CONFIGURATION REGISTER 22  
CLOCK CONFIGURATION REGISTER 2  
POWER CONTROL REGISTER 2  
UART CONFIGURATION REGISTER 31  
UART CONFIGURATION REGISTER 32  
CLOCK CONFIGURATION REGISTER 3  
FCE682  
Fig.6 Registers summary.  
ahdnbok,uflapegwidt  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
GENERAL REGISTERS  
PTL is set if overheating has occurred.  
The Card Select Register (see Table 1) is used for  
selecting the card on which the UART will act, and also to  
reset the ISO UART.  
INTAUXL is HIGH if the level on the INTAUX input has  
been changed.  
When PRTL2, PRTL1, PRL2 or PRL1 or PTL is HIGH,  
then INT is LOW. The bits having caused the interrupt are  
cleared when the HSR has been read-out. The same  
occurs with bit INTAUXL if not disabled.  
If SC1 = 1, then card 1 is selected; if SC2 = 1, then card 2  
is selected, if SC3 = 1, then card 3 is selected. These bits  
must be set one at a time. After reset, card 1 is selected by  
default. The bit Reset ISO UART (RIU) must be set to  
logic 1 by software before any action on the UART can  
take place. When reset, this bit resets all UART registers  
to their initial value.  
At power-on, or after a supply voltage dropout, SUPL is set  
and INT is LOW. INT will return HIGH at the end of the  
alarm pulse on pin RSTOUT. SUPL will be reset only after  
a status register read-out outside the ALARM pulse  
(see Fig.7).  
It should be noted that access to card 3 is only possible  
once either card 1 or 2 has been activated.  
In case of emergency deactivation (by PRTL1, PRTL2,  
SUPL, PRL2, PRL1 or PTL), the START bit is  
automatically reset by hardware.  
The Hardware Status Register (see Table 2) gives the  
status of the chip after a hardware problem has been  
detected.  
The three registers TOR1, TOR2 and TOR3 form a  
programmable 24-bit ETU counter, or two independant  
counters (one 16-bit and one 8-bit).  
Presence Latch 1 (PRL1) and Presence Latch 2 (PRL2)  
are HIGH when a change has occurred on PR1 and PR2.  
Supervisor Latch (SUPL) is HIGH when the supervisor has  
been activated.  
The value to load in TOR1, 2 and 3 is the number of ETUs  
to count.  
Protection 1 (PRTL1) and Protection 2 (PRTL2) are HIGH  
when a default has been detected on card readers 1  
and 2. (PRTL is the OR function of protection on VCC and  
RST).  
The TOC register is used for setting different  
configurations of the time-out counter as given in Table 7  
(all other configurations are undefined).  
Table 1 Card select register (write and read); address: 0  
(all significant bits are cleared after reset, except for SC1 which is set)  
CS7  
CS6  
CS5  
CS4  
CS3  
CS2  
CS1  
CS0  
not used  
not used  
not used  
not used  
RIU  
SC3  
SC2  
SC1  
Table 2 Hardware status register (read only); address: F  
(all significant bits are cleared after reset, except for SUPL which is set within the RSTOUT pulse)  
HS7  
HS6  
HS5  
HS4  
HS3  
HS2  
HS1  
HS0  
not used  
PRTL2  
PRTL1  
SUPL  
PRL2  
PRL1  
INTAUXL  
PTL  
Table 3 Time-out register 1 (write only); address: 9 (all bits are cleared after reset)  
TO17  
TO16  
TO15  
TO14  
TO13  
TO12  
TO11  
TO10  
TOL7  
TOL6  
TOL5  
TOL4  
TOL3  
TOL2  
TOL1  
TOL0  
Table 4 Time-out register 2 (write only); address: A (all bits are cleared after reset)  
TO27  
TO26  
TO25  
TO24  
TO23  
TO22  
TO21  
TO20  
TOL15  
TOL14  
TOL13  
TOL12  
TOL11  
TOL10  
TOL9  
TOL8  
2000 Nov 09  
11  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Table 5 Time-out register 3 (write only); address: B (all bits are cleared after reset)  
TO37  
TO36  
TO35  
TO34  
TO33  
TO32  
TO31  
TOL17  
TO30  
TOL23  
TOL22  
TOL21  
TOL20  
TOL19  
TOL18  
TOL16  
Table 6 Time-out configuration register (read and write); address: 8 (all bits are cleared after reset)  
TOC7  
TOC6  
TOC5  
TOC4  
TOC3  
TOC2  
TOC1  
TOC0  
TOC7  
TOC6  
TOC5  
TOC4  
TOC3  
TOC2  
TOC1  
TOC0  
Table 7 Time-out counter configurations  
TOC  
OPERATING MODE  
00  
61  
all counters are stopped  
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3  
and TOR2 is started after 61 is written in the TOC. An interrupt is given, and bit TO3 is set within the  
USR when the terminal count is reached. The counter is stopped by writing 00 in the TOC.  
65  
Counter 1 is an 8-bit auto reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1 starts  
counting the content of TOR1 on the first start bit (reception or transmission) detected on I/O after 65 is  
written in the TOC. When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in the USR  
is set, and the counter automatically restarts the same count until it is stopped. It is not allowed to  
change the content of TOR1 during a count. In this mode, the accuracy of counter 1 is ±0.5 ETU.  
Counters 3 and 2 are wired as a single 16-bit counter and starts counting the value TOR3 and TOR2  
when 65 is written in the TOC. When the counter reaches its terminal count, an interrupt is given and  
bit TO3 is set within the USR. Both counters are stopped when 00 is written in the TOC.  
68  
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and  
TOR1 is started after 68 is written in the TOC. The counter is stopped by writing 00 in the TOC. It is not  
allowed to change the content of TOR3, TOR2 and TOR1 within a count.  
7C  
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and  
TOR1 on the first start bit detected on I/O (reception or transmission) after the value has been written.  
It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current count will not  
be affected and the new count value will be taken into account at the next start bit. The counter is  
stopped by writing 00 in the TOC. In this configuration TOR3, TOR2 and TOR1 must not be all zero.  
E5  
Same configuration as TOC = 65, except that counter 1 will be stopped at the end of the 12th ETU  
following the first start bit detected after E5 has been written in the TOC.  
2000 Nov 09  
12  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
The time-out counter is very useful for processing the clock  
counting during ATR, the Work Waiting Time, or the  
waiting times defined in T = 1 protocol. It should be noted  
that the 200 and 400 CLK counter used during ATR is  
done by hardware when the start session is set; a specific  
hardware controls functionality BGT in T = 1 protocol, and  
a specific register is available for processing the extra  
guard time.  
– Timer 3 + 2 + 1 will count the BWT from the last start  
bit of the sent block  
– After reception of the first character of the block from  
the card, TOR3, TOR2 and TOR1 should be loaded  
with the CWT  
– Timer 3 + 2 + 1 will count the CWT between each  
received start bit  
– And so on.  
The possible use of the counters is as follows:  
• Before and after CLOCK STOP (example, where  
ETU = 372 clock pulses):  
• ATR (cold reset):  
– Before activation; TOR1 = C0H, TOR2 = 6EH,  
TOR3 = 0 and TOC = 65. Once activated, timer 2 + 3  
will count 40920 clock pulses before giving an  
interrupt.  
– After the last received character on I/O, TOR3 = 0,  
TOR2 = 6 and TOC = 61  
– Timer 3 + 2 will start counting 2232 clock pulses  
before giving an interrupt  
– On interrupt; TOR2 = 76H and TOC = 65. If a  
character is received from the card before the  
timeout, then counter 1 will be enabled. Counter 1 will  
give one interrupt every 192 ETUs, so the software  
will count 100 times to verify that the ATR is finished  
before 19200 ETUs. The UART will give an interrupt  
with bit Buffer Full (BF) at 10.5 ETUs after the start  
bit.  
– On interrupt, the software may stop the clock to the  
card  
– When it is necessary to restart the clock, TOR3 = 0,  
TOR2 = 2, TOC = 61 and restart the clock  
– Timer 3 + 2 gives an interrupt at 744 clock pulses,  
and then the software can send the first command to  
the card.  
– On interrupt; TOR3 = 25H, TOR2 = 80H and  
TOC = 65. Counter 1 keeps on counting  
ISO UART REGISTERS  
100 × 192 ETUs, while counter 2 and 3 counts  
9600 ETUs. This sequence is repeated until the  
character before the last one of the ATR.  
When the microcontroller wants to transmit a character to  
the selected card, it writes the data in direct convention in  
the UART Transmit Register (see Table 8). The  
transmission:  
– On interrupt TOR3 = 25H, TOR2 = 80H and  
TOC = E5. Timer 1 will be automatically stopped at  
the end of the last character of the ATR, allowing a  
count of 19200 ETUs.  
• Starts at the end of writing (on the rising edge of WR) if  
the previous character has been transmitted and if the  
extra guard time has expired; or  
– On interrupt TOC = 00.  
• Starts at the end of the extra guard time if this one has  
not expired; or  
• Work Waiting Time (WWT) in T = 0 protocol;  
– Before sending the first command to the card  
TOR1, TOR2 and TOR3 should be loaded with the  
correct 960 × WI × D value and TOC = 7C  
• Does not start if the transmission of the previous  
character is not completed.  
In the case of a synchronous card (bit SAN within UCR2  
is set), only D0 is relevant, and is copied on the I/O of the  
selected card. When the microcontroller wants to read  
data from the card it reads it from the UART Receive  
Register (see Table 9) in direct convention.  
– Timer 3, 2 and 1 will count the WWT between each  
start bit  
• Character Waiting Time (CWT) and Block Waiting Time  
(BWT) in T = 1 protocol:  
– Before sending the first block to the card, TOR3,  
TOR2 and TOR1 should be loaded with the CWT and  
TOC = 7C  
In case of a synchronous card, only D0 is relevant and is a  
copy of the state of the selected card I/O.  
When needed, this register may be tied to a FIFO whose  
length ‘n’ is programmable between 1 and 8.  
– Timer 3 + 2 + 1 will count the CWT between each  
start bit  
If n > 1, then no interrupt is given until the FIFO is full. The  
microcontroller may empty the FIFO at any time.  
– Before the end of the block, TOR3, TOR2 and TOR1  
should be loaded with the BWT  
2000 Nov 09  
13  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Error management in protocol:  
• When changing from transmission mode to reception  
mode.  
• T = 0:  
No bits within the MSR act upon INT:  
In the event of a parity error, the received byte is not  
stored in the FIFO, and the error counter is incremented.  
The error counter is programmable between 1 and 8.  
When the programmed number is reached, bit PE is set  
in the status register USR and INT goes LOW. The error  
counter must be reprogrammed to the desired value after  
its count has been reached.  
• The FIFO Control Register bits are given in Table 11,  
FL2, FL1 and FL0 determine the depth of the FIFO  
(000 = length 1, 111 = length 8).  
PEC2, PEC1 and PEC0 determine the number of parity  
errors before setting bit PE in the USR and pulling  
INT LOW; 000 indicates that if only one parity error has  
occurred, bit PE is set; 111 indicates that bit PE will be set  
after 8 parity errors.  
• T = 1:  
In the event of a parity error, the character is loaded in the  
FIFO, and bit PE is set whatever the programmed value  
in parity error counter.  
PEC2, PEC1 and PEC0 need to be reprogrammed to the  
desired value after bit PE has been set.  
When the FIFO is full, bit RBF in the status register USR  
is set. This bit is reset when at least one character has  
been read from the URR.  
In protocol T = 0:  
• If a correct character is received before the  
programmed error number is reached the error counter  
will be reset.  
When the FIFO is empty, bit FE is set as long as no  
character has been received.  
• If the programmed number of allowed parity errors is  
reached, bit PE in the USR will be set as long as the  
USR has not been read.  
The Mixed Status Register (see Table 10) relates the  
status of pin INTAUX, the cards presence contacts PR1  
and PR2, the BGT counter, the FIFO empty indication  
and the transmit/receive ready indicator TBE/RBF.  
In protocol T = 1:  
• The error counter has no action (bit PE is set at the first  
Bit INTAUX is set when the level on pin INTAUX is HIGH,  
it is reset when the level is LOW.  
wrong received character).  
• The UART Status Register (see Table 12) is used by  
the microcontroller to monitor the activity of the  
ISO UART and that of the time-out counter.  
Bit BGT is linked with a 22 ETU counter, which is started  
at every start bit on the I/O. Bit BGT is set if the count is  
finished before the next start bit. This helps to verify that  
the card has not answered before 22 ETUs after the last  
transmitted character, or not transmitting a character  
before 22 ETUs after the last received character.  
Transmission Buffer Empty (TBE) is HIGH when the  
UART is in transmission mode, and when the  
microcontroller may write the next character to transmit in  
the UTR. It is reset when the microcontroller has written  
data in the transmit register or when bit T/R within UCR1  
has been reset either automatically or by software.  
PR1 is HIGH when card 1 is present, PR2 is HIGH when  
card 2 is present.  
After detection of a parity error in transmission, it is  
necessary to wait 13 ETUs before rewriting the character  
which has been Not ACKnowledged (NAK) by the card.  
FE is set when the reception FIFO is empty. It is reset  
when at least one character has been loaded in the FIFO.  
Bit TBE/RBF (Transmit Buffer Empty/Receive Buffer Full)  
is set when:  
Reception Buffer Full (RBF) is HIGH when the FIFO is full.  
The microcontroller may read some of the characters in  
the URR, which clears bit RBF.  
• Changing from reception mode to transmission mode  
• A character has been transmitted by the UART  
• The reception FIFO is full.  
TBE and RBF share the same bit within the USR (when in  
transmission mode, the relevant bit is TBE; when in  
reception mode, it is RBF).  
Bit TBE/RBF is reset after Power-on or after one of the  
following:  
Framing Error (FER) is HIGH when the I/O was not in the  
high-impedance state at 10.25 ETUs after a start bit. It is  
reset when the USR has been read-out.  
• When bit RIU is reset  
• When a character has been written to the UTR  
• When at least one character has been read in the FIFO  
2000 Nov 09  
14  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Overrun (OVR) is HIGH if the UART has received a new  
character whilst the FIFO was full. In this case, at least one  
character has been lost.  
pulses (all activities on the I/O during the 200 first CLK  
pulses with RST LOW or HIGH are not taken into account).  
These 2 features are reinitialized at each toggling of RST.  
In protocol T = 0: Parity Error (PE) is HIGH if the UART has  
detected a number of received characters with parity  
errors equal to the number written in PEC2, PEC1 and  
PEC0 or if a transmitted character has been NAKed by the  
card.  
Bit TO1 is set when counter 1 has reached its terminal  
count.  
Bit TO3 is set when counter 3 has reached its terminal  
count.  
If any of the status bits FER, OVR, PE, EA, TO1 or TO3  
are set then INT will go LOW. The bit having caused the  
interrupt is reset at the end of a read operation of the USR.  
If TBE/RBF is set, and if the mask bit DISTBE/RBF within  
USR2 is not set, then INT will also be LOW. TBE/RBF is  
reset when data has been written to the UTR, when data  
has been read from the URR, or when changing from  
transmission mode to reception mode.  
In protocol T = 0: a character received with a parity error is  
not stored in the FIFO (the card is supposed to repeat this  
character).  
In protocol T = 1: a character with a parity error is stored in  
the FIFO and the parity error counter is not active.  
Early Answer (EA) is HIGH if the first start bit on the I/O  
during ATR has been detected between 200 and 384 CLK  
Table 8 UART transmit register (write only); address: D (all bits are cleared after reset)  
UT7  
UT6  
UT5  
UT4  
UT3  
UT2  
UT1  
UT0  
UT7  
UT6  
UT5  
UT4  
UT3  
UT2  
UT1  
UT0  
Table 9 UART receive register (read only); address: D (all bits are cleared after reset)  
UR7  
UR6  
UR5  
UR4  
UR3  
UR2  
UR1  
UR0  
UR7  
UR6  
UR5  
UR4  
UR3  
UR2  
UR1  
UR0  
Table 10 Mixed status register (read only); address: C  
(bits TBE, RBF and BGT are cleared after reset; bit FE is set after reset)  
MS7  
MS6  
MS5  
MS4  
MS3  
MS2  
MS1  
MS0  
not used  
FE  
BGT  
not used  
PR2  
PR1  
INTAUX  
TBE/RBF  
Table 11 FIFO control register (write only); address: C (all relevant bits are cleared after reset)  
FC7  
FC6  
FC5  
FC4  
FC3  
FC2  
FC1  
FC0  
not used  
PEC2  
PEC1  
PEC0  
not used  
FL2  
FL1  
FL0  
Table 12 UART status register (read only); address: E (all bits are cleared after reset)  
US7  
US6  
US5  
US4  
US3  
US2  
US1  
US0  
TO3  
not used  
TO1  
EA  
PE  
OVR  
FER  
TBE/RBF  
2000 Nov 09  
15  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
CARD REGISTERS  
When cards 1 2 or 3 are selected, then the following registers may be used for programming some specific parameters.  
The Programmable Divider Register (see Table 13) is used for counting the cards clock cycles forming the ETU. It is an  
auto-reload 8-bit counter decounting from the programmed value down to 0.  
Table 13 Programmable Divider Register (PDR1, 2 and 3) (read and write); address: 2 (all bits are cleared after reset)  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
The UART Configuration Register 2 bits are given in Table 14. If bit PSC is set to logic 1, then the prescaler value is 32.  
If bit PSC is set to logic 0, then the prescaler value is 31. One ETU will last a number of card clock cycles equal to  
prescaler x PDR. All baud rates specified in ISO 7816 norm are achievable with this configuration.  
Table 14 UART configuration register 2 (UCR21, 22 and 23) (read and write); address: 3  
(all relevant bits are cleared after reset)  
UC27  
UC26  
UC25  
UC24  
UC23  
UC22  
UC21  
UC20  
not used  
DISTBE/RBF  
DISAUX  
PDWN  
SAN  
AUTOCONV  
CKU  
PSC  
Table 15 Baud rates with a 3.58 MHz card clock frequency (31;12 means prescaler set to 31 and PDR set to 12)  
F
D
0
1
2
3
4
5
6
9
10  
11  
12  
13  
1
2
3
4
5
31;12  
9600  
31;6  
31;12  
9600  
31;6  
31;18  
6400  
31;9  
31;24  
4800  
31;12  
31;36  
3200  
31;18  
6400  
31;9  
31;48  
2400  
31;24  
4800  
31;12  
31;60  
1920  
31;30  
3840  
31;15  
7680  
32;16  
32;24  
32;32  
32;48  
32;64  
32;8  
32;4  
32;2  
32;1  
32;12  
32;6  
32;3  
32;16  
32;8  
32;4  
32;2  
32;1  
32;24  
32;12  
32;6  
32;32  
32;16  
32;8  
19200 19200 12800 9600  
31;3 31;3 31;6  
38400 38400  
19200 12800 9600  
31;3  
38400  
31;6  
19200  
31;3  
32;3  
32;4  
38400  
6
8
32;2  
31;1  
31;1  
31;2  
31;3  
31;4  
31;5  
32;2  
32;4  
115200 115200  
57600 38400 28800 23040  
9
31;3  
38400  
2000 Nov 09  
16  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
For other baud rates than those given in Table 15, there  
is the possibility to set bit CKU (clock UART) to logic 1. In  
this case, the ETU will last half of the formula given  
above.  
If the Disable TBE/RBF (DISTBE/RBF) interrupt bit is set,  
then reception or transmission of a character will not  
generate an interrupt:  
• This feature is useful for increasing communication  
speed with the card; in this case, a copy of the  
TBE/RBF bit within the MSR must be polled (and not  
the original) in order not to loose priority interrupts  
which can occur in the USR.  
If bit AUTOCONV is set, then the convention is set by  
software using bit CONV in the UART Configuration  
Register. If it is reset, then the configuration is  
automatically detected on the first received character  
whilst the Start Session (SS) bit is set.  
• The Guard Time Register (see Table 17) is used for  
storing the number of guard ETUs given by the card  
during ATR. In transmission mode, the UART will wait  
this number of ETUs before transmitting the character  
stored in the UTR. In T = 1 protocol, when GTR = FF  
means operation at 11 ETUs. In protocol T = 0,  
GTR = FF means operation at 12 ETUs.  
Synchronous/Asynchronous (SAN) is set by software if a  
synchronous card is expected. The UART is then  
bypassed, and only bit 0 in the URR and UTR is  
connected to the I/O. In this case the CLK is controlled by  
bit SC in the CCR.  
When Power-down mode (PDWN) is set by software, the  
crystal oscillator is stopped. This mode allows low  
consumption in applications where it is required. During  
this mode, it is not possible to select another card other  
than the currently selected one. There are 5 ways of  
escaping from the Power-down mode:  
• The UART Configuration Register (see Table 18) is  
used for setting the parameters of the ISO UART.  
The Convention (CONV) bit is set if the convention is  
direct. CONV is either automatically written by hardware  
according to the convention detected during ATR, or by  
software if the bit AUTOCONV is set.  
1. Insert card 1 or card 2  
The SS bit is set before ATR for automatic convention  
detection and early answer detection (this bit must be  
reset by software after reception of a correct initial  
character).  
2. Withdraw card 1 or card 2  
3. Select the TDA8007B by resetting CS (this assumes  
that the TDA8007B had been deselected after setting  
Power-down mode)  
The Last Character to Transmit (LCT) bit is set by  
software before writing the last character to be  
transmitted in the UTR. It allows automatic change to  
reception mode. It is reset by hardware at the end of a  
successful transmission.  
4. INTAUXL has been set due to a change on pin  
INTAUX  
5. If CS is permanently set to LOW, reset bit PDWN by  
software.  
After any of these 5 events, the TDA8007B will leave the  
Power-down mode, and will pull INT LOW when it is ready  
to communicate with the system microcontroller. The  
system microcontroller may then read the status  
registers, and INT will return HIGH (if the system  
microcontroller has woken the TDA8007B by reselecting  
it, then no bits will be set in the status registers).  
The Transmit/Receive (T/R) bit is set by software for  
transmission mode. A change from logic 0 to logic 1 will  
set bit TBE in the USR. Bit T/R is automatically reset by  
hardware if the LCT bit has been used before transmitting  
the last character.  
The Protocol (PROT) bit is set if the protocol type is  
asynchronous T = 1. If PROT = 0, the protocol is T = 0.  
If the Disable AUX (DISAUX) interrupt bit in UCR2 is set,  
then a change on INTAUX will not generate an interrupt  
(but bit INTAUXL in the HSR will be set; it is therefore  
necessary to read the HSR before a DISAUX reset to  
avoid an interrupt by INTAUXL). To avoid an interrupt  
during a change of card, it is better to set the DISAUX bit  
in UCR2 for both cards.  
The Flow Control (FC) bit is set if flow control is used (not  
described in this specification).  
If the Force Inverse Parity (FIP) bit is set to HIGH the  
UART will NAK a correctly received character, and will  
transmit characters with wrong parity bits.  
2000 Nov 09  
17  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Clock Configuration Register (see Table 19):  
When switching from XTAL/n to 1⁄2fint or vice verse, a  
maximum delay of 200 µs can occur between the  
command and the effective frequency change on CLK (the  
fastest switching time is from 1⁄2XTAL to 1⁄2fint or vice  
verse, the best for duty cycle is from 1⁄8XTAL to 1⁄2fint or  
vice verse).  
• For cards 1 and 2, the CCR defines the clock for the  
selected card.  
• For cards 1, 2 and 3 it defines the clock to the  
ISO UART. It should be noted that if bit CKU in the  
prescaler register of the selected card is set, then the  
ISO UART is clocked at twice the frequency of the card,  
which allows baud rates not foreseen in ISO 7816 norm  
to be reached.  
It is necessary to wait the maximum delay time before  
reactivating from Power-down mode.  
In the event of a synchronous card, then the CLK contact  
is the copy of the value written in Synchronous Clock (SC).  
In reception mode, the data from the card is available to  
UR0 after a read operation of the URR; in transmission  
mode, the data is written on the I/O line of the card when  
the UTR has been written to and remains unchanged when  
another card is selected.  
In case of an asynchronous card, the Clock Stop (CST) bit  
defines whether the clock to the card is stopped or not.  
If CST is set, then CLK is stopped LOW if SHL = 0, and  
HIGH if SHL = 1.  
If CST is reset, then CLK is determined by bits AC0, AC1  
and AC2; see Table 16. All frequency changes are  
synchronous, thus ensuring that no spike or unwanted  
pulse widths occur during changes.  
The Power Control Register (PCR), see Table 20:  
• Starts or stops card sessions.  
• Reads or writes on auxiliary card contacts C4 and C8.  
• Is available only for cards 1 or 2.  
Table 16 CLK value for an asynchronous card  
AC2  
AC1  
AC0  
CLK  
1⁄2XTAL  
1⁄2XTAL  
1⁄4XTAL  
1⁄8XTAL  
1⁄2fint  
1⁄2fint  
1⁄2fint  
1⁄2fint  
If the microcontroller sets START to logic 1, then the  
selected card is activated (see Section “Activation  
sequence”). If the microcontroller resets START to logic 0,  
then the card is deactivated (see Section “Deactivation  
sequence”). START is automatically reset in case of  
emergency deactivation.  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
If 3 V/5 V is set to logic 1, then VCC is 3 V. If 3 V/5 V is set  
to logic 0, then VCC is 5 V.  
When the card is activated, RST is the copy of the value  
written in RSTIN.  
If 1.8 V is set, then VCC = 1.8 V: It should be noted that no  
specification is guaranteed at this voltage.  
When switching from XTAL/n to 1⁄2fint or vice verse, only  
bit AC2 must be changed (AC1 and AC0 must remain the  
same). When switching from XTAL/n or 1⁄2fint to CLK  
STOP or vice verse, only bits CST and SHL must be  
changed.  
When writing to the PCR, C4 will output the value written  
to PCR4, and C8 the value written to PCR5. When reading  
from the PCR, PCR4 will store the value on C4, and PCR5  
the value on C8.  
Table 17 Guard time register (GTR1, 2 and 3) (read and write); address: 5 (all bits are cleared after reset)  
GT7  
GT6  
GT5  
GT4  
GT3  
GT2  
GT1  
GT0  
GT7  
GT6  
GT5  
GT4  
GT3  
GT2  
GT1  
GT0  
Table 18 UART configuration register 1 (UCR11, 12 and 13) (read and write); address: 6  
(all relevant bits are cleared after reset)  
UC7  
UC6  
UC5  
UC4  
UC3  
UC2  
UC1  
UC0  
not used  
FIP  
FC  
PROT  
T/R  
LCT  
SS  
CONV  
2000 Nov 09  
18  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Table 19 Clock configuration register (CCR1, 2 and 3) (read and write); address: 1 (all bits are cleared after reset)  
CC7  
CC6  
CC5  
CC4  
CC3  
CC2  
CC1  
CC0  
not used  
not used  
SHL  
CST  
SC  
AC2  
AC1  
AC0  
Table 20 Power control register (PCR1 and 2) (read and write); address: 7 (all relevant bits are cleared after reset)  
PCR7  
PCR6  
PCR5  
PCR4  
PCR3  
PCR2  
PCR1  
PCR0  
not used  
not used  
C8  
C4  
1V8  
RSTIN  
3V/5V  
START  
Table 21 Register summary  
VALUE AT  
RESET  
NAME ADDR R/W  
7
6
5
4
3
2
1
0
CSR  
HSR  
MSR  
00  
0F  
0C  
R/W not  
not  
used  
not  
used  
not  
used  
RIU  
SC3  
SC2  
SC1  
XXXX0000  
used  
R
R
not  
used  
PRTL2 PRTL1 SUPL  
PRL2  
PR2  
PRL1  
PR1  
INTAUX PTL  
L
X0010000  
not  
FE  
BGT  
not  
INTAUX TBE/RF X10XXXX0  
used  
used  
TOR1 09  
TOR2 0A  
TOR3 0B  
W
W
W
TOL7  
TOL6  
TOL5  
TOL4  
TOL3  
TOL2  
TOL1  
TOL0  
TOL8  
00000000  
00000000  
TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9  
TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 00000000  
TOC  
UTR  
URR  
FCR  
08  
R/W TOC7  
TOC6  
UT6  
TOC5  
UT5  
TOC4  
UT4  
TOC3  
UT3  
TOC2  
UT2  
UR2  
FL2  
TOC1  
UT1  
UR1  
FL1  
TOC0  
UT0  
UR0  
FL0  
00000000  
00000000  
00000000  
X000X000  
0D  
0D  
0C  
W
R
UT7  
UR7  
UR6  
UR5  
UR4  
UR3  
W
not  
PEC2  
PEC1  
PEC0  
not  
used  
used  
USR  
0E  
R
TO3  
not  
used  
TO1  
EA  
PE  
OVR  
FER  
TBE/  
RBF  
0X000000  
PDR  
02  
R/W PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
PSC  
00000000  
X0000000  
UCR2 03  
R/W not  
used  
DISTBE DISAUX PDWN SAN  
/RBF  
AUTOC CKU  
GTR  
05  
R/W GT7  
GT6  
FIP  
GT5  
FC  
GT4  
GT3  
T/R  
GT2  
LCT  
GT1  
SS  
GT0  
00000000  
X0000000  
UCR1 06  
R/W not  
used  
PROT  
CONV  
CCR  
PCR  
01  
07  
R/W not  
used  
not  
used  
SHL  
C8  
CST  
C4  
SC  
AC2  
AC1  
AC0  
00000000  
R/W not  
used  
not  
used  
1V8  
RSTIN 3V/5V  
START XX110000  
2000 Nov 09  
19  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Supply  
This pulse may be used as a reset pulse by the system  
microcontroller (pin RSTOUT, active HIGH). It is also used  
in order to either block any spurious noise on card contacts  
during the microcontrollers reset, or to force an automatic  
deactivation of the contacts in the event of supply dropout  
(see Sections “Activation sequence” and “Deactivation  
sequence”).  
The circuit operates within a supply voltage range of  
2.7 to 6 V. The supply pins are VDD, VDDA, GND and  
AGND. Pins VDDA and AGND supply the analog drivers to  
the cards and have to be externally decoupled because of  
the large current spikes that the cards and the step-up  
converter can create. Pins VDD and GND supply the rest of  
the chip. An integrated spike killer ensures that the  
contacts to the cards remain inactive during power-up or  
power-down. An internal voltage reference is generated  
which is used within the step-up converter, the voltage  
supervisor and the VCC generators.  
After Power-on, or after a voltage drop, bit SUPL is set  
within the Hardware Status Register (HSR) and remains  
set until HSR is read-out outside the alarm pulse. Pin INT  
is LOW for the duration that RSTOUT is active.  
If needed, a complete reset of the chip may be performed  
The voltage supervisor generates an alarm pulse, whose  
length is defined by an external capacitor tied to pin  
DELAY, when VDD is too low to ensure proper operation  
(1 ms per 1 nF typical).  
by discharging the capacitor CDELAY.  
V
th1  
V
DD  
V
th2  
C
DELAY  
t
w
RSTOUT  
SUPL  
INT  
Status read  
Power-on  
Supply dropout  
Reset by C  
DELAY  
Power-off  
FCE683  
Fig.7 Voltage supervisor.  
2000 Nov 09  
20  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Step-up converter  
Activation sequence  
Except for the VCC generator and the other cards contacts  
When the cards are inactive, VCC, CLK, RST, C4, C8  
and I/O are LOW, with low-impedance with respect to  
GND. The step-up converter is stopped.  
buffers, the whole circuit is powered by VDD, and VDDA  
.
If the supply voltage is 2.5 V, then a higher voltage is  
needed for the ISO contacts supply. When a card session  
is requested by the microcontroller, the sequencer first  
enables the step-up converter (a switched capacitors type)  
which is clocked by an internal oscillator at a frequency of  
approximately 2.5 MHz.  
When everything is satisfactory (voltage supply, card  
present and no hardware problems), the system  
microcontroller may initiate an activation sequence on a  
present card.  
After selecting the card and leaving the UART reset mode,  
and then configuring the necessary parameters for the  
counters and the UART, the START bit can be set within  
the PCR (t0) (see Fig.8):  
Suppose that VCC is the maximum of VCC1 and VCC2, then  
there are four possible situations:  
1. VDD = 3 V and VCC = 3 V: in this case the step-up  
converter acts as a doubler with a regulation of  
approximately 4.0 V.  
• The step-up converter is started (t1); if one card was  
already active, then the step-up converter was already  
on and nothing more occurs at this step  
2. VDD = 3 V and VCC = 5 V: in this case the step-up  
converter acts as a tripler with a regulation of  
approximately 5.5 V.  
• VCC starts rising (t2) from 0 to 5 V or 3 V with a  
controlled rise time of 0.17 V/µs (typ.)  
3. VDD = 5 V and VCC = 3 V: in this case the step-up  
• I/O rises to VCC (t3); C4 and C8 also rise if bits  
C4 and C8 within the PCR have been set to logic 1  
converter acts as a follower: VDD is applied to VUP  
.
4. VDD = 5 V and VCC = 5 V: in this case the step-up  
converter acts as a doubler with a regulation of  
approximately 5.5 V.  
(integrated 10 kΩ pull-up resistors to VCC  
)
• The CLK is sent to the card and RST is enabled (t4).  
After a number of CLK pulses that can be counted with the  
time-out counter, bit RSTIN may be set by software: RST  
The recognition of the supply voltage is done by the  
TDA8007B at approximately 3.5 V.  
will then rise to VCC  
.
The output voltage VUP is fed to the VCC generators. VCC  
and GND are used as a reference for all other card  
contacts.  
The sequencer is clocked by 1⁄64fint which leads to a time  
interval of t = 25 µs (typ.). Thus t1 = 0 to 1⁄64t, t2 = t1 + 3⁄2t,  
t3 = t1 + 7⁄2t and t4 = t1 + 4t.  
ISO 7816 security  
Deactivation sequence  
The correct sequence during activation and deactivation of  
the cards is ensured by two specific sequencers, clocked  
by a division ratio of the internal oscillator.  
When the session is completed, the microcontroller resets  
START HIGH (t10). The circuit then executes an automatic  
deactivation sequence (see Fig.9):  
Activation (START bit HIGH in PCR1 or PCR2) is only  
possible if the card is present (PRES active HIGH with an  
internal current source to GND) and if the supply voltage is  
correct (supervisor not active).  
• The card is reset (RST falls LOW) (t11)  
• The CLK is stopped (t12)  
• I/O, C4 and C8 fall to 0 V (t13)  
• VCC falls to 0 V with typical 0.17 V/µs slew rate (t14)  
The presence of the cards is signalled to the  
microcontroller by the Hardware Status Register (HSR).  
• The step-up converter is stopped and CLK, RST, VCC  
and I/O become low-impedance to GND (t15) (if both  
cards are inactive).  
Bits PR1 or PR2 (in the USR) are set if card 1 or card 2 is  
present. PRL1 or PRL2 are set if PR1 or PR2 has toggled.  
t11 = t10 + 1⁄64t, t12 = t11 + 1⁄2t, t13 = t11 + t, t14 = t11 + 3⁄2t  
and t15 = t11 + 7⁄2t.  
During a session, the sequencer performs an automatic  
emergency deactivation on one card in the event of card  
take-off, or short-circuit. Both cards are automatically  
deactivated in the event of a supply voltage drop, or  
overheating. The hardware status register is updated and  
the INT line falls, so that the system microcontroller is  
aware of what happened.  
tde = time that VCC needs to decrease to less than 0.4 V.  
2000 Nov 09  
21  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
START  
V
UP  
V
CC  
I/O  
RSTIN  
CLK  
RST  
t
t
t
t
= t  
act  
ATR  
FCE684  
0
2
3
4
t
1
Fig.8 Activation sequence.  
START  
RST  
CLK  
I/O  
V
CC  
V
UP  
t
t
t
t
t
t
15  
FCE685  
10  
11  
12  
13  
14  
t
de  
Fig.9 Deactivation sequence.  
22  
2000 Nov 09  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
PARAMETER  
analog supply voltage  
CONDITIONS  
MIN.  
−0.5  
MAX.  
+6.5  
UNIT  
VDDA  
VDD  
Vn  
V
supply voltage  
−0.5  
−0.5  
+6.5  
V
V
input voltage on all pins except S1, S2, S3, S4  
and VUP  
VDD + 0.5  
input voltage on pins S1, S2, S3, S4 and VUP  
−0.5  
−5  
+7.5  
+5  
V
In1  
In3  
DC current into all pins except S1, S2, S3, S4  
and VUP  
mA  
DC current from or to pins S1, S2, S3, S4  
and VUP  
−200  
+200  
mA  
Ptot  
Tstg  
Tj  
total power dissipation  
IC storage temperature  
junction temperature  
Tamb = −20 to +85 °C  
−
700  
mW  
°C  
−55  
−
+150  
125  
°C  
Ves  
electrostatic discharge voltage  
on pins I/O1, VCC1, RST1, CLK1, GNDC1,  
PRES1, I/O2, VCC2, RST2, CLK2, GNDC2  
and PRES2  
−6  
+6  
kV  
on pins C41, C42, C81 and C82  
on pins D0 to D7  
−5.5  
−1.8  
−2  
+5.5  
+1.8  
+2  
kV  
kV  
kV  
on other pins  
HANDLING  
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is  
desirable to take normal precautions appropriate to handling MOS devices.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
from junction to ambient  
CONDITIONS  
in free air  
VALUE  
UNIT  
Rth(j-a)  
78  
K/W  
2000 Nov 09  
23  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
CHARACTERISTICS  
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VDD  
supply voltage  
2.7  
−
−
6.0  
V
IDD(pd)  
supply current in  
Power-down mode  
VDD = 3.3 V; cards inactive;  
XTAL oscillator stopped  
−
350  
µA  
VDD = 3.3 V; cards active at  
−
−
3
mA  
VCC = 5 V; CLK stopped;  
XTAL oscillator stopped  
IDD(sm)  
IDD(om)  
supply current in Sleep  
mode  
both cards powered, but with CLK  
stopped  
−
−
−
−
5.5  
mA  
mA  
supply current in operating  
mode  
ICC1 = 65 mA; ICC2 = 15 mA;  
fXTAL = 20 MHz; fCLK = 10 MHz;  
5 V cards; VDD = 2.7 V  
315  
ICC1 = 50 mA; ICC2 = 30 mA;  
fXTAL = 20 MHz; fCLK = 10 MHz;  
3 V cards; VDD = 2.7 V  
−
−
−
−
−
215  
100  
2.50  
mA  
mA  
V
ICC1 = 50 mA; ICC2 = 30 mA;  
fXTAL = 20 MHz; fCLK = 10 MHz;  
3 V cards; VDD = 5 V  
Vth1  
threshold voltage on VDD  
(falling)  
2.25  
Vhys1  
Vth2  
hysteresis on Vth1  
50  
−
170  
mV  
V
threshold voltage on pin  
DELAY  
−
1.25  
−
VDELAY  
voltage on pin DELAY  
−
−
−
1
−
−
VDD + 0.3  
V
Io(DELAY)  
output current at pin DELAY pin grounded (charge)  
DELAY = VDD (discharge)  
−2  
2
−
−
−
−
µA  
mA  
nF  
ms  
V
CDELAY  
capacitance value  
ALARM pulse width  
−
tW(ALARM)  
CDELAY = 22 nF  
10  
RSTOUT (open-drain active HIGH output)  
IOH  
VOL  
IOL  
HIGH-level output current  
LOW-level output voltage  
LOW-level output current  
HIGH-level output voltage  
active LOW option; VOH = 5 V  
active LOW option; IOL = 2 mA  
active HIGH option; VOL = 0 V  
−
−
−
−
−
10  
µA  
V
−0.3  
−
+0.4  
−10  
µA  
V
VOH  
active HIGH option; IOH = −1 mA 0.8VDD  
VDD + 0.3  
Crystal oscillator  
fXTAL crystal frequency  
fext  
4
0
−
−
25  
25  
MHz  
MHz  
external frequency applied  
to pin XTAL1  
2000 Nov 09  
24  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Step-up converter  
fint  
oscillation frequency  
voltage on pin VUP  
2
2.5  
5.7  
4.1  
3.5  
3.7  
MHz  
V
VVUP  
at least one 5 V card  
both cards 3 V  
−
−
−
−
V
Vdet(dt)  
detection voltage for  
3.4  
3.6  
V
doubler/tripler selection  
Reset output to the cards (RST1 and RST2)  
Vo(inactive)  
output voltage in inactive  
mode  
no load  
inactive = 1 mA  
0
0
0
−
−
−
0.1  
0.3  
−1  
V
I
V
IRST(inactive) current from pin RST when  
inactive and pin grounded  
mA  
VOL  
VOH  
tr  
LOW-level output voltage  
HIGH-level output voltage  
rise time  
IOL = 200 µA  
IOH =−200 µA  
CL = 30 pF  
0
−
−
−
−
0.3  
VCC  
0.1  
0.1  
V
V
−
−
CC − 0.7  
V
µs  
µs  
tf  
fall time  
CL = 30 pF  
Clock output to the cards (CLK1 and CLK2)  
Vo(inactive)  
output voltage in inactive  
mode  
no load  
0
0
0
−
−
−
0.1  
0.3  
−1  
V
Iinactive = 1 mA  
V
ICLK(inactive) current from pin CLK when  
inactive and pin grounded  
mA  
VOL  
VOH  
tr  
LOW-level output voltage  
HIGH-level output voltage  
rise time  
IOL = 200 µA  
IOH = −200 µA  
CL = 30 pF  
0
V
−
−
1
0
−
−
−
−
−
−
−
−
0.3  
VCC  
8
V
CC − 0.5  
V
ns  
tf  
fall time  
CL = 30 pF  
8
ns  
fCLK  
clock frequency  
1 MHz Idle configuration  
operational  
1.85  
10  
55  
−
MHz  
MHz  
%
δ
duty factor  
CL = 30 pF  
45  
SR  
slew rate (rise and fall)  
CL = 30 pF  
0.2  
V/ns  
2000 Nov 09  
25  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Card supply voltage (VCC1 and VCC2) (2 ceramic multilayer capacitors with low ESR of minimum 100 nF should  
be used in order to meet these specifications)  
Vo(inactive)  
output voltage in inactive  
mode  
no load  
inactive = 1 mA  
0
0
−
−
−
−
0.1  
0.3  
−1  
V
I
V
IVCC(inactive) current from pin VCC when  
inactive and pin grounded  
mA  
VCC  
output voltage  
active mode; ICC < 65 mA;  
5 V card  
4.75  
2.78  
4.6  
5
3
−
5.25  
3.22  
5.4  
V
V
V
active mode; ICC < 50 mA;  
3 V card  
active mode; current pulses of  
40 nC with I < 200 mA;  
t < 400 ns; f < 20 MHz; 5 V card  
active mode; current pulses of  
24 nC with I < 200 mA;  
2.75  
−
3.25  
V
t < 400 ns; f < 20 MHz; 3 V card  
ICC  
SR  
output current  
slew rate  
3 V card; from 0 to 3 V  
5 V card; from 0 to 5 V  
−
−
−
−50  
−65  
mA  
−
mA  
up or down; maximum  
capacitance = 300 nF  
0.05  
0.16 0.22  
V/µs  
I
CC1 + ICC2 sum of both cards current  
−
−
−80  
mA  
Data lines (I/O1 and I/O2) (I/O1 has an integrated 10 kΩ pull-up at VCC1 and I/O2 at VCC2  
)
Vo(inactive)  
output voltage in inactive  
mode  
no load  
0
−
−
−
−
−
0.1  
0.3  
−1  
V
Iinactive = 1 mA  
V
Io(inactive)  
VOL  
current from I/O when  
inactive and pin grounded  
mA  
LOW-level output voltage  
I/O configured as an output;  
IOL = 1 mA  
0
−
−
0.3  
V
VOH  
HIGH-level output voltage  
I/O configured as an output;  
0.8VCC  
VCC + 0.25 V  
IOH < −40 µA  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
I/O configured as an input  
I/O configured as an input  
VIL = 0  
−0.3  
1.5  
−
−
−
−
+0.8  
VCC  
600  
V
V
LOW-level input current  
on I/O  
µA  
ILI(H)  
input leakage current HIGH VIH = VCC  
on I/O  
−
−
20  
µA  
ti(tr), ti(tf)  
input transition times  
output transition times  
CL < = 30 pF  
CL < = 30 pF  
−
−
8
−
1
µs  
µs  
kΩ  
to(tr), to(tf)  
−
0.1  
12  
Rpu  
internal pull-up resistance  
between I/O and VCC  
10  
2000 Nov 09  
26  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Auxiliary cards contacts (pins C41, C81, C42 and C82) (pins C41 and C81 have an integrated 10 kΩ pull-up  
at VCC1, pins C42 and C82 have an integrated 10 kΩ pull-up at VCC2  
)
Vo(inactive)  
output voltage inactive  
no load  
inactive = 1 mA  
0
−
−
−
−
−
0.1  
0.3  
−1  
V
I
V
Iinactive  
current from pins C4 or C8  
when inactive and pin  
grounded  
mA  
VOL  
VOH  
LOW-level output voltage  
C4 or C8 configured as an output;  
OL = 1 mA  
0
−
−
0.3  
V
I
HIGH-level output voltage  
I/O configured as an output;  
0.8VCC  
VCC + 0.25 V  
IOH < −40 µA  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level output voltage  
C4 or C8 configured as an input  
C4 or C8 configured as an input  
VIL = 0  
−0.3  
1.5  
−
−
−
−
+0.8  
VCC  
600  
V
V
LOW-level input current on  
pins C4 or C8  
µA  
ILI(H)  
input leakage current HIGH VIH = VCC  
on pins C4 or C8  
−
−
20  
µA  
t
i(tr), ti(tf)  
input transition times  
CL = 30 pF  
CL = 30 pF  
−
−
−
8
−
1
µs  
µs  
ns  
kΩ  
to(tr), to(tf)  
output transition times  
width of active pull-up pulse  
−
0.1  
−
tW(pu)  
200  
10  
Rint(pu)  
internal pull-up resistance  
between C4/C8 and VCC  
12  
f(max)  
maximum frequency on  
C4 or C8  
−
−
1
MHz  
Timing  
tact  
tde  
activation sequence duration  
−
−
−
−
130  
150  
µs  
µs  
deactivation sequence  
duration  
Protections and limitations  
ICC(sd)  
shutdown and limitation  
−
−100  
−
mA  
current at VCC  
II/O(lim)  
ICLK(lim)  
IRST(sd)  
limitation current on the I/O  
limitation current on pin CLK  
−15  
−70  
−20  
−
−
−
+15  
+70  
+20  
mA  
mA  
mA  
shutdown and limitation  
current on RST  
Tsd  
shutdown temperature  
−
150  
−
°C  
Card presence inputs 1s (pins PRES1 and PRES2)  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
input leakage current LOW  
−
−
−
−
−
0.3VDD  
−
V
VIH  
0.7VDD  
−20  
−20  
V
IIL(L)  
IIL(H)  
VIN = 0  
+20  
+20  
µA  
µA  
input leakage current HIGH VIN = VDD  
2000 Nov 09  
27  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Bidirectional data bus (pins D0 to D7)  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
input leakage current LOW  
input leakage current HIGH  
load capacitance  
−
−
−
−
−
−
−
−
−
0.3VDD  
−
V
VIH  
0.7VDD  
V
IIL(L)  
IIL(H)  
CL  
−20  
+20  
+20  
10  
µA  
µA  
pF  
V
−20  
−
VOL  
VOH  
LOW-level output voltage  
HIGH-level output voltage  
output transition time  
IOL = 5 mA  
−
0.2VDD  
−
IOH = −5 mA  
0.8VDD  
V
to(tr), to(tf)  
CL = 50 pF  
−
25  
ns  
Logic inputs (pins ALE, A0, A1, A2, A3, INTAUX, CS, RD and WR)  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
input leakage current LOW  
input leakage current HIGH  
load capacitance  
−0.3  
0.7VDD  
−20  
−20  
−
−
−
−
−
−
+0.3VDD  
VDD + 0.3  
+20  
V
VIH  
IIL(L)  
IIL(H)  
CL  
V
µA  
µA  
pF  
+20  
10  
Auxiliary I/O (pin I/OAUX)  
VIL  
LOW-level input voltage  
−0.3  
−
+0.3VDD  
VDD + 0.3  
+20  
V
VIH  
HIGH-level input voltage  
input leakage current HIGH  
LOW-level input current  
LOW-level output voltage  
HIGH-level output voltage  
0.7VDD  
−
V
IIL(H)  
IIL  
−20  
−
µA  
µA  
mV  
V
VIL = 0  
−
−
−600  
VOL  
VOH  
Rint(pu)  
IOL = 1 mA  
IOH = 40 µA  
−
−
300  
0.8VDD  
8
−
VDD +0.25  
12  
internal pull-up resistance  
between I/OAUX and VDD  
10  
kΩ  
t
i(tr), ti(tf)  
input transition time  
output transition time  
CL = 30 pF  
CL = 30 pF  
−
−
−
−
−
−
1
µs  
to(tr), to(tf)  
0.1  
1
µs  
fI/OAUX(max) maximum frequency on pin  
I/OAUX  
MHz  
Interrupt line INT (open-drain active LOW output)  
VOH  
IIL(H)  
LOW-level output voltage  
input leakage current HIGH  
IOH = 2 mA  
−
−
−
−
0.3  
10  
V
µA  
2000 Nov 09  
28  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Timing for multiplexed bus; see Fig.4  
tXTAL1  
period on XTAL1  
50  
20  
10  
10  
−
−
−
−
−
−
−
−
ns  
ns  
ns  
ns  
tW(ALE)  
tAVLL  
ALE pulse width  
address valid to ALE LOW  
t(AL−RWL)  
ALE LOW to RD or  
WR LOW  
tW(RD)  
RD pulse width for URR  
2tXTAL1  
10  
−
−
−
−
ns  
ns  
pulse width for other  
registers  
t(RL−DV)  
RD LOW to data out valid  
−
−
−
50  
ns  
ns  
t(RWH−AH)  
RD or WR HIGH to  
ALE HIGH  
10  
−
tW(WR)  
WR pulse width  
10  
10  
−
−
−
−
ns  
ns  
t(DV−WL)  
data in valid to WR LOW  
Timing for non-multiplexed bus; see Fig.5  
t(REH−CL) RD or EN HIGH to CS LOW  
t(CEL−DV) CS and EN LOW to data out when reading from URR; t(CEL−DV)  
10  
−
−
−
ns  
ns  
−
50  
valid  
is minimum 2tXTAL1  
t(CEH−DZ)  
t(AD−DV)  
CS and EN HIGH to data  
high-impedance  
−
−
−
−
10  
10  
ns  
ns  
addresses stable to data out  
valid  
t(RL−CEL)  
R/W LOW to CS or EN LOW  
10  
−
−
−
−
ns  
ns  
t(CREL−DZ)  
CS and R/W and EN LOW  
to data in high-impedance  
−
t(DV−WL)  
DATA valid to WR LOW  
10  
−
−
ns  
2000 Nov 09  
29  
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V
DD  
TP23 CS 8007B  
TP4  
3 V or  
5 V  
J1  
J1  
1
2
+5 V  
C3  
33 µF  
16 V  
TP22 INT  
TP20 WR  
TP18 ALE  
C15  
22 pF  
C14  
C12  
100 nF  
TP8  
GND  
V
Y2  
P2.0  
P2.1  
P2.2  
P2.3  
P2.4  
P2.5  
P2.6  
P2.7  
LPSEN  
ALE  
SS  
GND  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
R2  
XTAL1  
XTAL2  
P3.7  
P3.6  
P3.5  
P3.4  
P3.3  
P3.2  
P3.1  
P3.0  
RST  
P1.7  
P1.6  
P1.5  
P1.4  
P1.3  
P1.2  
P1.1  
P1.0  
0 Ω  
V
DD  
22 pF  
C23  
V
DD  
C4  
C3  
C2  
C1  
C51  
C61 C21  
C71 C31  
C81 C41  
C8  
C7  
C6  
C5  
C11  
100 nF  
C17  
100  
nF  
R1  
100 kΩ  
RSTOUT  
I/OAUX  
I/O1  
RD  
36  
1
TX  
RX  
D7  
89C51  
LEA  
2
35  
D6  
34  
7
6
5
4
3
2
1
0
P0.7  
P0.6  
P0.5  
P0.4  
P0.3  
P0.2  
P0.1  
P0.0  
3
7
6
5
4
3
2
1
0
V
C81  
D5  
8
DD  
4
33  
PRES1  
C41  
D4  
32  
7
5
K1  
K2  
6
D3  
6
31  
TDA8007B  
5
CARD_READ_LM01  
U5  
GNDC1  
CLK1  
D2  
30  
IC1  
7
4
D1  
8
29  
3
V
D0  
28  
CC1  
CARD 1  
2
9
P0(7:0)  
V
V
V
CC  
RST1  
I/O2  
DD  
FCE690  
1
C19  
100 nF  
10  
11  
12  
27  
SAM  
26  
C16  
AGND  
25  
C82  
R3  
0 Ω  
DD  
C1  
100 nF  
C22  
10 µF  
16 V  
100  
nF  
TP51  
GND  
V
DD  
C4  
C3  
C2  
C1  
C51  
C8  
C7  
C6  
C5  
C11  
C18  
100  
nF  
C61 C21  
C71 C31  
C81 C41  
C26  
100 nF  
C25  
100  
nF  
C27  
100 nF  
K1  
K2  
C24  
100 nF  
CARD_READ_LM01  
R4  
100 kΩ  
C13  
100 nF  
U6  
CARD 2  
C2  
V
DD  
10 µF  
16 V  
V
DD  
Fig.10 Application diagram.  
ahdnbok,uflapegwidt  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
PACKAGE OUTLINE  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.60  
mm  
0.25  
0.5  
1.0  
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
99-12-27  
00-01-19  
SOT313-2  
136E05  
MS-026  
2000 Nov 09  
31  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
SOLDERING  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
Introduction to soldering surface mount packages  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering is not always suitable  
for surface mount ICs, or for printed-circuit boards with  
high population densities. In these situations reflow  
soldering is often used.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
The footprint must incorporate solder thieves at the  
downstream end.  
Reflow soldering  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Several methods exist for reflowing; for example,  
infrared/convection heating in a conveyor type oven.  
Throughput times (preheating, soldering and cooling) vary  
between 100 and 200 seconds depending on heating  
method.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 230 °C.  
Manual soldering  
Wave soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
If wave soldering is used the following conditions must be  
observed for optimal results:  
2000 Nov 09  
32  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE  
BGA, LFBGA, SQFP, TFBGA  
WAVE  
not suitable  
REFLOW(1)  
suitable  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS  
PLCC(3), SO, SOJ  
not suitable(2)  
suitable  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2000 Nov 09  
33  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS  
STATUS  
DEFINITIONS (1)  
Objective specification  
Development This data sheet contains the design target or goal specifications for  
product development. Specification may change in any manner without  
notice.  
Preliminary specification Qualification  
This data sheet contains preliminary data, and supplementary data will be  
published at a later date. Philips Semiconductors reserves the right to  
make changes at any time without notice in order to improve design and  
supply the best possible product.  
Product specification  
Production  
This data sheet contains final specifications. Philips Semiconductors  
reserves the right to make changes at any time without notice in order to  
improve design and supply the best possible product.  
Note  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2000 Nov 09  
34  
Philips Semiconductors  
Product specification  
Double multiprotocol IC card interface  
TDA8007B  
NOTES  
2000 Nov 09  
35  
Philips Semiconductors – a worldwide company  
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Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
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