TDA8007BHL/C3,118_技术文档

TDA8007BHL

Multiprotocol IC card interface

Rev. 9.1 — 18 June 2012

Product data sheet

1. General description

The TDA8007BHL is a cost-effective card interface for dual smart card readers.

Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11,

EMV4.2 and EMV 2000. It is addressed on a non-multiplexed 8-bit databus, by means of

address registers AD0, AD1, AD2 and AD3. TDA8007BHL/C3 can be also addressed

through a multiplexed access. The integrated ISO UART and the time-out counters allow

easy use even at high baud rates with no real time constraints. Due to its chip select,

external input/output and interrupt features, it greatly simplifies the realization of a reader

of any number of cards. It gives the cards and the reader a very high level of security, due

to its special hardware against ESD, short-circuiting, power failure, etc. The integrated

step-up converter allows operation within a supply voltage range of 2.7 V to 6 V.

TDA8007BHL/C4 supports only non multiplex access and TDA8007BHL/C3 support both

non multiplexed and multiplexed access.

2. Features and benefits

 Control and communication through an 8-bit parallel interface, compatible with

non-multiplexed memory access, TDA8007BHL/C3 can be also addressed through a

multiplexed memory access

 Specific ISO UART with parallel access input/output for automatic convention

processing, variable baud rate through frequency or division ratio programming, error

management at character level for T = 0 and extra guard time register

 FIFO for 1 to 8 characters in reception mode

 Parity error counter in reception mode and in transmission mode with automatic

re-transmission

 Dual VCC generation: 5 V ± 5 %, 65 mA (max.); 3 V ± 8 %, 50 mA (max.) or

1.8 V ± 10 %, 30 mA (max.); with controlled rise and fall times

 Dual cards clock generation (up to 10 MHz), with three times synchronous frequency

doubling (f_XTAL, ¹⁄₂f_XTAL, ¹⁄₄f_XTALand ¹⁄₈f_XTAL

)

 Cards clock stop (at high or low level) or 1.25 MHz (from internal oscillator) for cards

Power-down mode

 Automatic activation and deactivation sequence through an independent sequencer

 Supports the asynchronous protocols T = 0 and T = 1 in accordance with:

ISO 7816 and EMV4.2

 Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times

processing

 Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT): 22 in T = 1

and 16 in T = 0

 Minimum delay between two characters in reception mode:

TDA8007BHL

NXP Semiconductors

Multiprotocol IC card interface

– in Protocol T = 0: 11.8 ETU

– in Protocol T = 1: 10.8 ETU

 Supports synchronous cards

 Current limitations in the event of short-circuit (pins I/O1, I/O2, VCC1, VCC2, RST1

and RST2)

 Special circuitry for killing spikes during power-on/power-off

 Supply supervisor for power-on/power-off reset

 Step-up converter (supply voltage from 2.7 V to 6 V), doubler, tripler or follower

according to V_CCand V_DD

 Additional input/output pin allowing use of the ISO UART for another analog interface

(pin I/OAUX)

 Additional interrupt pin allowing detection of level toggling on an external signal (pin

INTAUX)

 Fast and efficient swapping between the three cards due to separate buffering of

parameters for each card

 Chip select input allowing use of several devices in parallel and memory space paging

 Enhanced ESD protections on card side (except C4x, C8x): 6 kV (min.)

 Software library for easy integration within the application

 Power-down mode for reducing current consumption when no activity.

3. Applications

 Multiple smart card readers for multiprocessor applications (EMV banking, digital pay

TV and access control, etc.).

4. Quick reference data

Table 1.

Quick reference data

V_DD= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb= 25 C; unless otherwise specified.

Symbol

V_DD

Parameter

supply voltage

analog

Conditions

Min

2.7

Typ

Max

6.0

Unit

V

-

V_DDA

step-up converter

cards inactive; f_XTAL= 0 Hz

V_DD

6.0

V

supply voltage

I_DD(pd)

supply current in

power-down mode

-

350

3

A

cards active; V_CC= 5 V; f_CLK= 0 Hz;

f_XTAL= 0 Hz

mA

I_DD(sm)

supply current in sleep

mode

cards active; f_CLK= 0 Hz

-

5.5

mA

I_DD(oper)

supply current in

operating mode

I_CC1= 65 mA; I_CC2= 15 mA; f_XTAL= 20 MHz;

f_CLK= 10 MHz; V_DD= 2.7 V

315

TDA8007BHL

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Product data sheet

Rev. 9.1 — 18 June 2012

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TDA8007BHL

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Multiprotocol IC card interface

Table 1.

Quick reference data …continued

V_DD= 3.3 V; f_XTAL= 10 MHz; GND = 0 V; T_amb= 25 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC

card supply output

voltage

5 V card

including static loads

4.75

4.6

5.0

-

5.25

5.4

V

with 40 nC dynamic loads on 200 nF

capacitor

3 V card

including static loads

2.78

2.75

-

3.22

3.25

V

with 24 nC dynamic loads on 200 nF

capacitor

1.8 V card

including static loads

1.65

1.62

-

1.95

1.98

V

with 12 nC dynamic loads on 200 nF

capacitor

I_CC

card supply output

current

5 V card; operating

3 V card; operating

1.8 V card; operating

overload detection

-

65

50

30

-

mA

-

100

-

I_CC1+ I_CC2sum of both card supply operating; 5 and 3 V cards

output currents

80

SR

slew rate on V_CC(rise

and fall)

C_L(max)= 300 nF

0.05

-

0.16

-

0.22

150

V/s

s

t_deact

deactivation cycle

duration

t_act

activation cycle duration

crystal frequency

-

225

20

s

f_XTAL

f_ext

4

-

MHz

°C

external frequency

ambient temperature

applied to pin XTAL1

0

20

T_amb

40

+85

5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TDA8007BHL/C3 LQFP48

TDA8007BHL/C4 LQFP48

plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm

SOT313-2

TDA8007BHL

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6. Block diagram

V

DD

V

DDA

100 nF

220 nF

GND

19

SAP SAM

SBP SBM

AGND

27

23 21

26

22

24 25

1

RSTOUT

DELAY

SUPPLY

AND

SUPERVISOR

STEP-UP

CONVERTER

V

UP

48

20

220 nF

22 nF

40

39

45

44

43

42

36

37

28

29

30

31

32

33

34

35

38

2

6

INT

ALE

AD0

AD1

AD2

AD3

RD

C41

4

C81

8

CLK1

10

RST1

ISO7816

UART

9

V

CC1

3

I/O1

5

WR

D0

PRES1

ANALOG

DRIVERS

AND

7

CGND1

D1

14

C42

SEQUENCERS

D2

12

TIME-OUT

COUNTER

C82

D3

16

CLK2

D4

18

D5

RST2

17

D6

V

CC2

CLOCK

CIRCUIT

11

13

15

D7

I/O2

CS

PRES2

CGND2

I/OAUX

INTAUX

41

INT OSC

TDA8007B

XTAL OSC

47

46

XTAL2

XTAL1

fce534

Fig 1. Block diagram

TDA8007BHL

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7. Pinning information

7.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

RSTOUT

I/OAUX

I/O1

RD

D7

D6

D5

D4

D3

D2

D1

D0

3

4

C81

5

PRES1

C41

6

TDA8007BHL

7

CGND1

CLK1

8

9

V

CC1

10

11

12

RST1

I/O2

V

DD

SAM

C82

AGND

fce678

Fig 2. Pin configuration

7.2 Pin description

Table 3.

Pin description

Symbol

Description

RSTOUT

1

PMOS open-drain output for resetting external

devices

I/OAUX

I/O1

2

3

4

input or output for an I/O line from an auxiliary smart

card interface

input or output for the data line to/from card 1

(ISO C7 contact)

C81

auxiliary I/O for ISO C8 contact (synchronous cards,

for instance) for card 1

PRES1

C41

5

6

card 1 presence contact input (active high)

auxiliary I/O for ISO C4 contact (synchronous cards,

for instance) for card 1

CGND1

CLK1

V_CC1

7

ground for card 1; must be connected to GND

clock output to card 1 (ISO C3 contact)

card 1 supply output voltage (ISO C1 contact)

card 1 reset output (ISO C2 contact)

8

9

RST1

I/O2

10

11

input or output for the data line to/from card 2

(ISO C7 contact)

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Table 3.

Pin description …continued

Symbol

Description

C82

12

auxiliary I/O for ISO C8 contact (synchronous cards,

for instance) for card 2

PRES2

C42

13

14

card 2 presence contact input (active high)

auxiliary I/O for ISO C4 contact (synchronous cards,

for instance) for card 2

CGND2

CLK2

V_CC2

15

16

17

18

19

20

ground for card 2; must be connected to GND

clock output to card 2 (ISO C3 contact)

card 2 supply output voltage (ISO C1 contact)

card 2 reset output (ISO C2 contact)

ground

RST2

GND

V_UP

connection for the step-up converter capacitor;

connect a low ESR capacitor of 220 nF to AGND

SAP

SBP

V_DDA

SBM

21

22

23

24

contact 1 for the step-up converter; connect a low

ESR capacitor of 220 nF between pins SAP

and SAM

contact 3 for the step-up converter; connect a low

ESR capacitor of 220 nF between pins SBP

and SBM

positive analog supply voltage for the step-up

converter; may be higher than V_DD; decouple with a

good quality capacitor to GND

contact 4 for the step-up converter; connect a low

ESR capacitor of 220 nF between pins SBP

and SBM

AGND

SAM

25

26

analog ground for the step-up converter

contact 2 for the step-up converter; connect a low

ESR capacitor of 220 nF between pins SAP

and SAM

V_DD

27

positive supply voltage; decouple with a good quality

capacitor to GND

D0 to D7

28, 29, 30, 31, 32, 33,

34, 35

input/output of data 0-7;

TDA8007BHL/C3 in case of mulitplexed

configuration: address 0-7

RD

36

read or write selection input; high for read, low for

write

WR

CS

37

38

39

enable pin; same behavior as CS\ (active low)

chip select input (active low)

ALE

TDA8007BHL/C4: Not connected;

TDA8007BHL/C3: address latch enable input in

case of multiplexed configuration, connect to V_DDin

non-multiplexed configuration

INT

40

41

42

43

44

NMOS interrupt output (active low)

auxiliary interrupt input

INTAUX

AD3

register selection address 3 input

register selection address 2 input

register selection address 1 input

AD2

AD1

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Table 3.

Pin description …continued

Symbol

AD0

45

Description

register selection address 0 input

connection for an external crystal

XTAL2

XTAL1

46

47

connection for an external crystal or input for an

external clock signal

DELAY

48

connection for an external delay capacitor

8. Functional description

Remark: Throughout this document, it is assumed that the reader is familiar with ISO7816

terminology.

8.1 Interface control

The TDA8007BHL/C3 is sensitive to ESD in functional mode. This sensitivity is seen on

pin ALE: an electrostatic discharge causes an edge on this pin and changes its mode of

communication. When the mode of communication is the multiplexed mode, this has no

impact. But when the mode used is the non-multiplexed mode, the ESD may change the

mode to multiplexed mode, which is irreversible without power-off/power-on.

The TDA8007BHL/C4 is an evolution of the C3 version in which the communication mode

is set to non-multiplexed and can not be changed.

8.1.1 Non-Multiplexed configuration

The TDA8007BHL/C4 is only in the non-multiplexed configuration (Figure 3), where the

TDA8007BHL/C3 offers a multiplexed configuration in addition to a non-mulitplexed

configuration. The configuration can be chosen through the ALE-pin. If pin ALE is tied to

V

_DDor ground, the TDA8007BHL/C3 will be in the non-multiplexed configuration.

The TDA8007BHL can be controlled via an 12-bit parallel bus (bits D0 to D7 and bits A0 to

A3). The address bits are determined by means of pins AD0 to AD3. The read or write

control signal is on pin RD and a data write or read active low enable signal is on pin WR.

Signals CS and WR play the same role.

In read operations (see Figure 4) with signal RD = high, the data corresponding to the

chosen address is available on the bus when both signals CS and WR are low.

In write operations (see Figure 5 and 6) with signal RD = low, the data present on the bus

is written when signals CS and WR are low.

In both configurations, the TDA8007BHL/C4 is selected only when signal CS = low.

Signal INT is an active low interrupt signal.

TDA8007BHL

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Multiprotocol IC card interface

CS

D0 to D7

AD0 to AD3

WR

RD

REC

REGISTERS

001aam017

Fig 3. Non-multiplexed bus configuration

AD0 to AD3

RD

t

3

2

1

CS

WR

D0 to D7

DATA OUT

fce840

Fig 4. Control with non-multiplex bus (read)

TDA8007BHL

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AD0 to AD3

RD

t

7

CS

t

6

WR

t

5

4

D0 to D7

DATA IN

fce841

Fig 5. Control with non-multiplex bus (Write with CS)

AD0 to AD3

RD

t

7

CS

WR

t

5

6

4

D0 to D7

DATA IN

fce842

Fig 6. Control with non-multiplex bus (Write with EN)

8.1.2 Multiplexed configuration

The TDA8007BHL/C3 offers a multiplexed configuration in addition to a nun multiplexed

configuration.

The TDA8007BHL/C4 does not offer the multiplexed configuration.

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If a microcontroller with a multiplexed address and data bus (such as 80C51) is used, then

pins D0 to D7 may be directly connected to port P0 to P7, see Figure 7. Automatic

switching to the multiplexed bus configuration occurs only for TDA8007BHL/C3, if a rising

edge is detected on signal ALE.

In this event, pins AD0 to AD3 play no role and may be tied to VDD or ground.

When signal CS = low, the demulitplexing of address and data is performed internally

using signal ALE, a low pulse on pin RD allows the selected register to be read, a LOW

pulse on pin WR allows the selected register to be written to, see Figure 8. Using a 80C51

microcontroller, the TDA8007BHL/C3 is simply controlled with MOVX instructions.

AD0 to AD3

CS

D0 to D7

ALE

WR

RD

LATCH

REC

MUX

addresses

RD

REGISTERS

WR

fce679

Fig 7. Multiplexed bus recognition

ALE

t

AVLL

W(RD)

t

(RWH-AH)

W(ALE)

t

(RWH-AH)

AVLL

t

(AL-RWL)

CS

t

(AL-RWL)

DATA

READ

ADDRESS

D0 to D7

DATA WRITE

t

(DV-WL)

RD

t

(RL-DV)

W(WR)

WR

fce680

Fig 8. Control with multiplexed bus (read and write)

8.2 Control registers

The TDA8007BHL has two complete analog interfaces which can drive cards 1 and 2.

The data to and from these two cards shares the same ISO UART. The data to and from a

third card (card 3), externally interfaced (with a TDA8020 or TDA8004 for example), may

also share the same ISO UART.

TDA8007BHL

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Multiprotocol IC card interface

Cards 1, 2 and 3 have dedicated registers for setting the parameters of the ISO UART

(see Figure 9).

Programmable Divider Register (PDR)

Guard Time Register (GTR)

UART Configuration register 1 (UCR1)

UART Configuration Register 2 (UCR2)

Clock Configuration Register (CCR)

Cards 1 and 2 also have dedicated registers for controlling their power and clock

configuration. The Power Control Register (PCR) for card 3 is controlled externally.

Register PCR is also used for writing or reading on the auxiliary card contacts C4 and C8.

Card 1, 2 or 3 can be selected via the Card Select Register (CSR). When one card is

selected, the corresponding parameters are used by the ISO UART. Register CSR also

contains one bit for resetting the ISO UART (bit RIU = 0). This bit is reset after power-on

and must be set to logic 1 before starting with any one of the cards. It may be reset by

software when necessary.

When the specific parameters of the cards have been programmed, the UART may be

used with the following registers:

UART Receive Register (URR)

UART Transmit Register (UTR)

UART Status Register (USR)

Mixed Status Register (MSR).

In reception mode, a FIFO of 1 to 8 characters may be used and is configured with the

FIFO Control Register (FCR). This register is also used for the automatic re-transmission

of Not AcKnowledged (NAK) characters in transmission mode.

The Hardware Status Register (HSR) gives the status of the supply voltage, of the

hardware protections and of the card movements.

Registers HSR and USR give interrupts on pin INT when some of their bits have been

changed.

Register MSR does not give interrupts and may be used in the polling mode for some

operations; for this use, some of the interrupt sources within the registers USR and HSR

may be masked.

A 24-bit time-out counter may be started to give an interrupt after a number of ETU

programmed into the Time-Out Registers TOR1, TOR2 and TOR3. This will help the

microcontroller in processing different real-time tasks (ATR, WWT, BWT, etc.). This

counter is configured with a Time-Out counter Configuration (TOC) register. It may be

used as a 24-bit counter or as a 16-bit plus 8-bit counter. Each counter can be set to start

counting once data has been written, or on detection of a START bit on the I/O, or as

auto-reload.

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8.2.1 General registers

8.2.1.1 Card select register

The Card Select Register (CSR) is used for selecting the card on which the UART will act,

and also to reset the ISO UART.

Table 4.

7

Register CSR (address 00h; write and read)^[1]

6

5

4

3

2

1

0

CS7

CS6

CS5

CS4

RIU

SC3

SC2

SC1

[1] Register value at reset: all significant bits are cleared after reset, except bits CS7 to CS4 which are set to

their default value

Table 5.

Register CSR (address 00h; write and read)^[1]

Bit

7

Symbol

CS7

Description

IC identifier: default value for identification the IC

0010 = TDA8007BHL/C2

6

CS6

0011 = TDA8007BHL/C3 or TDA8007BHL/C4

5

CS5

4

CS4

3

RIU

reset ISO UART: When reset, this bit resets a large part of the UART

registers to their initial value. Bit RIU must be reset before any

activation; logic 0 for at least 10 ns duration. Bit RIU must be set to

logic 1 by software before any action on the UART can take place.

2

1

0

SC3

SC2

SC1

select card 3: If bit SC3 = 1, then card 3 is selected.

select card 2: If bit SC2 = 1, then card 2 is selected.

select card 1: If bit SC1 = 1, then card 1 is selected.

[1] Bits SC1, SC2 and SC3 must be set at one at a time. After reset no card is selected by default

8.2.1.2 Hardware status register

The Hardware Status Register (HSR) gives the status of the chip after a hardware

problem has been detected.

Table 6.

7

Register HSR (address 0Fh; read only)^[1]

6

5

4

3

2

1

0

HS7

PRTL2

PRTL1

SUPL

PRL2

PRL1

INTAUXL PTL

[1] Register value at reset: all significant bits are cleared after reset, except bit SUPL which is set within

pulse RSTOUT.

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Table 7.

Description of HSR bits

Bit

7

Symbol

HS7

Description

not used

6

PRTL2

protection 2: Bit PRTL2 = 1 when a fault has been detected on card

reader 2. Bit PRTL 2 is the OR-function of the protection on pin V_CC2

and pin RST2.

5

PRTL1

protection 1:. Bit PRTL1 = 1 when a fault has been detected on card

reader 1. Bit PRTL 1 is the OR-function of the protection on pin V_CC1

and pin RST1.

4

3

2

1

0

SUPL

PRL2

PRL1

INTAUXL

PTL

supervisor latch. Bit SUPL = 1 when the supervisor has been

activated.

presence latch 2: Bit PRL2 = 1 when a level change has occurred on

pin PRES2.

presence latch 1: Bit PRL1 = 1 when a level change has occurred on

pin PRES1.

auxiliary interrupt change: Bit INTAUXL = 1 if the level on

pin INTAUX has been changed.

overheating: Bit PTL = 1 if overheating has occurred.

When at least one of the bits PRTL2, PRTL1, PRL2, PRL1 or PTL is high, then INT is low.

The bits having caused the interrupt are cleared when register HSR has been read-out.

The same occurs with INTAUXL, if not disabled.

In case of an emergency deactivation (by bits PRTL2, PRTL1, SUPL, PRL2, PRL1

or PTL), bit START (bit 0 in the PCR) is automatically reset by hardware.

At power-on, or after a supply voltage drop-out, bit SUPL is set and pin INT = low. Pin INT

will return to high level at the end of the alarm pulse RSTOUT (see Figure 3).

Bit SUPL will be reset only after a status register read-out outside the alarm pulse.

A minimum time of 2 µs is needed between two successive read operations of

register HSR, as well as between reading of register HSR and activation (write in

register PCR).

8.2.1.3 Time-out registers

The three Time-Out Registers (TOR1, TOR2 and TOR3) form a programmable 24-bit ETU

counter, or two independent counters (one 16-bit and one 8-bit). The value to load in

registers TOR1, TOR2 and TOR3 is the number of ETU to count. The time-out counters

may only be used when a card is active with a running clock.

Table 8.

7

Register TOR1 (address 09H; write only)^[1]

6

5

4

3

2

1

0

TOL7

TOL6

TOL5

TOL4

TOL3

TOL2

TOL1

TOL0

[1] Register value at reset: all bits are cleared after reset.

Table 9.

7

Register TOR2 (address 0AH; write only)^[1]

6

5

4

3

2

1

0

TOL15

TOL14

TOL13

TOL12

TOL11

TOL10

TOL9

TOL8

[1] Register value at reset: all bits are cleared after reset.

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Table 10. Register TOR3 (address 0Bh; write only)^[1]

7

6

5

4

3

2

1

0

TOL23

TOL22

TOL21

TOL20

TOL19

TOL18

TOL17

TOL16

[1] Register value at reset: all bits are cleared after reset.

8.2.1.4 Time-out configuration register

The Time-Out Configuration (TOC) register is used for setting different configurations of

the time-out counter as given in Table 11; all other configurations are undefined.

Table 11. Register TOC (address 0Bh; read and write)^[1]

7

6

5

4

3

2

1

0

TOC7

TOC6

TOC5

TOC4

TOC3

TOC2

TOC1

TOC0

[1] Register value at reset: all bits are cleared after reset.

Table 12. Card registers (address 00h to F5h

Register Description

00H

05H

61H

All counters are stopped.

Counters 2 and 3 are stopped; counter 1 continues to operate in auto-reload mode.

Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value

stored in registers TOR3 and TOR2 is started after 61H is written in register TOC. An

interrupt is given, and bit TO3 is set within register USR when the terminal count is

reached. The counter is stopped by writing 00H in register TOC, and should be

stopped before reloading new values in registers TOR2 and TOR3.

65H

Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.

Counter 1 starts counting the content of register TOR1 on the first START bit

(reception or transmission) detected on pin I/O after 65H is written in register TOC.

When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in

register USR is set, and the counter automatically restarts the same count until it is

stopped. It is not allowed to change the content of register TOR1 during a count.

Counters 3 and 2 are wired as a single 16-bit counter and start counting the value in

registers TOR3 and TOR2 when 65H is written in register TOC. When the counter

reaches its terminal count, an interrupt is given and bit TO3 is set within register USR.

Both counters are stopped when 00H is written in register TOC. Counters 3 and 2

shall be stopped by writing 05H in register TOC before reloading new values in

registers TOR2 and TOR3.

68H

71H

Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in

registers TOR3, TOR2 and TOR1 is started after 68H is written in register TOC. The

counter is stopped by writing 00H in register TOC. It is not allowed to change the

content of registers TOR3, TOR2 and TOR1 within a count.

Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value

stored in registers TOR3 and TOR2 and is started on the first START bit detected on

pin I/O (reception or transmission) after the value has been written, and then on each

subsequent START bit. It is possible to change the content of registers TOR3 and

TOR2 during a count; the current count will not be affected and the new count value

will be taken into account at the next START bit. The counter is stopped by writing

00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1 must not

be all zero.

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Table 12. Card registers (address 00h to F5h …continued

Register Description

75H

Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter.

Counter 1 starts counting the content of register TOR1 on the first START bit

(reception or transmission) detected on pin I/O after 75H is written in register TOC.

When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in

register USR is set, and the counter automatically restarts the same count until it is

stopped. Changing the content of register TOR1 during a count is not allowed.

Counting the value stored in registers TOR3 and TOR2 is started on the first START

bit detected on pin I/O (reception or transmission) after the value has been written,

and then on each subsequent START bit. It is possible to change the content of

registers TOR3 and TOR2 during a count; the current count will not be affected and

the new count value will be taken into account at the next START bit. The counter is

stopped by writing 00H in register TOC. In this configuration, registers TOR3, TOR2

and TOR1 must not be all zero.

7CH

Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in

registers TOR3, TOR2 and TOR1 is started on the first START bit detected on pin I/O

(reception or transmission) after the value has been written, and then on each

subsequent START bit. It is possible to change the content of registers TOR3, TOR2

and TOR1 during a count; the current count will not be affected and the new count

value will be taken into account at the next START bit. The counter is stopped by

writing 00H in register TOC. In this configuration, registers TOR3, TOR2 and TOR1

must not be all zero.

85H

E5H

F1H

F5H

Same as value 05H, except that all the counters will be stopped at the end of the 12th

ETU following the first received START bit detected after 85H has been written in

register TOC.

Same configuration as value 65H, except that counter 1 will be stopped at the end of

the 12th ETU following the first START bit detected after E5H has been written in

register TOC.

Same configuration as value 71H, except that the 16-bit counter will be stopped at the

end of the 12th ETU following the first START bit detected after F1H has been written

in register TOC.

Same configuration as value 75H, except the two counters will be stopped at the end

of the 12th ETU following the first START bit detected after F5H has been written in

register TOC.

The time-out counter is very useful for processing the clock counting during ATR, the

Work Waiting Time (WWT) or the waiting times defined in protocol T = 1. It should be

noted that the 200 and n_maxclock counter (n_max= 368 for TDA8007BHL/C4) used during

ATR is done by hardware when the start session is set, specific hardware controls the

functionality of BGT in T = 1 and T = 0 protocols and a specific register is available for

processing the extra guard time.

Writing to register TOC is not allowed as long as the card is not activated with a running

clock.

Before restarting the 16-bit counter (counters 3 and 2) by writing 61H, 65H, 71H, 75H,

F1H or F5H in the TOC; or the 24-bit counter (counters 3, 2 and 1) by writing 68H in the

TOC; it is mandatory to stop them by writing 00h in the TOC.

Detailed examples of how to use these specific timers can be found in application note

“AN01054”.

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8.2.2 ISO UART registers

8.2.2.1 UART Transmit Register (UTR)

Table 13. Register UTR (address 0DH; write only)^[1]

7

6

5

4

3

2

1

0

UT7

UT6

UT5

UT4

UT3

UT2

UT1

UT0

[1] Register value at reset: all bits are cleared after reset.

When the microcontroller wants to transmit a character to the selected card, it writes the

data in direct convention in the UART transmit register. The transmission:

• Starts at the end of writing (on the rising edge of signal WR\) if the previous character

has been transmitted and if the extra guard time has expired

• Starts at the end of the extra guard time if this one has not expired

• Does not start if the transmission of the previous character is not completed

• With a synchronous card (bit SAN within register UCR2 is set), only signal D0 is

relevant and is copied on pin I/O of the selected card.

8.2.2.2 UART Receive Register (URR)

Table 14. Register URR (address 0DH; read only)^[1]

7

6

5

4

3

2

1

0

UR7

UR6

UR5

UR4

UR3

UR2

UR1

UR0

[1] Register value at reset: all bits are cleared after reset.

When the microcontroller wants to read data from the card, it reads it from the UART

Receive Register (URR) in direct convention:

• With a synchronous card, only D0 is relevant and is a copy of the state of the selected

card I/O

• When needed, this register may be tied to a FIFO whose length ‘n’ is programmable

between 1 and 8; if n >1, then no interrupt is given until the FIFO is full and the

controller may empty the FIFO when required

• With a parity error:

a. _ In protocol T = 0; the received byte is not stored in the FIFO and the error

counter is incremented. The error counter is programmable between 1 and 8.

When the programmed number is reached, then the bit PE is set in the status

register USR and INT0 falls low. The error counter must be reprogrammed to the

desired value after its count has been reached

b. _In protocol T = 1; the character is loaded in the FIFO and the bit PE is set

whatever the programmed value in the parity error counter

• When the FIFO is full, then the bit RBF in the status register USR is set. This bit is

reset when at least one character has been read from URR

• When the FIFO is empty, then the bit FE is set in the status register USR as long as

no character has been received.

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8.2.2.3 Mixed Status Register (MSR)

The MSR relates the status of pin INTAUX, the cards presence contacts PRES1

and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive

ready indicator TBE/RBF. It also gives useful indications when switching the clock to or

from 1/2 f_intand when driving the TDA8007BHL/C4 with fast controllers.

No bits within register MSR act upon signal INT.

Table 15. Register MSR (address 0Ch; read only)^[1]

7

6

5

4

3

2

1

0

CLKSW

FE

BGT

CRED

PR2

PR1

INTAUX

TBE/RBF

[1] Register value at reset: bits TBE/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set

after reset.

Table 16. Description of MSR bits

Bit

Symbol

Description

7

CLKSW

clock switch: Bit CLKSW is set when the TDA8007BHL/C4 has

performed a required clock switch from ¹⁄_nf_XTALto ⁄₂f_int, and is reset

when the TDA8007BHL/C4 has performed a required clock switch from

¹⁄₂f_intto ¹⁄_nf_XTAL. The application must wait until this bit is set or reset

before sending a new command to the card. This bit is reset at

power-on.

6

5

FE

FIFO Empty: Bit FE is set when the reception FIFO is empty. It is reset

when at least one character has been loaded in the FIFO.

BGT

block guard time: In protocol T = 1, bit BGT is linked with a 22-ETU

counter which is started at every START bit on pin I/O. Bit BGT is set if

the count is finished before the next START bit. This helps to verify that

the card has not answered before 22 ETU after the last transmitted

character, or that the reader is not transmitting a character before

22 ETU after the last received character.

In protocol T = 0, bit BGT is linked with a 16-ETU counter which is

started at every START bit on pin I/O. Bit BGT is set if the count is

finished before the next START bit. This helps to verify that the reader

is not transmitting a character before 16 ETU after the last received

character.

4

3

CRED

PR2

control ready: It is advised bit CRED is used for driving the

TDA8007BHL/C4 with high speed controllers. Before writing in

registers TOC or UTR, or reading from register URR, check if bit CRED

is set. If reset, it means that the writing or reading operation will not be

correct because the controller is acting faster than the required time for

this operation:

card 2 present: Bit PR2 = 1 when card 2 is present.

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Table 16. Description of MSR bits …continued

Bit

2

Symbol

PR1

Description

card 1 present. Bit PR1 = 1 when card 1 is present.

1

INTAUX

auxiliary interrupt. Bit INTAUX is set when pin INTAUX = high and it is

reset when pin INTAUX = low.

0

TBE/RBF

transmit buffer empty/receive buffer full.

Bit TBE/RBF = 1 when:

- changing from reception mode to transmission mode

- the reception FIFO is full.

- a character has been transmitted by the UART

Bit TBE/RBF = 0 after power-on or after one of the following:

- when bit RIU is reset

- when a character has been written to register UTR

- when at least one character has been read in the FIFO

- when changing from transmission mode to reception mode.

I/O

bit RBF

bit FE

INT

t

SB(FE)

t

SB(RBF)

RD

CS

t

W(RD)

bit CRED

t

RD(URR)

001aam014

Fig 10. Minimum time between two read operations in register URR - non-multiplexed bus

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I/O

bit TBE

INT

RD

CS

t

W(WR)

bit CRED

t

WR(UTR)

001aam016

Fig 11. Minimum time between two write operations in register UTR - non-multiplexed bus

RD

CS

T

W(RD)

bit CRED

001aam018

T

WR(TOC)

Fig 12. Minimum time between two write operations in register TOC - non-multiplexed bus

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I/O

bit RBF

bit FE

INT

t

SB(FE)

t

SB(RBF)

RD

t

W(RD)

bit CRED

t

RD(URR)

fce903

Fig 13. Minimum time between two read operations in register URR - multiplexed mode TDA8007BHL/C3

I/O

bit TBE

INT

WR

t

W(WR)

bit CRED

fce902

t

WR(UTR)

Fig 14. Minimum time between two write operations in register UTR - multiplexed mode TDA8007BHL/C3

WR

t

W(WR)

bit CRED

fce904

t

WR(TOC)

Fig 15. Minimum time between two write operations in register TOC - multiplexed mode TDA8007BHL/C3

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8.2.2.4 FIFO Control Registers (FSR)

The FCR relates the parity error count and the FIFO length.

Table 17. Register FCR (address 0Ch; write only)^[1]

7

6

5

4

3

2

1

0

FC7

PEC2

PEC1

PEC0

FC3

FL2

FL1

FL0

[1] Register value at reset: all relevant bits are cleared after reset.

Table 18. Description of FCR bits

Bit

7

Symbol

FC7

Description

not used

6

PEC2

PEC1

PEC0

Parity Error Count

5

PEC2, PEC1 and PEC0 determine the number of allowed repetitions

reception

4

The value 000 indicates that, if only one parity error has occurred,

bit PE is set; the value 111 indicates that bit PE will be set after 8 parity

errors.

In protocol T = 0:

If a correct character is received before the programmed error number

is reached, the error counter will be reset

- If the programmed number of allowed parity errors is reached, bit PE

in register USR will be set as long as register USR has not been read

- If a transmitted character has been NAK by the card, then the

TDA8007BHL/C4 will automatically re-transmit it a number of times

equal to the value programmed in bits PEC2, PEC1 and PEC0; the

character will be resent at 15 ETU

In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then

the automatic re-transmission is invalidated; the character manually

rewritten in register UTR will start at 13.5 ETU.

3

2

1

FC3

FL2

FL1

not used

FIFO length. Bits FL2, FL1 and FL0 determine the depth of the FIFO:

• 000 = length 1

• 111 = length 8.

0

FL0

8.2.2.5 UART Status Register (USR)

The USR is used by the microcontroller to monitor the activity of the ISO UART and that of

the time-out counter. If any of the status bits FER, OVR, PE, EA, TO1, TO2 or TO3 are

set, then signal INT = low. The bit having caused the interrupt is reset 2 ms after the rising

edge of signal RD during a read operation of register USR.

If bit TBE/RBF is set and if the mask bit DISTBE/RBF within register UCR2 is not set, then

also signal INT = low. Bit TBE/RBF is reset 3 clock cycles after data has been written in

register UTR, or 3 clock cycles after data has been read from register URR, or when

changing from transmission mode to reception mode.

In order to avoid counting these clock cycles, bit CRED (described in register MSR) may

be used.

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If LCT mode is used for transmitting the last character, then bit TBE is not set at the end of

the transmission.

Table 19. Register USR (address 0Eh; read only)^[1]

7

6

5

4

3

2

1

0

TO3

TO2

TO1

EA

PE

OVR

FER

TBE/RBF

[1] Register value at reset: all relevant bits are cleared after reset.

Table 20. Description of USR bits

Bit

Symbol

Description

7

TO3

Time-Out counter 3. Bit TO3 is set when counter 3 has reached its

terminal count.

6

5

4

TO2

TO1

EA

Time-Out counter 2. Bit TO2 is set when counter 2 has reached its

terminal count.

Time-Out counter 1. Bit TO1 is set when counter 1 has reached its

terminal count.

Early answer is high if the first START bit on the I/O during ATR has

been detected between the first 200 and 368 clock pulses with RST low

(all activities on the I/O during the first 200 clock pulses with RST low

are not taken into account) and before the first 368 clock pulses with

RST high. These two features are re-initialized at each toggling of RST

3

PE

Parity Error (PE). In protocol T = 0, bit PE = 1 if the UART has

detected a number of received characters with parity errors equal to the

number written in bits PEC2, PEC1 and PEC0 or if a transmitted

character has been NAK by the card a number of times equal to the

value programmed in bits PEC2, PEC1 and PEC0. It is set at 10.5 ETU

in the reception mode and at 11.5 ETU in the transmission mode.

In protocol T = 0, a character received with a parity error is not stored in

register FIFO (the card should repeat this character). In protocol T = 1,

a character with a parity error is stored in the FIFO and the parity error

counter is not active.

2

1

0

OVR

Overrun (OVR). Bit OVR = 1 if the UART has received a new character

whilst register FIFO was full. In this case, at least one character has

been lost.

FER

Framing Error (FER). Bit FER = 1 when pin I/O was not in the high

impedance state at 10.25 ETU after a START bit. It is reset when

register USR has been read-out.

TBE/RBF

Transmission Buffer Empty (TBE)/Reception Buffer Full (RBF).

Bits TBE and RBF share the same bit within register USR: when in

transmission mode the relevant bit is TBE; when in reception mode it is

RBF.

Bit TBE = 1 when the UART is in transmission mode and when the

microcontroller may write the next character to transmit in register UTR.

It is reset when the microcontroller has written data in the transmit

register or when bit T/R within register UCR1 has been reset either

automatically or by software. After detection of a parity error in

transmission, it is necessary to wait 13.5 ETU before rewriting the

character which has been NAK by the card. (Manual mode, see

Table 18)

Bit RBF = 1 when register FIFO is full. The microcontroller may read

some of the characters in register URR, which clears bit RBF.

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8.2.3 Card registers

When cards 1, 2 or 3 are selected, the following registers may be used for programming

some specific parameters.

8.2.3.1 Programmable Divider Register (PDR)

The programmable divider registers PDR1, PDR2 and PDR3 are used for counting the

cards clock cycles forming the ETU (see Figure 16).

These are auto-reload 8-bit counters.

Table 21. Register PDR1,PRDR2, PDR3 (address 02h; read and write)

7

6

5

4

3

2

1

0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

[1] Register value at reset: all bits are cleared after reset.

PROGRAMMABLE

DIVIDER

f

CLK

PRESCALER

(31 or 32)

MULTIPLEXER

ETU

REGISTER

(1 to 256)

2f

bit CKU

fce905

Fig 16. Block diagram

8.2.3.2 UART Configuration Registers (UCR) 2

The UART configuration registers 2 UCR12, UCR22 and UCR32, relate the UART

configuration.

Table 22. Register UCR1,UCR2, UCR3 (address 03h; read and write)^[1]

7

6

5

4

3

2

1

0

UC27

DISTBE/RBF DISAUX

PDWN

SAN

AUTOCONV CKU

PSC

[1] Register value at reset: all bits are cleared after reset.

Table 23. Description of UCR2 bits

Bit

7

Symbol

Description

UC27

not used

6

DISTBE/RBF disable TBE/RBF interrupt bit. If bit DISTBE/RBF = 1, then reception

or transmission of a character will not generate an interrupt. This

feature is useful for increasing communication speed with the card; in

this case, a copy of the bit TBE/RBF within register MSR must be

polled (and not the original) in order not to lose priority interrupts which

can occur in register USR.

5

DISAUX

disable auxiliary interrupt. If bit DISAUX in register UCR2 is set, then

a change on pin INTAUX will not generate an interrupt, but bit INTAUXL

will be set. Therefore, it is necessary to read register HSR before

bit DISAUX is to be reset to avoid an interrupt by bit INTAUXL. In order

to avoid an interrupt during a change of card, it is better to set

bit DISAUX in register UCR2 for all cards.

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Table 23. Description of UCR2 bits

Bit

Symbol

Description

4

PDWN

power-down mode. If bit PDWN is set by software, the crystal

oscillator is stopped. This mode allows low power consumption in

applications where this is required. During the Power-down mode, it is

not possible to select a card other than the one currently selected.

There are five ways of escaping from the Power-down mode:

- withdraw card 1 or 2

- Select the TDA8007BHL/C4 by resetting bit CS (this assumes that

the TDA8007BHL/C4 had been deselected after setting Power-down

mode)

- insert card 1 or card 2

- Bit INTAUXL has been set due to a change on pin INTAUX

- If pin CS = low permanently, reset bit PDWN by software.

After any of these events, the TDA8007BHL/C4 will leave the

Power-down mode.

Except in the case of a read operation of register HSR, signal INT will

be pulled to low level. The system microcontroller may then read the

status registers after 5 ms, and signal INT will return to high level (if the

system microcontroller has woken the TDA8007BHL/C4 by re-selecting

it, then no bits will be set in the status registers).

Note that the Power-down mode can only be entered if bit SUPL has

been cleared.

3

2

SAN

synchronous/asynchronous card. Bit SAN = 1 by software if a

synchronous card is expected. The UART is then bypassed and only

bit 0 in registers URR and UTR is connected to pin I/O. In this case the

clock is controlled by bit SC in register CCR.

AUTOCONV auto convention. If bit AUTOCONV = 1, then the convention is set by

software using bit CONV in register UCR1. If the bit is reset, then the

configuration is automatically detected on the first received character

whilst the start session (bit SS) is set.

Bit AUTOCONV must not be changed during a card session.

1

0

CKU

clock UART. For baud rates other than those given in Table 24, there is

the possibility to set bit CKU = 1. In this case, the ETU will last half the

number of card clock cycles equal to prescaler PDRx. Note that

bit CKU = 1 has no effect if f_CLK= f_XTAL. This means, for example, that

76800 baud is not possible when the card is clocked with the external

frequency on pin XTAL1.

PSC

prescale Select. If bit PSC = 1, then the prescaler value is 32. If

bit PSC = 0, then the prescaler value is 31. One ETU will last a number

of cards clock cycles equal to prescaler PDRx. All baud rates specified

in the ISO 7816 norm are achievable with this configuration (see

Table 24).

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Table 24. Baud rate selection using values F and D^[1]

PSC = 31: f_CLK= 3.58 MHz; PSC = 32: f_CLK= 4.92 MHz

D

F

0

1

2

3

4

5

6

9

10

11

12

13

1

2

3

4

5

6

8

9

31;12

9600

31;12

9600

31;18

6400

31;24

4800

31;36

3200

31;48

2400

31;60

1920

32;16

9600

32;24

6400

32;32

4800

32;48

3200

32;64

2400

31;6

31;9

31;12

31;18

6400

31;24

4800

31;30

3840

32;8

32;12

32;16

32;24

6400

32;32

4800

19200 19200 12800 9600

31;3 31;3 31;6

38400 38400

19200 12800 9600

31;9

31;12

31;15

7680

32;4 32;6 32;8

32;12

32;16

19200 12800 9600

38400 25600 19200 12800 9600

32;2 32;3 32;4 32;6 32;8

76800 51300 38400 25600 19200

31;3

38400

31;6

19200

31;3

38400

32;1

153600

32;2

32;3

32;4

76800 51300 38400

32;1

153600

32;2

76800

31;1

115200 115200

31;1

31;2

31;3

31;4

31;5

32;2

76800

32;4

38400

57600 38400 28800 23040

31;3

38400

[1] Example: 31;12 in the table means prescaler set to 31 and PDR set to 12

8.2.3.3 Guard Time Registers (GTR)

The guard time registers GTR1, GTR2 and GTR3 are used for storing the number of

guard ETU given by the card during ATR. In transmission mode, the UART will wait this

number of ETU before transmitting the character stored in register UTR.

When register GTRx = FF:

• In protocol T = 1

TDA8007BHL/C4 operates at 10.8 ETU

• In protocol T = 0

TDA8007BHL/C4 operates at 11.8 ETU.

Table 25. Register GTR1, GTR2, GTR3 (address 05H; read and write)^[1]

7

6

5

4

3

2

1

0

GT7

GT6

GT5

GT4

GT3

GT2

GT1

GT0

[1] Register value at reset: all bits are cleared after reset.

8.2.3.4 UART Configuration Registers (UCR) 1

The UART configuration registers 1 (UCR11, UCR21 and UCR31) set the parameters of

the ISO UART.

Table 26. Register UCR11, UCR21 and UCR31 (address 06H; read and write)^[1]

7

6

5

4

3

2

1

0

UC17

FIP

FC

PROT

T/R

LCT

SS

CONV

[1] Register value at reset: all bits are cleared after reset.

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Table 27. Description of UCRx1 bits

Bit

7

Symbol

UC17

FIP

Description

not used

6

Force Inverse Parity (FIP). If bit FIP is set to logic 1, the UART will

NAK a correctly received character, and will transmit characters with

wrong parity bits.

5

4

FC

Test. Bit FC is a test bit, and must be left at logic 0.

PROT

Protocol (PROT). Bit PROT is set if the protocol is T = 1

(asynchronous) and bit PROT = 0 if the protocol is T = 0.

3

T/R

Transmit/Receive (T/R). Bit T/R is set by software for transmission

mode. A change from logic 0 to 1 will set bit TBE in register USR.

Bit T/R is automatically reset by hardware if bit LCT has been used

before transmitting the last character.

2

LCT

Last Character to Transmit (LCT). Bit LCT is set by software before

writing the last character to be transmitted in the UTR. It allows

automatic change to reception mode. It is reset by hardware at the end

of a successful transmission. When LCT is being reset, the bit T/R is

also reset and the ISO 7816 UART is ready for receiving a character.

1

0

SS

Software convention Setting (SS). Bit SS is set by software before

ATR for automatic convention detection and early answer detection. It

is automatically reset by hardware at 10.5 ETU after reception of the

initial character.

CONV

Convention (CONV). Bit CONV is set if the convention is direct.

Bit CONV is either automatically written by hardware according to the

convention detected during ATR, or by software if the bit AUTOCONV

in register UCR2X is set.

8.2.3.5 Clock Configuration Registers (CCR)

The clock configuration registers CCR1, CCR2 and CCR3 relate the clock signals:

• For cards 1 and 2, register CCRx defines the clock for the selected card

• For cards 1, 2 and 3, register CCRx defines the clock to the ISO UART. It should be

noted that, if bit CKU in the prescaler register of the selected card (register UCR2) is

set, then the ISO UART is clocked at twice the frequency of the card, which allows

baud rates not foreseen in ISO 7816 norm to be reached.

Table 28. Register CCR1, CCR2 and CCR3 (address 01H; read and write)^[1]

7

6

5

4

3

2

1

0

CC7

CC6

SHL

GST

SC

AC2

AC1

AC0

[1] Register value at reset: all bits are cleared after reset.

Table 29. Description of CCRx bits

Bit

7

Symbol

CC7

Description

not used

6

CC6

not used

5

SHL

Stop High or Low (SHL). If bit CST = 1, then the clock is

stopped at low level if bit SHL = 0, and at high level if

bit SHL = 1.

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Table 29. Description of CCRx bits …continued

Bit

Symbol

Description

4

CST

Clock Stop (CST). In the case of an asynchronous card,

bit CST defines whether the clock to the card is stopped or not; if

bit CST is reset, then the clock is determined by bits AC0, AC1

and AC2.

3

SC

AC

Synchronous Clock (SC). In the event of a synchronous card,

then contact CLK is the copy of the value of bit SC; in reception

mode, the data from the card is available to bit UR0 after a read

operation of register URR; in transmission mode, the data is

written on the I/O line of the card when register UTR has been

written to and remains unchanged when another card is

selected.

2 to 0

Alternating Clock (AC). All frequency changes are

synchronous, thus ensuring that no spikes or unwanted pulse

widths occur during changes.

000 = f_XTAL

001 = ¹⁄₂f_XTAL

010 = ¹⁄₄f_XTAL

011 = ¹⁄₈f_XTAL

100 to 111 = ¹⁄₂f_int

Clock switching constraints:

• f_intis the frequency delivered by the internal oscillator

• In case of f_CLK= f_XTAL, the duty cycle must be ensured by the incoming clock signal on

pin XTAL1

• When switching from ¹⁄_nf_XTALto ¹⁄₂f_XTALor vice verse, only bit AC2 must be changed

(bits AC1 and AC0 must remain the same). When switching from ¹⁄_nf_XTALto ¹⁄₂f_XTALto

clock stopped or vice verse, only bits CST and SHL must be changed

• When switching from ¹⁄_nf_XTALto ¹⁄₂f_XTALor vice verse, a delay can occur between the

command and the effective frequency change on CLK (the fastest switching time is

from ¹⁄₂f_XTALto ¹⁄₂f_intor vice verse, the best for duty cycle is from ¹⁄₈f_XTALto ¹⁄₂f_intor

vice verse)

• It is necessary to survey the bit CLKSW in register MSR before re-transmitting

commands to the card.

8.2.3.6 Power Control Registers (PCR)

The power control registers PCR1 and PCR2:

• Start or stop card sessions

• Read from or write to auxiliary card contacts C4 and C8

• Are available only for cards 1 or 2.

To deactivate the card, only bit START should be reset.

Table 30. Register PCR1 and PCR2 (address 07H; read and write)^[1]

7

6

5

4

3

2

1

0

PCR7

PCR6

C8

C4

1V8

RSTIN

3V/5V

START

[1] Register value at reset: all bits are cleared after reset.

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Table 31. Description of PCRx bits

Bit

7

Symbol

PCR7

PCR6

C8

Description

not used

6

not used

5

Contact 8 (C8). When writing to register PCR, pin C8 will output

the value of bit C8. When reading from register PCR, bit C8 will

store the value on pin C8

4

3

C4

Contact 4 (C4). When writing to register PCR, pin C4 will output

the value of bit C4. When reading from register PCR, bit C4 will

store the value on pin C4.

1V8

1.8 V cards. If bit 1V8 is set, then V_CC= 1.8 V: it should be

noted that no specification is guaranteed with this V_CCvoltage

when the supply voltage V_DDis inferior to 3 V

2

1

0

RSTIN

3V/5V

START

Reset In (RSTIN). When the card is activated, pin RST is the

copy of the value written in bit RSTIN.

3 V or 5 V cards. If bit 3V/5V = 1, then V_CC= 3 V; if

bit 3V/5V = 0, then V_CC= 5 V.

Start. If the microcontroller sets bit START = 1, then the

selected card is activated (see Section 8.6); if the

microcontroller resets bit START = 0, then the card is

deactivated (see Section 8.7). Bit START is automatically reset

in case of emergency deactivation. To deactivate the card, only

bit START should be reset.

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8.3 Supply

V

th1

V

DD

V

th2

CDELAY

t

w

RSTOUT

SUPL

INT

Status read

Power-on

Supply dropout

Reset by C

Power-off

DELAY

fce683

Fig 17. voltage supervisor

The TDA8007BHL/C4 operates within a supply voltage range of 2.7 V to 6 V. The supply

pins are V_DD, V_DDA, GND and AGND.

Pins V_DDAand AGND supply the analog drivers to the cards and have to be decoupled

externally because of the large current spikes that the cards and the step-up converter

can create. V_DDAmay be different from V_DD

.

Pins V_DDand GND supply the remainder of the chip. An integrated spike killer ensures

that the contacts to the cards remain inactive during power-up and power-down. An

internal voltage reference is generated for use within the step-up converter, the voltage

supervisor and the V_CCgenerators.

The voltage supervisor generates an alarm pulse when V_DDis too low to ensure proper

operation. The alarm pulse length is defined by an external capacitor tied to pin DELAY

and is typically 1 ms per 2 nF.

The alarm pulse may be used as a reset pulse by the system microcontroller

(pin RSTOUT = high). It can also be used to block any spurious noise on card contacts

during the microcontrollers reset, or to force an automatic deactivation of the contacts in

the event of a supply drop-out (see Section 8.5 and 8.7).

After power-on, or after a voltage drop, bit SUPL is set within register HSR and remains

set until register HSR is read-out outside the alarm pulse. Signal INT = low for the

duration that signal RSTOUT is active.

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8.4 Step up converter

Except for the V_CCgenerator and the other cards contacts buffers, the whole circuit is

powered by V_DD, and V_DDA. If the supply voltage is 2.5 V, then a higher voltage is needed

for the ISO contacts supply. When a card session is requested by the microcontroller, the

sequencer first enables the step-up converter (a switched capacitors type) which is

clocked by an internal oscillator at a frequency of approximately 2.5 MHz.

Supposing that V_CCis the maximum of V_CC1and V_CC2, then the possible situations are:

• V_CC= 5 V

– For V_DD= 3 V the step-up converter acts as a voltage tripler with regulation of V_UP

at approximately 5.5 V

– For V_DD= 5 V the step-up converter acts as a voltage doubler with regulation of

V

_UPat approximately 5.5 V

• V_CC= 3 V

– For V_DD= 3 V the step-up converter acts as a voltage doubler with regulation of

V

_UPat approximately 4.0 V

– For V_DD= 5 V the step-up converter acts as a voltage follower and V_DDis applied

to V_UP

• V_CC= 1.8 V

– T he step-up converter acts as a voltage follower for any value of V_DD

.

The recognition of the supply voltage is done by the TDA8007BHL/C4 at approximately

3.5 V.

The output voltage V_UPis fed to the V_CCgenerators. V_CCand GNDC are used as a

reference for all other card contacts.

8.5 ISO 7816 security

The correct sequence during activation and deactivation of the cards is ensured by two

specific sequencers, the clock is defined by a division ratio of the internal oscillator.

Activation (bit START = 1 in registers PCR1 or PCR2) is only possible if the card is

present (pin PRES is active high with an internal current source to ground) and if the

supply voltage is correct (voltage supervisor not active).

The presence of the cards is signalled to the microcontroller by register HSR. Bits PR1

or PR2 in register MSR are set if card 1 or 2 is present. Bits PRL1 or PRL2 are set if

pins PRES1 or PRES2 have been toggled.

During a session, the sequencer performs an automatic emergency deactivation on one

card in the event of card take-off, or short-circuit. Both cards are automatically deactivated

in the event of a supply voltage drop, or overheating. Register HSR is updated and the

INT line falls so that the system microcontroller is aware of what happened.

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8.6 Activation sequence

When the cards are inactive, pins V_CC, CLK, RST, C4x, C8x and I/O are at low level and

have a low impedance with respect to ground. The step-up converter is stopped.

When everything is satisfactory (voltage supply, card present and no hardware problems),

the system microcontroller may initiate an activation sequence of a present card.

After selecting the card and leaving the UART reset mode, and then configuring the

necessary parameters for the counters and the UART, bit START can be set within

register PCR at t₀(see Figure 18)

1. The step-up converter is started (t₁); if one card was already active, then the step-up

converter was already on and nothing more occurs at this step.

2. Pin V_CCstarts rising (t₂) from 0 V to 3 V or 5 V with a controlled rise time of 0.17 V/µs

(typical).

3. Pin I/O rises to V_CC(t₃); pins C4x and C8x also rise if bits C4 and C8 within

register PCR have been set to logic 1 (integrated 14 k pull-up resistors to V_CC).

4. Clock pulse CLK is sent to the card (t₄) and pin RST is enabled.

5. After a number of CLK pulses that can be counted with the time-out counter,

bit RSTIN may be set by software and pin RST will then rise to V_CC

.

6. The sequencer is clocked by ¹⁄₆₄f_intwhich leads to a time interval of t = 25 µs (typical).

Thus:

t₁= 0 to ¹⁄₆₄t

t₂= t₁+ ³⁄₂t

t₃= t₁+ ⁷⁄₂

t₄= t₁+ 4t.

START

V

UP

V

CC

I/O

RSTIN

CLK

RST

t

0

t

= t

act

ATR

fce684

2

3

4

t

1

Fig 18. Activation sequence

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8.7 Deactivation sequence

When the session is completed, the microcontroller resets bit START at t₁₀. The circuit

then executes an automatic deactivation sequence (see Figure 19):

1. The card is reset by signal RST = low (t₁₁).

2. Clock pulse CLK is stopped (t₁₂).

3. Pins I/O, C4x and C8x fall to 0 V (t₁₃).

4. Pin V_CCfalls to 0 V with typical 0.17 V/µs slew rate (t₁₄).

5. The step-up converter is stopped (t₁₅) and pins CLK, RST, V_CCand I/O become low

impedance to ground, if both cards are inactive.

Thus:

t₁₁= t₁₀+ ¹⁄₆₄t

t₁₂= t₁₁+ ¹⁄₂t

t₁₃= t₁₁+ t

t₁₄= t₁₁+ ³⁄₂t

t₁₅= t₁₁+ ⁷⁄₂t

t_de= time that V_CCneeds to decrease to less than 0.4 V.

START

RST

CLK

I/O

V

CC

V

UP

t

10

t

15

fce685

11

12

13

14

t

de

Fig 19. Deactivation sequence

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9. Limiting values

Table 33. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

0.5

Max

+6.5

Unit

V

V_DD

supply voltage

V_DDA

analog supply voltage

V

V_I

input voltage

on pins SAM, SAP, SBM, SBP and V_UP

on all other pins

0.5

-

+7.5

V

V_DD+ 0.5 V

P_tot

T_stg

T_j

total power dissipation

storage temperature

T_amb= - 25 to +85 °C

700

mW

55

-

+150

125

°C

junction temperature

[1]

V_esd

electrostatic discharge voltage

human body model

on pins I/O1, I/O2, V_CC1, V_CC2, RST1,

RST2, CLK1, CLK2, CGND1, CGND2,

PRES1 and PRES2

6

+6

kV

on pins C4x, C8x

on all other pins

5

2

+5

+2

kV

[1] Human body model as define in JEDEC Standard JESD22-A114-B dated June 2000

10. Thermal characteristics

Table 34. Thermal characteristics

Symbol

Package name Parameter

LQFP48 thermal resistance from junction to

ambient

Conditions

Typ

78

Unit

K/W

R_th(j-a)

in free air

11. Characteristics

Table 35. Characteristics

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

2.7

-

6.0

V

V_DDA

analog

step-up converter

V_DD

supply voltage

I_DD(pd)

supply current in power-down mode

cards inactive; f_XTAL= 0 Hz

-

350

3

A

cards active; V_CC= 5 V;

f_CLK= 0 Hz; f_XTAL= 0 Hz

mA

I_DD(sm)

supply current in sleep mode

cards active; f_CLK= 0 Hz

-

5.5

mA

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Table 35. Characteristics …continued

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

I_DD(oper)

supply current in operating modem

5 V cards

-

315

mA

I_CC1= 65 mA; I_CC2= 15 mA;

f

_XTAL= 20 MHz;

f_CLK= 10 MHz; V_DD= 2.7 V

3 V cards

I

f

_CC1= 50 mA; I_CC2= 30 mA;

_XTAL= 20 MHz;

f_CLK= 10 MHz

V_DD= 2.7 V

V_DD= 5 V

-

215

100

mA

Voltage supervisor; see Figure 17

V_th1

threshold voltage on pin V_DD

hysteresis on V_th1

falling

2.10

50

-

2.50

170

V

V_hys1

mV

Capacitor connection: pin DELAY

V_th2

V_o

I_o

threshold voltage

output voltage

output current

-

1.25

-

V

-

V_DD+ 0.3

V

V_DELAY= 0 V (charge)

-

2

2

-

µA

mA

nF

ms

V_DELAY= V_DD(discharge)

-

C_o

t_W

output capacitance

alarm pulse width

1

-

C_DELAY= 22 nF

10

Output: pin RSTOUT (open-drain output)

Active high option

V_OH

I_OL

high-level output voltage

low-level output current

I_OH= 1mA

0.8V_DD

-

V_DD+ 0.3

V

V_OL= 0 V

10

µA

Active low option

I_OH

high-level output current

low-level output voltage

V_OH= 5 V

I_OL= 2 mA

-

10

µA

V

V_OL

0.3

+0.4

Crystal oscillator

f_XTALcrystal frequency

f_extexternal frequency on pin XTAL1

Step-up converter

4

0

-

20

MHz

f_int

internal oscillator frequency

2

2.5

5.7

4.1

3.5

3.7

-

MHz

V

V_VUP

voltage on pin V_UP

at least one 5 V card

both 3 V cards

-

V

V_det(dt)

detection voltage on pin V_DDfor

doubler or tripler selection

3.4

3.6

V

Reset output to the cards: pins RST1 and RST2

V_o(inactive)output voltage in inactive mode

no load

0

-

0.1

0.3

1

V

I_o(inactive)= 1 mA

V_o= 0 V

V

I_o(inactive)output current in inactive mode

mA

V

V_OL

V_OH

low-level output voltage

high-level output voltage

I_OL= 200 mA

I_OH= -200µA

0.3

V_CC

V_CC 0.5 -

V

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Table 35. Characteristics …continued

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

Conditions

C_L= 30 pF

Min

Typ

Max

0.1

Unit

µs

t_r

t_f

rise time

fall time

-

0.1

µs

Clock output to the cards: pins CLK1 and CLK2

V_o(inactive)output voltage in inactive mode

no load

0

-

0.1

0.3

1

0.3

V_CC

8

V

I_o(inactive)= 1 mA

V_o= 0 V

V

I_o(inactive)output current in inactive mode

mA

V

V_OL

V_OH

t_r

low-level output voltage

high-level output voltage

rise time

I_OL= 200 µA

I_OH= -200µA

C_L= 30 pF

V_CC 0.5 -

V

-

ns

t_f

fall time

C_L= 30 pF

-

8

ns

f_CLK

clock frequency

idle configuration (1 MHz)

operational

1

1.85

10

55

-

MHz

%

0



duty factor

C_L= 30 pF

45

0.2

SR

slew rate (rise and fall)

C_L= 30 pF

V/ns

[1]

Card supply output voltage: pins V_CC1and V_CC2

V_o(inactive)output voltage in inactive mode

no load

0

-

0.1

V

I_o(inactive)= 1 mA

V_o= 0 V

0

-

0.3

V

I_o(inactive)output current in inactive mode

-

- 1

mA

V

V_CC

output voltage in active mode

5 V card; I_CC< 65 mA

3 V card; I_CC< 50 mA

1.8 V card; I_CC< 30 mA

4.75

2.78

1.65

4.6

5

3

1.8

-

5.25

3.22

1.95

5.4

V

5 V card; current pulses of

40 nC with I < 200 mA,

t < 400 ns and f < 20 MHz

V

3 V card; current pulses of

24 nC with I < 200 mA,

t < 400 ns and f < 20 MHz

2.75

1.62

-

3.25

1.98

V

1.8 V card; current pulses of

12 nC with I < 200 mA,

t < 400 ns and f < 20 MHz

I_CC

output current

5 V card; V_CC= 0 to 5 V

3 V card; V_CC= 0 to 3 V

1.8 V card; V_CC= 0 to 1.8 V

-

- 65

- 50

- 30

- 80

mA

I_CC1+ I_CCsum of both output currents

2

SR

slew rate

up or down; maximum

capacitance of 300 nF

0.05

0.16 0.22

V/µs

Data lines: pins I/O1 and I/O2^[2]

R_puinternal pull-up resistance

between pin I/O and V_CC

no load

11

0

-

14

-

17

k

V

V_o(inactive)output voltage in inactive mode

0.1

0.3

- 1

I_o(inactive)= 1 mA

V_o= 0 V

-

V

I_o(inactive)output current in inactive mode

-

mA

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Table 35. Characteristics …continued

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Configured as output

V_OL

V_OH

low-level output voltage

I_OL= 1 mA

0

-

0.3

V

high-level output voltage

I_OH< 20 µA

0.8V_CC

0.75V_CC

V_CC+ 0.25 V

I_OH< 40 µA for 5 V and 3 V

cards

t_o(r), t_o(f)

output transition time (rise and fall

time)

C_L< 30 pF

-

0.1

µs

Configured as input

V_IL

low-level input voltage

0.3

-

+0.8

V_CC

600

20

V

V_IH

high-level input voltage

1.5

V

I_IL

low-level input current

V_IL= 0 V

V_IH= V_CC

-

µA

µs

I_LIH

high-level input leakage current

t_i(r), t_i(f)

input transition time (rise and fall time) C_L< 30 pF

1.2

Auxiliary cards contacts: pins C41, C81, C42 and C82^[3]

V_o(inactive)output voltage in inactive mode

no load

0

-

0.1

0.3

-1

V

I_o(inactive)= 1 mA

V_o= 0 V

-

V

I_o(inactive)output current in inactive mode

-

mA

ns

k

t_W(pu)

active pull-up pulse width

internal pull-up resistance

-

200

10

-

R_int(pu)

between pins C4x or C8x and

V_CC

8

12

f_max

maximum frequency

on card contact pins

-

1

MHz

Configured as output

V_OL

V_OH

low-level output voltage

I_OL= 1 mA

0

-

0.3

V

high-level output voltage

I_OH< -20µA

0.8V_CC

0.75V_CC

V_CC+ 0.25 V

I_OH< -40µA for 5 and 3 V

cards

t_o(r), t_o(f)

output transition time (rise and fall

time)

C_L= 30 pF

-

0.1

µs

Configured as input

V_IL

low-level input voltage

-

+0.8

V_CC

600

20

V

V_IH

high-level input voltage

1.5

V

I_IL

low-level input current

V_IL= 0 V

V_IH= V_CC

-

µA

µs

I_LIH

high-level input leakage current

t_i(r), t_i(f)

Timing

t_act

input transition time (rise and fall time) C_L= 30 pF

1.2

activation sequence duration

deactivation sequence duration

see Figure 18

see Figure 19

-

130

150

µs

t_de

Protection and limitation

I_CC(sd)

shutdown and limitation current at

-

100

-

mA

pin V_CC

I_I/O(lim)

limitation current on pin I/O

limitation current on pin CLK

15

70

-

+15

+70

mA

I_CLK(lim)

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Table 35. Characteristics …continued

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

- 20

-

Max

Unit

mA

°C

I_RST(sd)

I_RST(lim)

T_sd

shutdown current on pin RST

-

limitation current on pin RST

shutdown temperature

20

+20

-

150

Card presence inputs: pins PRES1 and PRES2

V_IL

V_IH

I_OL

I_OH

low-level input voltage

-

0.3V_DD

V

high-level input voltage

0.7V_DD

-

V

low-level output leakage current

high-level output leakage current

V_OL= 0.4 V

V_OH= 2.5 V

-

10

55

µA

Bidirectional data bus: pins D0 to D7

Configured as input

V_IL

V_IH

I_LIL

I_LIH

C_L

low-level input voltage

-

0.3V_DD

-

V

high-level input voltage

low-level input leakage current

high-level input leakage current

load capacitance

0.7V_DD

20

-

V

+20

10

µA

pF

Configured as output

V_OL

low-level output voltage

I_OL= 5 mA

I_OH= 5 mA

C_L= 50 pF

-

0.2V_DD

V

V_OH

high-level output voltage

0.8V_DD

-

V

t_o(r), t_o(f)

output transition time (rise and fall

time)

25

ns

Logic inputs: pins AD0, AD1, AD2, AD3, INTAUX, CS, RD and WR

V_IL

V_IH

I_LIL

I_LIH

C_L

low-level input voltage

0.3

0.7V_DD

20

-

0.3V_DD

V_DD+ 0.3

+20

V

high-level input voltage

low-level input leakage current

high-level input leakage current

load capacitance

V

µA

pF

20

+20

10

Logic inputs: pins ALE: only applicable for TDA8007BHL/C3

V_IL

V_IH

I_LIL

I_LIH

C_L

low-level input voltage

0.3

0.7V_DD

20

-

0.3V_DD

V_DD+ 0.3

+20

V

high-level input voltage

low-level input leakage current

high-level input leakage current

load capacitance

V

µA

pF

20

+20

10

Auxiliary input and output: pin I/OAUX^[4]

R_int(pu)

f_max

internal pull-up resistance

maximum frequency

between pin I/OAUX and V_DD

on pin I/OAUX

11

-

17

1

k

MHz

Configured as input

V_IL

V_IH

I_LIH

I_IL

low-level input voltage

0.3

0.7V_DD

20

-

0.3V_DD

V_DD+ 0.3

+20

V

high-level input voltage

V

high-level input leakage current

low-level input current

µA

V_IL= 0 V

600

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Table 35. Characteristics …continued

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25 °C; unless otherwise specified.

Symbol Parameter

t_i(r), t_i(f)input transition time (rise and fall time) C_L= 30 pF

Configured as output

Conditions

Min

Typ

Max

Unit

-

1.2

µs

V_OL

low-level output voltage

I_OL= 1 mA

I_OH= 40 mA

C_L= 30 pF

-

300

mV

V_OH

high-level output voltage

0.75V_DD

-

V_DD+ 0.25 V

t_o(r), t_o(f)

output transition time (rise and fall

time)

0.1

µs

Interrupt line: pin INT (open-drain output)

V_OH

I_LIH

low-level output voltage

I_OH= 2 mA

-

0.3

10

V

high-level input leakage current

µA

[1] To meet these specifications, two ceramic multilayer capacitors with low ESR of minimum 100 nF should be used.

[2] Pin I/O1 has an integrated 14 k pull-up resistance to V_CC1and pin I/O2 has an integrated 14 k pull-up resistance to V_CC2

[3] Pins C41 and C81 have an integrated 10 k pull-up resistance to V_CC1and pins C42 and C82 have an integrated 10 k pull-up

resistance to V_CC2

.

[4] Pin I/OAUX has a 14 k pull-up resistance to V_DD

.

12. Timings

Table 36. Timings

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25°C; unless otherwise specified.

Symbol Parameter Conditions

Min.

Typ. Max.

Unit

Timing for non-multiplexed bus

Read control; see Figure 4

t₁

t₂

t₃

RD high to CS low

10

-

ns

access time CS low to data out valid

CS high to data out (high)

50

10

-

Write control; see Figure 5 and 6

t₄

t₅

t₆

t₇

data valid to end-of-write

data hold time

10

-

ns

RD low to CS or WR low

address stable to CS or WR high

Timing for bit CRED

Read operations in UART receive register; see Figure 9

t_W(RD)

RD pulse width

10

-

ns

t_RD(URR)

t_SB(FE)

RD low to bit CRED = 1

set bit time FE

t_W(RD)+ 2T_cy(CLK)

t_W(RD)+ 3T_cy(CLK)ns

10.5

-

ETU

t_SB(RBF)

set time bit RBF

ETU

Write operations in UART transmit register; see Figure 10

t_W(WR)

WR pulse width

10

-

ns

t_WR(UTR)

WR low to I/O low

t_W(WR)+ 2T_cy(CLK)

t_W(WR)+ 3T_cy(CLK)ns

Write operations in time-out configuration register; see Figure 11

t_W(WR)

WR pulse width

10

-

ns

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Table 36. Timings

V_DD= 3.3 V; V_DDA= 3.3 V; T_amb= 25°C; unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Unit

[1]

t_WR(TOC)

WR low to bit CRED = 1

-

ETU

1

PSC

2

PSC

----------

Timing for multiplexed bus, only applicable for TDA8007BHL/C3

T_CY(XTAL1)XTAL1 cyle time

50

-

ns

t_W(ALE)

t_AVLL

t_(AL-RWL)

t_W(RD)

ALE pulse width

20

address valid to ALE low

ALE low to RD or WR low

RD pulse width

10

for register

URR

2T_CY(XTAL1)

for other

registers

10

-

ns

t_(RL-DV)

RD low to data read valid

- -

-

50

-

ns

t_(RWH-AH)RD or WR high to ALE high

10

t_W(WR)

WR pulse width

-

t_(DV-WL)

data write valid to WR low

-

[1] PSC is the programmed prescaler value (31 or 32).

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14. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 22. Package outline SOT313-2 (LQFP48)

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15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

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Product data sheet

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16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 23) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 37 and 38

Table 37. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 38. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 23.

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Product data sheet

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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17. Revision history

Table 39. Revision history

Document ID

Release date

20120618

Data sheet status

Change notice

Supersedes

TDA8007BHL v. 9.1

Modifications:

Product data sheet

-

TDA8007BHL v. 9

• Small text correction

20120612 Product data sheet

TDA8007BHL v. 9

Modifications:

-

TDA8007BHL v. 8

• Table 35 “Characteristics”: Card presence inputs: pins PRES1 and PRES2: values updated

20110111 Product data sheet TDA8007B_7

• Text changed to dedicate this data sheet to the C4 as well as the C3 variant.

20100512 Product data sheet TDA8007B_6

TDA8007BHL v. 8

Modifications:

-

TDA8007B_7

-

Modifications:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Text changed to dedicate this data sheet to the C4 variant.

TDA8007B_6

TDA8007B_5

TDA8007B_4

TDA8007B_3

TDA8007B_2

TDA8007B_1

20030218

20021115

20020215

20001109

20000829

19991111

Product specification

Objective specification

-

TDA8007B_5

TDA8007B_4

TDA8007B_3

TDA8007B_2

TDA8007B_1

-

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18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

18.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Product data sheet

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49 of 51

TDA8007BHL

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TDA8007BHL

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.1 — 18 June 2012

50 of 51

TDA8007BHL

NXP Semiconductors

Multiprotocol IC card interface

20. Contents

1

2

3

4

5

6

General description. . . . . . . . . . . . . . . . . . . . . . 1

16

Soldering of SMD packages. . . . . . . . . . . . . . 45

Introduction to soldering. . . . . . . . . . . . . . . . . 45

Wave and reflow soldering. . . . . . . . . . . . . . . 45

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 46

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 46

16.1

16.2

16.3

16.4

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

17

Revision history . . . . . . . . . . . . . . . . . . . . . . . 48

18

Legal information . . . . . . . . . . . . . . . . . . . . . . 49

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 49

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

18.1

18.2

18.3

18.4

8

Functional description . . . . . . . . . . . . . . . . . . . 7

Interface control . . . . . . . . . . . . . . . . . . . . . . . . 7

Non-Multiplexed configuration . . . . . . . . . . . . . 7

Multiplexed configuration . . . . . . . . . . . . . . . . . 9

Control registers . . . . . . . . . . . . . . . . . . . . . . . 10

General registers . . . . . . . . . . . . . . . . . . . . . . 13

Card select register . . . . . . . . . . . . . . . . . . . . 13

Hardware status register. . . . . . . . . . . . . . . . . 13

Time-out registers. . . . . . . . . . . . . . . . . . . . . . 14

Time-out configuration register. . . . . . . . . . . . 15

ISO UART registers . . . . . . . . . . . . . . . . . . . . 17

UART Transmit Register (UTR) . . . . . . . . . . . 17

UART Receive Register (URR) . . . . . . . . . . . 17

Mixed Status Register (MSR) . . . . . . . . . . . . . 18

FIFO Control Registers (FSR) . . . . . . . . . . . . 22

UART Status Register (USR) . . . . . . . . . . . . . 22

Card registers. . . . . . . . . . . . . . . . . . . . . . . . . 24

Programmable Divider Register (PDR). . . . . . 24

UART Configuration Registers (UCR) 2 . . . . . 24

Guard Time Registers (GTR) . . . . . . . . . . . . . 26

UART Configuration Registers (UCR) 1 . . . . . 26

Clock Configuration Registers (CCR). . . . . . . 27

Power Control Registers (PCR) . . . . . . . . . . . 28

register summary . . . . . . . . . . . . . . . . . . . . . . 30

Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Step up converter . . . . . . . . . . . . . . . . . . . . . . 32

ISO 7816 security. . . . . . . . . . . . . . . . . . . . . . 32

Activation sequence . . . . . . . . . . . . . . . . . . . . 33

Deactivation sequence . . . . . . . . . . . . . . . . . . 34

8.1

19

20

Contact information . . . . . . . . . . . . . . . . . . . . 50

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.1.1

8.1.2

8.2

8.2.1

8.2.1.1

8.2.1.2

8.2.1.3

8.2.1.4

8.2.2

8.2.2.1

8.2.2.2

8.2.2.3

8.2.2.4

8.2.2.5

8.2.3

8.2.3.1

8.2.3.2

8.2.3.3

8.2.3.4

8.2.3.5

8.2.3.6

8.2.4

8.3

8.4

8.5

8.6

8.7

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 35

Thermal characteristics . . . . . . . . . . . . . . . . . 35

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 35

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Application information. . . . . . . . . . . . . . . . . . 42

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44

Handling information. . . . . . . . . . . . . . . . . . . . 45

10

11

12

13

14

15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 June 2012

Document identifier: TDA8007BHL


型号：	TDA8007BHL/C3,118
厂家：	NXP
描述：	TDA8007BHL - Multiprotocol IC card interface QFP 48-Pin 外围集成电路
文件：	总51页 (文件大小：270K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA8007BHL/C3,118 [NXP]

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