TDA8024TT [NXP]
IC card interface; IC卡接口
| 型号： | TDA8024TT |
| 厂家： | 
NXP |
| 描述： | IC card interface |
| 文件： | 总29页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8024
IC card interface
Product specification
2004 July 12
Supersedes data of 2003 Aug 19
Philips Semiconductors
Product specification
IC card interface
TDA8024
CONTENTS
9
LIMITING VALUES
HANDLING
10
11
12
13
14
15
15.1
1
2
3
4
5
6
7
8
FEATURES
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
APPLICATION INFORMATION
PACKAGE OUTLINES
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
PINNING
FUNCTIONAL DESCRIPTION
15.2
15.3
15.4
15.5
8.1
Power supply
8.2
8.2.1
Voltage supervisor
Without external divider on pin PORADJ
(or with TDA8024AT)
With an external divider on pin PORADJ (not
for the TDA8024AT)
Application examples
Clock circuitry
Suitability of surface mount IC packages for
wave and reflow soldering methods
8.2.2
16
17
18
DATA SHEET STATUS
DEFINITIONS
8.2.3
8.3
DISCLAIMERS
8.4
I/O transceivers
8.5
Inactive mode
8.6
8.7
Activation sequence
Active mode
8.8
8.9
Deactivation sequence
VCC generator
8.10
Fault detection
2004 July 12
2
Philips Semiconductors
Product specification
IC card interface
TDA8024
1
FEATURES
2
APPLICATIONS
• IC card interface
• IC card readers for banking
• Electronic payment
• Identification
• 3 or 5 V supply for the IC (VDD and GND)
• Three specifically protected half-duplex bidirectional
buffered I/O lines to card contacts C4, C7 and C8
• Pay TV.
• DC/DC converter for VCC generation separately
powered from a 5 V ± 20% supply (VDDP and PGND)
3
GENERAL DESCRIPTION
• 3 or 5 V ± 5% regulated card supply voltage (VCC) with
The TDA8024 is a complete and cost-efficient analog
interface for asynchronous 3 or 5 V smart cards. It can be
placed between the card and the microcontroller to
perform all supply, protection and control functions. Very
few external components are required. The TDA8024AT is
a direct replacement for the TDA8004AT.
appropriate decoupling has the following capabilities:
– ICC < 80 mA at VDDP = 4 to 6.5 V
– Handles current spikes of 40 nAs up to 20 MHz
– Controls rise and fall times
– Filtered overload detection at approximately 120 mA
• Thermal and short-circuit protection on all card contacts
More information can be obtained from the Philips Internet
site (http://www.semiconductors.philips.com) and from
“Application note AN10141”.
• Automatic activation and deactivation sequences;
initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating, VDD or VDDP
drop-out
• Enhanced ESD protection on card side (>6 kV)
• 26 MHz integrated crystal oscillator
• Clock generation for cards up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
with synchronous frequency changes
• Non-inverted control of RST via pin RSTIN
• ISO 7816, GSM11.11 and EMV (payment systems)
compatibility
• Supply supervisor for spike-killing during power-on and
power-off and Power-on reset (threshold fixed internally
or externally by a resistor bridge); not for TDA8024AT
• Built-in debounce on card presence contacts
• One multiplexed status signal OFF.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8024T
SO28
SO28
plastic small outline package; 28 leads; body width 7.5 mm
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
SOT136-1
SOT361-1
TDA8024AT
TDA8024TT
TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm
2004 July 12
3
Philips Semiconductors
Product specification
IC card interface
TDA8024
5
QUICK REFERENCE DATA
SYMBOL
Power supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
2.7
−
6.5
V
VDDP
DC/DC converter supply
voltage
VCC = 5 V; ICC < 80 mA
VCC = 5 V; ICC < 20 mA
VDD = 3.3 V; fXTAL = 10 MHz
card inactive
4.0
3.0
5.0
6.5
6.5
V
V
−
IDD
supply current
−
−
−
−
1.2
1.5
mA
mA
card active; fCLK = fXTAL
CL = 30 pF
;
IDDP
DC/DC converter supply
current
VDDP = 5 V; fXTAL = 10 MHz
inactive mode
−
−
−
−
0.1
10
mA
mA
active mode; fCLK = fXTAL
;
CL = 30 pF; ICC = 0
Card supply
VCC
card supply voltage (including 5 V card
ripple voltage)
card active;
4.75
4.65
5.0
5.0
5.25
5.25
V
V
ICC < 80 mA DC
card active; current pulses
Ip = 40 nAs
3 V card
card active;
ICC < 65 mA DC
2.85
2.76
−
3.0
3.0
−
3.15
3.20
350
V
card active; current pulses
Ip = 40 nAs
V
VCC(ripple)(p-p) ripple voltage on VCC
(peak-to-peak value)
fripple = 20 kHz to 200 MHz
mV
ICC
card supply current
VCC = 0 to 5 V
VCC = 0 to 3 V
−
−
−
−
80
65
mA
mA
General
tde
deactivation time
50
80
100
µs
Ptot
total power dissipation
continuous operation;
−
−
0.56
W
Tamb = −25 to +85 °C
Tamb
ambient temperature
−25
−
+85
°C
2004 July 12
4
Philips Semiconductors
Product specification
IC card interface
TDA8024
6
BLOCK DIAGRAM
100 nF
100 nF
100 nF
V
V
DDP
DD
S1
7
S2
5
6
21
V
DD
SUPPLY
PGND
4
8
DC/DC CONVERTER
INTERNAL
REFERENCE
R1
V
ref
18
100 nF
INTERNAL OSCILLATOR
2.5 MHz
PORADJ
(1)
V
UP
VOLTAGE SENSE
R2
EN1 CLKUP
POWER_ON
ALARM
EN2
V
CC
17
23
20
19
V
CC
OFF
PV
CC
GENERATOR
RSTIN
100 nF
100 nF
14 CGND
CMDVCC
5V/3V
16
3
EN5
EN4
RST
RST
BUFFER
SEQUENCER
HORSEQ
1
2
15
CLKDIV1
CLKDIV2
CLK
CLOCK
BUFFER
10
CLOCK
CIRCUITRY
PRES
9
PRES
CLK
EN3
THERMAL
PROTECTION
24
25
XTAL1
XTAL2
OSCILLATOR
I/O
TRANSCEIVER
27
28
26
13
AUX1UC
AUX2UC
I/OUC
AUX1
TDA8024
I/O
12
TRANSCEIVER
AUX2
I/O
11
TRANSCEIVER
I/O
22
mdb051
GND
(1) Optional external resistor bridge. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18 is not connected
in the TDA8024AT.
Fig.1 Block diagram.
2004 July 12
5
Philips Semiconductors
Product specification
IC card interface
TDA8024
7
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
CLKDIV1
CLKDIV2
5V/3V
1
2
3
4
5
I
I
CLK frequency selection input 1
CLK frequency selection input 2
I
card supply voltage selection input; VCC = 5 V (HIGH) or VCC = 3 V (LOW)
DC/DC converter power supply ground
PGND
S2
S
I/O
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
VDDP
S1
6
7
S
DC/DC converter power supply voltage
I/O
DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
VUP
8
9
I/O
DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between VUP and PGND
PRES
PRES
I
I
card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
10
card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
I/O
11
12
13
14
15
16
17
I/O
I/O
I/O
S
data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to VCC
data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to VCC
data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to VCC
card signal ground
AUX2
AUX1
CGND
CLK
I/O
O
card clock to/from card reader contact C3
RST
VCC
card reset output from card reader contact C2
S
card supply voltage to card reader contact C1; decoupled to CGND via 2 × 100 nF
or 100 + 220 nF capacitors with ESR < 100 mΩ; note 1
PORADJ
18
I
Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used; this
pin is not connected for the TDA8024AT
CMDVCC
RSTIN
VDD
19
20
21
22
23
I
input from the host to start activation sequence (active LOW)
I
card reset input from the host
supply voltage
S
S
O
GND
ground
OFF
NMOS interrupt output to the host (active LOW); 20 kΩ integrated pull-up resistor
to VDD
XTAL1
24
25
26
27
28
I
crystal connection or input for external clock
XTAL2
O
crystal connection (leave open-circuit if external clock source is used)
host data I/O line; integrated 11 kΩ pull-up resistor to VDD
I/OUC
I/O
I/O
I/O
AUX1UC
AUX2UC
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
Note
1. The noise margin on VCC will be higher with the 220 nF capacitor.
2004 July 12
6
Philips Semiconductors
Product specification
IC card interface
TDA8024
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKDIV1
CLKDIV2
5V/3V
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
CLKDIV1
CLKDIV2
5V/3V
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
3
3
4
4
PGND
S2
PGND
S2
5
5
6
6
V
DDP
V
DDP
7
7
S1
GND
S1
GND
TDA8024T
TDA8024TT
8
8
V
V
DD
V
V
DD
UP
UP
9
9
PRES
PRES
I/O
RSTIN
PRES
PRES
I/O
RSTIN
10
11
12
13
14
10
11
12
13
14
CMDVCC
PORADJ
CMDVCC
PORADJ
AUX2
AUX1
CGND
V
CC
AUX2
AUX1
CGND
V
CC
RST
CLK
RST
CLK
001aab430
001aab431
Fig.2 Pin configuration TDA8024T.
Fig.3 Pin configuration TDA8024TT.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLKDIV1
CLKDIV2
5V/3V
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
3
4
PGND
S2
5
6
V
DDP
7
S1
GND
TDA8024AT
8
V
V
DD
UP
9
PRES
PRES
I/O
RSTIN
CMDVCC
n.c.
10
11
12
13
14
AUX2
AUX1
CGND
V
CC
RST
CLK
001aab382
Fig.4 Pin configuration TDA8024AT.
2004 July 12
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Philips Semiconductors
Product specification
IC card interface
TDA8024
8
FUNCTIONAL DESCRIPTION
The DC/DC converter function changes as follows:
• VCC = 5 V and VDDP > 5.8 V; voltage follower
• VCC = 5 V and VDDP < 5.7 V; voltage doubler
• VCC = 3 V and VDDP > 4.1 V; voltage follower
• VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Throughout this document it is assumed that the reader is
familiar with ISO7816 terminology.
8.1
Power supply
The supply pins for the IC are VDD and GND. VDD should
be in the range of 2.7 to 6.5 V. All signals interfacing with
the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader
contacts remain inactive during power-on or power-off.
Supply voltages VDD and VDDP may be applied to the IC in
any sequence.
After powering the device, OFF remains LOW until
CMDVCC is set HIGH.
The internal circuits are maintained in the reset state until
VDD reaches Vth2 + Vhys2 and for the duration of the
internal Power-on reset pulse, tW (see Fig.5). When VDD
falls below Vth2, an automatic deactivation of the contacts
is performed.
During power off, OFF falls LOW when VDD is below the
falling threshold voltage.
8.2
Voltage supervisor
8.2.1
WITHOUT EXTERNAL DIVIDER ON PIN PORADJ
(OR WITH TDA8024AT)
A DC/DC converter is incorporated to generate the
5 or 3 V card supply voltage (VCC). The DC/DC converter
should be supplied separately by VDDP and PGND. Due to
the possibility of large transient currents, the two 100 nF
capacitors of the DC/DC converter should be located as
near as possible to the IC and have an ESR less than
100 mΩ.
The voltage supervisor surveys the VDD supply. A defined
reset pulse of approximately 8 ms (tW) is used internally to
keep the IC inactive during power-on or power-off of the
VDD supply (see Fig.5).
As long as VDD is less than Vth2 + Vhys2, the IC remains
inactive whatever the levels on the command lines. This
state also lasts for the duration of tW after VDD has reached
The DC/DC converter functions as a voltage doubler or a
voltage follower according to the respective values of VCC
and VDDP (both have thresholds with a hysteresis of
100 mV).
a level higher than Vth2 + Vhys2
.
When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
V
V
+ V
hys2
th2
th2
V
DD
ALARM
(internal signal)
t
t
w
w
power-on
supply dropout
power-off
MDB053
Fig.5 Voltage supervisor.
8
2004 July 12
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.2.2
WITH AN EXTERNAL DIVIDER ON PIN PORADJ (NOT
FOR THE TDA8024AT)
Transposed, this becomes
R1
-------
R2
0.99
R1
R2
1
k
1 + 0.98 ×
= 1 +
×
<
-----------
1.01
------- --
If an external resistor bridge is connected to pin PORADJ
(R1 and R2 in Fig.1), then the following occurs:
1
--
k
1.01
R1
R2
R1
-------
R2
• The internal threshold voltage Vth2 is overridden by the
external voltage and by the hysteresis, therefore:
< 1 +
×
= 1 + 1.02 ×
-------
-----------
0.99
If V1 = Vth(ext)(rise)(max) and V2 = Vth(ext)(fall)(min)
Vhys(ext)
R1
-------
R2
Vth2(ext)(rise)
=
1 +
1 +
× Vbridge +
-------------------
2
activation will always be possible if VPORADJ > V1
and deactivation will always be done for VPORADJ < V2.
Vhys(ext)
R1
-------
R2
Vth2(ext)(fall)
=
× Vbridge –
-------------------
2
V1
k
Activation is always possible for VDD
>
------
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
V2
------
k
• The reset pulse width tW is doubled to approximately
16 ms.
and deactivation is always possible for VDD
That is V1 = 1.31 V and V2 = 1.19 V
<
.
Input PORADJ is biased internally with a pull-down current
source of 4 µA which is removed when the voltage on
pin PORADJ exceeds 1 V. This ensures that after
detection of the external bridge by the IC during power-on,
the input current on pin PORADJ does not cause
inaccuracy of the bridge voltage.
R1
-------
R2
3.135
--------------
1.31
and
<
– 1 × 0.98 = 1.365
Suppose R1 + R2 = 100 kΩ, then
100 kΩ
R2 =
= 42.3 kΩ and R1 = 57.7 kΩ.
-------------------
2.365
The minimum threshold voltage should be higher than 2 V.
The maximum threshold voltage may be up to VDD
.
Deactivation will be effective at
V2 × (1 + 1.02 × 1.365) = 2.847 V in any case.
8.2.3
APPLICATION EXAMPLES
If the microcontroller continues to function down to 2.80 V,
the slew rate on VDD should be less than 2 V/ms to ensure
that clock CLK is correctly delivered to the card until
time t12 (see Fig.9).
The voltage supervisor is used as Power-on reset and as
supply dropout detection during a card session.
Supply dropout detection is to ensure that a proper
deactivation sequence is followed before the voltage is too
low.
8.2.3.2
Microcontroller requiring a 3.3 V ±10% supply
For a microcontroller supplied by a 3.3 V with a ±1%
regulator and with resistors R1, R2 having a ±0.1%
tolerance, the minimum supply voltage is 3.267 V.
For the internal voltage supervisor to function, the system
microcontroller should operate down to 2.35 V to ensure a
proper deactivation sequence. If this is not possible,
external resistor values can be chosen to overcome the
problem.
The same calculations as in Section 8.2.3.1 conclude:
R1
-------
R2
3.267
--------------
1.310
<
– 1 × 0.998 = 1.491
8.2.3.1
Microcontroller requiring a 3.3 V ±20% supply
For a microcontroller supplied by 3.3 V with a ±5%
regulator and with resistors R1, R2 having a ±1%
tolerance, the minimum supply voltage is 3.135 V.
100 kΩ
Therefore R2 =
= 40.14 kΩ and R1 = 59.86 kΩ.
-------------------
2.49
Deactivation will be effective at
S1
S1 + S2
V2 × (1 + 1.002 × 1.491) = 2.967 V in any case.
VPORADJ = k × VDD, where k =
with S1 and S2
--------------------
If the microcontroller continues to function down to 2.97 V,
the slew rate on VDD should be less than 0.20 V/ms to
ensure that clock CLK is correctly delivered to the card
until time t12 (see Fig.9).
the actual values of nominal resistors R1 and R2.
This can be shown as
0.99 × R1 < S1 < 1.01 × R1 and
0.99 × R2 < S2 < 1.01 × R2
2004 July 12
9
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.3
Clock circuitry
The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
card as shown in the activation sequences shown in Figs 7
and 8.
The card clock signal (CLK) is derived from a clock signal
input to pin XTAL1 or from a crystal operating at up to
26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL, 1/2 × fXTAL, 1/4 × fXTAL
or 1/8 × fXTAL. Frequency selection is made via
inputs CLKDIV1 and CLKDIV2 (see Table 1).
If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse will be applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
Table 1 Clock frequency selection; note 1
8.4
I/O transceivers
CLKDIV1
CLKDIV2
fCLK
The three data lines I/O, AUX1 and AUX2 are identical.
fXTAL
0
0
------------
8
The idle state is realized by both I/O and I/OUC lines being
pulled HIGH via a 11 kΩ resistor (I/O to VCC and I/OUC to
VDD).
fXTAL
0
1
------------
4
Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus
fXTAL
allowing operation when VCC is not equal to VDD
.
1
1
1
0
------------
2
The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.
fXTAL
Note
1. The status of pins CLKDIV1 and CLKDIV2 must not be
changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of
any state of CLK is eight periods of XTAL1.
After a time delay td(edge), an N transistor on the slave side
is turned on, thus transmitting the logic 0 present on the
master side.
When the master side returns to logic 1, a P transistor on
the slave side is turned on during the time delay tpu and
then both sides return to their idle states.
The frequency change is synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; as shown in Fig.6, it is able to deliver more than
1 mA at an output voltage of up to 0.9VCC into an 80 pF
load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.
When changing the frequency dynamically, the change is
effective for only eight periods of XTAL1 after the
command.
The duty factor of fXTAL depends on the signal present at
pin XTAL1.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
In order to reach a 45 to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor of
48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be
45 to 55% depending on the circuit layout and on the
crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
2004 July 12
10
Philips Semiconductors
Product specification
IC card interface
TDA8024
Table 2 Card presence indication
OFF
CMDVCC
INDICATION
FCE661
6
12
HIGH
LOW
HIGH
HIGH
card present
card not present
V
o
I
o
(V)
(1)
4
(mA)
(2)
If the card is in the reader (this is the case if PRES or
PRES is active), the system microcontroller can start a
card session by pulling CMDVCC LOW. The following
sequence then occurs (see Fig.6):
8
1. CMDVCC is pulled LOW and the internal oscillator
changes to its high frequency (t0).
2
0
4
0
2. The voltage doubler is started (between t0 and t1).
3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope
(t2 = t1 + 1.5 × T) where T is 64 times the period of the
internal oscillator (approximately 25 µs).
0
20
40
60
t (ns)
4. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these
were pulled LOW until this moment).
5. CLK is applied to the C3 contact of the card reader (t4).
6. RST is enabled (t5 = t1 + 7T).
(1) Current.
(2) Voltage.
The clock may be applied to the card using the following
sequence:
Fig.6 I/O, AUX1 and AUX2 output voltage and
current as functions of time during a
LOW-to-HIGH transition.
1. Set RSTIN HIGH.
2. Set CMDVCC LOW.
3. Reset RSTIN LOW between t3 and t5; CLK will start at
this moment.
8.5
Inactive mode
After a Power-on reset, the circuit enters the inactive
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
4. RST remains LOW until t5, when RST is enabled to be
the copy of RSTIN.
5. After t5, RSTIN has no further affect on CLK; this
allows a precise count of CLK pulses before toggling
RST.
• All card contacts are inactive (approximately 200 Ω to
GND)
• Pins I/OUC, AUX1UC and AUX2UC are in the
If the applied clock is not needed, then CMDVCC may be
set LOW with RSTIN LOW. In this case, CLK will start at t3
(minimum 200 ns after the transition on I/O), and after t5,
RSTIN may be set HIGH in order to obtain an Answer To
Request (ATR) from the card.
high-impedance state (11 kΩ pull-up resistor to VDD
• Voltage generators are stopped
• XTAL oscillator is running
)
• Voltage supervisor is active
Activation should not be performed with RSTIN held
permanently HIGH.
• The internal oscillator is running at its low frequency.
8.6 Activation sequence
After power-on and after the internal pulse width delay, the
system microcontroller can check the presence of a card
using the signals OFF and CMDVCC as shown in Table 2.
2004 July 12
11
Philips Semiconductors
Product specification
IC card interface
TDA8024
CMDVCC
V
UP
V
CC
ATR
I/O
CLK
RSTIN
RST
I/OUC
t
t
t
t
t = t
4 5 act
0
2
3
MDB054
t
1
Fig.7 Activation sequence using RSTIN and CMDVCC.
CMDVCC
V
UP
V
CC
I/O
CLK
ATR
200 ns
RSTIN
RST
I/OUC
t
t
t
t = t
5 act
0
2
3
MDB055
t
t
4
1
Fig.8 Activation sequence at t3.
12
2004 July 12
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.7
Active mode
1. RST goes LOW (t10).
2. CLK is held LOW (t12 = t10 + 0.5 × T) where T is 64
times the period of the internal oscillator
(approximately 25 µs).
When the activation sequence is completed, the TDA8024
will be in its active mode. Data is exchanged between the
card and the microcontroller via the I/O lines. The
TDA8024 is designed for cards without VPP (the voltage
required to program or erase the internal non-volatile
memory).
3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).
4. VCC starts to fall towards zero (t14 = t10 + 1.5 × T).
5. The deactivation sequence is complete at tde, when
VCC reaches its inactive state.
8.8
Deactivation sequence
6. VUP falls to zero (t15 = t10 + 5T) and all card contacts
become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain at VDD (pulled-up via a 11 kΩ
resistor).
When a session is completed, the microcontroller sets the
CMDVCC line HIGH. The circuit then executes an
automatic deactivation sequence by counting the
sequencer back and finishing in the inactive mode (see
Fig.9):
7. The internal oscillator returns to its lower frequency.
CMDVCC
RST
CLK
I/O
V
CC
V
UP
t
t
t
14
12
t
13
MDB056
de
t
t
15
10
Fig.9 Deactivation sequence.
2004 July 12
13
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.9
VCC generator
There are two different cases (see Fig.10):
• CMDVCC HIGH outside a card session. Output OFF
is LOW if a card is not in the card reader, and HIGH if a
card is in the reader. A voltage drop on the VDD supply
is detected by the supply supervisor, this generates an
internal Power-on reset pulse but does not act upon
OFF. No short-circuit or overheating is detected
because the card is not powered-up.
The VCC generator has a capacity to supply up to 80 mA
continuously at 5 V and 65 mA at 3 V.
An internal overload detector operates at approximately
120 mA. Current samples to the detector are internally
filtered, allowing spurious current pulses up to 200 mA
with a duration in the order of µs to be drawn by the card
without causing deactivation. The average current must
stay below the specified maximum current value.
• CMDVCC LOW within a card session. Output OFF
goes LOW when a fault condition is detected. As soon
as this occurs, an emergency deactivation is performed
automatically (see Fig.11). When the system controller
resets CMDVCC to HIGH it may sense the OFF level
again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card
extraction (OFF goes HIGH again if a card is present).
For reasons of VCC voltage accuracy, a 100 nF capacitor
with an ESR < 100 mΩ should be tied to CGND near to
pin VCC, and a 100 or 220 nF capacitor (220 nF is the best
choice) with the same ESR should be tied to CGND near
card reader contact C1.
8.10 Fault detection
Depending on the type of card-present switch within the
connector (normally-closed or normally-open) and on the
mechanical characteristics of the switch, bouncing may
occur on the PRES signals at card insertion or withdrawal.
The following fault conditions are monitored:
• Short-circuit or high current on VCC
• Removal of a card during a transaction
• VDD dropping
There is a debounce feature in the device with an 8 ms
typical duration (see Fig.10). When a card is inserted,
output OFF goes HIGH only at the end of the debounce
time.
• DC/DC converter operating out of the specified values
(VDDP too low or current from VUP too high)
• Overheating.
When the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES or PRES and output OFF goes LOW.
PRES
OFF
CMDVCC
debounce
debounce
V
CC
deactivation caused by
cards withdrawal
deactivation caused by
short-circuit
MDB059
See “Application note AN10141” for software decision algorithm on OFF signal.
Fig.10 Behaviour of OFF, CMDVCC, PRES and VCC
.
2004 July 12
14
Philips Semiconductors
Product specification
IC card interface
TDA8024
OFF
PREST
RST
CLK
I/O
V
CC
V
UP
t
t
t
14
12
t
13
MDB057
de
t
t
15
10
Fig.11 Emergency deactivation sequence (card extraction).
2004 July 12
15
Philips Semiconductors
Product specification
IC card interface
TDA8024
9
LIMITING VALUES
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.3
MAX.
+6.5
UNIT
VDD
supply voltage
V
V
V
VDDP
DC/DC converter supply voltage
voltage on input and output pins
−0.3
−0.3
+6.5
+6.5
VI, VO
pins XTAL1, XTAL2, 5V/3V, RSTIN,
AUX1UC, AUX2UC, I/OUC,
CLKDIV1, CLKDIV2, CMDVCC, OFF
and PORADJ
Vcard
voltage on card pins
pins PRES, PRES, I/O, RST, AUX1, −0.3
AUX2 and CLK
+6.5
V
V
Vn
voltage on other pins
pins VUP, S1 and S2
−0.3
−
+6.5
150
Tj(max)
Tstg
maximum junction temperature
storage temperature
°C
°C
−55
+150
Vesd
electrostatic discharge voltage
card contacts in typical application;
notes 1 and 2
pins I/O, RST, VCC, AUX1, AUX2, −6
+6
kV
CLK, PRES and PRES
all pins; note 1
human body model; notes 2 and 3 −2
+2
kV
V
machine model; note 4
−200
+200
Notes
1. All card contacts are protected against any short-circuit with any other card contact.
2. Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ω and 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.
3. In accordance with EIA/JESD22-A114-B, June 2000.
4. In accordance with EIA/JESD22-A115-A, October 1997.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction
to ambient
in free air
TDA8024T
TDA8024AT
TDA8024TT
70
70
100(1)
K/W
K/W
K/W
Note
1. This figure was obtained using the following PCB technology: FR, 4 layers, 0.5 mm thickness, class 5, copper
thickness 35 µm, Ni/Go plating, ground plane in internal layers
2004 July 12
16
Philips Semiconductors
Product specification
IC card interface
TDA8024
12 CHARACTERISTICS
VDD = 3.3 V; VDDP = 5 V; Tamb = 25 °C; fXTAL = 10 MHz; all currents flowing into the IC are positive; see note 1; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
Temperature
Tamb
ambient temperature
supply voltage
−25
−
−
+85
°C
Supplies
VDD
2.7
4.0
3.0
−
6.5
6.5
6.5
1.2
1.5
V
VDDP
DC/DC converter supply
voltage
VCC = 5 V; ICC < 80 mA
VCC = 5 V; ICC < 20 mA
card inactive
5.0
−
V
V
IDD
supply current
−
mA
mA
card active; fCLK = fXTAL
CL = 30 pF
;
−
−
IDDP
DC/DC converter supply
current
inactive mode
−
−
−
−
0.1
10
mA
mA
active mode; fCLK = fXTAL
;
CL = 30 pF; ICC = 0
VCC = 5 V; ICC = 80 mA
VCC = 3 V; ICC = 65 mA
−
−
200
100
2.55
mA
mA
V
−
−
Vth2
falling threshold voltage on no external resistors at
2.35
2.45
VDD
pin PORADJ; VDD level falling
Vhys2
hysteresis of threshold
voltage Vth2
no external resistors at
pin PORADJ
50
100
150
mV
Pin PORADJ; note 2
Vth(ext)(rise)
Vth(ext)(fall)
Vhys(ext)
external rising threshold
voltage on VDD
external resistor bridge at
pin PORADJ; VDD level rising
1.240
1.190
30
1.28
1.22
60
1.310
1.26
90
V
external falling threshold
voltage on VDD
external resistor bridge at
pin PORADJ; VDD level falling
V
hysteresis of threshold
voltage Vth(ext)
external resistor bridge at
pin PORADJ
mV
mV/K
∆Vhys(ext)
hysteresis of threshold
voltage Vth(ext) variation
with temperature
external resistor bridge at
pin PORADJ
−
−
0.25
tw
width of internal Power-on no external resistors at
4
8
8
12
24
ms
ms
reset pulse
pin PORADJ
external resistor bridge at
pin PORADJ
16
IL(PORADJ)
leakage current on
pin PORADJ
VPORADJ < 0.5 V
VPORADJ > 1 V
−0.1
−1
−
4
−
−
10
µA
µA
W
+1
Ptot
total power dissipation
continuous operation;
0.56
Tamb = −25 to +85 °C
2004 July 12
17
Philips Semiconductors
Product specification
IC card interface
TDA8024
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
DC/DC converter
fCLK
clock frequency
card active
2.2
5.2
3.8
−
3.2
MHz
V
Vth(vd-vf)
threshold voltage for
voltage doubler to change
to voltage follower
5 V card
3 V card
5.8
4.1
6.2
4.4
V
VUP(av)
output voltage on pin VUP VCC = 5 V
(average value)
5.2
3.5
5.7
3.9
6.2
4.3
V
V
VCC = 3 V; VDDP = 3.3 V
Card supply voltage (pin VCC); note 3
CVCC
external capacitance on
pin VCC
note 4
80
−
400
nF
VCC
card supply voltage
5 V card
(including ripple voltage)
card inactive; ICC = 0 mA
card inactive; ICC = 1 mA
card active; ICC < 80 mA
−0.1
−0.1
4.75
4.65
0
+0.1
+0.3
5.25
5.25
V
V
V
V
0
5.0
5.0
card active; single current
pulse, Ip = −100 mA,
tp = 2 ms
card active; current pulses,
Ip = 40 nAs
4.65
4.65
5.0
5.0
5.25
5.25
V
V
card active; current pulses,
Ip = 40 nAs with
ICC < 200 mA, tp < 400 ns
3 V card
card inactive; ICC = 0 mA
card inactive; ICC = 1 mA
card active; ICC < 65 mA
−0.1
−0.1
2.85
2.76
0
+0.1
+0.3
3.15
3.20
V
V
V
V
0
3.0
3.0
card active; single current
pulse Ip = −100 mA;
tp = 2 ms
card active; current pulses,
Ip = 40 nAs
2.76
2.76
3.0
3.0
3.20
3.20
V
V
card active; current pulses,
Ip = 40 nAs with
ICC < 200 mA, tp < 400 ns
VCC(ripple)(p-p) ripple voltage on VCC
(peak to peak value)
fripple = 20 kHz to 200 MHz
−
−
350
mV
ICC
card supply current
VCC = 0 to 5 V
−
−
80
mA
mA
mA
V/µs
VCC = 0 to 3 V
−
−
65
VCC short-circuit to GND
slew up or down
100
0.08
120
0.15
150
0.22
SR
slew rate
2004 July 12
18
Philips Semiconductors
Product specification
IC card interface
TDA8024
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
Crystal oscillator (pins XTAL1 and XTAL2)
CXTAL1
CXTAL2
,
external capacitance on
pins XTAL1 and XTAL2
depends on type of crystal or
resonator used
−
−
15
pF
fXTAL
crystal frequency
2
0
−
−
26
26
MHz
MHz
fXTAL1
frequency applied on
pin XTAL1
VIL
VIH
LOW-level input voltage on
pin XTAL1
−0.3
−
−
+0.3VDD
V
HIGH-level input voltage
on pin XTAL1
0.7VDD
VDD + 0.3 V
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)
td(I/O-I/OUC),
td(I/OUC-I/O)
I/O to I/OUC, I/OUC to I/O
falling edge delay
−
−
200
ns
tpu
active pull-up pulse width
−
−
−
−
100
1
ns
fI/O(max)
maximum frequency on
data lines
MHz
Ci
input capacitance on data
lines
−
−
10
pF
Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11 kΩ pull-up resistors to VCC
)
Vo(inactive)
output voltage
inactive mode
no load
0
−
−
0
V
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.3
−1
V
Io(inactive) = 1 mA
inactive mode; pin grounded
IOL = 1 mA
V
Io(inactive)
VOL
output current
mA
V
LOW-level output voltage
0.3
VCC
I
OL ≥ 15 mA
HIGH-level output voltage no DC load
5 and 3 V cards; IOH < −40 µA 0.75VCC
CC − 0.4
V
VOH
0.9VCC
VCC + 0.1 V
VCC + 0.1 V
IOH ≥ 10 mA
0
0.4
0.8
V
V
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
0.3
1.5
−
VCC + 0.3 V
VIL = 0 V
VIH = VCC
600
10
µA
ILIH
HIGH-level input leakage
current
−
µA
tt(DI)
data input transition time
VIL(max) to VIH(min)
−
−
−
−
1.2
0.1
µs
µs
tt(DO)
data output transition time Vo = 0 to VCC; CL ≤ 80 pF;
10% to 90%
Rpu
Ipu
integrated pull-up resistor pull-up resistor to VCC
current when pull-up active VOH = 0.9VCC; C = 80 pF
9
11
13
kΩ
−1
−
−
mA
2004 July 12
19
Philips Semiconductors
Product specification
IC card interface
TDA8024
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP
MAX.
UNIT
Data lines to microcontroller (pins I/OUC, AUX1UC and AUX2UC; with integrated 11 kΩ pull-up resistors
to VDD
)
VOL
VOH
LOW-level output voltage
IOL = 1 mA
0
−
−
−
−
−
−
0.3
V
HIGH-level output voltage no DC load
0.9VDD
VDD + 0.1 V
VDD + 0.1 V
5 and 3 V cards; IOH < −40 µA 0.75VDD
VIL
VIH
ILIH
LOW-level input voltage
HIGH-level input voltage
−0.3
+0.3VDD
V
0.7VDD
VDD + 0.3 V
HIGH-level input leakage
current
VIH = VDD
VIL = 0 V
−
10
µA
IL
LOW-level input current
−
9
−
−
−
600
13
µA
kΩ
µs
µs
Rpu
tt(DI)
tt(DO)
integrated pull-up resistor pull-up resistor to VCC
data input transition time VIL(max) to VIH(min)
11
−
1.2
0.1
data output transition time Vo = 0 to VDD; CL < 30 pF;
10% to 90%
−
Ipu
current when pull-up active VOH = 0.9VDD; C = 30 pF
−1
−
−
mA
Internal oscillator
fOSC(int) frequency of internal
oscillator
Reset output to card reader (pin RST)
inactive mode
active mode
55
140
2.7
200
3.2
kHz
2.2
MHz
Vo(inactive)
output voltage
inactive mode
no load
0
0
0
−
0
−
−
−
−
−
−
−
−
−
−
0.1
0.3
−1
V
Io(inactive) = 1 mA
inactive mode; pin grounded
RST enabled
V
Io(inactive)
output current
mA
µs
V
td(RSTIN-RST) RSTIN to RST delay
VOL LOW-level output voltage
2
IOL = 200 µA
0.2
VCC
VCC
0.4
0.1
0.1
IOL = 20 mA (current limit)
V
CC − 0.4
V
VOH
HIGH-level output voltage IOH = −200 µA
IOH = −20 mA (current limit)
0.9VCC
V
0
−
−
V
tr
tf
rise time
fall time
CL = 100 pF; VCC = 5 or 3 V
CL = 100 pF; VCC = 5 or 3 V
µs
µs
Clock output to card reader (pin CLK)
Vo(inactive)
output voltage
inactive mode
no load
0
0
0
0
−
−
−
−
−
−
−
−
0.1
0.3
−1
V
Io(inactive) = 1 mA
CLK inactive; pin grounded
IOL = 200 µA
V
Io(inactive)
VOL
output current
mA
V
LOW-level output voltage
0.3
VCC
VCC
0.4
16
IOL = 70 mA (current limit)
V
CC − 0.4
V
VOH
HIGH-level output voltage IOH = −200 µA
IOH = −70 mA (current limit)
CL = 30 pF; note 5
0.9VCC
V
0
V
tr
rise time
−
ns
2004 July 12
20
Philips Semiconductors
Product specification
IC card interface
TDA8024
SYMBOL
PARAMETER
CONDITIONS
CL = 30 pF; note 5
MIN.
TYP
MAX.
16
UNIT
tf
fall time
−
−
−
ns
%
δ
duty factor (except for
CL = 30 pF; note 5
45
55
fXTAL
)
SR
slew rate
slew up or down; CL = 30 pF
0.2
−
−
V/ns
V
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−0.3
0.7VDD
−
−
−
−
+0.3VDD
VDD + 0.3 V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
0 < VIH < VDD
1
µA
ILIH
HIGH-level input leakage
current
−
−
1
µA
Card presence inputs (pins PRES and PRES); note 7
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−0.3
0.7VDD
−
−
−
−
+0.3VDD
V
VDD + 0.3 V
ILIL
LOW-level input leakage
current
0 < VIL < VDD
0 < VIH < VDD
5
µA
ILIH
HIGH-level input leakage
current
−
−
5
µA
Interrupt output (pin OFF; NMOS drain with integrated 20 kΩ pull-up resistor to VDD
)
VOL
VOH
Rpu
LOW-level output voltage
IOL = 2 mA
0
−
−
0.3
−
V
HIGH-level output voltage IOH = −15 µA
0.75VDD
16
V
integrated pull-up resistor 20 kΩ pull-up resistor to VDD
20
24
kΩ
Protection and limitation
ICC(sd) shutdown and limitation
−
130
150
+15
mA
mA
current pin VCC
II/O(lim)
limitation current pins I/O,
AUX1 and AUX2
−15
−
ICLK(lim)
IRST(lim)
Tsd
limitation current pin CLK
limitation current pin RST
shut-down temperature
−70
−20
−
−
+70
+20
−
mA
mA
°C
−
150
Timing
tact
tde
t3
activation time
see Fig.7
see Fig.8
see Fig.7
50
50
50
−
220
100
130
µs
µs
µs
deactivation time
80
−
start of the window for
sending CLK to the card
t5
end of the window for
sending CLK to the card
see Fig.7
140
5
−
220
11
µs
tdebounce
debounce time pins PRES see Fig.10
and PRES
8
ms
2004 July 12
21
Philips Semiconductors
Product specification
IC card interface
TDA8024
Notes
1. All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is
specified as a function of VDD or VCC it means their actual value at the moment of measurement.
2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18
is not connected in the TDA8024AT
3. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low
ESR both with values of 100 nF, or one 100 nF and one 220 nF (see Fig.13).
4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF.
t1
5. Transition time and duty factor definitions are shown in Fig.12; δ =
--------------
t1 + t2
6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1.
7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 µA current source to GND
(PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
t
t
f
r
V
V
V
OH
OH
OL
90%
90%
+ V
OL
2
10%
10%
t
t
2
1
MDB058
Fig.12 Definition of output and input transition times.
13 APPLICATION INFORMATION
• Track C3 should be placed as far as possible from the
other tracks
Performance can be affected by the layout of the
application. For example, an additional cross-capacitance
of 1 pF between card reader contacts C2 and C3 or C2
and C7 can cause contact C2 to be polluted with high
frequency noise from C3 (or C7). In this case, include a
100 pF capacitor between contacts C2 and CGND.
• The track connecting CGND to C5 should be straight
(the two capacitors on C1 should be connected to this
ground track)
• Avoid ground loops between CGND, PGND and GND
• Decouple VDDP and VDD separately; if the two supplies
are the same in the application, then they should be
connected in star on the main track.
Application recommendations:
• Ensure there is ample ground area around the TDA8024
and the connector; place the TDA8024 very near to the
connector; decouple the VDD and VDDP lines (these lines
are best positioned under the connector)
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 should be less than
100 ps.
• The TDA8024 and the microcontroller must use the
same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V,
CMDVCC, and OFF are referred to VDD; if pin XTAL1 is
to be driven by an external clock, also refer this pin to
VDD
Reference layouts are provided in “Application
note 10141”, available on request.
2004 July 12
22
Philips Semiconductors
Product specification
IC card interface
TDA8024
CLKDIV1
CLKDIV2
5V/3V
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
100 nF
10 µF
2
3
+5 V
PGND
S2
4
33 pF
3.3 V POWERED
MICROCONTROLLER
5
V
DDP
(1)
100 nF
6
GND
S1
7
100 nF
V
V
TDA8024
UP
DD
8
(2)
+3.3 V
PRES
PRES
I/O
RSTIN
(1)
100 nF
9
CMDVCC
PORADJ
10
11
12
13
14
+3.3 V
V
AUX2
AUX1
CC
RST
CLK
V
DD
58.1 kΩ
CGND
(3)
100 kΩ
+3.3 V
(4)
100 nF
(7)
CARD READ
(normally closed type)
41.9 kΩ
(5)
220 nF
C5 C1
C6 C2
(6)
C7 C3
C8 C4
K1
K2
MDB050
(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).
(2) TDA8024 and the microcontroller must use the same VDD supply.
(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
(4) Mount one low ESR-type 100 nF capacitor close to pin VCC
.
(5) Mount one low ESR-type 100 or 220 nF capacitor close to C1 contact (less than 100 mm from it).
(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks.
(7) Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2.
Pin 18 is not connected in the TDA8024AT.
Fig.13 Application diagram.
2004 July 12
23
Philips Semiconductors
Product specification
IC card interface
TDA8024
14 PACKAGE OUTLINES
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
H
v
M
A
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.71
0.014 0.009 0.69
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT136-1
075E06
MS-013
2004 July 12
24
Philips Semiconductors
Product specification
IC card interface
TDA8024
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
D
E
A
X
c
H
v
M
A
y
E
Z
15
28
Q
A
2
(A )
3
A
A
pin 1 index
1
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.8
0.5
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT361-1
MO-153
2004 July 12
25
Philips Semiconductors
Product specification
IC card interface
TDA8024
15 SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
15.1 Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 °C to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending
on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
15.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270 °C and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 July 12
26
Philips Semiconductors
Product specification
IC card interface
TDA8024
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
PLCC(5), SO, SOJ
not suitable(4)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not recommended(7)
suitable
not suitable
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
2004 July 12
27
Philips Semiconductors
Product specification
IC card interface
TDA8024
16 DATA SHEET STATUS
DATA SHEET
LEVEL
PRODUCT
STATUS(2)(3)
DEFINITION
STATUS(1)
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17 DEFINITIONS
18 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 July 12
28
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R63/03/pp29
Date of release: 2004 July 12
Document order number: 9397 750 13195
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