TDA8025HN/C1,557_技术文档

TDA8025

IC card interface

Rev. 01 — 6 April 2009

Product data sheet

1. General description

The TDA8025 is a cost-effective analog interface for asynchronous smart cards operating

at 3 V, 1.8 V or optionally, 1.2 V. Using few external components, the TDA8025 provides

integrated supply, protection and control functions for a range of applications.

2. Features

I Integrated circuit smart card interface

I 3 V, 1.8 V or 1.2 V smart card supply

I Low power consumption in inactive mode

I Three protected, half duplex, bidirectional buffered input/output lines (C4, C7 and C8)

I V_CCregulation:

N 3 V, 1.8 V or optionally 1.2 V at ± 5 % using one 220 nF and one 470 nF low ESR

multilayer ceramic capacitor.

N Current pulse handling for pulses of 40 nAs at V_CC= 3 V, 15 nAs at V_CC= 1.8 V or

V_CC= 1.2 V up to 20 MHz

I Thermal and short-circuit protection for all card contacts

I Automatic activation and deactivation sequences triggered by short-circuit, card

take-off, overheating, falling V_DD(INTF)and V_DD(INTREGD)

I Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV

I Clock signal using the internal oscillator or an external crystal (≤ 26 MHz) connected to

pin XTAL1

I Card clock generation up to 20 MHz with synchronous frequency changes of f_xtal

,

¹⁄₂f_xtal, ¹⁄₄f_xtalor ¹⁄₈f_xtalusing pins CLKDIV1 and CLKDIV2

I Non-inverted control of pin RST using pin RSTIN

I NDS certiﬁed

I Supply supervisors during power on and off:

N V_DD(INTREGD)using a ﬁxed threshold

N V_DD(INTF)using resistor bridge threshold adjustment

I Built-in debouncing on card presence contacts (typically 4.5 ms)

I Multiplexed status signal using pin OFFN

3. Applications

I Pay TV

I Electronic payment

I Identiﬁcation

I Bank card readers

TDA8025

NXP Semiconductors

IC card interface

4. Quick reference data

Table 1.

Symbol

Supplies

V_DDI(REG)

Quick reference data

Parameter

Conditions

Min

Typ

Max

Unit

regulator input

supply voltage

pin CONFIG = ground

3.6

3

5

5.5

3.6

V

pin CONFIG = V_DDI(REG); regulator is

bypassed

3.3

[1]

V_DD(INTF)

interface supply

voltage

pin CONFIG = ground

1.6

3.0

3.3

V

pin CONFIG = V_DDI(REG)and V_DD(INTF)not

connected to V_DDI(REG)and V_DD(INTREGD)

V_DDI(REG)

+ 0.3

pin CONFIG = V_DDI(REG)with V_DD(INTF)

connected to V_DDI(REG)and V_DD(INTREGD)

3

3.3

3.6

V

I_DDI(REG)

regulator input

supply current

inactive mode

V_DDI(REG)= 5 V; f_xtal= stopped

V_DDI(REG)= 5 V; f_xtal= 10 MHz;

-

300

2.5

µA

mA

f

_CLK= ¹⁄₈f_XTAL

active mode

V_CC= 3 V; I_CC= 65 mA

V_CC= 1.8 V; I_CC= 65 mA

V_CC= 1.2 V; I_CC= 30 mA

-

85

50

mA

Card supply voltage

V_CC

supply voltage

including ripple

inactive mode

no load

−0.1

-

+0.1

+0.3

V

I_CC= 1 mA

active mode

3 V card:

I_CC< 65 mA DC

single current pulse −100 mA; 2 µs

2.85

2.76

3.05

3.15

3.20

V

current pulses of 40 nAs at

I_CC< 200 mA; t < 400 ns

1.8 V card:

I_CC< 65 mA DC

1.71

1.66

1.83

1.89

1.94

V

single current pulse −100 mA; 2 µs

current pulses of 15 nAs with

I_CC< 200 mA; t < 400 ns

1.2 V card:

I_CC< 30 mA DC

1.1

1.2

1.3

V

single current pulse −100 mA; 2 µs

1.1

current pulses of 15 nAs with I_CC

< 200 mA; t < 400 ns

1.10

V_ripple(p-p)

peak-to-peak ripple pin V_CC; 20 kHz to 200 MHz

voltage

-

350

mV

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

2 of 38

TDA8025

NXP Semiconductors

IC card interface

Table 1.

Symbol

I_CC

Quick reference data …continued

Parameter

Conditions

0 V to 3 V

Min

Typ

Max

65

Unit

mA

supply current

-

0 V to 1.8 V

0 V to 1.2 V

up or down

-

65

mA

-

30

mA

SR

slew rate

0.02

0.14

0.26

V/µs

General

t_deact

P_tot

[2]

deactivation time

total sequence

35

-

80

-

100

µs

total power

dissipation

T_amb= −25 °C to +85 °C

0.56

W

T_amb

ambient temperature

−25

-

+85

°C

[1] To enable the microcontroller to provide the required maximum voltage input level on XTAL1, V_DD(INTF)must not exceed

V_DD(INTREGD)+ 0.3 V. See Section 8.1 on page 7 for speciﬁc limitations on the maximum V_DD(INTF)voltage and Table 8 on page 23 for

the limits of XTAL1.

[2] See Figure 12 on page 18.

5. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

TDA8025HN

HVQFN32 plastic thermal enhanced very thin quad ﬂat package; no leads;

SOT617-1

32 terminals; body 5 × 5 × 0.85 mm

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

3 of 38

TDA8025

NXP Semiconductors

IC card interface

6. Block diagram

V

DDI(REG)

TEST2

TEST1 TEST4

10 µF

GND

20

CONFIG

16

21

2

3

32

24

19

REGULATOR

TEST

TEST3

100 nF

V

DD(INTREGD)

V

DD(INTF)

R1

10 µF

SUPPLY

INTERNAL

REFERENCE

INTERNAL

OSCILLATOR

TDA8025

PORADJ 25

(1)

R2

VOLTAGE

SENSE

CLKUP

18

14

V

ALARMN

EN1

CC

V

CC

10

9

470 nF

PVCC

CGND

PRES

LOOP

PRESN

220 nF

17

15

22

1

EN4

EN3

RST

SEQUENCER

RESET

GENERATOR

RSTIN

CMDVCCN

OFFN

23

6

CLK

CLOCK

CIRCUIT

CLOCK

GENERATOR

EN2

CLK

CLKDIV1

CLKDIV2

ENCLKIN

VCC_SEL1

VCC_SEL2

V

DD(INTREGD)

INTERFACE

C5

C6

C7

C8

C1

5

MULTIPLEXER

THERMAL

PROTECTION

C2

C3

C4

26

7

11

13

12

I/O

TRANSCEIVER

Level shifter

(V

)

XTAL

DD(INTF)

8

AUX1

AUX2

I/O

TRANSCEIVER

OSCILLATOR

(V

)

DD(INTREGD)

I/O

220 nF

TRANSCEIVER

4

27

28

29

30

31

100 nF

XTAL1

AUX1UC

AUX2UC

V

XTAL2

I/OUC

001aai957

DD(INTF)

(1) Optional external resistor bridge. If this bridge is not needed, connect pin PORADJ to V_DD(INTF)

.

Fig 1. Block diagram

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

4 of 38

TDA8025

NXP Semiconductors

IC card interface

7. Pinning information

7.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CMDVCCN

TEST1

TEST3

OFFN

RSTIN

TEST2

V

DDI(REG)

DD(INTF)

TDA8025

CLKDIV2

CLKDIV1

GND

V

DD(INTREGD)

CC

VCC_SEL1

VCC_SEL2

RST

001aai958

Transparent top view

Fig 2. Pin conﬁguration (HVQFN32)

7.2 Pin description

Table 3.

Pin description

Pin Type^[1]Description

Symbol

CMDVCCN

TEST1

1

2

3

4

5

I

microcontroller start activation sequence input; active LOW

test pin; connect to GND

I

TEST2

I

test pin; connect to GND

V_DD(INTF)

CLKDIV2

P

I

interface supply voltage

sets the clock frequency; used together with pin CLKDIV1;

see Table 4 on page 12

CLKDIV1

6

7

I

sets the clock frequency; used together pin CLKDIV2; see Table 4 on

page 12

VCC_SEL1

optional 1.2 V selection control signal:

active HIGH: V_CC= 1.2 V

active LOW: disables 1.2 V selection

3 V or 1.8 V selection control signal:

active LOW: V_CC= 3 V

VCC_SEL2

8

I

active HIGH: V_CC= 1.8 V when pin VCC_SEL1 is active LOW

card presence contact input; active LOW^[2]

card presence contact input; active HIGH^[2]

card input/output data line (C7)^[3]

card auxiliary 2 input/output data line (C8)^[3]

card auxiliary 1 input/output data line (C4)^[3]

PRESN

PRES

I/O

9

I

10

11 I/O

12 I/O

13 I/O

AUX2

AUX1

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

5 of 38

TDA8025

NXP Semiconductors

IC card interface

Table 3.

Pin description …continued

Symbol

CGND

CLK

Pin Type^[1]Description

14

15

16

G

O

I

card signal ground

card clock (C3)

CONFIG

3.3 V or 5 V core regulator supply voltage selection; see Figure 3 on

page 7

RST

V_CC

17

18

O

P

card reset (C2)

card supply (C1); decouple to pin CGND using one 470 nF and one

220 nF capacitor with an Equivalent Series Resistance

(ESR) < 100 mΩ

V_DD(INTREGD)19

P

G

P

I

internally regulated supply voltage

ground

GND

20

21

22

23

V_DDI(REG)

RSTIN

OFFN

regulator input supply voltage

microcontroller card reset input; active HIGH

NMOS interrupt to microcontroller^[4]; active LOW; see Section 8.10

on page 19

O

TEST3

24

25

26

27

28

O

I

test pin; do not connect to the application

PORADJ

ENCLKIN

XTAL2

power-on reset threshold adjustment input^[4]

enable external clock on pin XTAL1; active HIGH

crystal connection pin; open when used with an external clock source

crystal connection pin; supply reference V_DD(INTREGD)

external clock input; supply reference V_DD(INTF)

microcontroller input/output data line^[4]

microcontroller auxiliary 1 input/output data line^[4]

microcontroller auxiliary 2 input/output data line^[4]

test pin; connect to GND

I

O

I

XTAL1

I/OUC

29 I/O

30 I/O

31 I/O

AUX1UC

AUX2UC

TEST4

32

I

[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.

[2] If pin PRESN or pin PRES is true, the card is considered to be present. During card insertion, debouncing

can occur on these signals. To counter this, the TDA8025 has a built-in debouncing timer (typically 4.5 ms).

[3] Using the internal pull-up resistor connected to pin V_CC

.

[4] Using the internal pull-up resistor connected to pin V_DD(INTF)

.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

6 of 38

TDA8025

NXP Semiconductors

IC card interface

8. Functional description

Remark: Throughout this document the ISO7816 terminology conventions have been

adhered to and it is assumed that the reader is familiar with these.

8.1 Power supplies

Two supply selections can be made using pin CONFIG (see Figure 3) depending on the

active state of the pin:

• pin CONFIG is LOW: supply is pin V_DDI(REG). The voltage range of the pin is between

3.6 V and 5.5 V. The regulator output range is between 3 V and 3.6 V.

• pin CONFIG is HIGH: supply pins V_DDI(REG)and V_DD(INTREGD)are connected together

to bypass the regulator. Pin V_DDI(REG)voltage is between 3 V and 3.6 V.

Remark: V_DD(INTF)must not exceed V_DD(INTREGD)+ 0.3 V.

10 µF

V

DDI(REG)

10 µF

100 nF

V

DD(INTREGD)

GND CONFIG

20 16

GND CONFIG

20 16

21

19

21

19

REGULATOR

SUPPLY

INTERNAL

REFERENCE

18

14

V

18

14

V

CC

VOLTAGE

SENSE

V

VOLTAGE

SENSE

V

CC

LOOP

CC

470 nF

220 nF

470 nF

220 nF

LOOP

CGND

001aai959

001aai960

3.6 V < V_DDI(REG)< 5.5 V

3 V < V_DD(INTREGD)< 3.6 V

Fig 3. Power strategy

The following examples illustrate the voltage restrictions for V_DD(INTF)

.

• CONFIG pin driven to GND: when V_DD(INTREGD)is generated by the internal regulator,

V_DD(INTF)must not exceed 3.3 V.

• CONFIG pin is driven by V_DDI(REG)without V_DD(INTF)tied to V_DDI(REG)while

V_DD(INTREGD)is tied to V_DDI(REG): V_DD(INTF)must not exceed V_DDI(REG)+ 0.3 V.

• CONFIG pin is driven by V_DDI(REG)with V_DD(INTF)tied to both V_DDI(REG)and

V_DD(INTREGD): there no are restrictions for V_DD(INTF)

.

The TDA8025 is held in the reset state until V_DD(INTREGD)reaches V_th+ V_hysand

PORADJ V_th+ V_hysplus the t_w(POR)delay. If the V_DD(INTREGD)and PORADJ signals fall

below V_th, an automatic contact deactivation is triggered.

All interface signals to the microcontroller are referenced to V_DD(INTF). In addition, all card

contacts remain inactive during power-up and power-down cycles.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

7 of 38

TDA8025

NXP Semiconductors

IC card interface

After powering up the device, pin OFFN remains LOW until pins CMDVCCN and PRES

are both HIGH or pin CMDVCCN is HIGH and pin PRESN is LOW. During power off, pin

OFFN is driven LOW when V_DD(INTREGD)is below the falling threshold voltage (V_th).

When pin CMDVCCN is HIGH, the internal oscillator frequency (f_osc(int)) is switched to Low

frequency (inactive) mode to reduce power consumption.

8.2 Voltage supervisors

8.2.1 Block diagram

V

DD(INTF)

R1

PORADJ

V

DD(INTREGD)

R2

REFERENCE

VOLTAGE

V

DD(INTREGD)

001aai961

Fig 4. Voltage supervisor circuit

8.2.2 Description

The voltage supervisors provide both the Power-On Reset (POR) and supply drop-out

detection functions. They control the internal regulated supply voltage (V_DD(INTREGD)) and

the microcontroller interface supply voltage (V_DD(INTF)) to ensure problem-free operation of

the TDA8025.

By monitoring both V_DD(INTREGD)and V_DD(INTF), the voltage supervisors ensure these

voltages are high enough to ensure correct operation of the TDA8025 and ﬂawless

communication between it and the microcontroller. This information is combined and sent

to the digital controller in order to reset the TDA8025.

An extension of the power-on reset pulse width of ± 8 ms (t_w(POR)) is used to maintain the

TDA8025 in inactive mode after the supply voltage power on or off sequences (see

Figure 5).

V

+ V

hys

th

V

th

V

DD(INTREGD)

ALARMN

(internal signal)

t

w(POR)

Power on

Supply dropout

Power off

001aai962

Fig 5. Voltage supervisors V_DD(INTREGD)and V_DD(INTF)

Rev. 01 — 6 April 2009

TDA8025_1

Product data sheet

8 of 38

TDA8025

NXP Semiconductors

IC card interface

8.2.3 V_DD(INTREGD)voltage supervisor with pin PORADJ connected to V_DD(INTF)

The TDA8025 remains in inactive mode irrespective of the levels on the command lines

when

• V_DD(INTREGD)is less than V_th+ V_hys(on pin V_DD(INTREGD)

)

• Pin PORADJ (monitoring V_DD(INTF)) is less than V_th+ V_hys

In both cases, this lasts for the duration of t_w(POR)after V_DD(INTREGD)(on pin V_DD(INTREGD)

)

and V_DD(INTF)(on pin V_DD(INTF)) have reached a level higher than V_th+ V_hys. Two threshold

voltages (V_th) are set by the hardware as follows:

• V_DD(INTREGD)threshold voltage: is set to the minimum supply voltage (2.7 V) speciﬁed

for the digital part of the TDA8025

• V_DD(INTF)threshold voltage: is set to 1.24 V; see Table 8 on page 23 for detailed

information.

8.2.4 V_DD(INTF)voltage supervisor with external divider on pin PORADJ

An external resistor bridge can be used to divide V_DD(INTF)on pin PORADJ to adapt the

detection threshold when monitoring the microcontroller interface supply voltage.

Connecting the external resistor bridge as illustrated in Figure 4 on page 8 (R1 connected

to V_DD(INTF)and R2 connected to GND) to pin PORADJ overrides the internal threshold

voltage V_thon pin V_DD(INTF)

.

The threshold voltage on pin V_DD(INTF)is calculated as follows:

1 + R1

R2

V_thon pin V_DD(INTF)= V_bg

(1)

---------------

where

• V_bgis the bandgap voltage

When the resistor bridge is not used, pin PORADJ must be connected to pin V_DD(INTF)

.

8.2.4.1 R1 and R2 resistor value calculation

This section describes how to calculate the values for resistors R1 and R2, taking into

account the IC detector threshold spread and the external resistance, while ensuring

reliable activation.

If for example, the controller is supplied by a regulator at 3.3 V ± 20 %. Activation can be

triggered above V_DD(INTF)= 3.3 V − 20 % (in this example 2.64 V). This activation

threshold is deﬁned as V_{DD(INTF)actmin}; i.e. the minimum value of V_DD(INTF)above which

activation can always be triggered.

In addition to this external input, activation is permitted provided all the following

conditions are met (see Table 8 on page 23): card presence, IC temperature, V_DD(INTF)

and V_DD(INTREGD)supplies, etc.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

9 of 38

TDA8025

NXP Semiconductors

IC card interface

The voltage on PORADJ (V_PORADJ) can be calculated as: V_PORADJ= α × V_DD(INTF)

where:

• V_DD(INTF)is the interface supply voltage

• ratio α

1

α =

(2)

(3)

----------------

R1

R2

1 +

------

An activation can be triggered if

V_th(max)

V_DD(INTF)× α > V_th(max)V_DD(INTF)

>

-------------------

α

where

• V_th(max)is the maximum rising external threshold voltage

The resistance spread of R1 between a minimum value R1_minand a maximum value

R1_maxinduces a spread of the ratio α. This is also true for R2. Based on this:

V_th(max)

V_{DD(INTF)actmin}

=

(4)

(5)

-------------------

α_min

where

1

α_min

=

------------------------

R1_max

1 +

--------------

R2_min

If ∆R1 is the maximum spread of R1 and ∆R2 is the maximum spread of R2 then:

∆R1

R1_max= R1_nom+ ∆R1 = R1_nom1 +

(6)

(7)

---------------

R1_nom

∆R2

R2_min= R2_nom– ∆R2 = R2_nom1 –

---------------

R2_nom

V_th(max)

1

α_min

=

(8)

------------------------------------------------------------

----------------------------------------------

R1_nom(1 + β)

---------------------------------------

V_{DD(INTF)actmin}

∆R1

R1_nom1 +

---------------

1 +

-------------------------------------

R1_nom

R2_nom(1 – β)

1 +

--------------------------------------------------

∆R2

R2_nom1 –

---------------

R2_nom

where

• where β is the accuracy ratio of R1 and R2 (R1 and R2 are considered to be of the

same type).

Then

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

10 of 38

TDA8025

NXP Semiconductors

IC card interface

R1_nom

V

(1 – β)

----------------

(1 + β)

=

^{DD(INTF)actmin}– 1

---------------------------------------

(9)

---------------

R2_nom

V_th(max)

R_sum

R2_nom

=

(10)

------------------------------

--------------------------------------------------------------------------------------------

R1_nom

V

(1 – β)

----------------

(1 + β)

1 +

^{DD(INTF)actmin}– 1

---------------

---------------------------------------

R2_nom

V_th(max)

If we target 1 % accuracy resistors (β = 0.01) and R_sum= 100 kΩ; V_th(max)= 1.33 V (see

Table 8 on page 23) and V_{DD(INTF)actmin}= 2.64 V then

• R1_nom= 50.88 kΩ

• R2_nom= 49.12 kΩ

Deactivation always occurs when

V_th(min)

V_PORADJ< V_th(min)V_{DD(INTF)deactmax}

=

(11)

-------------------

α_max

where

• V_th(min)is the minimum falling external threshold voltage

• V_{DD(INTF)deactmax}is the maximum value of V_DD(INTF)below which deactivation always

occurs

• α_max

V_th(min)

1

α_max

=

(12)

----------------------------------------------

R1_nom(1 – β)

---------------------------------------------

V_{DD(INTF)deactmax}

1 +

-------------------------------------

R2_nom(1 + β)

With the resulting values for R1_nom, R2_nomand β; V_th(min)= 1.17 V (see Table 8 on

page 23) then V_{DD(INTF)deactmax}is 2.28 V.

8.3 Clock circuits

The clock signal (pin CLK) to the card is either generated by the clock signal input on pin

XTAL1 or from a crystal (f_xtal≤ 26 MHz) connected between pins XTAL1 and XTAL2. The

voltage level applied to pin ENCLKIN deﬁnes which clock signal is used. When pin

ENCLKIN is HIGH, connect the external clock to pin XTAL1.

Driving pin ENCLKIN LOW causes the external crystal to generate frequency f_xtal. Using

pins CLKDIV1 and CLKDIV2, the crystal frequency can be set to either f_xtal, ¹⁄₂f_xtal, ¹⁄₄f_xtal

or ¹⁄₈f_xtal

.

The frequency change is synchronous and as such during transition, no pulse is shorter

than 45 % of the smallest period. In addition, only the ﬁrst and last clock pulse around the

change have the correct width. When dynamically changing the frequency, the

modiﬁcation is only effective after 10 periods of XTAL1.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

11 of 38

TDA8025

NXP Semiconductors

IC card interface

The duty cycle on pin CLK should be between 45 % and 55 %. To ensure this, the

following must be applied:

• when the CLK frequency is f_xtal

:

If an external clock is connected to pin XTAL1, the duty cycle should be between 48 %

and 52 % with an input signal period transition time of less than 5 %.

If a crystal is used to generate f_xtal, the duty cycle on pin CLK should be between

45 % and 55 % depending on the layout, crystal characteristics and frequency.

• when CLK frequency is either f_xtal, ¹⁄₂f_xtal, ¹⁄₄f_xtalor ¹⁄₈f_xtal

:

The duty cycle is guaranteed between 45 % and 55 % of the period frequency

divisions.

When a crystal is used, it runs when pin ENCLKIN is driven LOW.

CLKDIV1

CLKDIV2

6

5

15 CLK

CLOCK

CIRCUIT

ENCLKIN 26

MULTIPLEXER

XTAL

OSCILLATOR

27

28

XTAL1

XTAL2

(1)

≤ 26 MHz

001aai963

(1) External crystal (optional).

Fig 6. Clock circuits

The clock signal is applied to the card based on the activation sequence as shown on the

timing diagrams; see Figure 8 on page 15 to Figure 13 on page 19.

When the signal applied to XTAL1 is controlled by the microcontroller, the clock signal is

sent to the card only after the activation sequence ﬁnishes.

Table 4.

Clock conﬁguration

Clock circuitry deﬁnition (pins CLKDIV1 and CLKDIV2 can be changed simultaneously; a

>10 XTAL1 period delay is needed. The minimum duration of any CLK state is 10 XTAL1 periods).

CLKDIV1

CLKDIV2

CLK

0

1

0

1

0

¹⁄₈f_xtal

¹⁄₄f_xtal

¹⁄₂f_xtal

f_xtal

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

12 of 38

TDA8025

NXP Semiconductors

IC card interface

8.4 Input and output circuits

When pins I/O and I/OUC are driven HIGH using an 11 kΩ resistor between pins I/O and

V_CCand/or between pins I/OUC and V_DD(INTF), both lines enter the idle state. Pin I/O is

referenced to V_CCand pin I/OUC to V_DD(INTF), thus allowing operation at V_CC≠ V_DD(INTF)

.

The ﬁrst side on which a falling edge occurs becomes the master. An anti-latch circuit

disables falling edge detection on the other line, making it the slave. After a time delay

t_d(edge), the NMOS transistor on the slave-side is turned on. It then sends logic 0 to the

master-side. When the master returns logic 1, the PMOS transistor on the slave side is

turned on during the time delay (t_pu). After this sequence, both the master and slave return

to their idle states.

The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8025

capable of delivering more than 1 mA, up to an output voltage of 0.9 V_CC, at a load of

80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the

internal pull-up resistor value and load current. The current sent to and received from the

card’s I/O lines is internally limited to 15 mA at a maximum frequency of 1 MHz.

001aai964

8

4

I

I/O

(A)

V I/O

(V)

OH

V I/O

6

4

2

0

3

2

1

0

I

I/O

OH

0

20

40

60

80

100

t (ns)

Fig 7. Output voltage and current on pins I/O, AUX1 and AUX2 as a function of time

during LOW-to-HIGH transitions

8.5 Inactive mode

After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum

number of circuits are active while the TDA8025 waits for the microcontroller to start a

session. The inactive mode conditions are as follows:

• all card contacts are inactive. The impedance between the contacts and GND is

approximately 200 Ω.

• pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 kΩ pull-up

resistor connected to V_DD(INTF)

• the voltage generators and crystal oscillator are stopped

• the voltage supervisor is active

• the internal oscillator runs in low frequency mode

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

13 of 38

TDA8025

NXP Semiconductors

IC card interface

8.6 Activation sequence

After the power-on and internal pulse width delay, the microcontroller checks the presence

of the card using signal OFFN.

• The card is present when pins OFFN and CMDVCCN are HIGH

• The card is not present when pin OFFN is LOW and pin CMDVCCN is HIGH

If the card is in the reader (either pin PRESN or pin PRES is true), the microcontroller can

start a card session by pulling pin CMDVCCN LOW. When using an external crystal, the

following sequence is applied (see Figure 8):

1. pin CMDVCCN is pulled LOW (t0)

2. the crystal oscillator is triggered

3. the internal oscillator changes to its high frequency (t1)

4. V_CCrises either from 0 V to 3 V or 1.8 V on a controlled slope (t2)

5. pins I/O, AUX1 and AUX2 which were pulled LOW are driven HIGH (t3)

6. the clock (pin CLK) is applied to the C3 contact (t4)

7. pin RST is enabled (t5)

Calculation of the time delays is as follows:

• t1 = t0 + 2.13 ms

• t2 = t1

• t3 = t1 + 5T/2

• t4 = driven by host controller; > t3 and < t5

• t5 = t1 + 11T/2

Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.

±25 µs. t3 is called t_d(start)and t5 is called t_d(end)

.

The clock is applied to the card in one of the following ways:

• using pin RSTIN: The clock (pin CLK) start-up can be selected at either t3 or t5 using

pin RSTIN. When pin RSTIN is HIGH and pin CMDVCCN is LOW, setting pin RSTIN

to LOW between delays t3 and t5 sends signal CLK. Pin RSTIN should be held LOW

until after delay t5. After passing t5, pin RST is a copy of pin RSTIN and has no further

effect on pin CLK. It enables the microcontroller to precisely choose the CLK start by

counting clock cycles from the falling edge of the RSTIN signal.

• not using pin RSTIN: If this feature is not needed, set both pins CMDVCCN and

RSTIN to LOW. The clock (pin CLK) will start at delay t3 (a minimum 200 ns after the

input/output transition). After delay t5, pin RSTIN can be set HIGH to receive the card

Answer To Request (ATR).

Remark: Do not perform activation with pin RSTIN permanently pulled HIGH.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

14 of 38

TDA8025

NXP Semiconductors

IC card interface

CMDVCCN

XTAL

V

CC

I/O

ATR

CLK

RSTIN

RST

I/OUC

OSCINT

low frequency

t0 t1 = t2

high frequency

t

t4

t

= t

d(start)

d(end) act

001aai965

Fig 8. Activation sequence: CLK controlled by pin RSTIN with the crystal oscillator

CMDVCCN

XTAL

V

CC

I/O

ATR

CLK

> 200 ns

RSTIN

RST

I/OUC

OSCINT

low frequency

t0 t1 = t2

high frequency

t4

t

= t

d(end) act

t

d(start)

001aai966

Fig 9. Activation sequence: CLK not controlled by pin RSTIN with the crystal oscillator

The following sequence occurs when using an external clock connected to pin XTAL1 (see

Figure 10):

1. external clock (XTAL1) started by the microcontroller (t0)

2. CMDVCCN is pulled LOW and the internal oscillator changes to its high frequency (t1)

3. V_CCrises either from 0 V to 3 V or 0 V to 1.8 V on a controlled slope (t2)

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

15 of 38

TDA8025

NXP Semiconductors

IC card interface

4. pins I/O, AUX1 and AUX2 are enabled (t3)

5. CLK is applied to the C3 contact (t4)

6. pin RST is enabled (t5)

Calculation of the time delays is as follows:

• t1 = t0 + 2.13 ms

• t2 = t1 = 3T/2 + 3(¹⁄_fosc(int)low

)

• t3 = t1 + 5T/2

• t4 = driven by the host controller; > t3 and < t5

• t5 = t1 + 11T/2

Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.

±25 µs). t3 is called t_d(start)and t5 is called t_d(end). f_osc(int)lowis the low (or inactive mode)

frequency of the deﬁned f_osc(int)parameter.

The CLK is applied to the card under control of pin RSTIN in exactly the same way as with

the crystal oscillator.

Remark: Do not perform activation with pin RSTIN permanently pulled HIGH.

CMDVCCN

XTAL1

V

CC

I/O

ATR

CLK

RSTIN

RST

I/OUC

OSCINT

low frequency

t0 t1 = t2

high frequency

t

t4

t

= t

d(start)

d(end) act

001aai967

Fig 10. Activation sequence: CLK controlled by pin RSTIN with an external clock

connected to pin XTAL1

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

16 of 38

TDA8025

NXP Semiconductors

IC card interface

CMDVCCN

XTAL1

V

CC

I/O

ATR

CLK

> 200 ns

RSTIN

RST

I/OUC

OSCINT

low frequency

t0 t1 = t2

high frequency

t4

t

= t

d(end) act

t

d(start)

001aai968

Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock

connected to pin XTAL1

8.7 Active mode

When the activation sequence has ﬁnished, the TDA8025 is in active mode. This mode

enables data exchange between the card and the microcontroller using the input and

output lines.

Depending on the layout and application test conditions, line C2 could become polluted

with high frequency noise from line C3. For example, due to an additional 1 pF

capacitance between lines C2/C3 and/or lines C2/C7. It is recommended that a 100 pF

capacitor is added between line C2 and pin CGND, if this occurs.

When building the application, the following recommendations should be adhered to:

• Keep track C3 as far away as possible from other tracks.

• Keep the connection between pin CGND and line C5 straight. The two capacitors on

line C1 should be connected to this ground track.

• Do not use ground loops between CGND and GND.

Following these layout recommendations will ensure that noise remains within the

speciﬁcations and jitter on line C3 is less than 100 ps.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

17 of 38

TDA8025

NXP Semiconductors

IC card interface

8.8 Deactivation sequence

When a session is completed, the microcontroller sets pin CMDVCCN to HIGH. The

circuit then executes an automatic deactivation sequence by counting the sequencer back

to the inactive state (see Figure 12 and Figure 13):

1. pin RST is pulled LOW (t11)

2. the clock is stopped, pin CLK is LOW (t12)

3. pins I/O, AUX1 and AUX2 are pulled LOW (t13)

4. V_CCfalls to zero (t14). The deactivation sequence is completed when V_CCreaches its

inactive state

5. all card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC and

AUX2UC remain pulled up to V_DD(INTREGD)using the 11 kΩ resistor

6. The internal oscillator returns to its low frequency mode

Calculation of the time delays is as follows:

• t11 = t10 + 3T/64

• t12 = t11 + T/2

• t13 = t11 + T

• t14 = t11 + 3T/2

Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.

±25 µs).

CMDVCCN

RST

CLK

I/O

V

CC

XTAL

OSCINT

high frequency

low frequency

t10 t11

t12

t

t13

t14

001aai969

deact

Fig 12. Deactivation sequence with a crystal oscillator

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

18 of 38

TDA8025

NXP Semiconductors

IC card interface

CMDVCCN

RST

CLK

I/O

V

CC

XTAL1

OSCINT

high frequency

low frequency

t10 t11

t12

t

t13

t14

001aai970

deact

Fig 13. Deactivation sequence with an external clock connected to pin XTAL1

8.9 V_CCregulator

Table 5.

Selection of V_CCusing pins VCC_SEL1 and VCC_SEL2

VCC_SEL1

VCC_SEL2

V_CC

0

1

0

1

0

1

3 V

1.8 V

1.2 V

The V_CCbuffer is able to continuously deliver up to:

• 65 mA at 3 V

• 65 mA at 1.8 V

• 30 mA at 1.2 V

The V_CCbuffer has an internal overload protection with a threshold value of ±135 mA.

This detection is ﬁltered, enabling spurious current pulses up to 200 mA with a duration of

up to 200 ns to be drawn by the card without causing deactivation. However, the average

current value must be below maximum.

To enhance V_CCstability, one 470 nF capacitor should be tied to pin CGND near pin 18

and one 220 nF capacitor should be tied to pin CGND near the C1 contact. Both

capacitors should have an ESR < 100 mΩ.

8.10 Fault detection

The following conditions are monitored by the fault detection circuit:

• Short-circuit or high current on pin V_CC

• Card removal during transaction

• V_DD(INTREGD)falling

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

19 of 38

TDA8025

NXP Semiconductors

IC card interface

• V_DD(INTF)falling

• Overheating

Fault detection monitors two different situations (see Figure 15 on page 21):

1. Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in

the reader and HIGH if the card is in the reader. Any supply voltage drop on

V_DD(INTREGD)or V_DD(INTF)is detected by the supply supervisor. This generates an

internal power-on reset pulse but does not act upon the pin OFFN signal. The card is

not powered-up and as such short-circuits and overheating are not detected.

2. Within card sessions, pin CMDVCCN is LOW: when pin OFFN falls LOW, the fault

detection circuit triggers the automatic emergency deactivation sequence (see

Figure 14). When the system controller resets pin CMDVCCN to HIGH, after the

deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN

returns to HIGH. This check identiﬁes the fault as either a hardware problem or a card

removal incident.

On card insertion or removal, bouncing can occur in the PRES and/or PRESN signals.

This depends on the type of card presence switch in the connector (normally open or

normally closed) and the mechanical characteristics of the switch. To correct for this, a

debouncing feature is integrated in to the TDA8025. This feature operates at a typical

duration of 640 × (¹⁄_fosc(int)low). See Figure 15 for an overview of the debouncing feature.

Remark: f_osc(int)lowis the low frequency (or inactive) mode of the deﬁned f_osc(int)

parameter.

On card insertion, pin OFFN goes HIGH after the debouncing time has elapsed. When the

card is extracted, the automatic card deactivation sequence is performed on the ﬁrst true

or false transition on pin PRESN or pin PRES. After this pin OFFN goes LOW.

OFFN

PRESN

RST

CLK

I/O

V

CC

XTAL

OSCINT

high frequency

low frequency

t10

t12

t

t13

t14

001aai971

deact

Fig 14. Emergency deactivation sequence after card removal

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

20 of 38

TDA8025

NXP Semiconductors

IC card interface

PRES

OFFN

CMDVCCN

t

deb

(1)

(2)

V

CC

001aai972

(1) Deactivation caused by card removal.

(2) Deactivation caused by short circuit.

Fig 15. Operation of debounce feature pin OFFN in combination with pins CMDVCCN,

PRES and V_CC

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

21 of 38

TDA8025

NXP Semiconductors

IC card interface

9. Limiting values

Remark: All card contacts are protected against any short-circuit to any other card

contact. Stress beyond the levels indicated in Table 6 can cause permanent damage to

the device. This is a short-term stress rating only and under no circumstances implies

functional operation under long-term stress conditions.

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

−0.3

Max

+5.5

Unit

V

V_DDI(REG)

regulator input supply voltage

V_DD(INTREGD)internal regulated supply voltage

V

V_I

input voltage

pins CMDVCCN, TEST1, TEST2,

CLKDIV2, CLKDIV1, VCC_SEL1,

VCC_SEL2, CONFIG, RSTIN,

OFFN, TEST3, PORADJ, ENCLKIN,

XTAL2, XTAL1, I/OUC, AUX1UC and

AUX2UC

V

card contact pins PRES, PRESN,

I/O, RST, AUX1, AUX2 and CLK

−0.3

+6.5

V

T_stg

P_tot

T_j

storage temperature

−55

-

+150

0.56

150

+85

+6

°C

W

total power dissipation

junction temperature

T_amb= −25 °C to +85 °C

-

°C

kV

T_amb

V_ESD

ambient temperature

electrostatic discharge voltage

−25

−6

pins I/O, RST, V_CC, AUX1, CLK,

AUX2, PRES and PRESN; within

typical application

Human Body Model (HBM); all pins;

EIA/JESD22-A114-B, June 2000

−2

+2

kV

V

Machine Model (MM); all pins;

−200

+200

EIA/JESD22-A115-A, October 1997

Charged Device Model (CDM);

all pins, except corner pins

−500

−750

+500

+750

V

only corner pins (1, 8, 9, 16, 17,

24, 25 and 32)

10. Thermal characteristics

Table 7.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

42

Unit

thermal resistance from junction to ambient

with exposed pad soldered

K/W

without exposed pad soldered

62

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

22 of 38

TDA8025

NXP Semiconductors

IC card interface

11. Characteristics

Table 8.

Characteristics of IC supply voltage

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply

V_DDI(REG)

regulator input

supply voltage

pin CONFIG = ground

3.6

3

5

5.5

3.6

V

pin CONFIG = V_DDI(REG)

regulator is bypassed

;

3.3

[1]

[2]

V_DD(INTREGD)internal

regulated supply

voltage

pin CONFIG = ground

3

3.3

3.6

V

V_DD(INTF)

interface supply pin CONFIG = ground

1.6

3.0

3.3

V

voltage

pin CONFIG = V_DDI(REG)

V_DDI(REG)+ 0.3

and V_DD(INTF)not

connected to V_DDI(REG)

and V_DD(INTREGD)

pin CONFIG = V_DDI(REG)

3

3.3

3.6

V

with V_DD(INTF)connected

to V_DDI(REG)and

V_DD(INTREGD)

I_DDI(REG)

regulator input

supply current

inactive mode

V_DDI(REG)= 5 V

-

300

2.5

µA

f

_xtal= stopped

V_DDI(REG)= 5 V

mA

f

_xtal= 10 MHz;

_CLK= ¹⁄₈f_xtal

active mode

V_CC= 3 V; I_CC= 65 mA

V_CC= 1.8 V;

-

85

mA

I

_CC= 65 mA

V_CC= 1.2 V;

_CC= 30 mA

-

50

mA

I

I_DD(INTF)

V_th

interface supply

current

100

µA

threshold voltage pin V_DD(INTREGD); falling

pin V_DD(INTREGD); rising

2.60

2.65

1.17

1.19

50

2.70

2.80

1.24

1.26

100

2.80

2.95

1.31

1.33

150

V

pin PORADJ; falling

V

pin PORADJ; rising

V

V_hys

hysteresis

voltage

pin V_DD(INTREGD)

mV

t_w(POR)

∆V_th/∆T

power-on reset

pulse width

5

-

8

-

18

ms

threshold voltage

variation with

temperature

0.25

mV/°C

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

23 of 38

TDA8025

NXP Semiconductors

IC card interface

Table 8.

Characteristics of IC supply voltage …continued

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol

I_L

Parameter

Conditions

Min

−0.1

−1

Typ

+4

-

Max

+10

+1

Unit

µA

leakage current pin PORADJ < 0.5 V

pin PORADJ > 1 V

µA

Card supply voltage^[3]

C_dec

decoupling

connected to V_CC

550

-

830

nF

capacitance

V_CC

supply voltage

including ripple

inactive mode

no load

−0.1

-

+0.1

+0.3

V

I_CC= 1 mA

active mode

3 V card:

I_CC< 65 mA DC

2.85

2.76

3.05

3.15

3.20

V

single current pulse

−100 mA; 2 µs

current pulses of

40 nAs at

2.76

3.05

3.20

V

I_CC< 200 mA;

t < 400 ns

1.8 V card:

I

_CC< 65 mA DC

1.71

1.66

1.83

1.89

1.94

V

single current pulse

−100 mA; 2 µs

current pulses of

15 nAs with I_CC

1.66

1.83

1.94

V

< 200 mA; t < 400 ns

1.2 V card:

I_CC< 30 mA DC

1.1

1.2

1.3

V

single current pulse

−100 mA; 2 µs

current pulses of

15 nAs with I_CC

< 200 mA; t < 400 ns

1.10

-

1.2

-

1.3

V

V_ripple(p-p)

I_CC

peak-to-peak

ripple voltage

pin V_CC; 20 kHz to

200 MHz

350

mV

supply current

0 V to 3 V

-

65

mA

V/µs

0 V to 1.8 V

0 V to 1.2 V

up or down

-

65

-

30

SR

slew rate

0.02

0.14

0.26

Crystal oscillator: pins XTAL1 and XTAL2

C_ext

external

pins XTAL1/XTAL2;

-

15

pF

capacitance

depending on the crystal

or resonator speciﬁcation

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

24 of 38

TDA8025

NXP Semiconductors

IC card interface

Table 8.

Characteristics of IC supply voltage …continued

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_xtal

f_ext

V_IL

V_IH

crystal frequency card clock reference;

crystal oscillator

2

-

26

MHz

external

frequency

external clock on

pin XTAL1

0

-

26

MHz

V

LOW-level input pin XTAL1

voltage

−0.3

+0.3V_DD(INTF)

HIGH-level input pin XTAL1

voltage

V_DD(INTF)

≤

0.7V_DD(INTF)

-

V_DD(INTF)+ 0.3

V

V_DD(INTREGD)

V_DD(INTF)

V_DD(INTREGD)

Data lines: pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC

>

V_DD(INTREGD)

0.3

+

t_d

delay time

falling edge on pins I/O

and I/OUC or vise versa

-

200

100

1

ns

t_w(pu)

f_io

pull-up pulse

width

ns

input/output

frequency

on data lines

MHz

pF

C_i

input

10

capacitance

Data lines to the card: pins I/O, AUX1 and AUX2^[4]

V_o

output voltage

output current

inactive mode

no load

0

-

0.1

0.3

−1

V

I_o= 1 mA

V

I_o

from data lines when in

inactive mode with pins

grounded

-

mA

V_OL

LOW-level output I_OL= 1 mA

voltage

0

-

0.3

V

I_OL≥ 15 mA

V

_CC− 0.4

V_CC

V_OH

HIGH-level

no DC load

0.9V_CC

V_CC+ 0.1

output voltage

I_OH< −40 µA; 3 V

0.75V_CC

I_OH< −20 µA; 1.8 V or

1.2 V card

current limit I_OH= −15 mA

0

-

0.4

V

V_IL

LOW-level input V_CC= +3 V

−0.3

0.6V_CC

+0.8

voltage

V_CC= +1.8 V

+0.6

V_CC= +1.2 V

+0.4

V_IH

HIGH-level input

voltage

V_CC+ 0.3

V_hys

I_IL

hysteresis

voltage

pin I/O

-

350

-

mV

LOW-level input pin I/O; V_IL= 0 V

current

600

µA

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

25 of 38

TDA8025

NXP Semiconductors

IC card interface

Table 8.

Characteristics of IC supply voltage …continued

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_IH

HIGH-level input pin I/O; V_IH= V_CC

current

-

10

µA

t_r(i)

t_r(o)

t_f(i)

input rise time

V_ILmaximum to

_IHminimum

-

1.2

0.1

1.2

0.1

13

µs

kΩ

mA

V

output rise time C_L≤ 80 pF; 10 % to 90 %;

-

0 V to V_CC

input fall time

V_ILmaximum to

_IHminimum

-

V

t_f(o)

R_pu

I_OH

output fall time

C_L≤ 80 pF; 10 % to 90 %;

0 V to V_CC

-

pull-up

resistance

between I/O and V_CC

8

−8

11

−6

HIGH-level

pin I/O when active

−4

output current

pull-up; V_OH= 0.9V_CC

C = 80 pF

;

Data lines to the system: pins I/OUC, AUX1UC and AUX2UC^[5]

V_OL

LOW-level output I_OL= 1 mA

voltage

0

-

0.3

V

V_OH

HIGH-level

output voltage

no DC load

_OH≤ 40 µA;

_DD(INTF)> 2 V

_OH≤ 20 µA;

_DD(INTF)< 2 V

0.9V_DD(INTF)

-

V_DD(INTF)+ 0.1

V

I

V

0.75V_DD(INTF)

I

V

0.75V_DD(INTF)

-

V_DD(INTF)+ 0.1

V

V_IL

V_IH

V_hys

I_IH

LOW-level input

voltage

−0.3

-

+0.3V_DD(INTF)

V

HIGH-level input

voltage

0.7V_DD(INTF)

-

V_DD(INTF)+ 0.3

V

hysteresis

voltage

pin I/OUC

-

8

-

0.19V_DD(INTF)

-

V

HIGH-level input pin I/OUC; V_IH= V_DD(INTF)

current

-

10

600

13

1.2

0.1

1.2

0.1

µA

kΩ

µs

I_IL

LOW-level input pin I/OUC; V_IL= 0 V

current

-

R_pu

t_r(i)

t_r(o)

t_f(i)

pull-up

resistance

between I/OUC and

V_DD(INTF)

11

-

input rise time

V_ILmaximum to

V_IHminimum

output rise time C_L≤ 80 pF;10 % to 90 %;

-

0 V to V_CC

input fall time

V_ILmaximum to

_IHminimum

-

V

t_f(o)

output fall time

C_L≤ 80 pF; 10 % to 90 %;

-

0 V to V_CC

TDA8025_1

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Table 8.

Characteristics of IC supply voltage …continued

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol

I_OH

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level

pin I/OUC when active

−1

-

mA

output current

pull-up; V_OH= 0.9V_DD

C = 30 pF

;

Internal oscillator

f_osc(int)internal oscillator inactive mode

55

140

2.7

200

3.2

kHz

frequency

active mode

1.9

MHz

Reset output to the card: pin RST

V_o

output voltage

inactive mode

no load

0

-

0.1

0.3

−1

V

I_o= 1 mA

V

I_o

output current

delay time

when inactive and pin

RST grounded

0

mA

t_d

between pins RSTIN and

RST; RST enabled

-

2

µs

V_OL

LOW-level output I_OL= 200 µA

0

-

0.2

V

voltage

current limit I_OL= 20 mA

I_OH= −200 µA

V

_CC− 0.4

V_CC

0.4

V

V_OH

HIGH-level

0.9V_CC

V

output voltage

current limit I_OH= −20 mA

0

-

V

[6]

t_r

t_f

rise time

fall time

C_L= 100 pF;

V

0.1

µs

_CC= 3 V, 1.8 V or 1.2 V

C_L= 100 pF;

_CC= 3 V, 1.8 V or 1.2 V

Clock output to the card: pin CLK

-

0.1

µs

V

V_o

output voltage

output current

inactive mode

no load

0

-

0.1

0.3

−1

V

I_o= 1 mA

V

I_o

pin CLK when inactive

and grounded

0

mA

V_OL

LOW-level output I_OL= 200 µA

0

-

0.3

V_CC

0.4

16

V

voltage

current limit I_OL= 70 mA

I_OH= −200 µA

V

_CC− 0.4

V

V_OH

HIGH-level

0.9V_CC

V

output voltage

current limit I_OH= −70 mA

C_L= 30 pF

0

V

[6]

t_r

rise time

fall time

-

ns

%

V/ns

t_f

C_L= 30 pF

-

16

δ

duty cycle

slew rate

except for f_xtal; C_L= 30 pF

rise and fall; C_L= 30 pF;

45

0.2

55

SR

-

V_CC= 3 V or 1.8 V

C_L= 30 pF; V_CC= 1.2 V

0.1

-

V/ns

TDA8025_1

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Table 8.

Characteristics of IC supply voltage …continued

T_amb= 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; f_xtal= 10 MHz; all

currents ﬂowing into the IC are positive; unless otherwise speciﬁed. Parameters speciﬁed as a function of

V

_DD(INTF), V_DDI(REG), V_DD(INTREGD)or V_CCrefer to the actual value at the time of measurement.

Symbol Parameter Conditions Min Typ

Control inputs: pins CLKDIV1, CLKDIV2, CMDVCCN, RSTIN, VCC_SEL2, VCC_SEL1 and ENCLKIN^[7]

Max

Unit

V_IL

V_IH

V_hys

I_IL

LOW-level input

voltage

−0.3

-

+0.3V_DD(INTF)

V

HIGH-level input

voltage

0.7V_DD(INTF)

-

V_DD(INTF)+ 0.3

V

hysteresis

voltage

control inputs

-

0.14V_DD(INTF)

-

V

LOW-level input V_IL= 0 V

current

-

1

µA

I_IH

HIGH-level input V_IH= V_DD(INTF)

current

Control inputs CMDVCCN and CONFIG^[7]

f_CMDVCCN

frequency on pin

CMDVCCN

-

150

kHz

V

V_IL

LOW-level input

voltage

−0.3

-

+0.3V_DD(INTF)

V_IH

HIGH-level input

voltage

0.7

-

V_DD(INTREGD)

0.3

+

V

V_DD(INTREGD)

V_hys

I_IL

hysteresis

voltage

pin CONFIG

-

0.14V_DD(INTF)

-

V

LOW-level input V_IL= 0 V

current

-

1

µA

I_IH

HIGH-level input V_IH= V_DD(INTREGD)

current

Card detection inputs: pins PRES and PRESN^[7][8][9]

V_IL

V_IH

V_hys

I_IL

LOW-level input

voltage

−0.3

-

+0.3V_DD(INTREGD)

V

HIGH-level input

voltage

0.7

V_DD(INTREGD)

0.3

+

V

V_DD(INTREGD)

hysteresis

voltage

pins PRES and PRESN

-

0.17

V_DD(INTREGD)

-

V

LOW-level input V_IL= 0 V

current

-

5

µA

I_IH

HIGH-level input V_IH= V_DD(INTREGD)

current

-

OFFN output^[10]: pin OFFN

V_OL

V_OH

R_pu

LOW-level output I_OL= 2 mA

voltage

0

-

0.3

-

V

HIGH-level

I_OH= −15 µA

0.75V_DD(INTF)

16

-

V

output voltage

pull-up

to V_DD

20

24

kΩ

resistance

[1] Two decoupling capacitors connected in parallel to V_DD(INTREGD)rated at 100 nF and 1 µF.

TDA8025_1

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[2] To enable the microcontroller to provide the required maximum voltage input level on XTAL1, V_DD(INTF)must not exceed

V_DD(INTREGD)+ 0.3 V. See Section 8.1 on page 7 for speciﬁc limitations on the maximum V_DD(INTF)voltage and Table 8 on page 23 for

the limits of XTAL1.

[3] To meet these speciﬁcations, V_CCshould be decoupled to pin CGND using two low ESR, ceramic multilayer capacitors one of 470 nF

and one of 220 nF with an ESR of < 100 mΩ.

[4] Using the internal pull-up resistor to V_CC

.

[5] Using the internal pull-up resistor to V_DD(INTF)

.

[6] The transition time and the duty factor deﬁnitions are shown in Figure 16 on page 30; δ = t1/(t1 + t2).

[7] Pins PRESN and CMDVCCN are active LOW. Pins RSTIN and PRES are active HIGH; see Table 4 on page 12 for pins CLKDIV1 and

CLKDIV2; see Table 5 on page 19 for pins VCC_SEL1 and VCC_SEL2.

[8] If PRESN or PRES is true, the card is considered to be present. A debouncing feature of 4.5 ms typical is built-in.

[9] Pin PRES has an integrated current source to pin GND, pin PRES to V_DD(INTREGD); the card is considered as present if at least one of

the two inputs is true.

[10] Pin OFFN is an NMOS drain, using an internal pull-up resistor to V_DD(INTREGD)

.

Table 9.

Symbol

I_CC

Protection characteristics

Parameter

Conditions

Min

Typ

Max

Unit

supply current

shutdown current on

pin V_CC

95

135

185

mA

pin V_CC

pin CLK

pin RST

135

−70

−20

−15

175

225

+70

+20

+15

mA

-

I_IO

input/output current

pins I/O, AUX1 and

AUX2

T_sd

shutdown temperature

-

150

-

°C

Table 10. Timing characteristics

Symbol

Parameter

Conditions

Min

35

Typ

Max

3000

240

Unit

[1]

[2]

[3]

t_act

activation time

total sequence with the crystal oscillator

external clock

-

µs

35

-

t_deact

t_d

deactivation time

delay time

total sequence

35

80

100

CLK sent to a card with the crystal oscillator

t_d(start)= t3

[1]

35

-

3000

3090

µs

t_d(end)= t5

160

CLK sent to card using an external clock

t_d(start)= t3

[2]

[4]

35

-

150

240

12

µs

ms

t_d(end)= t5

160

3.2

-

t_deb

debounce time

on pins PRES and PRESN

4.5

[1] See Figure 8 on page 15.

[2] See Figure 10 on page 16.

[3] See Figure 12 on page 18.

[4] See Figure 15 on page 21.

TDA8025_1

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t

f

r

V

OH

90 %

(V

+ V )/2

OL

OH

10 %

V

OL

001aai973

t1

t2

Fig 16. Deﬁnition of output and input transition times

TDA8025_1

Product data sheet

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12. Application information

V

MICROCONTROLLER

DD(INTF)

V

DD(INTF)

R1

V

DD(INTF)

R2

V

DD(INTF)

32 31 30 29 28 27 26 25

CMDVCCN

TEST1

TEST3

OFFN

RSTIN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

DDI(REG)

TEST2

C5

100 nF

C3

V

DDI(REG)

DD(INTF)

10 µF

TDA8025

CLKDIV2

CLKDIV1

GND

V

DD(INTREGD)

CC

C4

VCC_SEL1

VCC_SEL2

100 nF

RST

9

10 11 12 13 14 15 16

C1

470 nF

V

DD(INTREGD)

CARD

CONNECTOR

C2

220 nF

C5

C1

C2

C3

C4

K1

C6

C7

C8

K2

RD Ω

V

DDI(REG)

001aai974

Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 for detailed information on

the V_DD(INTF)restrictions.

Fig 17. Application diagram (3 V < V_DDI(REG)< 3.6 V)

TDA8025_1

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V

MICROCONTROLLER

DD(INTF)

V

DD(INTF)

R1

V

DD(INTF)

R2

V

DD(INTF)

32 31 30 29 28 27 26 25

CMDVCCN

TEST1

TEST3

OFFN

RSTIN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

DDI(REG)

TEST2

C5

100 nF

C3

V

DDI(REG)

DD(INTF)

10 µF

TDA8025

CLKDIV2

CLKDIV1

GND

V

DD(INTREGD)

CC

C3

VCC_SEL1

VCC_SEL2

10 µF

RST

C4

9

10 11 12 13 14 15 16

C1

470 nF

100 nF

CARD

CONNECTOR

C2

220 nF

C5

C1

C2

C3

C4

K1

C6

C7

C8

K2

RD Ω

V

DDI(REG)

001aaj350

Refer to Table 8 on page 23 and Section 8.1 “Power supplies” on page 7 for detailed information on

the V_DD(INTF)restrictions.

Fig 18. Application diagram (3.6 V < V_DDI(REG)< 5.5 V)

TDA8025_1

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Rev. 01 — 6 April 2009

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13. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 19. Package outline SOT617-1

TDA8025_1

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14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

TDA8025_1

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14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 20) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 11 and 12

Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 20.

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

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TDA8025

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 20. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

15. Abbreviations

Table 13. Abbreviations

Acronym

ATR

Description

Answer To Request

ESD

ElectroStatic Discharge

ESR

Equivalent Series Resistance

Negative-channel Metal-Oxide Semiconductor

Power-On Reset

NMOS

POR

PMOS

Positive-channel Metal-Oxide Semiconductor

16. Revision history

Table 14. Revision history

Document ID

Release date

20090406

Data sheet status

Change notice

Supersedes

TDA8025_1

Product data sheet

-

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

TDA8025_1

Product data sheet

Rev. 01 — 6 April 2009

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TDA8025

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19. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

19

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

8.1

8.2

8.2.1

8.2.2

8.2.3

Functional description . . . . . . . . . . . . . . . . . . . 7

Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage supervisors . . . . . . . . . . . . . . . . . . . . . 8

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V_DD(INTREGD)voltage supervisor with

pin PORADJ connected to V_DD(INTF). . . . . . . . 9

8.2.4

V_DD(INTF)voltage supervisor with external

divider on pin PORADJ. . . . . . . . . . . . . . . . . . . 9

R1 and R2 resistor value calculation . . . . . . . . 9

Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input and output circuits . . . . . . . . . . . . . . . . . 13

Inactive mode . . . . . . . . . . . . . . . . . . . . . . . . . 13

Activation sequence . . . . . . . . . . . . . . . . . . . . 14

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Deactivation sequence . . . . . . . . . . . . . . . . . . 18

8.2.4.1

8.3

8.4

8.5

8.6

8.7

8.8

8.9

V_CCregulator . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.10

Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 19

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22

Thermal characteristics. . . . . . . . . . . . . . . . . . 22

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 23

Application information. . . . . . . . . . . . . . . . . . 31

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33

9

10

11

12

13

14

Soldering of SMD packages . . . . . . . . . . . . . . 34

Introduction to soldering . . . . . . . . . . . . . . . . . 34

Wave and reﬂow soldering . . . . . . . . . . . . . . . 34

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 34

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 35

14.1

14.2

14.3

14.4

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 36

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 37

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

17.1

17.2

17.3

17.4

18

Contact information. . . . . . . . . . . . . . . . . . . . . 37

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 April 2009

Document identifier: TDA8025_1


型号：	TDA8025HN/C1,557
厂家：	NXP
描述：	TDA8025 - Low voltage supply smart card interface QFN 32-Pin
文件：	总38页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA8025HN/C1,557 [NXP]

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