TDA8029HL/C207_技术文档

AN10207

Smart Card reader application with TDA8029 Mask 06 and

Mask 07

Rev. 1.0 — 2 February 2011

Application note

Document information

Info

Content

Keywords

Abstract

TDA8029, Smart card interface, ISO 7816-3 and ISO 7816-4, E.M.V. 4.0

This application note describes the software implemented in both

TDA8029 mask 06 (TDA8029HL/C206) and TDA8029 mask 07

(TDA8029HL/C207) in order to handle a communication between a

system controller and a smart card.

Both mask 06 and mask 07 can support all the asynchronous smart cards

using either T=0 or T=1 protocol and some synchronous smart cards

(S=9, S=10 and I2C).

Mask 07 fixes an issue in the case 4 APDU command with” Le”

parameter less or equal to 2 (see annex IV).

The control of the TDA8029 by the host controller is done using a RS232

serial interface.

AN10207

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Smart Card reader application with TDA8029

Revision history

Rev

Date

Description

1.0

20110202

Initial release

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

AN10207

All information provided in this document is subject to legal disclaimers.

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1. Introduction

TDA8029 is a smart card coupler providing all the analogue electrical interface signals to

the smart card. This coupler is able to manage asynchronous cards due to its specific

ISO7816 UART and to its embedded 80C51 microcontroller core; it can also manage

synchronous cards such as I2C cards or prepaid telephone cards.

The software embedded in this device is able to support any ISO 7816 asynchronous

smart card (T=0 or T=1 protocol) and some synchronous cards (I2C, S9 and S10).

It completely handles the communication layer between the card and the host system.

A specific protocol called “ALPAR” has been defined on the serial interface between

TDA8029 and the host system; it uses the APDUs frame types to convey the

asynchronous card commands and specific frames for the synchronous cards. A

dedicated command has been added to carry TPDUs frames for T=1 protocol only.

A board has been built in order to demonstrate a communication between a smart card

and a host system.

When the host is a PC communicating with the TDA8029 using a RS232 link, a software

called SCRTester can be used (see detailed description in Annex I, page 46).

The following diagram illustrates this application.

VDD

ISO7816

RS232

MAX232

TDA8029

serial link

HOST

CONTROLLER

SMART CARD

019aab397

CAKE8029_11D

Fig 1. TDA8029 application diagram example

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Smart Card reader application with TDA8029

2. Hardware and power management

2.1 Hardware

The board CAKE 8029_11D (see Annex II, page 48) has been made to demonstrate the

features of the TDA8029 with both Mask 06 and Mask 07 software.

This board is supplied under +2.7 V to +6 V.

In case of RSR232 host interface configuration, it may be connected to a PC by means

of the serial port.

Depending on the PC which is used, the communication between the PC and the board

can be fixed at different baud rates (from 4800 to 115200 baud).

The default baud rate is 38400 and it can be changed by a special command in

SCRTester (set_serial_baud_rate on page 29).

In case of I2C-bus host interface configuration, it should be connected to the I2C-bus

master using SDA and SCL lines and possibly WakeUpSlave and SlaveI2CMute lines.

2.2 Host Controller Interface

The TDA8029 with mask 06 or mask 07 software can be interfaced to the host controller

by using either a RS232 serial link or an I2C-bus.

The choice of the interface is done according to the state of P17 (i.e. pin 1 of the

TDA8029) at the powering on or at the reset of the TDA8029.

Table 1.

Host interface hardware configuration

Interface

P17 (#1)

VDD

RS232 (see section 5)

I2C (see section 6)

GND

2.3 Power management: Energy Saving Mode

In order to benefit from the low power features of the TDA8029, both Mask 06 and mask

07 software implements a special management of the TDA8029 called Energy Saving

Mode (ESM).

In this mode, outside an exchange of commands between the host and the TDA8029, the

card clock is either switched off (level high or low) or set to Fint/2 depending on the clock

stop mode described in its ATR and the microcontroller is set in power down mode. This

mechanism allows a lower average current consumption for the TDA8029.

This mode cannot be used for EMV approval.

A general description of ESM mechanism can be summarized on the following figure:

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WakeUp

E

Acknowledge

R

Command

frame

Answer

frame

Host interface

E

R

PWDN

X

/ n

CLK STOP or Fint / 2

TAL

E: host controller > TDA8029

R: TDA8029 > host controller

019aab398

Fig 2. ESM Mechanism

In this figure, the “host interface” symbolizes the link between the host controller and the

TDA8029: it may be either a RS232 link or an I2C-bus.

When the host wants to send a command frame to the TDA8029, it first wakes it up. The

waking up process is different according to the type of the interface used. It will be

detailed hereafter (see section Dialog structure in case of Energy Saving Mode

activated§5.2 and §6.3).

As soon as it is able to receive and treat a command frame, the TDA8029 indicates it to

the host controller using an acknowledge process. When using an I2C-bus interface, this

stage may be possibly skipped (as the I2C-bus mechanism already implements an

acknowledge notion).

Then, the host controller can send the complete command frame to be treated by the

TDA8029.

When the TDA8029 has finished the execution of the command, it sends back the

corresponding answer to the host.

When the exchange is completed, the TDA8029 goes back in power down mode after

having switched the clock of the card to the lower current consumption available

configuration. If the card does not support the clock stop mode or does not specify it in its

ATR, the clock will be set to Fint/2. Note that a command (set_esm_properties, page 29)

allows to force a clock stop mode even if the card does not specify it. Stop the clock

rather than leave it at Fint/2 provides a significant power consumption saving.

To activate this mode P26 (i.e. pin 25 of the TDA8029) has to be connected to V_DDor to

be left open at the powering on of the board (or at the reset), whereas connecting P26

(pin 25) to ground will force the TDA8029 to never enter into this energy saving mode.

Table 2.

ESM

ESM hardware configuration

P26 (#25)

ON

VDD or not connected

GND

OFF

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2.4 Shutdown mode

The TDA8029 can be set to shutdown mode using the shutdown pin SWDN (pin #5).

When this pin is switched to low state then the bit SDWN within HSR will be set, causing

an interrupt on INT0 pin (#29).

The TDA8029 will read the status, deactivate the card if it is active, set all ports to 1 and

enter in power down mode by setting the bit PD in the C51 PCON register. In this mode,

it will consume less than 20 µA.

When the shutdown pin is set to high state back, a power-on-reset operation is

performed so the chip recovers the same state than at power on.

The host controller should observe a waiting time before sending commands to the

TDA8029. This waiting time depends on the value of capacitor connected to the pin

CDEL (#6), determining the power on reset pulse width. Typically, this pulse width is

1 ms par 2 nF (see next chapter).

2.5 Power-On Reset

The CDEL pin is used to add a delay between a power on or a supply dropout, and the

effective start of the chip. This delay is used as a reset pulse for the internal controller.

V

+ V

hys1

th1

V

th1

V

DD

V

th2

CDEL

TDA8029 state

RESET

ACTIVE

RESET

ACTIVE

019aab320

Fig 3. CDEL pin action overview

The delay is defined by the load time of the capacitor connected on the pin: 1 ms per

2 nF typically as shown in figure 4, next page.

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The minimum advised value for the capacitor on CDEL is 22 nF.

In some application, a bigger delay can be needed when the overall system reset needs

more than 10 ms (22 nF typical capacitor value). In this case the below figure allows to

select the right capacitor value.

alarm pulse

time (t

)

pulse

100 ms

50 ms

11 ms

CDEL

capacitor

22 nF

minimum

100 nF

typical

220 nF

maximum

advised value

019aab257

Fig 4. Correspondence between reset delay and CDEL capacitor

3. Software aspect

Both mask 06 and mask 07 has been developed in order to be used either in ISO7816-3

or E.M.V. 4.0 environment. It is compliant with erratum #13 Test Bench Description –

Executable Tests TBD/EXE/T01 3.0, November 21^st2002.

Some specific error messages are dedicated to the E.M.V. environment (ATR

parameters not allowed).

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Smart Card reader application with TDA8029

4. Protocol “ALPAR”

The communication between the host controller and the TDA8029 obeys to a protocol

named ALPAR.

This protocol encapsulates the useful data of a message in an invariant frame structure

and defines a dialog structure of messages exchanges.

Data is exchanged between the host controller and TDA8029 in blocks, each made up of

binary characters on one byte:

4 header characters

0 to 506 data characters (C-APDU or R-APDU)

1 LRC character

4 bytes

0 to 506 bytes

C-APDU or R-APDU

Information field

1 byte

LRC

HEADER

019aab399

Fig 5. Frame structure

The 4 header bytes include the following bytes:

st

nd

rd

th

1

byte

0

2

byte

3

byte

4 byte

A

1

0

Data length to transmit excluding

header and LRC

Command byte

st

A = 0: Acknowledge of the frame (1 byte = 60)

st

A = 1: Nack of the frame (message with a status error, 1 byte = E0)

019aab400

Fig 6. 4 header bytes

The LRC (Longitudinal Redundancy Check) byte is such that the exclusive-oring of all

bytes including LRC is null.

4.1

General dialog structure

The host controller is the master for the transmission; each command from the master is

followed by an answer from TDA8029 including the same command byte as the input

command.

However, in some cases (card insertion or extraction, a time out detection on Rx line or

an automatic emergency deactivation of the card) the TDA8029 is able to initiate an

exchange.

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4.1.1 Successful command

System to TDA8029:

60

XX XX

length

YY

nnnnnnnnnnnnnnnnnnnn

Data (C-APDU)

ZZ

ACK

code

LRC

TDA8029 to System:

(1)

60

UU UU

length

YY

mmmmmmmmmmmmmm

Data (R-APDU)

TT

ACK

code

LRC

019aab401

(1) The same command byte YY is returned in the answer from TDA8029.

Fig 7. Successful command frame description

4.1.2 Unsuccessful command

System to TDA8029:

60

XX XX

length

YY

nnnnnnnnnnnnnnnnnnnn

Data (C-APDU)

ZZ

ACK

code

LRC

TDA8029 to System:

(1)

E0

UU UU

length

YY

SS

TT

NACK

code

Status

LRC

019aab402

(1) In that case, the status contains the error code information (see error list)

Fig 8. Unsuccessful command frames

4.1.3 Answer with an acknowledge (power_off, idle_mode, power_down_mode)

System to TDA8029 (example: power_off):

60

00 00

length

4D

2D

ACK

code

LRC

TDA8029 to System:

60

00 00

length

4D

2D

ACK

code

LRC

019aab403

(1) In the case where the answer is an acknowledge of the command, the TDA8029 sends back a

frame with the same content of the command.

Fig 9. Acknowledge frame

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5. RS232 Interface

5.1

General description

The serial interface between the TDA8029 and the host controller is a full duplex

interface using the two lines RX and TX.

RX (pin 32) is used to receive data from the host controller; TX (pin 31) is used to send

data to the host controller.

No flow control or supplementary line is used (no hand check).

The serial data format used is:

• start bit

• data bits

• stop bit, no parity

The default baud rate is 38400 baud, but it can be changed (from 4800 to 115200 baud)

by a host command set_serial_baud_rate (page 29).

Warning: in order to comply with standard baudrates values (4800, 9600, 19200…), the

crystal used with TDA8029 must be fixed to the 14.745 MHz as defined in the reference

schematics. There is no big constraint on its precision (must be less than 1 %).

If the crystal frequency is different, then the baudrate is changed accordingly.

e.g. If the crystal freq. is equal to 10 MHz, then the default baudrate will become:

10 x 38400 / 14.745 = 26042 bps.

In case of RS232 interface mode configuration, the TDA8029 has to be connected as

follows:

V

or not

DD

connected

V

or not

DD

connected

P17

P26

RX

TX

32

31

1

ESM ON

TDA8029

25

ESM OFF

GND

019aab252

Fig 10. RS232 Interface configuration

5.2 Dialog structure in case of Energy Saving Mode activated

As it is explained in §2.3, both Mask 06 and mask 07 implement a special management

of the TDA8029 for energy savings purpose. This Energy Saving Mode is activated when

P26 (i.e. pin 25) is tied to V_DDof left open at reset of the TDA8029.

Due to this Energy Saving Mode implementation, the serial interface is adapted as

follows.

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5.2.1 Communication initiated by the system controller

t

5 6

1

2

3

4

RX

TX

0xAA

OpCmdFr

AcqFr

OpAnswFr

PWDN

CLK

X

/n

STOP or Flit/2

TAL

019aab253

Fig 11. Communication initiated by the system controller

To initiate a normal exchange with the TDA8029, the host has to first send a specific

frame composed of only one character (0xAA) to wake up the TDA8029. When the

TDA8029 is completely waked up, it sends an acknowledged frame back to the host.

System to TDA8029 (Specific waking up frame)

AA

TDA8029 to System (Acknowledgement frame)

60

00 00

length

BB

DB

ACK

code

LRC

After this synchronization stage, the operational communication can start as described in 4.1.

System to TDA8029:

60

XX XX

length

YY

nnnnnnnnnnnnnnnnnnnn

Data (C-APDU)

ZZ

ACK

code

LRC

TDA8029 to System:

60 or E0

XX XX

length

YY

nnnnnnnnnnnnnnnnnnnn

Status or Data (R-APDU)

ZZ

ACK or NACK

code

LRC

After having sent its complete frame, the TDA8029 returns in power down.

019aab404

Fig 12. Communication initiated by the system controller

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5.2.2 Communication initiated by the TDA8029

Any card event (extraction or insertion, overcurrent on VCC or RST, overheating) will

wake up the TDA8029.

In that case, this is the TDA8029 which initiates the communication.

t

11

7

8

9

10

RX

TX

AcqFr

WkUpFr

InformationalFr

PWDN

card deactivated

CLK

STOP or Flit/2

HW event

(1)

019aab254

(1) In this example the card is deactivated due to hardware event

Fig 13. Communication initiated by the TDA8029

It first sends the following specific frame to warn the host that it wants to send data. This

frame is the same than the one used to acknowledge a received waking-up character

(section 5.2.1) except that the length in that case is equal to one (as it is equal to zero in

case of a normal acknowledge frame).

TDA8029 to System

60

00 01

length

BB

01

DB

ACK

code

data

LRC

After that, the TDA8029 waits until the host replicates this frame.

System to TDA8029

60

00 01

length

BB

01

DB

ACK

code

data

LRC

Then, the TDA8029 sends the informational frame and returns in power down mode.

TDA8029 to System:

60 or E0

XX XX

length

YY

nnnnnnn

data

ZZ

ACK or NACK

code

LRC

019aab405

Fig 14. Communication initiated by the TDA8029 – Frame description

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For instance, a card insertion will generate the following informational frame:

TDA8029 to System

60

00 01

length

A0

01

C0

ACK

code

data

LRC

Whereas in the case of a card extraction, the frame will be:

TDA8029 to System

60

00 01

length

A0

00

C1

ACK

code

data

LRC

019aab406

Fig 15. Card move – frame example

5.2.3 Timing considerations

The following timings are referenced in the figures page 11 and 12.

t₁: Waking up and clock switching time (typically 550 µs).

t₂: TDA8029 reaction time (typically 33 µs).

t₃: Host-dependant reaction time. (no limit).

t₄: Process time (depends on the type of the command frame).

t₅: Clock switching time (typically 80 µs).

t₆: Power Down setting time (typically 0.3 ms).

t₇: Waking up and clock switching time (typically 550 µs).

t₈: TDA8029 reaction time (typically 630 µs).

t₉: Host-dependant reaction time. (no limit).

t₁₀: TDA8029 reaction time (typically 630 µs).

t₁₁: Power Down setting time (typically 0.3 ms).

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5.2.4 Abnormal communication process

Three different cases can be met:

• Time out detected on Rx line (more than 10 ms between the leading edge of two

characters inside the command frame sent by the host controller). As soon as the

time out is detected, the TDA8029 sends back an error frame:

System to TDA8029

TDA8029 to system

System to TDA8029

TDA8029 to system

0xAA

0x60 0x00 0x00 0xBB 0xDB

ACK Length Code (Parameters) LRC (erroneous frame)

NACK 0x00 0x01 Code 0xFF LRC

Then the TDA8029 goes back to power down mode.

• Card extraction detected during a card IO card session: if the TDA8029 detects a

card extraction as it is processing an APDU with the card, it returns two consecutive

messages back to the host controller

System to TDA8029

TDA8029 to system

System to TDA8029

TDA8029 to system

0xAA

0x60 0x00 0x00 0xBB 0xDB

ACK Length 0x00 Parameters LRC (C-APDU)

NACK 0x00 0x01 0x00 0xC0 LRC (card absent)

ACK 0x00 0x01 0xA0 0x00 LRC (card extraction)

Then the TDA8029 goes back to power down mode.

• Unexpected reception detected during a communication process; the TDA has not

finished to process a received command frame (it has not sent completely its answer

frame while the host controller sends a new command frame): in that case, the

TDA8029 sends the correct answer to the first received command and then sends

the error frame informing the host that it has lost at least a command frame.

System to TDA8029

TDA8029 to system

System to TDA8029

TDA8029 to system

0xAA

0x60 0x00 0x00 0xBB 0xDB

ACK Length Code1 (Parameters) LRC

ACK Length Code2 (Parameters) LRC

ACK or NACK Length Code1 (Parameters) LRC

NACK 0x00 0x01 Code2 0xF1 LRC

Then the TDA8029 goes back to power down mode.

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6. I2C-bus interface

6.1 General description

As specified in the I2C-bus specification, only two lines may be used to manage the

serial link between the TDA8029 and the system controller:

a serial data line (SDA), has to be connected to RX (pin 32 of the TDA8029)

and a serial clock line (SCL), has to be connected to P16 (pin 2 of the

TDA8029).

In addition to I2C specification, two other lines can be used to manage Energy Saving

Mode mechanism:

WakeUpSlave,line used to wake up the TDA8029 before sending an I2C frame

to it has to be connected to INT1 (pin 30 of the TDA8029)

SlaveI2CMute,line used by the TDA8029 to indicate to the host controller either

that it is ready to receive a command frame or to send the corresponding

answer, or to signal an hardware event has to be connected to P27 (pin 24 of the

TDA8029).

2

GND

wake up I C

V

or not

DD

connected

30

SDA

P17

P26

32

2

1

ESM ON

TDA8029

SCL

25

24

ESM OFF

2

slave I C mute

GND

019aab256

Fig 16. I2C Bus interface configuration

In fact, ESM may be used even with a pure 2 lines I2C-bus.

In that case, the pin 30 of the TDA8029 has to be connected together with SDA line.

Table 3.

I2C modes

ESM

I2C Mode

RX (#32)

SDA

P26 (#26)

GND

INT1 (#30)

nu

P27 (#24)

2 lines

4 lines

OFF

ON

nu

SDA

VDD

SDA

ON

SDA

VDD

WakeUpSlave SlaveI2CMute

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As the system controller is the I2C-bus master, it will initiate all the exchanges. Each

command from the master is followed by an answer from TDA8029.

Normally, as it is a I2C-bus slave, the TDA8029 can not warn the host controller by

means of the bus when an hardware event happens (abnormal deactivation of the card,

movement detection, …). The line SlaveI2CMute can be used for that.

When such an event occurs, the TDA8029 falls down the SlaveI2CMute line so that the

host controller can known that something has happened on the reader side.

The host controller can send a GetReaderStatus (see section 9.1.3) command frame to

receive details on the current state of the TDA8029.

This particularity may be deactivated by means of the set_esm_properties command

(see page 29). In that case, the TDA8029 does not inform the host controller when a

specific event happens on the card. Of course, the TDA8029 takes in charge the security

of the card and automatically deactivates it if needed.

6.2 Energy Saving Mode deactivated

When the TDA8029 is not configured in Energy Saving Mode, it is able to accept a

command sent by the host controller as soon as it has finished to handle the previous

one (no waking up delay).

On the other hand, after having received a complete command frame from the host, the

TDA8029 will need a variable delay time to achieve the related task before to send back

an answer to the host.

This time depends on the kind of the command, the kind of the card (baudrate, CWT,

BWT, …), the length of the card exchange, and so on…

During this execution time, the TDA8029 will be mute, i.-e. it will not acknowledge any

incoming messages from the host controller.

Once the command message is processed, the TDA8029 will be available to give its

answer when the host controller will address it.

SDA

SCL

P

Host

command

Sa

Sn

P

Sn

P

Sa TDA8029

response

P

Command not yet

completed

Answer

ready

PWDN

CLK

not in power down mode

X

/ n

TAL

Sn: Start condition not acknowledged

Sa: Start condition acknowledged by the TDA8029

P : Stop condition

019aab407

Fig 17. I2C communication with ESM off

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6.3 Energy Saving Mode activated

When used in Energy Saving Mode, the goal is that the TDA8029 stays in power down

mode outside an I2C-bus exchange with it.

SDA

SCL

S

Host

command

P

S

TDA8029

response

P

S: Start condition P: Stop condition

PWDN

CLK

STOP or Fint / 2

X

TAL

/ n

019aab408

Fig 18. I2C communication with ESM on

6.3.1 4 lines I2C-bus

If the host controller sends directly an I2C frame to the TDA8029 as it was asleep, it will

not be able to acknowledge its address (due to waking-up delay).

Consequently, the lines WakeUpSlave and SlaveI2CMute are used to manage the

complete exchange:

1 -Before sending a frame to the TDA8029, the host controller wakes it up with a

negative pulse on WakeUpSlave line (minimum duration of 0.8 µs)

2 -As soon as it is completely waked up, the SlaveI2CMute line falls down,

3 -The host controller can now send the I2C write command frame. The SlaveI2CMute

line goes up after the TDA8029 has recognized its I2C address (0x50)

4 -Once the command frame is received, the TDA8029 processes it. When it is ready to

give corresponding results to the host controller, the SlaveI2CMute line falls down again

5 -The host controller can now send I2C read command frame. The SlaveI2CMute line

goes up after the TDA8029 has recognized its I2C address (0x51)

6 -Once the answer has been totally read by the host controller, the TDA8029 returns in

power down mode until the next host controller exchange.

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SDA

SCL

S

Host

command

P

S

TDA8029

response

P

S: Start condition

P: Stop condition

address recognized

WakeUpSlave

SlaveI2CMute

command

treated

PWDN

CLK

STOP or Fint / 2

X

/ n

TAL

019aab409

Fig 19. 4 lines I2C communication example initiated by the host

Moreover, in that configuration, if the TDA8029 has to warn the host controller to inform it

about a hardware event, it can do it by falling down the SlaveI2CMute line outside a

normal exchange. Then, the host sends a command with GetReaderStatus (see section

9.1.3) opcode to get detailed information from the TDA8029. In that case, the host

controller should not use the WakeUpSlave line as the TDA8029 is already waked up.

SDA

SCL

S

Host

command

(GetReaderStatus)

P

S

TDA8029

response

P

address recognized

SlaveI2CMute

PWDN

command

treated

hardware

event

019aab410

Fig 20. 4 lines I2C communication example initiated by the TDA8029

Remark: The main advantage of this mode (4 lines I2C-bus) is that the current

consumption of the TDA8029 is completely optimized.

When the I2C-bus master addresses to other slave than the TDA8029, the latter is not

waked up (this is not SDA or SCL line which wakes it up but the dedicated WakeUpSlave

line).

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6.3.2 2 lines I2C-bus

As described in the table in §6.1, the Energy Saving Mode can be used even with a host

controller using a pure I2C-bus interface, without the two additional lines WakeUpSlave

and SlaveI2CMute.

In that case, the SDA line has to be connected on pin 30 of the TDA8029 in addition to

pin 32.

Thus, when the TDA8029 is asleep, every frame on the I2C-bus wakes it up; even if the

frame is not addressed to the TDA8029. That is the main drawback (according to the

current consumption) of this configuration.

As soon as it recognizes its address on the I2C-bus, the TDA8029 acknowledges it and

then the normal exchange can go.

The embedded microcontroller needs a delay time before to come back completely

operational when waked up by a I2C-bus frame. During this period, the I2C command will

not be acked by the TDA8029 and the host has to try again until its command will be

correctly acked.

SDA

SCL

Sn

P

Sa

Host

command

P

Sn

P

Sn

P

Sa TDA8029

response

P

Command not yet

completed

PWDN

CLK STOP or Fint / 2

Sn: Start condition not acknowledged

X

TAL

/ n

Sa: Start condition acknowledged by the TDA8029

P : Stop condition

019aab411

Fig 21. 2 lines I2C communication

6.4 Data link layer

I2C-bus slave:

Slave address: 0x50

Frequency:

Maximum SCL frequency: 60 kHz

For further details on restrictions on I2C bus, see Annex V: Recommendation rules when

using the I2C interface page 63.

Clock synchronizing:

As an I2C-bus slave, the TDA8029 can slow down the bus clock by extending each clock

low period. The speed of any I2C-bus master is thereby adapted to the internal operating

rate of the TDA8029.

This synchronizing mechanism is also called clock stretching.

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6.5 I2C transactions

The I2c transactions use the protocol ‘ALPAR’ described previously.

6.5.1 I2C write command message

The host system sends the following I2C message structure to the TDA8029:

TDA8029

System controller

1.

2.

3.

WRITE SLAVE ADDRESS STAGE

'I2C START CONDITION', 50h

PROTOCOL 'ALPAR' STAGE

60h, Msb of length, Lsb of length, Opcode, Data[1],..., Data[Length], LRC

STOP STAGE

'I2C STOP CONDITION'

019aab412

Fig 22. I2C write protocol

6.5.2 I2C read command message, normal answer

In this case, the I2C message structure is:

TDA8029

System controller

1.

2.

3.

READ SLAVE ADDRESS STAGE

'I2C START CONDITION', 51h

PROTOCOL 'ALPAR' STAGE

(1)

60h, Msb of length, Lsb of length, Opcode, Data[1],..., Data[Length], LRC

STOP STAGE

'I2C STOP CONDITION'

019aab413

(1) The pattern 60h indicates a normal answer from the TDA8029

Fig 23. I2C read protocol

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6.5.3 I2C read message, error answer.

The I2C message structure is shown below:

TDA8029

System controller

1.

2.

3.

READ SLAVE ADDRESS STAGE

'I2C START CONDITION', 51h

PROTOCOL 'ALPAR' STAGE

E0h, 00h, 01h, Opcode, Error code, LRC

(1)

STOP STAGE

019aab414

(1) The pattern E0h indicates an error answer from the TDA8029.

Fig 24. I2C read protocol - Error

6.5.4 Examples of I2C transactions

This table below shows some I2C transactions between the host system and the

TDA8029. The data sent by the TDA8029 are in bold:

Table 4.

Opcode

I2C communication examples

I2C write message

I2C read messages

Check card presence

S, 50, 60, 00, 00, 09, LRC, P

If card present:

S, 51, 60, 00, 01, 09, 01, LRC, P

If card absent:

S, 51, 60, 00, 01, 09, 00, LRC, P

Mask Number

S, 50, 60, 00, 00, 0A, LRC, P

S, 51, 60, 00, 0E, 0A, data, LRC, P

Power up card 3v,

E.M.V.

S, 50, 60, 00, 01, 6D, 01, LRC, P

If card powered up successfully:

S, 51, 60, 00, 0F, 6D, ATR, LRC, P

If card absent, error message:

S, 51, E0, 00, 01, 6D, C0, LRC, P

Power up card 5v, ISO S, 50, 60, 00, 01, 6E, 00, LRC, P

If card powered up successfully:

S, 51, 60, 00, 0D, 6E, ATR, LRC, P

If card absent, error message:

S, 51, E0, 00, 01, 6E, C0, LRC, P

Power off card

S, 50, 60, 00, 00, 4D, LRC, P

Note: In the I2C messages given above:

‘S’ stands for I2C start condition

‘P’ means I2C stop condition.

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7. Command bytes

7.1 General commands

The following command bytes are available (listed in numerical order):

Table 5.

Command summary

Command

Code

00_H

01_H

02_H

03_H

04_H

05_H

06_H

07_H

08_H

09_H

0A_H

0B_H

0C_H

0D_H

10_H

11_H

12_H

13_H

23_H

4D_H

69_H

6B_H

6C_H

68_H

6D_H

6E_H

Answer from reader

page

32

33

41

37

38

28

35

34

29

33

34

40

32

37

40

31

32

card_command (APDU)

process_T=1_command

write_I2C

Card response (APDU) or error message

T=1 frame or error message

Acknowledge or error message

Data read from the card or error message

Acknowledge or error message

Indication of the card presence

1 parameter giving the mask number

Acknowledge

read_S9

read_S9_protection

write_S9_protected

write_S9_unprotected

verify_pin_S9

compare_S9

check_pres_card

send_num_mask

set_card_baud_rate

ifsd_request

Acknowledge or error message

Data read from the card or error message

Acknowledge

set_serial_baud_rate

negotiate (PPS)

set_clock_card

read_I2C

read_2C_extended

read_current_I2C

power_off

power_up_iso

ATR from the card or error message

Acknowledge or error message

ATR from the card or error message

power_up_S9

power_up_I2C

power_up_1.8V

power_up_3V

power_up_5V

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Command

Code

A2_H

A3_H

A4_H

A5_H

A6_H

AA_H

C1_H

C2_H

Answer from reader

Acknowledge

page

30

idle_mode (clock stop low)

power_down_mode

idle_mode (clock stop high)

set_nad

Acknowledge

30

Acknowledge

30

Acknowledge or error message

36

28

39

get_card_param

get_reader_status

power_up_S10

Fi, Di, CLK, T of the card in use or error message

Information about the current state of the reader

ATR from the card or error message

process_S10

Data read from the card or error message (read operation)

Acknowledge or error message (write operation)

read_IO

set_IO

CE_H

CF_H

Value on the IO pins

Acknowledge

42

Table 6.

Outgoing commands (only)

Command

Code

A0_H

Parameter Description

Card_take_off

Card_insertion

00_H

01_H

These commands are sent as soon as a card is inserted or extracted

without any command coming from the system. These commands use the

same operating code but the extra parameter gives the additional

information.

A0_H

These outgoing commands are sent only when the host is waiting for a

reply or is in stand by; when the card is extracted whereas the host is

sending a frame to TDA8029, the card_take_off message will be sent from

TDA8029 only when it has received the complete frame coming from the

host controller. This system prevents any conflict on the serial line.

Card deactivated

Time out

XX_H

A1_H

FF_H

The card is deactivated due to a hardware

problem (short on Vcc, overcurrent)

Time out problem on (TDA8029) Rx line

This command is used in order to warn the host controller that the last

communication has broken down (time out problem) so that the Rx line of

TDA8029 does not remain blocked.

The time out condition is a silence greater than 10 ms in the host

command frame.

Frame lost

XX_H

F1_H

An unexpected host controller command frame has been received by the

TDA8029 while it was busy to process a previous command frame.

In the last three commands, the code value is the previous code value used during a

normal exchange.

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8. Error list

The error list gives the status code identification and a brief signification of the status

error code.

Table 7.

List of error codes

Status code

08_H

20_H

21_H

22_H

24_H

26_H

27_H

29_H

30_H

31_H

32_H

33_H

34_H

35_H

38_H

39_H

3B_H

40_H

55_H

80_H

81_H

83_H

84_H

86_H

88_H

89_H

8A_H

Meaning

Length of the data buffer too short

Wrong APDU

Too short APDU

Card mute now (during T=1 exchange)

Bad NAD

Resynchronized

Chain aborted

Overflow from card

Non negotiable mode (TA2 present)

Protocol is neither T=0 nor T=1 (negotiate command)

T=1 is not accepted (negotiate command)

PPS answer is different from PPS request

Error on PCK (negotiate command)

Bad parameter in command

TB3 absent

PPS not accepted (no answer from card)

Early answer of the card during the activation

Card Deactivated

Unknown command

Card mute (after power on)

Time out (waiting time exceeded)

Too much parity errors in reception

Too much parity errors in transmission

Bad FiDi

ATR duration greater than 19200 etus (E.M.V.)

CWI not supported (E.M.V.)

BWI not supported (E.M.V.)

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Status code

Meaning

8B_H

8C_H

8D_H

92_H

93_H

94_H

95_H

96_H

97_H

98_H

99_H

9B_H

A0_H

B0_H

B1_H

B2_H

B3_H

B4_H

B5_H

B6_H

B7_H

C0_H

C1_H

C3_H

C6_H

CC_H

CD_H

E1_H

E2_H

E3_H

WI (Work waiting time) not supported (E.M.V.)

TC3 not accepted (E.M.V.)

Parity error during ATR

Specific mode byte TA2 with b5 byte=1

TB1 absent during a cold reset (E.M.V.)

TB1different from 00 during a cold reset (E.M.V.)

IFSC<10H or IFSC=FFH

Wrong TDi

TB2 is present in the ATR (E.M.V.)

TC1 is not compatible with CWT

IFSD not accepted

Not T=1 card

Procedure byte error

Writing attempt in a protected byte (S9 cards)

Pin Code error (S9 cards)

Writing error (S9 cards)

Too much data requested in a reading operation (S9 cards)

Error counter protected (S9 cards)

Writing attempt without Pin Code verification (S9 cards)

Protected bit already set (S9 cards)

Verify Pin Code error (S9 cards)

Card absent

I/O line locked while the TDA8029 attempts to access to an I2C or S10 card

Checksum error

ATR not supported

No acknowledge from the I2C synchronous card

Generic error during an exchange with an I2C synchronous card

Card clock frequency not accepted (after a set_clock_card command)

UART overflow

Supply voltage drop-off

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Status code

Meaning

E4_H

E5_H

E9_H

F0_H

F1_H

FF_H

Temperature alarm

Card deactivated

Framing error

Serial LRC error

At least one command frame has been lost

Serial time out

Table 8.

Error codes for each command

Possible returned error code

Command

Power UP 1.8V, 3V, 5V

31h, 35h, 38h, 3Bh, 80h, 85h, 86h, 88h, 89h, 8Ah, 8Bh, 8Ch, 8Dh,

92h, 93h, 94h, 95h, 96h, 97h, 98h, C0h, C3h, C4h, C6h, C7h, E2h,

E3h, E4h, E9h, F0h, F1h, FFh

Power up in ISO mode

31h, 35h, 3Bh, 80h, 96h, C0h, C3h, C4h, C6h, C7h, E2h, E3h, E4h,

E9h, F0h, F1h, FFh

T=0

08h, 20h, 21h, 0x40, A1h, 81h 83h, 84h, 91h, A0h, C0h, E2h, E3h,

E4h, E9h, F0h, F1h, FFh

Card

Command

T=1

08h, 22h, 24h, 25h, 26h, 27h, 28h, 29h, 0x40, A1h, 83h, 90h, C0h,

E2h, E3h, E4h, E9h, F0h, F1h, FFh

Negotiate

30h, 31h, 33h, 34h, 35h, 39h, 0x40, A1h, C0h, E2h, E3h, E4h, E9h,

F0h, F1h, FFh

Set Clock Card

Set card baud rate

Set Nad

C0h, E1h, F0h, F1h, FFh

86h, C0h, F0h, F1h, FFh

24h, F0h, F1h, FFh

Get card parameters

Ifsd request

0x40, A1h, C0h, F0h, F1h, FFzh

0Ah, A1h, 9Bh, C0h, E2h, E3h, E4h, E9h, F0h, F1h, FFh

F0h, F1h, FFh

Send mask number

Check presence card

Set serial baud rate

Power off

F0h, F1h, FFh

55h, F0h, F1h, FFh

F0h, F1h, FFh

Idle mode clock stop low

and high

55h, F0h, F1h, FFh

Get reader status

Power down mode

Read IO and Set IO

F0h, F1h, FFh

55h, F0h, F1h, FFh

F0h, F1h, FFh

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Command

Possible returned error code

Power up I2C

C0h, F0h, F1h, FFh

Read I2C

C0h, C1h, CCh, CDh, F0h, F1h, FFh

55h, C0h, C1h, CCh, CDh, F0h, F1h, FFh

C0h, F0h, F1h, FFh

Read I2C extended

Read current I2C

Write I2C

Power up S9

Read S9

B3h, C0h, F0h, F1h, FFh

Read S9 protection

Write S9 unprotected

Write S9 protected

Verify PIN S9

B3h, C0h, F0h, F1h, FFh

55h, B0h, B2h, B5h, C0h, F0h, F1h, FFh

55h, B1h, B4h, B7h, C0h, F0h, F1h, FFh

55h, B6h, B7h, C0h, F0h, F1h, FFh

C0h, F0h, F1h, FFh

Compare S9

Power up S10

Process command S10

C0h, C1h, F0h, F1h, FFh

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9. Commands description

9.1 General commands

9.1.1 send_num_mask

This command is used to identify the software version which is masked in TDA8029

ROM.

For example the current software will be coded as: “06 Release 1.1” (14 ASCII

characters)

System to TDA8029: 60 00 00 0A 6A

TDA8029 to System: 60 00 0E 0A 30 36 20 52 65 6C 65 61 73 65 20 31 2E 31 0E

9.1.2 check_card_presence

This command is used to check the presence of a card.

System to TDA8029: 60 00 00 09 69

TDA8029 to System: 60 00 01 09 PRES LRC

Where PRES indicates the presence of a card (00 if there is no card, 01 if a card is

present).

9.1.3 get_reader_status

This command is used to check the status of the reader.

System to TDA8029: 60 00 00 AA CA

TDA8029 to System: 60 00 01 AA STATUS LRC

Where the latched state of the TDA8029 is given in STATUS byte.

nu

SUPL

PROTL PTL

PRES

PRES card presence (0: card absent, 1: card present)

PTL overheating detection

PROTL default detected on card reader (protection on VCC or RST)

SUPL supervisor activation

The byte STATUS is cleared (except PRES bit) after having launch this command.

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9.1.4 set_serial_baud_rate

This command is used for changing the baud rate onto the serial link between the host

and the interface card. The default value is set to 38400 baud.

A parameter has to be transmitted in order to choose the baud rate:

System to TDA8029: 60 00 01 0D PAR LRC

TDA8029 to System: 60 00 00 0D 6D

Table 9.

Baud rate parameter

Baud rate (Baud)

4800

Parameter

00

01

02

03

04

05

06

9600

19200

38400

57600

76800

115200

After a baud rate change, the new value takes place for the next command sent by the

host.

9.1.5 set_esm_properties

This command is used to fix the behavior of the TDA8029 if the Energy Saving Mode is

activated.

By default, the clock stop information contained in the ATR of the activated card is used

during the session with this card to set the clock when the TDA8029 enters in power

down mode. Thus, if the card does not explicitly indicate that it supports clock stop mode

(High or Low), the card clock will be set to Fint/2.

To save even more energy during these periods, the clock mode can be forced using this

command.

System to TDA8029: 60 00 02 BC STOP STATE LRC

TDA8029 to System: 60 00 00 BC DC

Where STOP indicates the clock stop request:

00 to set the clock according to card indications

01 to force the clock stopping

(default behavior)

STATE is the clock stop level if requested (when STOP = 01):

00 to stop clock LOW

01 to stop clock HIGH

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Note 1: This command can be used only when the Energy Saving Mode is activated. If

launched when the Energy Saving Mode is not activated, an UNKNOWN_COMMAND

error will be returned by the TDA8029.

Note 2: Once this command has been launched to the TDA8029, all the further

activations of cards will follow the behavior defined within this command. One has to use

this command again to change the behavior, e.g. to come back to a clock at Fint/2.

Furthermore, even if this command is used to force a clock mode, when a card with

defined clock stop conditions is encountered, the clock stop mode indicated in the card’s

ATR will be used.

9.1.6 time_out

This command is sent from TDA8029 to the host controller if, during a transmission from

the host controller to TDA8029, the time interval between 2 characters exceeds 10ms.

This timing is calculated between each character of a frame, starts after the first

character, and is disabled after the last character of the frame. This feature has been

implemented in order to avoid any blocking of the transmission line between the host

controller and TDA8029.

TDA8029 to System: E0 00 01 6F FF 71

9.1.7 idle_mode (clock stop low)

This command is used to set the controller in idle mode. The card, if activated, has its

clock (CLK) set to low level but is still active.

Any command from the host on the serial line will wake up the device.

System to TDA8029: 60 00 00 A2 C2

TDA8029 to System: 60 00 00 A2 C2

idle_mode (clock stop high)

This command is used to set the controller in idle mode. The card, if activated, has its

clock (CLK) set to high level but is still active.

Any command from the host on the serial line will wake up the device.

System to TDA8029: 60 00 00 A4 C4

TDA8029 to System: 60 00 00 A4 C4

9.1.8 power_down_mode

This command is used to set the controller in power down mode; if the card is active, it is

then deactivated. Exiting this mode is possible with a hardware reset of TDA8029 or an

external interruption (INT0, INT1 or Rx).

System to TDA8029: 60 00 00 A3 C3

TDA8029 to System: 60 00 00 A3 C3

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9.2 Asynchronous card related commands

9.2.1 power_up commands

There are four different power up commands (5V, 3V, 1.8V or ISO). Two of them

(power_up_3V and power_up_5V) have to be followed by a parameter:

00_Hindicates that all the parameters of the ATR of the card compliant with

ISO7816-3 will be taken into account.

01_Hindicates that only the ATR of cards whose parameters are inside the E.M.V.

4.0 specification scope will be taken into account; cards having an ATR which

does not comply with E.M.V. 4.0 requirements will be rejected.

9.2.1.1 power_up_5V

This command allows to activate the card at a VCC of 5V. All the signals going to the

card will be referenced to this VCC.

An activation sequence is processed following the ISO7816-3 normalization (VCC is

rising, I/O is enabled, CLK is started, and RST is processed). If the card answers to this

command, the answer will content all the ATR parameters; these parameters are

memorized in TDA8029 and will be taken into account during the whole card session (till

the card is deactivated or till a warm reset is processed). The structure of the answer is

the following:

System to TDA8029:

60

00 01

length

6E

01

0F

ACK

code

E.M.V.

LRC

TDA8029 to System:

60

XX XX

length

6E

nnnnnnnnnnnnnnnnnnnn

ATR parameters

ZZ

ACK

code

LRC

019aab415

Fig 25. power_up_5V frame exchange

If the card is in specific mode, TDA8029 will process the next command directly using the

new interface parameters of this specific mode. If the card proposes a different Fi/Di in

the ATR than the default value (Fi/Di=372), it is up to the application to make a PPS

command by using the negotiate command. If the card proposes 2 different protocols in

its ATR, it is up to the application to make a PPS command by using the negotiate

command.

If the card does not answer to the reset, a status giving an error code is returned to the

application.

In the case of E.M.V. compliant power up, if the card is using T=1 protocol, just after

having received the ATR, TDA8029 sends an IFSD request to the card indicating that the

reader can manage a data buffer of 254 bytes (FEH).

The power_up_5V command can be used to generate a warm reset if the card is already

activated.

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9.2.1.2 power_up_3V

This command allows to activate the card at a VCC of 3V. Every signal going to the card

will be referenced to this VCC.

See power_up_5V for the other characteristics.

9.2.1.3 power_up_1.8V

This command allows to activate the card at a VCC of 1.8V. Every signal going to the

card will be referenced to this VCC.

See power_up_5V for the other characteristics.

9.2.1.4 power_up_iso

This command does not need any argument. The principle consists to activate the card

as described in ISO 7816-3:

attempt to activate the card at a VCC of 3V, if the cards answers correctly and if

it indicates in its ATR that it is a class A or a class AB card (TAi with T=15), then

the command is finished and the ATR is returned to the host,

if in the previous stage, the card did not answer correctly or did not specify in its

ATR that it was a class A or a class AB card, a new activation of the card is

launched at 5V. If the card does not answer to the reset, a status giving an error

code is returned to the application, otherwise the answer contains all the

parameters of the card.

See power_up_5V for the other characteristics (when parameter of the command is ISO,

not E.M.V.).

9.2.2 power_off

This command is used to deactivate the card whatever it has been activated for 3V or 5V

operation. A deactivation sequence is processed following the ISO 7816-3 normalization

in about 100µs.

System to TDA8029: 60 00 00 4D 2D

TDA8029 to System: 60 00 00 4D 2D

9.2.3 card_command (APDU)

This command is used to transmit card commands under APDU format from system to

TDA8029 whatever T=0 or T=1 protocol are used. Short or extended commands (see

limitations in chapter 10.1) can be used.

An answer to such a command is also made in APDU format from TDA8029 to the

system.

Example:

System to TDA8029: 60 00 07 00 00 A4 00 00 02 4F 00 8E

TDA8029 to System: 60 00 02 00 90 00 F2

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9.2.4 process_T=1_command

This command may be used if the application layer provides the complete T=1 frame

including prologue, information and epilogue fields. If it is not the case, the above

card_command opcode shall be used.

This command is used from the application layer in order to send a complete T=1 frame

to the card. This command includes the specific framing used in T=1 protocol (Prologue

Field, Information Field, Epilogue Field) and will be sent transparently to the card. The

answer from the card will be sent as a complete T=1 frame to the application layer. The

internal timing of a block (Character Waiting Time) will be handled by TDA8029. The

block Waiting Time will also be controlled by TDA8029. In case of Waiting Time

Extension request (WTX) from the card, it will be taken into account by the TDA8029.

System to TDA8029

TDA8029 to System

60 XX XX 01 NAD PCB LEN A₁A₂…… A_NEDC

60 00 06 01 NAD PCB LEN SW1 SW2 EDC

LRC

Where A1 A2…..An is information field sent to the card

XX XX is the length of the frame from NAD to EDC

In case of chaining:

System to TDA8029

TDA8029 to System

System to TDA8029

TDA8029 to System

60 XX XX 01 NAD 20 LEN A₁A₂…… A_NEDC

60 00 04 01 NAD 90 00 EDC

LRC

60 YY YY 01 NAD 40 LEN A_N+1A_N+2… … A_ZEDC LRC

60 ZZ ZZ 01 NAD PCB LEN D₁D₂… … D_NEDC LRC

9.2.5 negotiate

This command is used to make a PPS (Protocol and Parameter Selection) to the card, if

in its ATR the card proposes a different Fi/Di or 2 different protocols. By using this

command a PPS will be made to the card with the Fi or Di and protocol type entered as a

parameter (PP). It is up to the host to make the correct Fi/Di submission to the card.

Example:

System to TDA8029: 60 00 02 10 PP FD LRC

TDA8029 to System: 60 00 00 10 70

Where FD is the ratio Fi/Di given by TA1 parameter of the ATR and PP is the protocol to

be used.

If the command is acknowledged, any subsequent exchanges between the card and

TDA8029 will be made by using the new parameters.

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9.2.6 Ifsd_request

This command is used to send a S(IFS request) block to the card indicating the

maximum length of information field of blocks which can be received by the interface

device in T=1 protocol. The initial size following the answer to reset is 32 bytes and this

size shall be used throughout the rest of the card session or until a new value is

negotiated by the terminal by sending a S(IFS request) block to the card.

In E.M.V. mode, the IFSD size is automatically negotiated to 254 just after the ATR has

been received.

System to TDA8029: 60 00 01 0C PAR LRC

TDA8029 to System: 60 00 00 0C 6C

Where PAR is the IFSD size.

9.2.7 set_clock_card

This command is used for changing the card clock frequency. The default value is set to

FXTAL/4 which is 3.68625 MHz.

A parameter has to be transmitted in order to choose the card clock frequency:

System to TDA8029: 60 00 01 11 PAR LRC

Table 10. set_clock_card parameter

Based on a crystal with a frequency equal to 14.745MHz

Frequency

Parameter

Fxtal =14.745MHz

Fxtal/2=7.37MHz

Fxtal/4=3.68MHz

Fxtal/8=1.84MHz

00

02

04

06

After a card clock frequency change, all the waiting times are internally set to the new

value.

Before applying the requested clock, the compatibility of the frequency with the current Fi

used by the card is checked as described in ISO7816-3. For example, if the card has

answered in its ATR a Fi parameter of 372 or 558 (fmax ≤ 6MHz), a change of the card

clock frequency to Fxtal (14.745MHz) or Fxtal/2 (7.37MHz) will not be processed and an

error status will be sent to the application.

9.2.8 card_take_off and card_insertion

These two commands are sent directly to the system processor as soon as a card

extraction or insertion has occurred.

TDA8029 to System:

60 00 01 A0 00 C1

60 00 01 A0 01 C0

for a card extraction

for a card insertion.

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9.2.9 set_card_baud_rate

This command is used mainly for cards which are not fully ISO 7816-3 compliant with

specific and negotiable modes. As a matter of fact some cards are in specific mode but

they do not give TA2 parameter in their answer to reset. So the UART has to be set to

the right baud rate by means of this specific command which programs the baud rate.

For non ISO baud rates there is a possibility to increase the capability of the reader by

setting the bit CKU which divides by 2 the number of clock cycles of the etu and thus

doubles the baud rate of the ISO UART.

Example:

System to TDA8029: 60 00 02 0B XX CKU LRC

TDA8029 to System: 60 00 00 0B LRC

Where XX is the value of FiDi

if CKU=0, the baud rate is defined by FiDi

if CKU=1, the baud rate is 2 * the baud rate is defined by FiDi

For an etu of 372 clock cycles: XX=FiDi=0x11

prescaler = 31, divider = 12; 31 * 12 = 372, CKU=0.

Table 11. Mask06 and Mask07 supported baudrates

As the baud rates in dark boxes are using CKU bit, they are not reachable when CLK = Xtal

TA1

CLK/ETU

372

186

93

TA1

CLK/ETU

744

TA1

CLK/ETU

186

TA1

CLK/ETU

32

TA1

CLK/ETU

1536

768

0x01

0x02

0x03

0x04

0x08

0x11

0x12

0x13

0x14

0x18

0x21

0x22

0x23

0x28

0x31

0x32

0x33

0x34

0x35

0x38

0x41

0x42

0x43

0x44

0x48

0x51

0x52

0x53

0x54

0x55

0x56

0x58

0x61

0x62

0x63

0x64

0x68

0x69

0x91

0x92

0x93

0x94

0x95

0x96

0xA1

0xA2

0xA3

0xA4

0xA5

0xA8

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC8

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

372

93

16

186

46.5

124

768

384

192

96

384

46.5

31

93

192

46.5

62

1860

930

96

372

186

93

48

1116

558

465

48

128

232.5

155

64

2948

1024

512

46.5

31

279

1024

512

256

128

64

139.5

93

558

279

139.5

46.5

512

256

1488

744

256

128

64

372

64

32

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9.2.10 set_nad

Smart Card reader application with TDA8029

This command is used from the application layer in order to specify a SAD (source

address) and a DAD (destination address) for a logical connection using T=1 protocol as

defined in ISO7816-3. The default value is 00 and will be kept until the send NAD

command has been notified to the TDA8029. Any NAD submission where SAD and DAD

are identical (except 00) will be rejected. If bits b4 or b8 of the NAD required are set to 1

(VPP programming) the NAD will be rejected.

The NAD shall be initialized before any information exchange with the card using T=1

protocol, otherwise and error message will be generated.

System to TDA8029: 60 00 01 A5 NAD LRC

TDA8029 to System: 60 00 00 A5 LRC

Where NAD is the new value of NAD immediately taken into account.

9.2.11 get_card_param

This command is used from the application level in order to get the Fi and Di parameters

of the card in use, the current card clock frequency, and the protocol in use.

FiDi parameter will be given on one byte (FiDi), the card clock frequency on one byte

(CC), and the protocol on one byte (TT).

FiDi will give the value of the current Fi Di (Example 11H for Fi=372 and Di=1)

CC will take the value of the 4 lowest bits of CCR register.

TT will take value 00H for protocol T=0 and value 01H for protocol T=1.

If there is no card in use, an error message will be generated.

System to TDA8029: 60 00 00 A6 C6

TDA8029 to System: 60 00 03 A6 FiDi CC TT LRC

Where:

FIDI gives the current FIDI coded as in TA1 parameter,

CC gives the value of the card clock frequency as coded in CCR register of TDA8029,

TT gives the protocol used by the card (00 for protocol T=0, 01 for protocol T=1).

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9.3 Synchronous card related commands

9.3.1 Synchronous card S=9

9.3.1.1 power_up_S9

The card is powered under 5V and answers 4 bytes as Answer To Reset.

System to TDA8029: 60 00 00 6B 0B

TDA8029 to System: 60 00 04 6B XX₁XX₂XX₃XX₄LRC

Where XX₁XX₂XX₃XX₄are the data sent by the card in its ATR.

The card is then ready to operate.

9.3.1.2 read_S9

This command allows to read bytes of 8 bits in the card from the specified address.

System to TDA8029: 60 00 04 03 AD_HAD_LNB_HNB_LLRC

TDA8029 to System: 60 NB_HNB_L03 D₁D₂D₃…D_nLRC

Where AD_HAD_L

NB_HNB_L

indicates the address where to read (coded on 2 bytes)

is the number of bytes to read (coded on 2 bytes)

D₁D₂D_3…D_nare the NB_HNB_Ldata read

9.3.1.3 read_S9_protection

This command allows to read bytes of 8 bits + the protect bit as the 9^thbit in the card

from the specified address.

System to TDA8029: 60 00 04 04 AD_HAD_LNB_HNB_LLRC

TDA8029 to System: 60 (NB_HNB_L)*2 04 D₁0/1 D₂0/1 D₃0/1…D_n0/1 LRC

Where AD_HAD_L

NB_HNB_L

indicates the address where to read (coded on 2 bytes)

is the number of bytes to read (coded on 2 bytes)

D₁0/1 D₂0/1 D₃0/1 _…D_n0/1 are the NB_HNB_Ldata read

The process is the same as for the command read_8bit_S9 except that the value of the

protect bit is added in the answer.

Each byte read is followed by one byte that informs if the byte is protected or not (0x00:

protected, 0x01 not protected).

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9.3.1.4 write_S9_protected

This command allows to write bytes with protected bit as 9^thbit from the specified

address.

System to TDA8029: 60 NB_HNB_L05 AD_HAD_LD1 D2 D3 Bn LRC

TDA8029 to System: 60 00 00 05 LRC

Where AD_HAD_L

(NB_HNB_L)-2

indicates the address where to write (coded on 2 bytes)

is the number of bytes to write (coded on 2 bytes)

D1 D2 D3…Dn are the data to write in the card

9.3.1.5 write_S9_unprotected

This command allows to write bytes without protection from the specified address.

System to TDA8029: 60 NB_HNB_L06 AD_HAD_LD1 D2 D3 Dn LRC

TDA8029 to System: 60 00 00 06 LRC

Where AD_HAD_L

(NB_HNB_L)-2

indicates the address where to write (coded on 2 bytes)

is the number of bytes to write (coded on 2 bytes)

D1 D2 D3…Dn are the data to write in the card

9.3.1.6 verify_pin_code

System to TDA8029: 60 00 03 07 XX PIN1 PIN2 LRC

TDA8029 to System: 60 00 00 07 LRC

Where XX in the bit mask for error counter

PIN1 is the first PIN CODE

PIN2 is the second PIN CODE

9.3.1.7 compare

System to TDA8029: 60 00 03 08 AD_HAD_LXX LRC

TDA8029 to System: 60 00 00 08 LRC

Where AD_HAD_Lindicates the address of byte to compare

XX

is the byte to compare

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9.3.2 Card S=10

9.3.2.1 power_up_S10

This command powers up the S10 card; 4 bytes of Answer To Reset from the card are

expected.

System to TDA8029: 60 00 00 C1 A1

TDA8029 to System: 60 00 04 C1 xx₁xx₂xx₃xx₄LRC

Where xx₁xx₂xx₃xx₄are the data sent by the card in its ATR.

The card is then ready to operate.

9.3.2.2 process_S10

This command allows either to read or to write bytes from or into an S10 card from the

specified address.

In case of a read command:

System to TDA8029: 60 00 03 C2 CB AD NB LRC

TDA8029 to System: 60 NB_HNB_L12 D1 D2 D3…Dn LRC

Where CB

is the control byte

AD

NB

is the address byte

is the number of bytes to read

D1 D2 D3…Dn are the NB data read

In case of a write command:

System to TDA8029: 60 ML_HML_LC2 CB AD D1 D2 D3…Dn LRC

TDA8029 to System: 60 00 00 C2 A2

Where ML_HML_L

is the total message length

is the control byte

CB

AD

is the address byte

D1 D2 D3…Dn are the data to write in the card

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9.3.3 I2C cards

9.3.3.1 power_up_I2C

This command powers up the I2C card; no data are expected from the card.

System to TDA8029: 60 00 00 6C 0C

TDA8029 to System: 60 00 00 6C 0C

The card is then ready to operate.

9.3.3.2 read_I2C

This command allows to read bytes from the specified address in a standard I2C card.

System to TDA8029: 60 00 05 12 I2CAd AD_HAD_L00 NB LRC

TDA8029 to System: 60 NB_HNB_L12 xx xx xx xx xx xx xx xx xx LRC

Where I2CAd

is the physical I2C address of the embedded component

AD_HAD_Lindicates the address where to read (coded on 2 bytes)

NB

is the number of bytes to read (coded on 1 byte)

are the NB_HNB_Ldata read

xx xx xx

Remark: Normally ADH should be fixed to 00h since this command is used with standard

I2C cards.

The field ADH has been added to manage multiple blocks memory found in some I2C

cards (Gemplus GFM4K for example). In that case, ADH contains the number of the

page to read (00 H or 01H).

9.3.3.3 read_I2C_extended

This command allows to read bytes from the specified address in an extended I2C card.

System to TDA8029: 60 00 05 13 I2CAd AD_HAD_LNB_HNB_LLRC

TDA8029 to System: 60 NB_HNB_L13 xx xx xx xx xx xx xx xx xx LRC

Where I2CAd

is the physical I2C address of the embedded component

AD_HAD_Lindicates the address where to read (coded on 2 bytes)

NB_HNB_Lis the number of bytes to read (coded on 2 bytes)

xx xx xx

are the NB_HNB_Ldata read

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9.3.3.4 read_current_I2C

This command allows to read bytes from the current address in a standard I2C card.

System to TDA8029: 60 00 03 23 I2CAd NB_HNB_LLRC

TDA8029 to System: 60 NB_HNB_L23 D1 D2 D3…Dn LRC

Where I2CAd

NB_HNB_L

is the physical I2C address of the embedded component

is the number of bytes to read (coded on 2 bytes)

D1 D2 D3…Dn are the NB_HNB_Ldata read

9.3.3.5 write_I2C

This command allows to write bytes in an I2C card from a specified address.

Two different cases can be met depending on the type of the I2C card: using the

extended mode or not.

If the card is using extended mode, then the address is coded on 2 bytes, as if the card is

not using the extended mode, the address is coded only on one byte. This is the

responsibility of the application layer to know if the current card is using the extended

mode or not.

Card using extended mode:

System to TDA8029: 60 NB_HNB_L02 I2CAd AD_HAD_LD1 D2 D3 … Dn LRC

TDA8029 to System: 60 00 00 02 LRC

Where I2CAd

AD_HAD_L

(NB_HNB_L)-3

is the physical I2C address of the embedded component

indicates the address where to write (coded on 2 bytes)

is the number of bytes to write (coded on 2 bytes)

D1 D2 D3…Dn are the data to write in the card

Card not using extended mode:

System to TDA8029: 60 NB_HNB_L02 I2CAd AD D1 D2 D3 … Dn LRC

TDA8029 to System: 60 00 00 02 LRC

Where I2CAd

AD

is the physical I2C address of the embedded component

indicates the address where to write (coded on 1 byte)

is the number of bytes to write (coded on 2 bytes)

(NB_HNB_L)-2

D1 D2 D3…Dn are the data to write in the card

Remark: This function does not manage the change of segment in the EEPROM. The

maximum length of the data stream that can be programmed in one step depends of the

embedded component.

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9.4 General purpose IO commands

9.4.1 read_IO

This command is used to read the current state of the four general purpose IO of the

TDA8029.

System to TDA8029: 60 00 00 CE AE

TDA8029 to System: 60 00 01 CE VAL LRC

VAL is coded as follows:

0

P2.7

P2.6

P1.7

P1.6

0 if IO = GND, 1 if IO = V

DD

019aab416

Fig 26. Read IO command – VAL byte description

9.4.2 set_IO

This command is used to set one of the general purpose IO of the TDA8029 to a

specified logic level.

System to TDA8029: 60 00 02 CF IO VAL LRC

TDA8029 to System: 60 00 00 CF AF

Where IO and VAL are coded as follows:

Table 12. IO coding in set_IO command

IO

Port

P1.6

P1.7

P2.6

P2.7

0x01

0x02

0x03

0x04

Table 13. VAL coding in set_IO command

VAL

Level to apply

GND

0x00

0X01

VDD

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10. Information field for asynchronous cards

The data buffer has a size of 512 bytes whose 6 bytes located at the end of the buffer

are used by the internal library; so the data buffer has a real size of 506 bytes.

The information field that can include up to 506 bytes is composed of APDUs

(Application Protocol Data Unit) according to the ISO7816-4 normalization definition.

Different examples are given according to Annex A of the E.M.V.’96 in T = 0.

TAL (System)

TTL (TDA8029)

Case 1 command

⎨60, 00, 04, 00, CLA, INS, P1, P2, LRC⎬

⇒

1442443

4 header bytes

⇐

⎨60, 00, 02, 00, 90, 00,

LRC⎬

Case 2 command

⎨60, 00, 05, 00, CLA, INS, P1, P2, 00, LRC⎬

⇒

⇐

⎨60, Licc+2, 00, [Data (Licc)], 90, 00,

LRC⎬

Case 3 command

⎨60, Lc+5, 00, CLA, INS, P1, P2, Lc, [data Lc], LRC⎬

⇒

⇐

⎨60, 00, 02, 00, 90, 00, LRC⎬

Case 4 command

⎨60, Lc+5+1, 00, CLA, INS, P1, P2, Lc, [data Lc], 00,

LRC⎬

⇒

⇐

⎨60, Licc+2, 00, [data Licc], 90, 00,

LRC⎬

Case 2 command

using the 61 and 6C procedure byte

Le = Licc or Le ≥ Licc

⎨60, 00, 05, 00, CLA, INS,P1, P2, 00, LRC⎬

⇒

⇐

60, D1+D2+Dn+2, 00, [data D1+D2+Dn], 90, 00, LRC⎬

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10.1 Extended cases

In T=0 protocol, the extended cases for APDUs are not supported on this mask.

In T=1 protocol, the use of the extended cases for APDUs is transparent from the host

point of view as explained below as the TPDUs are identical to the APDUs.

Case 2 extended example:

APDU: CLA INS P1 P2 00 B2 B3 where B2 B3 is the length coded on 2 bytes (from 1 to

65535). With both mask 06 and mask 07 release, B2 B3 shall never exceed 498 bytes.

System to TDA8029: 60 00 07 00 CLA INS P1 P2 00 B2 B3 LRC

TDA8029 to card: NAD PCB 07 CLA INS P1 P2 00 B2 B3 EDC

Card to TDA8029: NAD PCB LEN1 D1 D2 …. Di EDC

Where LEN1 is related to the negotiated data buffer size.

TDA8029 to card: Rblock for acknowledge.

Card to TDA8029: NAD PCB LEN2 Di+1 D1+2 …. Dn SW1 SW2 EDC

Where n = B2 B3

For this example it is supposed that only one chaining step is necessary.

TDA8029 to System: 60 B4 B5 00 D1 D2 …….. Dn SW1 SW2 LRC

(B4 B5 =n+2)

References: ISO 7816-4 §5.3 and Annex B.

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11. Conclusion

The following features give the general characteristics of both mask 06 and mask 07:

1.8V, 3V and 5V cards supported

E.M.V. 4.0 validated but possibility to switch to full ISO 7816-3

Data buffer up to 506 bytes

Asynchronous protocols (T=0 and T=1) supported

A I2C, S9, S10 synchronous cards supported

Serial link for control and communication with variable baud rates from 4800 to

115200 baud

Automatic hardware protections in the event of card take off, supply voltage drop

short circuit or overheating

All ISO7816-3 baud rates supported on the I/O line

Possible selection of card clock frequencies

Communication with the host made at the APDU level (asynchronous cards) or

also possible at TPDU level for protocol T=1

Single +2.7V to +6.0V supply voltage

Settings of switches for the configuration:

Table 14. Host interface hardware configuration

Interface

P17 (#1)

RS232 (see section 5)

I2C (see section 6)

VDD

GND

Table 15. ESM hardware configuration

ESM

P26 (#25)

ON

VDD or not connected

GND

OFF

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12. ANNEX I: SCRTESTER

SCRTester is a PC software allowing to communicate with a Philips smart card reader

(CAKE8029_11D for instance) through an RS232 serial link.

SCRTester can be used when the TDA8029 mask 06 or mask 07 is configured to be

interfaced with a host controller by using a RS232 serial link

12.1 Installation

SCRTester is supplied in two floppy disks. Run the setup.exe file located on the floppy #1

to install SCRTester on your computer, and then follow the given indications.

Once installed, SCRTester is available in C:\Program Files\Philips Semiconductors

directory (SCRTester.exe).

12.2 Run SCRTester

When SCRTester is launched for the first time, the following screen appears:

019aab417

Fig 27. SCRTester main window

SCRTester includes a complete help file that can be launched by pressing F1 function

key or by selecting the HelpÆContents menu item.

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SCRTester tries to establish a serial connection with the reader on COM1 port. If this port

is not available, the following warning message appears and then the user has to

manually configure the port used by the reader by using the Reader menu item (select

the correct port COMx and after that use the Connect command).

019aab418

Fig 28. SCRTester – Serial port connection error window

12.2.1 The top right window

The top right window contains the command script file, which can be directly modified by

the user.

The commands have to be written following the correct format defined in this application

note. By default, SCRTester is configured in Command mode (Script menu item), i.-e.

ALPAR header frame (except Command byte) and LRC character are not needed.

For example, to send a send_num_mask command to the reader (p. 28), one has to

write

0A;

In the script window, SCRTester will automatically send the complete frame to the

reader:

60 00 00 0A 6A

12.2.2 The bottom right window

The bottom right window contains all the commands sent to the reader (in red color) and

the received answers (in blue color).

12.2.3 The left window: card parameters

In case of send_num_mask or power_up commands, the left window is refreshed with

received information from the reader:

The current mask number string is displayed,

The complete ATR is decomposed into individual fields.

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13. ANNEX II: Hardware information

IC2

MAX3241CA1

C14

C1+

C15

28

24

1

V+

0.22 μF_35 V

C17

27

C1-

C2+

C2-

C19

22 pF

C18

22 pF

1 μF_16 V

VDD

BP1

Y1

C16

V-

1 μF_16 V

3

8

1

2

1 μF_16 V

VDD

14.745 MHz

TX TP12

T1IN

T2IN

T3IN

T1OUT

T2OUT

T3OUT

K1

14

13

12

9

19

11

J3

GND

TP4

SUBD09FC

P16

VDD

TP21

1

SHUTDOWN

TP3

RxD

6

7

8

9

R1OUTB

R2OUTB

R1OUT

R2OUT

2

3

4

5

TxD

21

20

19

18

17

16

15

C3

P17

P16

P27

TP28

R1IN

R2IN

R3IN

R4IN

R5IN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

4

5

6

7

8

PSEN

ALE

10 μF_16 V

C4

R1

VDD

0 Ω

RX TP11 R3OUT

R4OUT

100 nF

GND

SDWN

CDEL

I_O

EA

VDD

IC1

TDA8029

U1

C6

220 nF

TEST

SAM

PGND

SBM

R5OUT

CARD_READ_CCM01_2251

C5

22 nF

_EN

C5I C1I

C6I C2I

C7I C3I

C8I C4I

23

22

_SHDN

R2

I/O TP15

ARD

C40

33 pF

180 Ω

GND

VCC

PRES TP14

PRES

25

26

VDD

K1

K2

C13

VDD

0.22 μF_35 V

C9

GNDC TP18

CLK TP16

VCC TP19

RST TP17

220 nF

R3

100 Ω

C18

VUP

TP25

220 nF

C7

VDD

C38

100 nF

C8

220 nF

VDD TP2

J1

+5 V

2

100 pF

AMP;MTA396D2

J2

C11

C2

33 μF

16 V

C1

100 nF

C12

JACK2.5_H

GND TP1

J1

GND

1

10 μF

16 V

VDD

AMP;MTA396D2

019aab419

Fig 29. Design example - Electrical schematic

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TP1

TP2

J1

J2

C1

BP1

C2

K1

Y1

C14

C15

C13

TP11

TP12

IC2

25

C16

1

IC1

C17

17

9

C5

TP25

TP14

C7

C8

TP15

TP18

TP16

C30

R1

C6

TP17

TP19

J3

019aab420

Fig 30. Design example - Components top view

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U1

R3

R2

C40

019aab421

Fig 31. Design example - Components bottom view

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019aab422

Fig 32. Design example – Layout top view

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019aab423

Fig 33. Design example – Layout bottom view

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019aab424

Fig 34. Design example – BOM 1

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019aab425

Fig 35. Design example – BOM 2

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14. ANNEX III: Part of Implementation Conformance Statement EMV 4.0

Table 16. Implemented protocol types

Please mark the boxes with yes or no

Item

number

Protocol type

Reference

Status Support

(Y/N)

1

ATR

EMV 2000, §4

EMV 2000, §5.2.2

EMV 2000, §5.2.4

EMV 2000, §5.3.1

EMV 2000, §5.3.2

ISO 7816-3

m

o

Y

N

2

Character protocol T=0

Block protocol T=1

Transport of APDUs by T=0

Transport of APDUs by T=1

ATR

3

4

5

6

7

Character protocol T=0

Block protocol T=1

Transport of APDUs by T=0

Transport of APDUs by T=1

Other protocol

ISO 7816-3

o

8

ISO 7816-3

o

9

ISO 7816-3

o

10

11

ISO 7816-3

o

To be precised

o

Table 17. General Protocol Information

Please answer the questions by marking the boxes:

Item

Parameter

Reference

Value(s)

number

1

2

3

Maximum time to issue a warm reset?

Maximum time to issue a deactivation?

EMV 2000, §2.1.3.2 About

41000 CLK

EMV 2000, §2.1.5

Terminal

dependent

Maximum time for the terminal to transmit a

command after receiving data from the card?

—

Terminal

dependent

Reference

Y/N

4

5

Does the terminal reject an ICC returning TCK in a EMV 2000, §4.3.4

T=0 ATR?

N

Does the terminal continue the card session as

soon as all characters indicated in T0 and/or TDi

have been received?

EMV 2000, §4.3.4

Y

Status Reference

Y/N

6

7

Implicit negotiable mode (without PPS)

Explicit negotiable mode (with PPS)

m

EMV 2000, §4.2, 5

o*

* Outside the scope of the EMV 2000 specification

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Table 18. Protocol — Timing

Please answer the questions by marking the boxes with the maximum timing allowed by the terminal before it rejects the

ICC behavior

Item

number

1

Parameter

Reference

Status Maximum

allowed*

Maximum

supported

20,160 etus

Maximum ATR duration before warm

reset or deactivation?

EMV 2000,

§4.4

m

20,160 etus

(4^thbullet)

2

Maximum inter-character time

supported before deactivation during

ATR?

EMV 2000,

§4.4

(3^rdbullet)

m

10,080 etus

3

4

5

Default work waiting time in T=0?

EMV 2000,

§5.2.2.1

m

c1

m

D x 10,080 etus

Work waiting time in T=0 with “01” ≤

TC2 ≤ “09”?

EMV 2000,

§5.2.2.1

D x (960 x WI etus +

480) etus

D x (960 x WI etus +

480) etus

Maximum block waiting time supported EMV 2000,

(2BWI x 960 x 372 x D (2BWI x 960 x 372 x D

before error correction in T=1?

§5.2.4.2.2

/ F) + 11+ D x 960

etus

/ F) + 11+ D x 960

etus

6

Maximum character waiting time

EMV 2000,

m

16 etus for CWI = 1 to 16 etus for CWI = 1

supported before deactivation or block §5.2.4.2.2

retransmission request in T=1?

47 etus for CWI = 5

to 47 etus for CWI = 5

c1: applies only if the terminal is able to support such values of TC2.

• The minimum allowed is above the given value in a strict inequality meaning.

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Table 19. Parameter Values for ATR

Please supply the supported values

Item

Param. Reference

Status

Values

number

Allowed

Supported

‘3B’, ‘3F’

1

2

3

4

5

6

7

8

TS

EMV 2000, §4.3.1

m

c1

m

“3F,” ‘3B”

TA1

TB1

TC1

EMV 2000, §4.3.3.1

EMV 2000, §4.3.3.2

EMV 2000, §4.3.3.3

“11” – “12” and “13”

“00” … “10” and “14” … “FF”

TA1 absent

“11” – “12” and “13”

(see attached list)

TA1 absent

“00” (cold reset)

any value (warm reset)

TB1 absent (warm reset)

any value (warm reset)

TB1 absent (warm reset)

any value

and

(2^CWI> (N+1) if T=1)

9

TC1

TD1

EMV 2000, §4.3.3.3

EMV 2000, §4.3.3.4

m

TC1 absent

10

m.s. nibble: any*

l.s. nibble: “0,” ”1”

m.s. nibble: any*

l.s. nibble: “0,” ”1”

11

12

13

14

15

16

17

18

TD1

TA2

TB2

TC2

TD2

EMV 2000, §4.3.3.4

EMV 2000, §4.3.3.5

EMV 2000, §4.3.3.6

EMV 2000, §4.3.3.7

EMV 2000, §4.3.3.8

m

TD1 absent

c1

m

“00” … ‘”FF”

‘00’, ‘01’, ‘80’, ‘81’

TA2 absent

p**

m

None

“0A”

‘0A’

p**

C1

“00”

“01” … ”09” and “0B” … ”FF”

m

(T=1)

m.s. nibble: any*

l.s. nibble: “1,” “E”

m.s. nibble: any*

l.s. nibble: “1,” “E”

19

20

TD2

TA3

EMV 2000, §4.3.3.8

EMV 2000, §4.3.3.9

p**

l.s. nib. neither “1” nor “E”

“10” … “FE”

m

(T=1)

“10” … “FE”

TA3 absent

21

22

TA3

EMV 2000, §4.3.3.9

p**

“00” … “0F,” “FF”

TA3 absent

m

(T=1)

23

TB3

EMV 2000, §4.3.3.10

m

(T=1)

m.s. nibble: “0” … ”4” and

l.s. nibble: “0” … ”5” and

m.s. nibble: “0” … ”4” and

l.s. nibble: “0” … ”5” and

2

^CWI> (N+1)

2^CWI> (N+1)

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Item

Param. Reference

Status

Values

24

TB3

EMV 2000, §4.3.3.10

p**

m.s. nibble > “4” or

l.s. nibble > “5” or

^CWI≤ (N+1)

2

25

26

TB3

TC3

EMV 2000, §4.3.3.10

EMV 2000, §4.3.3.11

p**

TB3 absent

TC3 = “00”

m

TC3 = “00”

(T=1)

27

TC3

EMV 2000, §4.3.3.11

p**

TC3 ≠ “00”

c1: the terminal may allow specific mode or value only if it is able to support it.

• Provided the values are consistent with characters actually returned.

** Shaded boxes indicate a prohibited capability.

List of supported Fi Di dividers:

0x01, 0x02, 0x03, 0x04, 0x08, 0x11, 0x12, 0x13, 0x14, 0x18, 0x21, 0x22, 0x23, 0x28,

0x31, 0x32, 0x33, 0x34, 0x35, 0x38, 0x41, 0x42, 0x43, 0x44, 0x48, 0x51, 0x52, 0x53,

0x54, 0x55, 0x56, 0x58, 0x61, 0x62, 0x63, 0x64, 0x68, 0x69, 0x91, 0x92, 0x93, 0x94,

0x95, 0x96, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA8, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6,

0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC8, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6

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Table 20. Protocol T=0 - Parameter Values

Please supply the supported values

Item

Parameter

Reference

Status Values

number

Allowed

Supported

1

Terminal minimum inter-character time

EMV 2000, §5.2.2.1

(according to TC1)

m

“12” … “266”

“12” …

“266”

2

3

4

ICC minimum inter-character time

EMV 2000, §5.2.2.1

m

“11.8”

“15”

“11.8”

“15”

ICC–terminal minimum inter-character time

Terminal–ICC minimum inter-character time

“16”

Table 21. Protocol T=1 - Implemented Features

Please mark the boxes with yes or no

Item

number

Function

Reference

Status Support

(Y/N)

1

Node addressing: modification of received NAD ≠ “00” during the EMV 2000, §5.2.4.1.1.1

card session

o

Y

2

3

Byte wise parity checking

EMV 2000, §5.2.5

m

Y

N

Y

Behavior on BWT or WTX excess

EMV 2000, §5.2.5.1

c1-1

c1-2

c1: on BWT or WTX excess, the IFM shall implement one of the two following behaviors:

c1-1: deactivate

c1-2: request for block retransmission

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Table 22. Block Types

Please mark the boxes with yes or no.

Item

Block

Reference

Sending

Receipt

number

Status Support Status Support

(Y/N)

Y

(Y/N)

Y

1

I-block

EMV 2000, §5.2.4.1.1.2

EMV 2000, §5.2.4.4

m

2

R-block

Y

m

Y

3

Chained I-blocks

S(RESYNCH request)

Y

m

Y

4

EMV 2000, §5.2.5.1 / 8. and note c1

EMV 2000, §5.2.5.1 / 8. and note c2

Y

m*

o***

Y

4a

5

N

Y

S(RESYNCH response)

(c1/c2)

EMV 2000, §5.2.5.1 / 8. note

p**

m

Y

6

7

8

9

S(RESYNCH response)

(else)

EMV 2000, §5.2.5.1 / 8.

note

m***

na

m

N

S(IFS request) with INF = ‘FE’ is

the first block sent following ATR

EMV 2000, §5.2.4.3 / 1.

EMV 2000, §5.2.4.3 / 1

EMV 2000, §5.2.4.3 / 3.

Y

S(IFS request) otherwise

p**

m

Y

S(IFS response)

m

10

11

12

13

14

S(ABORT request)

S(ABORT response)

S(WTX request)

EMV 2000, §5.2.5.1 / 9. and note p**

EMV 2000, §5.2.5.1 / 9. and note c3

m

Y

m*

m

EMV 2000, §5.2.4.3 / 10.

p**

m

S(WTX response)

Vpp error request

m*

EMV 2000, §5.2.4.1.1.2

p**

note 8

15

Vpp error response

EMV 2000, §5.2.4.1.1.2

p**

m*

Y

note 8

c1: the terminal may issue a S(RESYNCH request) if it supports ISO-compliant

resynchronization for proprietary reasons; otherwise, it shall deactivate the ICC contacts

when loosing synchronization.

c2: strictly identical to c1 except that the resynch is proprietary and not ISO compliant

c3: when the terminal receives an S(ABORT request), it may issue an S(ABORT

response) if it supports abortion; otherwise, it shall deactivate the ICC contacts.

•

The ICC sending this type of block is a protocol error; the terminal shall apply EMV 2000, §5.2.5

(“Error Detection and Correction for T=1”).

** Shaded boxes indicate a prohibited capability.

*** Optional for cases related to c1/c2; otherwise, mandatory as protocol error.

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Table 23. Parameter Values for T=1

Please supply the supported values

Item

number

1

Parameter

Reference

Status

Values

Allowed

Supported

LEN of INF

EMV 2000, §5.2.4.1.1.3

reference specification

m

“0” …

“254”

“0” … “254”

2

3

IFSD

EMV 2000, §5.2.4.2.1

EMV 2000, §5.2.4.2.2

m

“254”

TC1 minimum

“11” …

“266”

“11” … “266”

4

5

ICC intercharacter minimum time EMV 2000, §5.2.4.2.2

m

“10.8”

“21”

“10.8”

“21”

ICC Block guard time

EMV 2000, §5.2.4.2.2

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15. ANNEX IV: Specific Case 4 command correction with Mask 07

15.1 ANALYSE OF THE ISSUE

This issue occurs when the following conditions are fulfilled:

Protocol T= 0,

C-APDU of case 4 type i.e. CLA INS P1 P2 Lc [Lc Data] Le when Le is equal 1 or 2,

The warning status words 62 h XXh is returned by the card,

The number of returned data (excluding the status words) is equal to 1or 2.

In EMV4.0 document, this transaction is named ‘Case 4 command with warning

condition’.

15.2 Correct transaction with TDA8029C207

HOST

READER

CARD

CLA INS P1 P2 Lc [Lc Data] Le =>

CLA INS P1 P2 Lc =>

<= INS

[Lc Data]

=>

<= 62 XX

00 C0 00 00 00

00 C0 00 00 YY

<= 6C YY

<= C0 [YY Data] 90 00

The R-APDU [YY Data] 62 XX is returned to the host.

15.3 Transaction performed by the TDA8029C206

HOST

READER

CARD

CLA INS P1 P2 Lc [Lc Data] Le =>

CLA INS P1 P2 Lc =>

<= INS

[Lc Data]

=>

<= 62 XX

00 C0 00 00 00

00 C0 00 00 YY

<= 6C YY

<= C0 [YY Data] 90 00

Instead of returning [YY Data] 62 XX, the TDA8029C206 sends back the R-APDU [YY Data]

90 00 when YY is equal 1 or 2.

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16. Annex V: Recommendation rules when using the I2C interface

First, the IIC clock shall not exceed 60 KHz and needs to have a 50 % duty cycle.

You should insert 6 µs delay between the start condition and clock low and 15 µs delay

before and after the ACK.

The IIC master shall support the clock stretching mechanism in order to work properly

with the TDA8029.

For any exchange, a write command followed by a read command need to be sent in

order to complete the exchange.

A delay may be inserted between the write command and the read command otherwise

the TDA8029 may not acknowledge the address saying it is not yet ready (see picture 3).

STA 50 60 00 00 0A 6A STO (Write command for mask number)

STA 51 60 00 0E 0A 30 37 20 52 65 6C 65 61 73 65 20 31 2E 30 05 STO (Read

command for Mask7 release 1.0)

You will find bellow some scope pictures showing a “Mask Number” command

exchanged between the PC and the TDA8029 demo board (60Kbauds).

019aab426

(1) Channel 1: SDA; Channel2: SCL

Fig 36. Zoom of the Mask number command from Host

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019aab426

(1) Channel 1: SDA; Channel2: SCL

Fig 37. Zoom of the answer from TDA8029

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019aab427

(1) Channel 1: SDA; Channel2: SCL

Fig 38. Zoom of the NAK of the address during the Answer from TDA8029

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17. Legal information

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products.

17.1 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.2 Disclaimers

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Evaluation products — This product is provided on an “as is” and “with all

faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates

and their suppliers expressly disclaim all warranties, whether express,

implied or statutory, including but not limited to the implied warranties of non-

infringement, merchantability and fitness for a particular purpose. The entire

risk as to the quality, or arising out of the use or performance, of this product

remains with customer.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In no event shall NXP Semiconductors, its affiliates or their suppliers be

liable to customer for any special, indirect, consequential, punitive or

incidental damages (including without limitation damages for loss of

business, business interruption, loss of use, loss of data or information, and

the like) arising out the use of or inability to use the product, whether or not

based on tort (including negligence), strict liability, breach of contract, breach

of warranty or any other theory, even if advised of the possibility of such

damages.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability

towards customer for the products described herein shall be limited in

accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Notwithstanding any damages that customer might incur for any reason

whatsoever (including without limitation, all damages referenced above and

all direct or general damages), the entire liability of NXP Semiconductors, its

affiliates and their suppliers and customer’s exclusive remedy for all of the

foregoing shall be limited to actual damages incurred by customer based on

reasonable reliance up to the greater of the amount actually paid by

customer for the product or five dollars (US$5.00). The foregoing limitations,

exclusions and disclaimers shall apply to the maximum extent permitted by

applicable law, even if any remedy fails of its essential purpose.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.3 Trademarks

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Notice: All referenced brands, product names, service names and

trademarks are property of their respective owners.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP

Semiconductors accepts no liability for any assistance with applications or

customer product design. It is customer’s sole responsibility to determine

whether the NXP Semiconductors product is suitable and fit for the

customer’s applications and products planned, as well as for the planned

AN10207

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NXP Semiconductors

Smart Card reader application with TDA8029

18. List of figures

Fig 1.

Fig 2.

Fig 3.

Fig 4.

TDA8029 application diagram example ............3

ESM Mechanism...............................................5

CDEL pin action overview.................................6

Correspondence between reset delay and

CDEL capacitor.................................................7

Fig 5.

Fig 6.

Fig 7.

Fig 8.

Fig 9.

Fig 10.

Fig 11.

Frame structure.................................................8

4 header bytes ..................................................8

Successful command frame description............9

Unsuccessful command frames........................9

Acknowledge frame ..........................................9

RS232 Interface configuration.........................10

Communication initiated by the system

controller .........................................................11

Fig 12.

Communication initiated by the system

controller .........................................................11

Fig 13.

Fig 14.

Communication initiated by the TDA8029.......12

Communication initiated by the TDA8029 –

Frame description ...........................................12

Fig 15.

Fig 16.

Fig 17.

Fig 18.

Fig 19.

Card move – frame example...........................13

I2C Bus interface configuration.......................15

I2C communication with ESM off ....................16

I2C communication with ESM on ....................17

4 lines I2C communication example initiated by

the host ...........................................................18

Fig 20.

4 lines I2C communication example initiated by

the TDA8029...................................................18

Fig 21.

Fig 22.

Fig 23.

Fig 24.

Fig 25.

Fig 26.

Fig 27.

Fig 28.

2 lines I2C communication..............................19

I2C write protocol............................................20

I2C read protocol ............................................20

I2C read protocol - Error .................................21

power_up_5V frame exchange .......................31

Read IO command – VAL byte description .....42

SCRTester main window.................................46

SCRTester – Serial port connection error

window............................................................47

Fig 29.

Fig 30.

Fig 31.

Fig 32.

Fig 33.

Fig 34.

Fig 35.

Fig 36.

Design example - Electrical schematic ...........48

Design example - Components top view.........49

Design example - Components bottom view...50

Design example – Layout top view .................51

Design example – Layout bottom view ...........52

Design example – BOM 1 ...............................53

Design example – BOM 2 ...............................54

Zoom of the Mask number command from

Host ................................................................63

Fig 37.

Fig 38.

Zoom of the answer from TDA8029................64

Zoom of the NAK of the address during the

Answer from TDA8029....................................65

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Smart Card reader application with TDA8029

19. List of tables

Table 1. Host interface hardware configuration ..............4

Table 2. ESM hardware configuration.............................5

Table 3. I2C modes.......................................................15

Table 7. List of error codes ...........................................24

Table 8. Error codes for each command.......................26

Table 9. Baud rate parameter.......................................29

Table 10. set_clock_card parameter...............................34

Table 12. IO coding in set_IO command.........................42

Table 13. VAL coding in set_IO command......................42

Table 14. Host interface hardware configuration ............45

Table 15. ESM hardware configuration...........................45

Table 16. Implemented protocol types............................55

Table 17. General Protocol Information ..........................55

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Smart Card reader application with TDA8029

20. Contents

9.1.6

9.1.7

time_out............................................................30

idle_mode (clock stop low) ...............................30

1.

Introduction .........................................................3

2.

Hardware and power management....................4

Hardware............................................................4

Host Controller Interface ....................................4

Power management: Energy Saving Mode........4

Shutdown mode .................................................6

Power-On Reset.................................................6

idle_mode (clock stop high) ..............................................30

9.1.8

9.2

9.2.1

9.2.1.1

9.2.1.2

9.2.1.3

9.2.1.4

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.2.7

9.2.8

9.2.9

2.1

2.2

2.3

2.4

2.5

power_down_mode..........................................30

Asynchronous card related commands ............31

power_up commands .......................................31

power_up_5V ...................................................31

power_up_3V ...................................................32

power_up_1.8V ................................................32

power_up_iso...................................................32

power_off..........................................................32

card_command (APDU) ...................................32

process_T=1_command...................................33

negotiate...........................................................33

Ifsd_request......................................................34

set_clock_card .................................................34

card_take_off and card_insertion .....................34

set_card_baud_rate .........................................35

set_nad.............................................................36

get_card_param ...............................................36

Synchronous card related commands ..............37

Synchronous card S=9.....................................37

power_up_S9 ...................................................37

read_S9............................................................37

read_S9_protection..........................................37

write_S9_protected ..........................................38

write_S9_unprotected ......................................38

verify_pin_code ................................................38

compare ...........................................................38

Card S=10........................................................39

power_up_S10 .................................................39

process_S10 ....................................................39

I2C cards..........................................................40

power_up_I2C..................................................40

read_I2C...........................................................40

read_I2C_extended..........................................40

read_current_I2C .............................................41

write_I2C ..........................................................41

General purpose IO commands .......................42

read_IO ............................................................42

set_IO...............................................................42

3.

Software aspect...................................................7

4.

4.1

4.1.1

4.1.2

4.1.3

Protocol “ALPAR”...............................................8

General dialog structure.....................................8

Successful command.........................................9

Unsuccessful command.....................................9

Answer with an acknowledge (power_off,

idle_mode, power_down_mode) ........................9

5.

5.1

5.2

RS232 Interface .................................................10

General description..........................................10

Dialog structure in case of Energy Saving Mode

activated...........................................................10

Communication initiated by the system

controller ..........................................................11

Communication initiated by the TDA8029........12

Timing considerations ......................................13

Abnormal communication process ...................14

9.2.10

9.2.11

9.3

5.2.1

9.3.1

5.2.2

5.2.3

5.2.4

9.3.1.1

9.3.1.2

9.3.1.3

9.3.1.4

9.3.1.5

9.3.1.6

9.3.1.7

9.3.2

9.3.2.1

9.3.2.2

9.3.3

9.3.3.1

9.3.3.2

9.3.3.3

9.3.3.4

9.3.3.5

9.4

6.

6.1

6.2

6.3

6.3.1

6.3.2

6.4

I2C-bus interface ...............................................15

General description..........................................15

Energy Saving Mode deactivated.....................16

Energy Saving Mode activated.........................17

4 lines I2C-bus .................................................17

2 lines I2C-bus .................................................19

Data link layer ..................................................19

I2C transactions ...............................................20

I2C write command message...........................20

I2C read command message, normal answer..20

I2C read message, error answer......................21

Examples of I2C transactions...........................21

6.5

6.5.1

6.5.2

6.5.3

6.5.4

7.

7.1

8.

Command bytes ................................................22

General commands..........................................22

Error list .............................................................24

9.4.1

9.4.2

9.

9.1

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

Commands description ....................................28

General commands..........................................28

send_num_mask..............................................28

check_card_presence......................................28

get_reader_status ............................................28

set_serial_baud_rate........................................29

set_esm_properties..........................................29

10.

10.1

11.

Information field for asynchronous cards.......43

Extended cases................................................44

Conclusion.........................................................45

ANNEX I: SCRTESTER.....................................46

Installation ........................................................46

12.

12.1

continued >>

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Smart Card reader application with TDA8029

12.2

Run SCRTester................................................46

12.2.1

12.2.2

12.2.3

The top right window........................................47

The bottom right window..................................47

The left window: card parameters ....................47

13.

14.

ANNEX II: Hardware information.....................48

ANNEX III: Part of Implementation

Conformance Statement EMV 4.0 ....................55

15.

ANNEX IV: Specific Case 4 command

correction with Mask 07....................................62

ANALYSE OF THE ISSUE...............................62

Correct transaction with TDA8029C207...........62

Transaction performed by the TDA8029C206..62

15.1

15.2

15.3

16.

Annex V: Recommendation rules when using

the I2C interface ................................................63

17.

Legal information ..............................................66

Definitions ........................................................66

Disclaimers.......................................................66

Trademarks......................................................66

17.1

17.2

17.3

18.

19.

20.

List of figures.....................................................67

List of tables ......................................................68

Contents.............................................................69

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in the section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 February 2011

Document identifier: AN10207


型号：	TDA8029HL/C207
厂家：	NXP
描述：	Microcontroller 微控制器外围集成电路
文件：	总70页 (文件大小：1753K)
中文：	中文翻译
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TDA8029HL/C207 [NXP]

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