TDA8030HL [NXP]
USB smart card reader (OTP or ROM); USB智能卡读卡器（OTP或ROM）的
| 型号： | TDA8030HL |
| 厂家： | 
NXP |
| 描述： | USB smart card reader (OTP or ROM) |
| 文件： | 总57页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8030; TDA8031
USB smart card reader
(OTP or ROM)
Product specification
2003 Jul 04
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
CONTENTS
8.5
USB INTERFACE
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
End-points
1
2
3
4
5
6
7
FEATURES
Phase-locked loop
Bit clock recovery
Interface signals with the microcontroller
Block diagram
USB registers
Instruction set
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
Analog interface
Suspend mode
PINNING
9
LIMITING VALUES
7.1
7.2
TDA8030
TDA8031
10
11
12
13
14
14.1
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
8
FUNCTIONAL DESCRIPTION
8.1
ISO7816 UART AND ASSOCIATED LOGIC
Interface control
Control registers
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
General registers
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
ISO UART REGISTERS
CARDS REGISTERS
Registers summary
SUPPLY
Power switch control
3.3 V regulator
DC-to-DC converter
Supply supervisor
ISO7816 SECURITY
Introduction
Protections and limitations
Activation sequence
Deactivation sequence
MICROCONTROLLER
Low power modes
14.2
14.3
14.4
14.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
15
16
17
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
8.4.1
2003 Jul 04
2
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
1
FEATURES
• 83C51 core with 16 kbytes EPROM (ROM); 256 bytes
RAM; 512 bytes AUXRAM; Timer 0,1, 2 and enhanced
UART
• Full speed USB interface device which complies with
USB 1.1 specification; accessible with MOVX
instructions
• Control input and output; 1 generic input and output and
2 generic input end-points
• Current limitations on cards contacts and emergency
deactivation in case of over consumption or overheating
• Compatible with bus powered and suspend mode
supply current requirements
• Special circuitry for killing spikes during power-on or
power-off
• Specific ISO7816 UART; accessible with MOVX
instructions for automatic convention processing;
variable baud rate through frequency or division ratio
programming; error management at character level for
T = 0 protocol; extra guard time register
• Supply supervisor for power-on or power-off reset
• High efficiency inductive DC-to-DC converter for VCC
generation
• VCC generation (5 or 3 V maximum current 55 mA or
1.8 V maximum current 35 mA) with controlled
rise and fall times; current limitation and overload
detection at 100 mA
• Soft switch on for avoiding current inrush at plug in
• Enhanced ESD protections on cards contacts (6 kV
minimum)
• Software library for easy integration within the
application.
• Cards clock generation with three times synchronous
frequency doubling (12, 6, 3 and 1.5 MHz)
• Cards clock STOP HIGH or LOW or 1.25 MHz (from an
integrated oscillator) for cards power reduction mode
2
APPLICATIONS
• Automatic activation and deactivation sequences
• Smart card readers for PC’s or Set Top Boxes.
through an independent sequencer
• Supports the asynchronous protocols T = 0 and T = 1 in
accordance with ISO7816 and EMV
3
GENERAL DESCRIPTION
The TDA8030; TDA8031 is a bus powered full-speed USB
device. All analog and digital functions for an EMV
compliant Smart Card Reader are built-in. The embedded
83C51 microcontroller has 16 kbytes EPROM (ROM for
TDA8031), 256 bytes RAM and 512 bytes of AUXRAM.
• Versatile 24-bit time-out counter for Answer To Reset
(ATR) and waiting times processing
• Supports synchronous cards
• Specific Elementary Time Unit (ETU) counter for Block
Guard Time (BGT)
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA8030HL
TDA8031HL
LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
2003 Jul 04
3
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
5
QUICK REFERENCE DATA
SYMBOL
VDDU
IDDU
PARAMETER
CONDITIONS
MIN.
4.2
TYP.
MAX.
5.5
UNIT
bus supply voltage
bus supply current
−
−
V
VCC = 5 V; ICC = 40 mA;
fclk = 6 MHz
−
100
mA
Isus
suspend current
card inactive; microcontroller in
Power-down mode
−
−
500
µA
VCC
card supply voltage
including static load; 5 V card
with dynamic loads on 200 nF
including static loads; 3 V card
with dynamic loads on 200 nF
including static loads; 1.8 V card
with dynamic loads on 200 nF
5 V card
4.75
4.60
2.85
2.75
1.64
1.62
−
5
−
3
−
5.25
5.40
3.15
3.25
1.96
1.98
−55
−55
−35
100
100
+85
V
V
V
V
1.8
−
V
V
ICC
card supply current
−
mA
mA
mA
mA
mA
°C
3 V card
−
−
1.8 V card
−
−
Ilim
current limit on VCC
−
−
Iod
overload detection on VCC
ambient temperature
−
−
Tamb
−25
−
2003 Jul 04
4
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
6
BLOCK DIAGRAM
V
DD
6.8 µH
CDELAY
31
LX
24
7
RESET
SUPPLY
SUPERVISOR
V
23
UP
STEP-UP
CONVERTER
1 µF
25 STGND
54
52
53
EA/V
TIME-OUT
COUNTER
PP
8xC51
MICROCONTROLLER
PSEN
ALE/PROG
20
16 kbytes EPROM
256 bytes RAM
TIMER 0, 1, 2
V
CC
21
ISO7816
UART
63, 64,
1 to 6
RST
CGND
CLK
I/O
18
19
13
17
15
16
ANALOG
DRIVERS
AND
P10 to P17
P30 to P37
32 to 39
CLOCK
CIRCUITRY
SEQUENCER
ENHANCED UART
C4
C8
PRES
P32/INT0
P33/INT1
44 to 51
TDA8030
P20 to P27
62 to 55
P00 to P07
CPROG
ALE
P36/WR
P37/RD
12
42
INTERFACE
CONTROL
3.3 V
LDO
V
DDD
CDEC
1 µF
43
27
512 bytes
AUXRAM
DGND
22
V
DDU
TEST
POWER
SWITCH
CONTROL
28
26
UGND
41
40
V
PLL
XTAL1
XTAL2
XTAL
OSCILLATOR
DD
10 µF
29
30
10
+
D
INTERNAL
OSCILLATOR
USB
ATX
USB
INTERFACE
D−
DELATT
8
9
11
14
MGU881
RFU RFU RFU RFU
Fig.1 Block diagram (TDA8030).
5
2003 Jul 04
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
V
DD
6.8 µH
CDELAY
31
LX
24
7
RESET
SUPPLY
SUPERVISOR
V
23
UP
STEP-UP
CONVERTER
1 µF
25 STGND
54
EA
TIME-OUT
COUNTER
8xC51
MICROCONTROLLER
52
53
PSEN
ALE
20
16 kbytes EPROM
256 bytes RAM
TIMER 0, 1, 2
V
CC
21
ISO7816
UART
63, 64,
1 to 6
RST
CGND
CLK
I/O
18
19
13
17
15
16
ANALOG
DRIVERS
AND
P10 to P17
P30 to P37
32 to 39
CLOCK
CIRCUITRY
SEQUENCER
ENHANCED UART
C4
C8
PRES
P32/INT0
P33/INT1
44 to 51
TDA8031
P20 to P27
P00 to P07
62 to 55
ALE
P36/WR
P37/RD
42
V
DDD
INTERFACE
CONTROL
CDEC
1 µF
3.3 V
LDO
43
27
DGND
512 bytes
AUXRAM
22
V
DDU
TEST
POWER
SWITCH
CONTROL
28
26
UGND
41
40
V
PLL
XTAL1
XTAL2
XTAL
OSCILLATOR
DD
10 µF
29
30
10
+
D
INTERNAL
OSCILLATOR
USB
ATX
USB
INTERFACE
D−
DELATT
12
8, 11
2
9, 14
2
MGU882
SCANEN
RFU
RFU
Fig.2 Block diagram (TDA8031).
6
2003 Jul 04
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
7
PINNING
TDA8030
7.1
SYMBOL
P12
PIN
DESCRIPTION
1
2
8xC51 general purpose I/O port (USB_MC_READY)
8xC51 general purpose I/O port (USB_CLK_EN_N)
8xC51 general purpose I/O port (USB_RESET_N)
P13
P14
3
P15
4
8xC51 general purpose I/O port (USB_SOFTCONNECT_EXT)
8xC51 general purpose I/O port (available for the application)
8xC51 general purpose I/O port (available for the application)
P16
5
P17
6
RESET
RFU
RFU
DELATT
7
reset input (active HIGH, integrated pull-down resistor to ground)
test pin; leave open-circuit in the application
8
9
test pin; leave open-circuit in the application
10
delayed attachment reference signal output for external pull-up resistor on pin D+ (an internal
1.5 kΩ pull-up resistor is already embedded on-chip)
RFU
11
12
test pin; leave open-circuit in the application
CPROG
connect to GND within the application; for programming the EPROM connect to VDD as well
as pin TEST (pin 22); also used for test purposes
I/O
13
14
15
16
17
18
19
20
data input/output from the card (C7); 14 kΩ integrated pull-up resistor connected to VCC
test pin; leave open-circuit in the application
RFU
C8
auxiliary I/O for C8 contact; 14 kΩ integrated pull-up resistor connected to VCC
card presence detection input (active HIGH; no need for external pull-up)
auxiliary I/O for C4 contact; 14 kΩ integrated pull-up resistor connected to VCC
cards ground (C5) Must be connected to GND
PRES
C4
CGND
CLK
VCC
clock output (C30)
card supply output voltage (ISO C1 contact); must be decoupled with two 100 nF low ESR
ceramic capacitors to CGND
RST
21
22
23
24
25
26
27
28
29
30
31
cards reset output (C2)
TEST
VUP
test pin input
output of the DC-to-DC converter (decouple with a 1 µF capacitor to STGND)
LX
DC-to-DC converter inductor connection (a Schottky diode should be tied to VUP
DC-to-DC converter ground connection
soft switched positive supply voltage (decouple with 10 µF capacitor to GND)
positive supply voltage for the bus (4.2 to 5.5 V)
bus ground
)
STGND
VDD
VDDU
UGND
D+
USB D+ data line
D−
USB D− data line
CDELAY
connection for an external capacitor to ground determining the Power-on reset pulse width
(typ 1 ms per 2 nF)
P30/RxD
P31/TxD
P32/INT0
P33/INT1
32
33
34
35
8xC51 general purpose I/O port/serial input port (available for the application)
8xC51 general purpose I/O port/serial output port (available for the application)
8xC51 general purpose I/O port/external interrupt 0 (used by the ISO UART))
8xC51 general purpose I/O port/external interrupt 1 (used by the USB interface)
2003 Jul 04
7
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
P34
PIN
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DESCRIPTION
8xC51 general purpose I/O port (USB_SUSPEND in TDA8030)
8xC51 general purpose I/O port (USB_WAKEUP_N in TDA8031)
external data memory write strobe
P35
P36/WR
P37/RD
XTAL2
external data memory read strobe
12 MHz crystal output; leave open-circuit if an external clock is used
external 12 MHz crystal connection or input for an external clock signal
3.3 V regulated digital supply voltage output (decouple with 1 µF ceramic capacitor)
Digital ground
XTAL1
VDDD
DGND
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
PSEN
8xC51 general purpose I/O port/address 8 (available for the application)
8xC51 general purpose I/O port/address 9 (available for the application)
8xC51 general purpose I/O port/address 10 (available for the application)
8xC51 general purpose I/O port/address 11 (available for the application)
8xC51 general purpose I/O port/address 12 (available for the application)
8xC51 general purpose I/O port/address 13 (USB_MP_C)
8xC51 general purpose I/O port/address 14 (USB_MP_SEL)
8xC51 general purpose I/O port/address 15 (ISO_UART_CS)
Program Store Enable: read strobe to external program memory when executing code from
the external program memory; PSEN is activated twice each machine cycle except when two
PSEN activations are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
ALE/PROG
53
54
Address Latch Enable/Program Pulse: output pulse for latching the low byte of the address
during an access to external memory. In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency and can be used for external timing or clocking. It should be noted
that one ALE pulse is skipped during each access to external data memory. This pin is also
the program pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR Auxiliary0. With this bit set ALE will be active only during a MOVX instruction.
EA/VPP
External Access Enable/Programming Supply Voltage: EA must be externally held LOW to
enable the device to fetch code from external program memory locations starting with 0000H.
If EA is held HIGH the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (16 kbytes boundary). This pin also receives
the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit 1
is programmed EA will be internally latched on reset.
P07/AD7
P06/AD6
P05/AD5
P04/AD4
P03/AD3
P02/AD2
P01/AD1
P00/AD0
P10
55
56
57
58
59
60
61
62
63
64
8xC51 general purpose I/O port/address/data 7
8xC51 general purpose I/O port/address/data 6
8xC51 general purpose I/O port/address/data 5
8xC51 general purpose I/O port/address/data 4
8xC51 general purpose I/O port/address/data 3
8xC51 general purpose I/O port/address/data 2
8xC51 general purpose I/O port/address/data 1
8xC51 general purpose I/O port/address/data 0
8xC51 general purpose I/O port (USB_INT_MASK)
8xC51 general purpose I/O port (USB_SOFTCONNECT_INT)
P11
2003 Jul 04
8
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
P12
P13
1
2
3
4
5
6
7
8
9
48 P24/A12
P23/A11
47
P14
46 P22/A10
45 P21/A9
P15
P16
P20/A8
44
P17
43 DGND
RESET
RFU
RFU
42
41
V
DDD
XTAL1
TDA8030
40 XTAL2
39 P37/RD
38 P36/WR
37 P35
DELATT 10
RFU 11
CPROG 12
I/O 13
36 P34
RFU 14
C8 15
P33/INT1
35
34 P32/INT0
33 P31/TxD
PRES 16
MGU883
Fig.3 Pin configuration (top view).
2003 Jul 04
9
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
7.2
TDA8031
SYMBOL
P12
PIN
DESCRIPTION
1
2
8xC51 general purpose I/O port (USB_MC_READY)
8xC51 general purpose I/O port (USB_CLK_EN_N)
8xC51 general purpose I/O port (USB_RESET_N)
P13
P14
P15
P16
P17
3
4
8xC51 general purpose I/O port (USB_SOFTCONNECT_EXT)
8xC51 general purpose I/O port (available for the application)
8xC51 general purpose I/O port (available for the application)
5
6
RESET
RFU
7
reset input (active HIGH, integrated pull-down resistor to ground)
test pin; leave open-circuit in the application
8
RFU
9
test pin; leave open-circuit in the application
DELATT
10
delayed attachment reference signal output for external pull-up resistor on pin D+ (an internal
1.5 kΩ pull-up resistor is already embedded in the chip)
RFU
11
12
test pin; leave open-circuit in the application
SCANEN
connect to GND within the application; for programming the EPROM connect to VDD as well
as pin TEST (pin 22); also used for test purposes
I/O
13
14
15
16
17
18
19
20
data input/output from the card (C7); 14 kΩ integrated pull-up resistor connected to VCC
test pin; leave open-circuit in the application
RFU
C8
auxiliary I/O for C8 contact; 14 kΩ integrated pull-up resistor connected to VCC
card presence detection input (active HIGH; no need for external pull-up)
auxiliary I/O for C4 contact; 14 kΩ integrated pull-up resistor connected to VCC
cards ground (C5) Must be connected to GND
PRES
C4
CGND
CLK
VCC
clock output (C30)
card supply output voltage (ISO C1 contact); must be decoupled with two 100 nF low ESR
ceramic capacitors to CGND
RST
21
22
23
24
25
26
27
28
29
30
31
cards reset output (C2)
TEST
VUP
test pin input
output of the DC-to-DC converter (decouple with a 1 µF capacitor to STGND)
LX
DC-to-DC converter inductor connection (a Schottky diode should be tied to VUP
DC-to-DC converter ground connection
soft switched positive supply voltage (decouple with 10 µF capacitor to GND)
positive supply voltage for the bus (4.2 to 5.5 V)
bus ground
)
STGND
VDD
VDDU
UGND
D+
USB D+ data line
D−
USB D− data line
CDELAY
connection for an external capacitor to ground determining the Power-on reset pulse width
(typ 1 ms per 2 nF)
P30/RxD
P31/TxD
P32/INT0
P33/INT1
P34
32
33
34
35
36
8xC51 general purpose I/O port/serial input port (available for the application)
8xC51 general purpose I/O port/serial output port (available for the application)
8xC51 general purpose I/O port/external interrupt 0 (used by the ISO UART))
8xC51 general purpose I/O port/external interrupt 1 (used by the USB interface)
8xC51 general purpose I/O port (USB_SUSPEND in TDA8030)
2003 Jul 04
10
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
P35
PIN
DESCRIPTION
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
8xC51 general purpose I/O port (USB_WAKEUP_N in TDA8030)
external data memory write strobe
P36/WR
P37/RD
XTAL2
external data memory read strobe
12 MHz crystal output; leave open-circuit if an external clock is used
external 12 MHz crystal connection or input for an external clock signal
3.3 V regulated digital supply voltage output (decouple with 1 µF ceramic capacitor)
Digital ground
XTAL1
VDDD
DGND
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
PSEN
8xC51 general purpose I/O port/address 8 (available for the application)
8xC51 general purpose I/O port/address 9 (available for the application)
8xC51 general purpose I/O port/address 10 (available for the application)
8xC51 general purpose I/O port/address 11 (available for the application)
8xC51 general purpose I/O port/address 12 (available for the application)
8xC51 general purpose I/O port/address 13 (USB_MP_C)
8xC51 general purpose I/O port/address 14 (USB_MP_SEL)
8xC51 general purpose I/O port/address 15 (ISO_UART_CS)
Program Store Enable: read strobe to external program memory when executing code from
the external program memory; PSEN is activated twice each machine cycle except when two
PSEN activations are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
ALE
EA
53
54
Address Latch Enable/Program Pulse: output pulse for latching the low byte of the address
during an access to external memory. In normal operation ALE is emitted at a constant rate of
1/6 the oscillator frequency and can be used for external timing or clocking. It should be noted
that one ALE pulse is skipped during each access to external data memory. This pin is also
the program pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR Auxiliary0. With this bit set ALE will be active only during a MOVX instruction.
External Access Enable/Programming Supply Voltage: EA must be externally held LOW to
enable the device to fetch code from external program memory locations starting with 0000H.
If EA is held HIGH the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (16 kbytes boundary). This pin also receives
the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit 1
is programmed EA will be internally latched on reset.
P07/AD7
P06/AD6
P05/AD5
P04/AD4
P03/AD3
P02/AD2
P01/AD1
P00/AD0
P10
55
56
57
58
59
60
61
62
63
64
8xC51 general purpose I/O port/address/data 7
8xC51 general purpose I/O port/address/data 6
8xC51 general purpose I/O port/address/data 5
8xC51 general purpose I/O port/address/data 4
8xC51 general purpose I/O port/address/data 3
8xC51 general purpose I/O port/address/data 2
8xC51 general purpose I/O port/address/data 1
8xC51 general purpose I/O port/address/data 0
8xC51 general purpose I/O port (USB_INT_MASK)
8xC51 general purpose I/O port (USB_SOFTCONNECT_INT)
P11
2003 Jul 04
11
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
P12
P13
1
2
3
4
5
6
7
8
9
48 P24/A12
P23/A11
47
P14
46 P22/A10
45 P21/A9
P15
P16
P20/A8
44
P17
43 DGND
RESET
RFU
RFU
42
41
V
DDD
XTAL1
TDA8031
40 XTAL2
39 P37/RD
38 P36/WR
37 P35
DELATT 10
RFU 11
SCANEN 12
I/O 13
36 P34
RFU 14
P33/INT1
35
C8 15
34 P32/INT0
33 P31/TxD
PRES 16
MGU884
Fig.4 Pin configuration (top view).
2003 Jul 04
12
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8
FUNCTIONAL DESCRIPTION
The registers within the ISO7816 UART may be written to
or read from by using the standard 83C51 MOVX
instructions. It should be noted, that only if pin P27/A15 is
HIGH, can the UART be accessed.
Throughout this specification, it is assumed that the reader
is aware of ISO7816 and USB norms terminology.
8.1
ISO7816 UART AND ASSOCIATED LOGIC
When pin P27/A15 is HIGH, the demultiplexing of address
and data is done internally by means of the ALE signal.
A LOW pulse on pin P37/RD enables the selected register
to be read, a LOW pulse on pin P36/WR enables the
selected register to be written to.
This section describes how the integrated ISO7816 UART
operates, how it can be programmed by means of its
control registers and how it is internally interfaced to the
embedded microcontroller.
The ISO UART interrupt line is directly connected to the
microcontrollers External Interrupt 0 input, pin P32/INT0.
For that reason, the External Interrupt 0 of the 83C51
microcontroller must be enabled to ensure a proper
function.
8.1.1
INTERFACE CONTROL
The ISO7816 UART can be controlled via an 8-bit parallel
bus. This bus is directly (internally) connected to Port 0
(P07 to P00) of the embedded 83C51 microcontroller.
ALE
CS
address
data read
address
data write
D0 to D7
RD
WR
MGU885
Fig.5 Control via MOVX instructions.
2003 Jul 04
13
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.2
CONTROL REGISTERS
The Hardware Status Register (HSR) gives the status of
the supply voltage, of the hardware protections and of the
card movements.
The TDA8030; TDA8031 has 1 analog interface for
7 contacts cards. The data to and from the cards is fed into
an ISO UART.
The USR and HSR give interrupts on pins INT when some
of their bits have been changed.
The Card Select Register (CSR) contains one bit for
resetting the ISO UART (RIU, active LOW). This bit is reset
after power-on and must be set HIGH before starting any
operation. It may be reset by software when necessary.
The MSR does not give interrupts and may be used in the
polling mode for some operations; when this is the case,
the bit Transmit Buffer Empty/Receive Buffer Full
(TBE/RBF) within the USR may be masked.
The following dedicated registers enable the parameters
of the ISO UART and the ETU counters to be set:
A 24-bit time-out counter may be started to provide an
interrupt after a number of ETUs programmed in time-out
registers TOR1, TOR2 and TOR3. This will help the
microcontroller when processing different real-time tasks
(ATR, WWT and BWT etc.), mainly if the microcontrollers
and cards clock are asynchronous.
• Programmable Divider Register (PDR)
• Guard Time Register (GTR)
• Two UART Control Registers (UCR1 and UCR2)
• Clock Configuration Register (CCR)
• Time-Out Configuration Register (TOCR)
• Three Time-Out Registers (TOR1, TOR2 and TOR3).
This counter is configured with a Time-Out Counter
Configuration register (TOCC) and may be used as a
24-bit or as a 16 + 8-bit counter. Each counter may be set
to start counting once data has been written, or on
detection of a start bit on the I/O or as autoreload.
There is also a dedicated Power Control Register (PCR)
for controlling the power to the card.
When the specific parameters of the card have been
programmed, the UART may be used with the following
registers:
8.1.3
GENERAL REGISTERS
8.1.3.1
Card select register
• UART Receive Register (URR)
• UART Transmit Register (UTR)
• UART Status Register (USR)
• Mixed Status Register (MSR).
The Card Select Register (CSR) is used for resetting the
ISO UART.
The bit Reset ISO UART (RIU) must be set to logic 1 by
software before any action on the UART. When set to
logic 0, this bit resets a large part of the UART registers to
their default value; see Table 1. A minimum pulse of 10 ns
is needed on RIU. This bit must be reset before any new
activation.
In the reception mode, a FIFO of 1 to 8 characters may be
used and is configured with the FIFO Control Register
(FCR). This register may also be used for programming an
automatic repetition of NAKed characters in the
transmission mode.
Table 1 Card select register (address 00H; write and read); note 1
7
6
5
4
3
2
1
0
−
−
−
−
RIU
−
−
−
Note
1. All bits are cleared after reset.
2003 Jul 04
14
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.3.2
Hardware status register
The Hardware Status Register (HSR) gives the status of the chip after a hardware problem has been detected.
Table 2 Hardware Status Register (address 0FH; read only); note 1
7
6
5
4
3
2
1
0
−
−
PRTL
SUPL
−
PRL
−
PTL
Note
1. All bits are cleared after reset.
Table 3 Description of the HSR bits
BIT
SYMBOL
DESCRIPTION
7 and 6
5
−
not used
PRTL
Protection 1: Bit PRTL = 1 when a default has been detected on card reader. Bit PRTL
is the OR function of the protection on pins VCC and RST.
4
3
2
1
0
SUPL
−
Supervisor Latch: Bit SUPL = 1 when the supervisor has been activated.
not used
PRL
−
Presence Latch: Bit PRL = 1 when a change has occurred on pin PRES.
not used
PTL
Overheating: Bit PTL = 1 if overheating has occurred.
When either bits PRTL, PRL or PTL is logic 1, then pin INT0 is LOW. The bits having caused the interrupt are cleared
when the HSR has been readout (2 × fint cycles after the rising edge of RD).
At power-on, or after a supply voltage drop-out, SUPL is set and INT0 is LOW. INT0 will return HIGH at the end of the
internal Power-on reset pulse defined by the value of the capacitor connected to pin CDELAY. SUPL will be reset only
after a status register readout outside the Power-on reset pulse; see Fig.8.
In the event of emergency deactivation (by PRTL, SUPL, PRL and PTL), bit START will be automatically reset by
hardware.
8.1.3.3
Time-out registers
The three Time-Out Registers TOR1, TOR2 and TOR3 form a programmable 24-bit ETU counter, or two independant
counters (one 16-bit and one 8-bit).
The value to load in TOR1, TOR2 and TOR3 is the number of ETUs to count.
Table 4 Time-out register 1 (address 09H; write only); note 1
7
6
5
4
3
2
1
0
TOL7
TOL6
TOL5
TOL4
TOL3
TOL2
TOL1
TOL0
Note
1. All bits are cleared after reset.
2003 Jul 04
15
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 5 Time-out register 2 (address 0AH; write only); note 1
7
6
5
4
3
2
1
0
TOL15
TOL14
TOL13
TOL12
TOL11
TOL10
TOL9
TOL8
Note
1. All bits are cleared after reset.
Table 6 Time-out register 3 (address 0BH; write only); note 1
7
6
5
4
3
2
1
0
TOL23
TOL22
TOL21
TOL20
TOL19
TOL18
TOL17
TOL16
Note
1. All bits are cleared after reset.
8.1.3.4
Time-out configuration register
The Time-Out Configuration register (TOCR) is used for setting different configurations of the time-out counter according
to Table 8; all other configurations are undefined.
The timers can operate in 3 modes:
1. Software triggered
2. Start bit triggered
3. Autoreload.
Table 7 Time-out configuration register (address 08H; read and write); note 1
7
6
5
4
3
2
1
0
TOC7
TOC6
TOC5
TOC4
TOC3
TOC2
TOC1
TOC0
Note
1. All bits are cleared after reset.
2003 Jul 04
16
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 8 Time-out counter configuration
TOC VALUE
OPERATING MODE
00H
05H
61H
All counters are stopped.
Counters 2 and 3 are stopped; counter 1 continues to operate in autoreload mode.
Counter 1 is stopped and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3
and TOR2 is started after 6H is written in the TOCR. An interrupt is given and bit TO3 is set within the
USR when the terminal count is reached. The counter is stopped by writing 00H in the TOCR and will
be stopped before reloading a new value in TOR2 and TOR3.
65H
Counter 1 is an 8-bit autoreload counter and counters 3 and 2 form a 16-bit counter. Counter 1 starts
counting the content of TOR1 on the first START bit (reception or transmission) detected on I/O after
65H is written in the TOCR. When Counter 1 reaches its terminal count, an interrupt is given, bit TO1 in
the USR is set and the counter automatically restarts the same count until it is stopped. It is not allowed
to change the content of TOR1 during a count. Counters 3 and 2 are wired as a single 16-bit counter
and starts counting the value TOR3 and TOR2 when 65H is written in the TOCR. When the counter
reaches its terminal count, an interrupt is given and bit TO3 is set within the USR. Both counters are
stopped when 00H is written in the TOCR. Counters 3 and 2 will be stopped by writing 05H in the
TOCR before reloading a new value in TOR2 and TOR3.
68H
7CH
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3,
TOR2 and TOR1 is started after 68H is written in the TOCR. The counter is stopped by writing 00H in
the TOCR. It is not allowed to change the content of TOR3, TOR2 and TOR1 within a count.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3,
TOR2 and TOR1 on the first start bit detected on I/O (reception or transmission) after the value has
been written. It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current
count will not be affected and the new count value will be taken into account at the next start bit. The
counter is stopped by writing 00H in the TOCR. In this configuration TOR3, TOR2 and TOR1 must not
be all zero.
85H
E5H
Same as 05H, except that all the counters will be stopped at the end of the 12th ETU following the first
received start bit detected after 85H has been written in the TOCR.
Same configuration as TOCR = 65H, except that Counter 1 will be stopped at the end of the 12th ETU
following the first start bit detected after E5H has been written in the TOCR.
The time-out counter is very useful for processing the clock
counting during ATR, the Work Waiting Time (WWT) or the
waiting times defined in T = 1 protocol. The 200 and
384 clock counter used during ATR is done by hardware
when Start Session is set, a specific hardware takes care
of BGT in T = 1 protocol and a specific register is present
for processing the extra guard time.
The minimum time interval between 2 successive write
operations in TOCR is 2⁄31 or 2⁄32 ETU.
It is obvious that the counters may only be used once the
card has been activated.
Detailed examples of how to use these specific timers can
be found in Application Note “AN01012”.
It is not allowed to change the content of the TOR registers
whilst a counter is in software triggered mode, or in
autoreload mode. In these modes, it is mandatory to stop
the counters (TOCR = 00H or 05H) before updating the
count value in the TOR registers. In start bit triggered
mode, the value may be changed at any time; the new
count value will be taken into account on the next start bit.
2003 Jul 04
17
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.4
ISO UART REGISTERS
UART transmit register
• Does not start if the transmission of the previous
character is not completed.
8.1.4.1
When the transmission is completed:
When the microcontroller wants to transmit a character to
the card, it writes the data in direct convention in this
register.
• In T = 0, bit TBE is set at 11.5 ETU, and bit PE in the
event of parity error
• In T = 1, bit TBE is set at 10.5 ETU.
The transmission:
In the event of synchronous cards (bit SAN set within
UCR2), UT0 is only relevant and is copied on the I/O of the
card. It is possible to write within the UTR before setting
the transmission mode, which may be useful in some
cases.
• Starts at the end of this writing (2 clock cycles after the
rising edge of WR) if the previous character has been
transmitted and if the extra guard time has expired
• Starts at the end of the extra guard time if this one has
not expired
• Starts at 13.5 ETU in manual mode and 15 ETU in
automatic mode if the previous character has been
NAKed by the card; see Section 8.1.4.4
Table 9 UART transmit register (address 0DH; write only); note 1
7
6
5
4
3
2
1
0
UT7
UT6
UT5
UT4
UT3
UT2
UT1
UT0
Note
1. All bits are cleared after reset.
8.1.4.2
UART receive register
In both protocols, when a character has been stored, then
the bit RBF in the status register USR is set at 10.5 ETU.
This bit is reset when the character has been read from the
URR.
When the microcontroller wants to read data from the card,
it reads it from this register in direct convention.
In the event of synchronous cards, only UR0 is relevant
and is a copy of the state of the card I/O.
When the URR is empty, then bit FE (in the MSR) is set as
long as no character has been received.
In the event of parity error:
• The bit PE in the status register USR is set at 10.5 ETU
and INT0 falls LOW
• In protocol T = 0, the received byte is not stored in URR;
In protocol T = 1, the received byte is stored.
Table 10 UART receive register (address 0DH; read only); note 1
7
6
5
4
3
2
1
0
UR7
UR6
UR5
UR4
UR3
UR2
UR1
UR0
Note
1. All bits are cleared after reset.
2003 Jul 04
18
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.4.3
Mixed status register
The Mixed Status Register (MSR) relates the status of the cards presence contact PRES, the BGT counter, the FIFO
empty indication, the transmit/receive ready indicator TBE/RBF and the completion of clock switching to or from 1⁄2fint.
Table 11 Mixed status register (address 0CH; read only); note 1
7
6
5
4
3
2
1
0
CLKSW
FE
BGT
−
−
PR
−
TBE/RBF
Note
1. Bits TBE/RBF are cleared after reset; bit FE is set after reset.
Table 12 Description of the MSR bits; note 1
BIT
SYMBOL
DESCRIPTION
7
CLKSW
Clock switch: Bit CLKSW = 1 when the TDA8030; TDA8031 has performed a required
clock switch from 1⁄nfxtal to 1⁄2fint and is reset when the TDA8030; TDA8031 has
performed a required clock switch from 1⁄2fint to 1⁄nfxtal; the application will wait until this
bit has been set or reset before setting the microcontroller in power-down mode or
restarting sending commands after leaving power-down mode (only needed when the
clock is not stopped). This bit is also reset by RIU and at power-on.
6
5
FE
FIFO Empty: Bit FE = 1 when the reception FIFO is empty; it is reset when at least one
character has been loaded in the FIFO.
BGT
Block Guard Time: In T = 1 protocol, the bit BGT is linked with a 22 ETU counter, which
is started at every start bit on the I/O. If the count is finished before the next start bit,
then bit BGT is set. This helps to ensure that the card has not answered before 22 ETU
after the last transmitted character, or that the reader is not transmitting a character
before 22 ETU after the last received character.
In T = 0 protocol, the bit BGT is linked to a 16 ETU counter, which is started at every
start bit on the I/O. If the count is finished before the next start bit, then the bit BGT is
set. This helps to ensure that the reader is not transmitting too early after the last
received character.
4 and 3
not used
2
1
0
PR
−
Presence: Bit PR = 1 when the card is present.
not used
TBE/RBF
Transmit Buffer Empty/Receive Buffer Full: Bit TBE/RBF = 1 when:
• Changing from reception mode to transmission mode
• A character has been transmitted by the UART (except when a character has been
transmitted free of parity error while LCT = 1)
• The reception buffer is full.
Bit TBE/RBF = 0 after power-on, or after one of the following:
• When the bit RIU is reset
• When a character has been written into register UTR
• When the character has been read in register URR
• When changing from transmission mode to reception mode.
Note
1. No bits within the MSR have an effect on INT0.
2003 Jul 04
19
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.4.4
FIFO control register
The FIFO Control Register (FCR) relates the parity error count and the FIFO length.
Table 13 FIFO control register (address 0CH; write only); note 1
7
6
5
4
3
2
1
0
−
PEC2
PEC1
PEC0
−
FL2
FL1
FL0
Note
1. All bits are cleared after reset.
Table 14 Description of the FCR bits
BIT
SYMBOL
DESCRIPTION
7
−
not used
6 to 4
PEC2 to
PEC0
Parity Error Count: PEC2, PEC1 and PEC0 determine the number of parity errors
before setting the bit PE within the USR and pulling INT0 LOW; 000 means that only
one parity error has occurred and bit PE is set.
The value 000 indicates that if only one parity error has occurred bit PE is set; the value
111 indicates that PE will be set after 8 parity errors.
In protocol T = 0:
• If a correct character is received before the programmed error number is reached the
error counter will be reset
• If the programmed number of allowed parity errors is reached, bit PE in the USR will
be set as long as the USR has not been read
• If a transmitted character has NAKed by the card, then the TDA8030; TDA8031 will
automatically re-transmit it a number of times equal to the value programmed in PEC2,
PEC1 and PEC0. The character will be resent at 15 ETU
• In transmission mode, if bits PEC2, PEC1 and PEC0 are at logic 0, then the automatic
re-transmission is invalidated; the character manually rewritten in the UTR will start at
13.5 ETU.
In protocol T = 1:
• The error counter has no action; bit PE is set at the first incorrectly received character.
3
−
not used
2 to 0
FL2 to FL0 FIFO Length: Bits FL2, FL1 and FL0 determine the depth of the FIFO:
• 000 = length 1
• 111 = length 8
2003 Jul 04
20
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.4.5
UART status register
The UART Status Register (USR) is used by the microcontroller to monitor the activity of the ISO UART and of the
time-out counter.
Table 15 UART status register (address 0EH; read only); note 1
7
6
5
4
3
2
1
0
TO3
−
TO1
EA
PE
OVR
FER
TBE/RBF
Note
1. All bits are cleared after reset.
Table 16 Description of the USR bits
BIT
SYMBOL
DESCRIPTION
7
TO3
Time-Out counter 3: Bit TO3 = 1 when counter 3, or counters 3 + 2 or counters
3 + 2 + 1 have reached their terminal count.
6
5
4
−
not used
TO1
EA
Time-Out counter 1: Bit TO1 = 1 when counter 1 has reached its terminal count.
Early Answer: When bit RST is LOW, EA is HIGH if the first start bit on the I/O during
ATR has been detected between 200 and 384 clock pulses (all activities on the I/O
during the first 200 clock pulses with RST LOW are not taken into account). When RST
is HIGH, EA is HIGH if a start bit has been detected before the 384th clock pulse. These
two features are reinitialized at each toggling of RST.
3
PE
Parity Error: In T = 0 protocol, PE = 1 if the UART has detected a number of received
characters with parity error equal to the number written in PEC2, PEC1 and PEC0 or if a
transmitted character has been NAKed by the card a number of times equal to the value
programmed in PEC2, 1 and 0. It is set at 10.5 ETU in reception mode and at 11.5 ETU
in transmission mode.
In T = 0 protocol, a character received with a parity error is not stored in the FIFO, the
card is supposed to repeat this character. In T = 1 protocol, a character with a parity
error is stored in the FIFO and the parity error counter is not operating.
2
1
0
OVR
FER
Overrun: Bit OVR = 1 if the UART has received a new character while the URR was full.
In this case, at least one character has been lost. OVR is set at 10.5 ETU.
Framing Error: Bit FER = 1 when the I/O was not in high-impedance state at 10.25 ETU
after a start bit. It is reset when the USR has been read-out.
TBE/RBF
Transmission Buffer Empty/Reception Buffer Full: Bits TBE and RBF share the same bit
within the USR. When in transmission mode the relevant bit is TBE; when in reception
mode it is RBF.
Bit TBE = 1 when the UART is in transmission mode and when the microcontroller may
write the next character to transmit in the UTR. It is reset when the microcontroller has
written data in the Transmit Register, or when the bit T/R within UCR1 has been reset
either automatically or by software. TBE is set at 11.5 ETU in T = 0 protocol and at
10.5 ETU in T = 1 protocol.
Bit RBF = 1 when the FIFO is full. The microcontroller may read some of the characters
in the URR, which clears the bit RBF. Bit RBF is also reset when entering the reception
mode and is set at 10.5 ETU.
2003 Jul 04
21
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
If any of the status bits FER, OVR, PE, EA, TO1 or TO3
are set, then INT0 is LOW. The bit having caused the
interrupt is reset 2 × fint cycles after the rising edge of RD
during a read operation of the USR. If TBE/RBF is set and
if the mask bit DISTBE/RBF within UCR2 is not set, then
INT0 is also LOW. TBE/RBF is reset 2 clock cycles after
data has been written into the UTR, or 2 clock cycles after
data has been read from the URR, or when changing from
transmission mode to reception mode if the FIFO had not
been left full when going to transmission mode. If the Last
Character to Transmit (LCT) is used for transmitting the
last character, then TBE will not be set at the end of the
transmission.
8.1.5
CARDS REGISTERS
When working with a card, the following registers may be
used for programming some specific parameters:
8.1.5.1
Programmable divider register
The Programmable Divider Register (PDR) is used for
counting the cards clock cycles which form the ETU. It is
an autoreload 8-bit counter decounting from the
programmed value down to 0.
Table 17 Programmable divider register (address 02H; read and write); note 1
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Note
1. All bits are cleared after reset.
8.1.5.2
UART configuration register 2
Table 18 UART configuration register 2 (address 03H; read and write); note 1
27
26
25
24
23
22
21
20
ENINT1
DISTBE/
RBF
−
−
SAN
AUTOCONV
CKU
PSC
Note
1. All bits are cleared after reset.
2003 Jul 04
22
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 19 Description of the UCR2 bits
BIT
SYMBOL
DESCRIPTION
27
ENINT1
Enable Interrupt 1: If bit ENINT1 = 1, then a HIGH-to-LOW transition on INT1 will
wake-up the microcontroller from power-down mode. When not in power-down mode,
bit ENINT1 has no effect.
26
DISTBE/
RBF
Disable TBE/RBF interrupts: If bit DISTBE/RBF = 1, then reception or transmission of a
character will not generate an interrupt. This feature is useful for increasing
communication speed with the card; in this case, the copy of TBE/RBF bit within the
MSR must be polled and not the original, in order not to loose priority interrupts which
can occur in the USR.
25
24
23
−
−
not used
not used
SAN
Synchronous/Asynchronous: Bit SAN is set by software if a synchronous card is
expected. Then, the UART is bypassed and only bit 0 in the URR and UTR is connected
to the I/O. In this case, the clock is controlled by bit SC in the CCR.
22
21
AUTOCONV Auto convention: If bit AUTOCONV = 1, then the convention is set by software with bit
CONV in the UART Configuration Register. If it is reset, then the configuration is
automatically detected on the first received character while the bit SS (Start Session) is
set.
CKU
Clock UART: Bit CKU is used to clock the UART at twice the clock frequency of the
card. An ETU will last 31 × PDR clock pulses if CKU = 0 and half if CKU = 1. It should
be noted that when CKU = 1 it has no effect if fCLK = fXTAL1. This means, for example,
that a baud rate of 76800 is not possible when the card is clocked with the frequency on
XTAL1.
20
PSC
Prescaler: If bit PSC = 1, then the prescaler value is 32. If PSC = 0, then the prescaler
value is 31. One ETU will last a number of cards clock cycles equal to PSC × PDR. All
baud rates specified in “ISO7816” norm are achievable with this configuration.
CLK
÷ 31 or 32
MUX
÷ PDR
ETU
PSC
2 × CLK
MGU886
CKU
Fig.6 ETU generation.
2003 Jul 04
23
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.5.3
Baud rate selection using F and D; card clock frequency fCLK = 3.58 MHz for PSC = 31 and 4.92 MHz for
PSC = 32 (31;12 means prescaler set to 31 and PDR set to 12)
F
D
0
1
2
3
4
5
6
9
10
11
12
13
1
2
3
4
5
6
8
9
31;12
9600
31;12
9600
31;18 31;24 31;36
31;48
2400
31;60
1920
32;16
9600
32;24
6400
32;32
4800
32;48
3200
32;64
2400
6400
4 800 3200
31;6
31;6
31;9
31;12 31;18
31;24
4800
31;30
3840
32;8
19200
32;12
12800 9600
32;16
32;24
6400
32;32
4800
19200 19200 12800 9600
31;3 31;3 31;6
38400 38400
6400
31;9
31;12
31;15
7680
32;4
38400
32;6 32;8
32;12
32;16
19200 12800 9600
25600 19200 12800 9600
32;3 32;4 32;6 32;8
51300 38400 25600 19200
32;2 32;3 32;4
76800 51300 38400
31;3
38400
31;6
19200
32;2
76800
31;3
38400
32;1
153600
32;1
153600
32;2
76800
31;1
115200 115200
31;1
31;2
31;3
31;4
31;5
32;2
76800
32;4
38400
57600 38400 28800 23040
31;3
38400
8.1.5.4
Guard time register
The Guard Time Register (GTR) is used for storing the number of guard ETUs given by the card during ATR.
In transmission mode, the UART will wait this number of ETU + 0.5 before transmitting the character stored in UTR.
In T = 1 protocol, GTR = FFH means operation at 11.5 ETU. In T = 0 protocol and GTR = FFH means operation at
12.5 ETU.
Table 20 Guard time register (address 05H; read and write); note 1
7
6
5
4
3
2
1
0
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
Note
1. All bits are cleared after reset.
8.1.5.5
UART configuration register 1
The UART Configuration Register 1 (UCR1) is used for setting the parameters of the ISO UART.
Table 21 UART configuration register 1 (address 06H; read and write); note 1
7
6
5
4
3
2
1
0
−
FIP
FC
PROT
T/R
LCT
SS
CONV
Note
1. All bits are cleared after reset.
2003 Jul 04
24
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 22 Description of the UCR1 bits
BIT
SYMBOL
DESCRIPTION
7
6
−
not used
FIP
Force Inverse Parity: If FIP = 1, then the UART will NAK a correct received character
and will transmit characters with wrong parity bit.
5
4
FC
Bit FC is a test bit and must be left at logic 0.
PROT
Protocol: Bit PROT = 1 if the protocol type is asynchronous T = 1. If PROT = 0, the
protocol is T = 0.
3
2
T/R
Transmit/Receive: Bit T/R is set by software for transmission mode. A change from
0 to 1 will set bit TBE in the USR. T/R is automatically reset by hardware if LCT has
been used before transmitting the last character.
LCT
Last Character to Transmit: Bit LCT is set by software before writing the last character
to transmit into the UTR. It allows automatic change to reception mode when reset by
hardware at the end of a successful transmission (11 + 28
10 + 28 31 or 28
⁄
31 or 28
⁄
32 ETU in T = 0 and
⁄
⁄
32
ETU in T = 1). When LCT is being reset, the bit T/R is also reset and
the UART is then ready for receiving a character.
1
0
SS
Start Session: Bit SS is set by software before ATR for automatic convention detection
and early answer detection. It is automatically reset by hardware at 10.5 ETU after
reception of the initial character.
CONV
Convention: Bit CONV = 1 if the convention is direct. CONV is either automatically
written to by hardware, according to the convention detected during ATR, or by software
if bit AUTOCONV is set.
8.1.5.6
Clock configuration register
The Clock Configuration Register (CCR) defines the clock to the card and the clock to the ISO UART. If bit CKU in the
Prescaler Register (UCR2) of the card is set, then the ISO UART is clocked at twice the frequency to the card, this allows
higher baud rates to be reached than foreseen in the ISO7816 norm.
Table 23 Clock configuration register (address 01H; read and write); note 1
7
6
5
4
3
2
1
0
−
−
SHL
CST
SC
AC2
AC1
AC0
Note
1. All bits are cleared after reset.
2003 Jul 04
25
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 24 Description of the CCR bits
BIT
SYMBOL
DESCRIPTION
7
6
5
−
−
not used
not used
SHL
Stop HIGH or LOW: If bit CST = 1, then the clock is stopped at LOW level if SHL = 0
and at HIGH level if SHL = 1. In these modes, the bias current in the card drivers is
reduced; the current drawn by the card (ICC) should be less than 10 mA at all VCC
voltages.
4
3
CST
SC
Clock stop: In case of asynchronous cards, bit CST defines whether the clock to the
card is stopped or not. If bit CST is reset, then the clock is determined by bits AC0,
AC1 and AC2; see Table 25. All frequency changes are synchronous, thus ensuring
that no spike or unwanted pulse widths occurs during changes.
Synchronous Clock: In the event of synchronous cards, the clock contact is a copy of
the value written in SC. In reception mode, the data from the card is available in bit UR0
after a read operation of the URR register. In transmission mode, bit UT0 is written on
the I/O line of the card when UTR register has been written.
2 to 0
AC2 to AC0 When switching from 1⁄nfxtal to 1⁄2fint or vice versa, only bit AC2 must be changed;
AC1 and AC0 must remain the same. When switching from 1⁄nfxtal or 1⁄2fint to CLK STOP
or vice versa, only bits CST and SHL must be changed.
When switching from 1⁄nfxtal to 1⁄2fint or vice versa, a maximum delay of 200 µs can occur
between the command and the effective frequency change on pin CLK. The fastest
switch is from 1⁄2fxtal to 1⁄2fint or vice versa, the best duty cycle is from 1⁄8fxtal to 1⁄2fint or
vice versa. The status bit CLKSW within the MSR gives the effective switch moment.
Table 25 CLK value for an asynchronous card
AC2
AC1
AC0
CLK(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fxtal
1⁄2fxtal
1⁄4fxtal
1⁄8fxtal
1⁄2fint
1⁄2fint
1⁄2fint
1⁄2fint
Note
1. If fCLK = fXTAL, the duty cycle must be ensured by the incoming clock signal on XTAL1.
2003 Jul 04
26
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.1.5.7
Power control register
The Power Control Register (PCR) performs two tasks:
1. Starts or stops card sessions
2. Reads from or writes to auxiliary card contacts C4 and C8.
Table 26 Power control register (address 07H; read and write); note 1
7
6
5
4
3
2
1
0
−
−
C8
C4
1.8V
RSTIN
3/5V
START
Note
1. All bits are cleared after reset.
Table 27 Description of the PCR bits
BIT
SYMBOL
DESCRIPTION
7
6
5
−
−
not used
not used
C8
Contact 8: When writing to the PCR bit C8 will output the value of bit C8. When reading
from the PCR, bit C8 will store the value on pin C8.
4
C4
Contact 4: When writing to the PCR bit C4 will output the value written of bit C4. When
reading from the PCR bit C4 will store the value on pin C4.
3
2
1
1.8V
RSTIN
3/5V
1.8 V cards: if bit 1.8V is set, then VCC = 1.8 V.
Reset bit: When the card is activated, pin RST is the copy of the value written in RSTIN.
3 or 5 V cards: If bit 3/5V is set to logic 1, then VCC is 3 V; If bit 3/5V is set to logic 0,
then VCC is 5 V.
0
START
Start: If the microcontroller sets bit START to logic 1, then the selected card is activated;
see Section 8.3.3. If the microcontroller resets START to logic 0, then the card is
deactivated; see Section 8.3.4. START is automatically reset in the event of emergency
deactivation.
For deactivating the card, only bit START should be reset.
2003 Jul 04
27
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8.1.6
REGISTERS SUMMARY
VALUE
WHEN
RIU = 0
VALUE AT
RESET
NAME
ADDR
R/W
7
6
5
4
3
2
1
0
CSR
CCR
PDR
UCR2
00H
01H
02H
03H
R/W
R/W
R/W
R/W
−
−
−
−
−
−
RIU
SC
−
−
−
XXXX0XXX
XX000000
00000000
00XX0000
XXXX0XXX
XX000000
00000000
00XX0000
SHL
PD5
−
CST
PD4
−
AC2
PD2
AC1
PD1
CKU
AC0
PD0
PSC
PD7
PD6
PD3
SAN
ENINT1 DISTBE/
RBF
AUTOCO
NV
GTR
UCR1
PCR
TOC
05H
06H
07H
08H
09H
0AH
0BH
0CH
0CH
0DH
0DH
0EH
0FH
R/W
R/W
R/W
R/W
W
GT7
−
GT6
FIP
GT5
FC
GT4
PROT
C4
GT3
T/R
GT2
LCT
GT1
SS
GT0
CONV
START
TOC0
TOL0
00000000
X0000000
XX110000
00000000
00000000
00000000
00000000
010XXXX0
X000X000
00000000
00000000
0X000000
XX01X0X0
00000000
X0000000
XX110000
00000000
00000000
00000000
00000000
010XXXX0
X000X000
00000000
00000000
00000000
XX01X0X0
−
−
C8
1.8 V
TOC3
TOL3
TOL11
TOL19
−
RSTIN
TOC2
TOL2
TOL10
TOL18
PR
3/5 V
TOC1
TOL1
TOL9
TOL17
−
TOC7
TOL7
TOL15
TOL23
CLKSW
−
TOC6
TOL6
TOL14
TOL22
FE
TOC5
TOL5
TOL13
TOL21
BGT
PEC1
UT5
TOC4
TOL4
TOL12
TOL20
−
TOR1
TOR2
TOR3
MSR
FCR
W
TOL8
W
TOL16
TBE/RBF
FL0
R
W
PEC2
UT6
UR6
−
PEC0
UT4
−
FL2
FL1
UTR
W
UT7
UR7
TO3
−
UT3
UR3
PE
UT2
UT1
UR1
FER
−
UT0
URR
USR
HSR
R
UR5
UR4
UR2
UR0
R
TO1
EA
OVR
PRL
TBE/RBF
PTL
R
−
PRTL
SUPL
−
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.2
SUPPLY
For programming the EPROM of the TDA8030; TDA8031,
by applying a logic 1 to pin CPROG it will disable the
regulator, so that the microcontroller will be powered-up at
5 V.
The supply to the chip is delivered by the USB-bus (pins
VDDU and UGND).
8.2.1
POWER SWITCH CONTROL
8.2.3
DC-TO-DC CONVERTER
A power switch control is used in order to limit the inrush
current when plugging the reader into the bus. The main
decoupling capacitor is connected to the output of this
power switch control (pin VDD).
In case of a 5 V card, the card buffers are supplied by an
inductive DC-to-DC converter.
In case of a 3 or 1.8 V card, the DC-to-DC converter is
transparent and the card buffers are then supplied directly
8.2.2
3.3 V REGULATOR
by VDD.
The output voltage of the 3.3 V linear regulator is used for: The external components for the DC-to-DC converter
should be an inductance of 6.8 µH, a low ESR capacitor of
1 µF and a Schottky diode (type BAT54).
• Powering-up the microcontroller and the ISO7816
UART
The power efficiency is approximately 85% up to
ICC = 55 mA. The current is limited at 100 mA during the
start-up phase to avoid spurious supply drop-outs.
• It is the reference voltage for the signalling pull-up
resistor connected to pin D+.
If this voltage is used within the application, the current
should not exceed 10 mA.
The DC-to-DC converter is transparent for a 3 V card.
For stability reasons, a 1 µF low ESR decoupling capacitor
is needed between the output of the regulator (VDDD) and
the specific regulator ground (DGND).
V
DD
V
LX
UP
clock
N drive
reset
P drive
low
up
V
MGU887
ref
Fig.7 DC-to-DC converter.
2003 Jul 04
29
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.2.4
SUPPLY SUPERVISOR
This pulse is used as a Power-on reset pulse and also to
either block any spurious spikes on card contacts during
microcontrollers reset, or to force an automatic
deactivation of the contacts in the event of supply
drop-out; see Sections 8.3.3 and 8.3.4.
The switched supply voltage (VDD) is surveyed by a
voltage supervisor, to ensure proper Power-on reset when
the reader is plugged into the USB-bus, to maintain all
cards contacts inactive during power-on and also to
enforce an emergency deactivation sequence in case of
After power-on, or after a voltage drop, bit SUPL is set
within the Hardware Status Register (HSR) and remains
set until HSR is readout outside the alarm pulse. As long
as the Power-on reset is active, INT0 is LOW.
VDD drop-out or when the reader is unplugged from the
USB-bus.
The voltage supervisor generates an alarm pulse, whose
length is defined by an external capacitor tied to the
CDELAY pin, when VDD is too low to ensure proper
operation (1 ms per 2 nF typical).
The same events occurs when the RESET pin has been
set active; the RESET pin should be set HIGH for a
minimum of 100 µs for a proper reset.
supply dropout
reset by pin RESET
V
th1
V
DD
V
th2
CDELAY
RESET
t
t
t
w
w
w
SUPL
INT0
MGU888
power- off
status read
power-on
Fig.8 Voltage supervisor.
2003 Jul 04
30
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.3
ISO7816 SECURITY
8.3.3
ACTIVATION SEQUENCE
8.3.1
INTRODUCTION
When the card is inactive, VCC, CLK, RST, I/O, C4 and C8
are LOW, with low-impedance with referenced to CGND.
The DC-to-DC converter is stopped.
The correct sequence during activation and deactivation of
the cards is ensured through a specific sequencer, clocked
by a division ratio of the internal oscillator.
When everything is in normal conditions (no error flag set),
the microcontroller will initiate an activation sequence of
the card.
Activation (START bit HIGH in the Power Control Register)
is only possible if the card is present (PRES active HIGH)
and if the supply voltage is correct (supervisor not active). After leaving the UART reset mode and then configuring
the necessary parameters for the UART, the START bit in
The presence of the card is signalled to the microcontroller
the PCR (t0) will be activated. The following sequence then
by the Hardware Status Register (HSR).
occurs:
Bit PRL in the HSR is set if the card is present. Bit PRL in
the HSR is set if bit PRL has toggled.
1. The DC-to-DC converter is started (t1)
2. VCC starts rising from 0 to 5 V or 3 or 1.8 V with a
During a session, the sequencer performs an automatic
emergency deactivation on the card in the event of card
take off, a short-circuit, a supply drop-out or overheating.
When the HSR register is updated and the INT0 line goes
LOW, the microcontroller will also be updated.
controlled rise time of 0.17 V/µs typically (t2)
3. I/O, C4 and C8 rise to VCC (t3); integrated 10 kΩ
pull-up resistors connected to VCC
4. Clock pulses are sent to the card and RST is enabled
(t4).
8.3.2
PROTECTIONS AND LIMITATIONS
After a number of clock pulses that can be counted with the
Time-Out Counter, the bit RSTIN may be set by software
The TDA8030; TDA8031 features the following protections
and limitations:
and RST will rise to VCC
.
The sequencer is clocked by 1⁄64fint which leads to a time
interval of t = 25 µs typical.
1. ICC limited to 100 mA, deactivated when this limit is
reached
Thus t1 = 0 to 3⁄64t, t2 = t1 + 5⁄2t, t3 = t1 + 9⁄2t
and t4 = t1 + 5t.
2. Current to and from RST is limited to 20 mA,
deactivated when this limit is reached
3. Deactivation when the temperature of the die exceeds
150 °C
4. Current to and from the I/O is limited to 10 mA
5. Current to and from pin CLK is limited to 70 mA (not in
current reduction modes, when clock is stopped)
6. ESD protection on all cards contacts + PRES at
6 kV (min.), thus no need of extra components for
protection against ESD flash caused by a charged
card being introduced in the slot
7. Short-circuit between any cards contacts can last any
duration without any damage.
2003 Jul 04
31
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
START
V
UP
V
CC
I/O
CLK
RST
t
t
t
t
t t
4 = act
ATR
0
1
2
3
MGU889
Fig.9 Activation sequence.
8.3.4
DEACTIVATION SEQUENCE
Automatic emergency deactivation is performed in the
following cases:
When the session is completed, the microcontroller resets
START (t10). The circuit then executes an automatic
deactivation sequence as follows:
1. Withdrawal of the card (PRES LOW)
2. Overcurrent detection on VCC (bit PRTL set)
3. Overcurrent detection on RST (bit PRTL set)
4. Overheating (bit PTL set)
1. Card reset (RST falls LOW; t11)
2. Clock (CLK) is stopped LOW (t12)
3. I/O, C4 and C8 fall to 0 V (t13)
5. Supply too low (bit SUPL set)
4. VCC falls to 0 V with typical 0.17 V/µs slew rate (t14)
6. RESET pin active HIGH.
5. The DC-to-DC converter is stopped and CLK, RST,
VCC, I/O, C4 and C8 become low-impedance to CGND
(t15).
In all of these cases, the deactivation sequence as
described above occurs.
If the reason for the deactivation is a card take-off, an
overcurrent or overheating, then INT0 will be LOW and the
corresponding bit in the Hardware Status Register will be
set. The START bit is automatically reset.
Thus:
t11 = t10 + 1⁄64t
t12 = t11 + 1⁄2t
t13 = t11 + t
If the reason is a supply drop-out, then the deactivation
sequence occurs and a complete reset of the chip is
performed. When the supply recovers, then the SUPL bit
will be set in the HSR.
t
14 = t11 + 3⁄2t
t15 = t11 + 7⁄2t
tde = time that VCC needs to decrease to less than 0.3 V.
2003 Jul 04
32
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
START
RST
CLK
I/O
V
CC
V
UP
t
de
t
t
t
t
t
t
15
MGU890
10 11
12
13
14
Fig.10 Deactivation sequence.
2003 Jul 04
33
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.4
MICROCONTROLLER
The 80C51 microcontroller has four 8-bit I/O ports, three
16-bit timer/event counters, a multi-source, 4-level priority
nested interrupt structure, an enhanced UART and on-chip
oscillator and timing circuits. For systems that require
extra memory capability up to 64 kbytes, it can be
expanded by using standard TTL compatible memories
and logic.
The embedded microcontroller is an 80C51RB+ with an
internal 16 kbyte EPROM (80C51FB with 16 kbyte ROM
for the TDA8031), 256 RAM and 512 AUXRAM. It has the
same instruction set as the 80C51.
The embedded microcontroller is clocked by the frequency
present on pin XTAL1.
1. 80C51 Central Processing Unit (CPU)
2. Full static operation
The embedded microcontroller may be reset by an active
HIGH signal on pin RESET, but it is also reset by the
Power-on reset signal generated by the voltage
supervisor.
3. Security bits: ROM 2 bits
4. Encryption array of 64 bits
5. 4-level priority structure
6. 6 interrupt sources
The external interrupt INT0 is used by the ISO UART, by
the analog drivers and by the ETU counters. It must be left
open-circuit in the application.
7. Full duplex enhanced UART with framing error
detection and automatic address recognition
The external interrupt INT1 is used by the USB interface.
It must be left open-circuit in the application.
8. Power control modes (the clock can be stopped and
resumed in IDLE mode and power-down mode)
A general description, together with the added features, is
described below.
9. Wake-up from power-down by a falling edge on pins
INT0 and INT1; with an embedded delay counter
The added features to the 80C51 microcontroller are
similar to the 8XC51FB/RB+ microcontrollers, except for
the wake-up from power-down mode, which is enabled by
a falling edge on pin INT0 (card reader event) or on pin
INT1 due to the addition of an extra delay counter and
enable configuration bits within the UCR2 register; see
Section 8.4.1. For further information please refer to the
published specification of the 8xC51RB + /FB in “Data
Handbook IC20; 80C51-Based 8-bit Microcontrollers”.
10. Programmable clock output
11. Second DPTR register
12. Asynchronous port reset
13. Low EMI (inhibit ALE).
Table 28 gives a list of main features to get a better
understanding of the differences between a standard
80C51, an 8XC51RB+ and the embedded microcontroller
in the TDA8030; TDA8031.
Table 28 Principal blocks in the 80C51, 8XC51RB+ and the TDA8030; TDA8031
FEATURE
ROM/EPROM
80C51
8XC51RB+
TDA8030; TDA8031
4 kbytes
128 bytes
no
16 kbytes
256 bytes
256 bytes
yes
16 kbytes
256 bytes
512 bytes
no
RAM
ERAM (MOVX)
PCA
WDT
T0
no
no
yes
no
yes
yes
yes
T1
yes
yes
yes
T2
no
yes
yes
lowest interrupt priority vector at 002BH
4 level priority interrupt
enhanced UART
delay counter
no
no
no
yes
yes
no
yes
yes
yes
2003 Jul 04
34
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.4.1
LOW POWER MODES
The bits in the Interface Engine (IE) must be enabled with
INT0 and INT1. Within the INT0 interrupt service routine,
the microcontroller has to read out the Hardware Status
Register (HSR at 0FH) and/or the UART Status register
(USR at 0EH) by means of MOVX instructions in order to
establish the exact interrupt reason and to reset the
interrupt source.
Stop Clock Mode: The static design enables the clock
speed to be reduced down to 0 MHz (stopped). When the
oscillator is stopped, the RAM and Special Function
Registers (SFRs) retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any
value. The power-down mode is suggested for the lowest
power consumption.
For enabling a wake-up by INT1, the bit ENINT1 within
UCR2 must be set.
IDLE Mode: In the Idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The
instruction to invoke the Idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM
and all of the special function registers remain intact during
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
An integrated delay counter maintains INT0 and INT1
LOW long enough to allow the oscillator to restart properly.
A falling edge on pins INT0 and INT1 is enough to awaken
the whole circuit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the
instruction that put the device into power-down.
8.5
USB INTERFACE
8.5.1
END-POINTS
Power-down Mode: To save even more power, a
power-down mode can be invoked by software. In this
mode, the oscillator is stopped and the instruction that
invoked the power-down is the last instruction executed.
The TDA8030; TDA8031 has 4 logic end-points which are
listed in Table 29.
Each physical end-point, except for the control ones, can
be enabled or disabled. All enabled end-points generate
interrupts to the microcontroller via INT1 when the
end-point needs to be serviced.
Either a hardware reset or external interrupt can be used
to exit from the power-down mode. Applying a reset
redefines all of the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
The implementation of the function makes use of an SRAM
for buffering the data.
Logic end-points can be accessed by the microcontroller
interface.
Table 29 Mapping of logic to physical end-point numbers for used end-points
PHYSICAL END-POINT
LOGIC
END-POINT
END-POINT NAME
Control end-point
BUFFER SIZE
OUT
IN
0
1
2
3
16
32
8
0
2
−
−
1
3
4
5
Generic end-point (may be used as bulk
Generic end-point (may be used as interrupt)
Generic end-point
8
2003 Jul 04
35
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.5.2
PHASE-LOCKED LOOP
A 12 to 48 MHz clock multiplier PLL is integrated on-chip. No external components are needed for the operation of the
PLL.
8.5.3
BIT CLOCK RECOVERY
The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4× oversampling principle.
It is able to track jitter and frequency drift as specified by the USB specification.
8.5.4
INTERFACE SIGNALS WITH THE MICROCONTROLLER
Table 30 The following I/O ports of the 83C51 are used for controlling the USB bus:
PORT
FUNCTION
USB_INT_MASK
DESCRIPTION
P10
should be set to logic 1 before entering power-down mode during suspend
and reset to logic 0 when leaving power-down mode
P11
P12
P13
P14
P15
USB_SOFTCONNECT_INT
USB_MC_READY
when set to logic 1, the internal 1.5 kΩ resistor is connected to pin D+
the device is ready to accept a new transaction
USB_CLK_EN_N
when LOW, this signal indicates that the bus is no longer suspended
a LOW-level will reset the USB interface
USB_RESET_N
USB_SOFTCONNECT_EXT
when set to logic 1, VDDD is applied on the optional external 1.5 kΩ resistor
which has been placed between pins D+ and DELATT
P33
P34
P35
P25
P26
USB_INT_N
interrupt to the microcontroller
USB_SUSPEND
USB_WAKEUP_N
USB_MP_C
the device is in suspended state (TDA8030 only)
remote wake-up (TDA8030 only)
if set to logic 1, the data to the bus is a command; if set to logic 0 it is data
if set to logic 1, the USB interface is selected
USB_MP_SEL
8.5.5
BLOCK DIAGRAM
The digital interface consists of 3 major blocks:
• The Philips Serial Interface Engine (SIE) handles the USB protocol (i.e. synchronization pattern, recognition,
parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generating, PID verification/generation, address
recognition and handshake evaluation/generation)
• A Memory Management Unit (MMU), controlling the buffering of data to and from the bus
• An interface to the embedded 83C51 microcontroller.
OSCILLATOR
RAM
+
D
SERIAL
INTERFACE
ENGINE
MEMORY
MANAGEMENT
UNIT
MICRO-
CONTROLLER
INTERFACE
ANALOG
TRANSCEIVER
MICRO-
CONTROLLER
USB bus
D−
MGU891
Fig.11 USB block diagram.
2003 Jul 04
36
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.5.6
USB REGISTERS
8.5.7
INSTRUCTION SET
A first MOVX@DPTR instruction enables the module to be
selected (via DPH) and send the command. A second one
communicates the data (read or write).
8.5.7.1
Overview
Table 31 summarizes all commands that can be used by
the embedded microcontroller.
Table 31 Instruction set
COMMAND NAME
Device commands; see Table 32
Set address device
Set end-points enable device
RECIPIENT
CODING
FUNCTION
DATA PHASE
0XD0H
set address
write 1 byte
0XD8H
0XF3H
0XF4H
set EP enable
set mode
write 1 byte
write 1 byte
read 1 byte
Set mode
device
device
Read interrupt
register
Read current frame
number
device
0XF5H
read 1 or 2 bytes
Read chip ID
device
device
device
0XFDH
0XFEH
0XFEH
0XFFH
read 2 bytes
read 1 byte
write 1 byte
read 1 byte
Get device status
Set device status
Debug command: get device
error code
End-point commands; see Table 41
Select end-point
control output
0X00H
0X01H
0X02H
0X03H
0X04H
0X05H
0X40H
0X41H
0X42H
0X43H
0X44H
0X45H
0X40H
0X41H
0X42H
0X43H
0X44H
0X45H
0XF0H
0XF0H
0XF2H
0XFAH
select EP0 output
select EP0 input
read 1 byte (optional)
read 1 byte (optional)
read 1 byte (optional)
read 1 byte (optional)
read 1 byte (optional)
read 1 byte (optional)
read 1 byte
control input
end-point 1 output
end-point 1 input
end-point 2 input
end-point 3 input
Select end-point/clear control output
interrupt
control input
read 1 byte
end-point 1 output
end-point 1 input
end-point 2 input
end-point 3 input
control output
read 1 byte
read 1 byte
read 1 byte
read 1 byte
Set end-point status
write 1 byte
control input
write 1 byte
end-point 1 output
end-point 1 input
end-point 2 input
end-point 3 input
selected end-point
selected end-point
selected end-point
selected end-point
write 1 byte
write 1 byte
write 1 byte
write 1 byte
Read buffer
Write buffer
Clear buffer
Validate buffer
read n + 2 bytes
write n + 2 bytes
read 1 byte (optional)
none
2003 Jul 04
37
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 32 Device commands
COMMAND
DESCRIPTION
Set address
The set address command is used to set the USB assigned address and to enable the function. In
the event that the status phase of the set address transaction is not successful, the device address
will not be updated. The power-on value is given in Table 33.
Set end-points
enable
A value of 1 written to the register indicates that the non-control end-points are enabled. The
power-on value is given in Table 34.
Set Mode
The default value is logic 0; if logic 1 is written in this register, then NAKing is reported and will
generate an interrupt. When set to logic 0, only successful transactions are reported.
Read interrupt
register
This command indicates the origin of an interrupt. The end-point interrupt bits are cleared by the
Select end-point/Clear Interrupt command. The power-on value is given in Table 35.
Read Current
Frame Number
The Read Current Frame Number returns the frame number of the last received Start Of Frame
(SOF). The frame number is eleven bits wide. The frame number is returned LSB first, so, if the
user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read;
see Table 36.
The frame number returned by this commend can be invalid in the event of one of the following
conditions:
• If no SOF was received by the device at the beginning of a frame, the frame number returned is
that of the last successfully received SOF
• If the SOF frame number contained a CRC error, the frame number received will be the corrupted
frame number as received by the device.
Read chip ID
The chip Identification is 16 bits wide. The command divides the ID into bytes and returns the least
significant byte first: For the TDA8030; TDA8031, the ID is fixed at 2B00H.
Get Device
Status
The Get Device Status command returns the Device Status Register; refer to the Set Device Status
command
Set Device
Status
The Set Device Status command sets bits in the Device Status Register.
In Table 37, the Type column indicates if the bit can be written and if the bit is cleared after reading
the register. The Interrupt column indicates if the bit generates an interrupt when it is set.
Debug
command: Get
Error Code
The Get Error Code command returns the error code of the last generated error; this command is
for debugging purpose. The 4 least significant bits form the error code. Bit 4 (Error Occurred) can
be cleared by each new transfer. The power-on value is given in Table 39.
This command is only useful during debugging.
Table 40 gives an overview of the Error Codes.
Table 33 Power-on value for Set address
FUNCTION
7
6
5
4
3
2
1
0
Device
−
0
0
0
0
0
0
0
address(1)
Enable(2)
0
−
−
−
−
−
−
−
Notes
1. The value written becomes the address.
2. A logic 1 enables the function.
After a bus reset, the address is reset to 000 0000. The enable bit is set. The device will respond on packets for function
address 000 0000, end-point 0 (default end-point).
2003 Jul 04
38
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 34 Power-on value for Set end-points enable
FUNCTION
Enable all
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
0
end-points
Reserved
−
−
−
−
−
−
−
−
Table 35 Power-on value for Read interrupt register
FUNCTION
7
6
5
4
3
2
1
0
Physical EP0 (control output end-point)
Physical EP1 (control input end-point)
Physical EP2 (generic output end-point)
Physical EP3 (generic input end-point)
Physical EP4 (generic input end-point)
Physical EP5 (generic input end-point)
Reserved
−
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
0
−
−
−
−
−
−
−
Device event(1)
Note
1. The Device event bit is cleared by issuing the Get Device Status command.
Table 36 Read current frame number
BYTE
Byte 0
Byte 1
7
F
0
6
F
0
5
F
0
4
F
0
3
F
0
2
F
F
1
F
F
0
F
F
Table 37 Set device status command functions
FUNCTION
Reserved
Suspend
Suspend change read only;
cleared on read
read only;
TYPE
INTERRUPT
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
−
0
−
0
−
−
0
−
−
read/write
no
yes
Bus reset
Reserved
yes
−
−
−
−
−
−
0
−
−
−
−
−
−
−
−
cleared on read
−
−
−
2003 Jul 04
39
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 38 Set device status command function bits
FUNCTION
DESCRIPTION
Suspend
The Suspend bit represents the current Suspend state. It is logic 1 when the device has not seen
any activity on its upstream port for more than 3 ms. It is reset to logic 0 on any activity.
When the device is suspended, (Suspend bit = 1) and the microcontroller writes logic 0 into it,
the device will generate a remote wake-up. When the device is not suspended, writing a logic 0
has no effect. Writing a logic 1 in this register has no an effect.
Suspend Change
The Suspend Change bit is set to logic 1 when the Suspend bit toggles. The Suspend bit can
toggle because:
• The device goes into the suspended state
• The device receives resume signalling on its upstream port
• The Suspend Change bit is reset after the register has been read.
Bus reset
The Bus reset bit is set when the device receives a bus reset. It is cleared when read. On a bus
reset, the device will automatically go to the default state (unconfigured and responding to
address 0).
Table 39 Power-on value for Get Error Code
FUNCTION
Error code
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
0
−
0
−
−
0
−
−
0
−
−
0
−
−
Error occurred
Reserved
Table 40 Error codes
ERROR CODE[3:0]
DESCRIPTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
no error
PID encoding error
unknown PID
unexpected packet
error in token CRC
error in data CRC
time-out error
babble
error in end of packet
sent NAK
sent Stall
buffer overrun error
reserved
bitstuff error
error in sync
wrong toggle bit in data PID; ignored data
2003 Jul 04
40
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 41 End-point commands
COMMAND
DESCRIPTION
Select end-point
The select end-point command initializes an internal pointer to the start of the selected buffer.
Optionally, this command can be followed by a data read, which returns some additional
information on the packet in the buffer. The command code of the select end-point is equal to
the physical end-point number. The power-on value is given in Tables 42 and 43.
Select End-point/
Clear Interrupt
These commands are identical to Select End-point commands, but with the following
differences:
• They clear the associated interrupt
• In the event of a control output end-point; they clear the set-up and overwritten bits
• The read one byte is mandatory.
Set end-point status The Set end-point status command sets status bits 7 to 5 and 0 of the end-point. The command
code is equal to the sum of 40H and the physical end-point number. Not all bits can be set for all
types of end-points. The power-on value is given in Tables 44 and 45.
Read buffer
Write buffer
Clear buffer
The Read buffer command is followed by a number of data reads, which return the contents of
the selected end-point data buffer. After each read, the internal buffer pointer is incremented.
The buffer pointer is not reset to the beginning of the buffer by the Read buffer command. This
means that reading a buffer can be interrupted by any other command (except for the Select
end-point).
The data buffer organization is given in Table 46.
The Write buffer command is followed by a number of data writes, which load the data buffer of
the selected end-point. After each write, the internal buffer pointer is incremented
The buffer pointer is not reset to the beginning of the buffer by the Write buffer command. This
means that writing to a buffer can be interrupted by any other command (except for the Select
end-point and Select end-point/Clear Interrupt).
The data buffer organization is given in Table 47.
When a packet sent by the host has been received successfully, an internal end-point buffer full
flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller
has read the data, it should free the buffer by the Clear buffer command. When the buffer is
cleared, new packets will be accepted.
When bit 0 of the optional data byte is set to logic 1, the previously received packet was
overwritten by a set-up packet.
A buffer cannot be cleared when its Packet overwritten bit is set. The power-on value is given in
Table 48.
Validate buffer
When the microcontroller has written data into an input buffer, it should set the buffer full flag by
the Validate buffer command. This indicates that the data in the buffer is valid and can be sent
to the host when the next input token is received.
A control input buffer cannot be validated when the Packet overwritten bit of its corresponding
output buffer is set.
2003 Jul 04
41
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 42 Power-on value for Select end-point
FUNCTION
Full or empty
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
−
−
−
−
0
−
−
−
−
0
−
−
−
−
0
−
−
−
−
0
−
−
−
−
−
Stall
Set-up
Packet overwritten
Sent NAK
Reserved
Table 43 Description of the Power-on value for Select end-point bits
FUNCTION
Full or empty
DESCRIPTION
If set to logic 1, the buffer of the selected end-point is full.
In the event of an output end-point, this bit is cleared by executing the Clear Buffer command, if
the buffer was not overwritten.
In the event of an input end-point, this bit is set by the Validate Buffer command.
If set to logic 1, the selected end-point is stalled.
Stall
Set-up
If set to logic 1, the last received packet for the selected end-point was a set-up packet. The
value of this bit is updated after each successfully received packet (i.e. an ACKED package on
that particular end-point).
Packet overwritten
Sent NAK
If set to logic 1, the previously received packet was overwritten by a set-up packet. The value of
this bit is cleared by the Select End-point command.
If set to logic 1, the device has sent a NAK. If the host sends an output packet to a filled output
buffer, the device returns a NAK. If the host sends an input token to an empty input buffer, the
device returns a NAK.
This bit is set when a NAK is sent and the Interrupt On Nak feature is enabled.
This bit is reset after the device has sent an ACK after an output packet or when the device has
seen an ACK after sending an input packet. It is only defined for the 2 physical control
end-points.
Table 44 Power-on value for Set end-point status; notes 1 and 2
FUNCTION
Stall
7
6
5
4
3
2
1
0
CTRL EP
GEN IN/OUT
GEN IN
−
−
−
−
−
0
−
0
−
−
−
−
−
−
−
−
−
−
−
−
−
0
−
−
def
X
def
def
def
def
def
def
Disable
Rate feedback
mode
X
Interrupt unmasked
Conditional stall
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
X
X
X
X
X
def
Notes
1. X = dont care.
2. def means that the bit can be set if the end-point is of the specified type.
2003 Jul 04
42
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
Table 45 Description of the Power-on value for Set end-point status bits
FUNCTION
Stall
DESCRIPTION
If set to logic 1, the end-point is stalled.
Disable
If set to logic 1, the end-point is disabled. After a bus reset; each end-point is enabled, i.e. this
bit is set to logic 0.
Rate feedback
mode
If set to logic 0, the interrupt end-point is in toggle mode. If set to logic 1, the interrupt end-point
is in rate feedback mode.
Interrupt unmasked If set to logic 1, an event on the end-point causes an interrupt to the microcontroller.
Conditional stall
If set to logic 1, both end-points zero are stalled; unless the set-up packet bit is set.
A stalled control end-point is automatically unstalled when it receives a SET-UP token,
regardless of the content of the packet. If the end-point stays in the stalled state, the
microcontroller should re-install it.
When a stalled end-point is unstalled (either by the Set end-point status command or by
receiving a Set-up token) it is also re-initialized. This flushes the buffer: in case of an output
buffer, it waits for a DATA 0 PID; in case of an input buffer, it writes a DATA 0 PID. Even when
unstalled, setting the stalled bit to logic 0 initializes the end-point.
When an end-point is stalled by the Set end-point status command, it is also re-initialized.
Table 46 Data buffer organization (read)
BYTE
7(1)
6(2)
5
4
3
2
1
0
Byte 0
Byte 1
Byte 2
....
0/1
0/1
−
−
−
−
−
0
−
number of data bytes in buffer
data byte 0
Byte n + 1
data byte n − 1
Notes
1. Bit 7 of Byte 0 indicates whether the packet in the buffer was received successfully over the USB-bus. When this bit
is set to logic 1, the packet was received successfully.
2. Bit 6 of Byte 0 indicates whether the packet in the buffer is a set-up packet.
Table 47 Data buffer organization (write)
BYTE
7
−
−
6
5
4
3
2
1
0
Byte 0
Byte 1
Byte 2
....
−
−
−
−
−
−
0
number of data bytes in buffer
data byte 0
Byte n + 1
data byte n − 1
Table 48 Power-on value for Clear buffer
FUNCTION
7
6
5
4
3
2
1
0
Packet overwritten
Reserved
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
−
2003 Jul 04
43
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.5.8
ANALOG INTERFACE
8.5.9
SUSPEND MODE
The transceiver interfaces directly to the USB cables
through termination resistors. They are able to transmit
and receive serial data at full speed (12 Mbits/s).
When the USB interface enters Suspend mode, the
software should set the microcontroller in power-down
mode in order to respect the suspend current condition.
The following sequence should be executed:
A 1.5 kΩ pull-up resistor is integrated between pins D+
and VDDD and is connected by software by the
microcontroller; in case a ±5% resistor is preferred, it can
be externally connected between pins DELATT and D+
(DELATT is also controlled by software and is floating
when OFF, or connected to VDDD when ON).
1. When the device enters the Suspend mode, it
generates an interrupt on pin INT1
2. The software should set USB_INT_MASK to logic 1
3. Then it should wait until CLK_EN_N is HIGH before
entering power-down mode.
When the device detects an activity on the bus, it resets
CLK_EN_N to logic 0 and generates an interrupt on pin
INT1. When leaving the Suspend mode, the following
sequence should be executed:
1. The software should read the DEVICE_STATUS to
enable the interrupt to be cleared
2. Reset USB_INT_MASK to logic 0.
2003 Jul 04
44
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
bus supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VDDU
Vn
V
V
input voltage on all pins
total power dissipation
−0.5
−
+6.5
tbf
Ptot
Tstg
Tj
mW
°C
IC storage temperature
junction temperature
−55
−
+150
125
°C
Vesd
electrostatic discharge voltage
pins I/O, VCC, RST, C4, C8, CLK and PRES
all other pins
TDA8030; HBM JEDEC
−5
+5
kV
kV
V
−1
+1
MM JEDEC
MM JEDEC
−50
−100
+50
+100
V
Vesd
electrostatic discharge voltage
pins I/O, VCC, RST, C4, C8, CLK and PRES TDA8031; HBM JEDEC −6
+6
kV
kV
mA
all other pins
−1.5
−100
+1.5
+100
Ilu
latch-up free current on all pins
JEDEC; maximum
voltage is 1.5/−0.5 supply
voltage of the block
10 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
VALUE
63
UNIT
Rth(j-a)
in free air
K/W
2003 Jul 04
45
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
11 CHARACTERISTICS
VDDU = 5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDU
VDD
supply voltage for the bus
4.2
4.2
−
5.5
5.5
V
supply voltage after inrush
current suppression switch
−
−
−
V
IDDU
Isus
supply current for the bus
5 V card; ICC = 40 mA;
fclk = 6 MHz
−
−
100
500
mA
µA
suspend current
card inactive;
microcontroller in
power-down mode
Vth(VDD)
Vhys
threshold voltage on VDD
falling
3.6
−
−
3.8
V
hysteresis voltage on
Vth(VDD)
150
350
mV
Vth(CDELAY) threshold voltage on pin
CDELAY
−
1.25
−
V
VCDELAY
voltage on pin CDELAY
−
−
−
VDD + 0.3
V
Io(CDELAY)
output current on pin
CDELAY
pin ground; charge
current
−2
−
µA
V
CDELAY = VDD
;
−
−
9
−
−
mA
nF
discharge current
CCDELAY
capacitor on pin CDELAY
22
Crystal oscillator (XTAL1 and XTAL2)
fXTAL
VIL
crystal frequency
−
12
−
MHz
V
LOW-level input voltage on
pin XTAL1
−0.3
−
+0.3VDDD
VIH
HIGH-level input voltage on
pin XTAL1
0.7VDDD
−
VDDD + 0.3
V
DC-to-DC converter
fclk
clock frequency
−
−
−
−
12
5.5
5
−
−
−
−
MHz
V
VUP
output voltage
VCC = 5 V
VCC = 3 or 1.8 V
L = 6.8 µH; C = 1 µF
V
PE
power efficiency
85
%
VDDD voltage regulator
VDDD
output voltage
PROG = 0
3
−
−
3.6
5.5
V
V
PROG = 1 (TDA8030
only)
4.5
IDDD
Cdec
output current
0
−
−
25
mA
nF
decoupling capacitor
1000
−
2003 Jul 04
46
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset output to the card (RST)
Vinact
output voltage in inactive
mode
no load
inact = 1 mA
0
0
0
−
0.1
0.3
−1
V
I
−
−
V
Iinact
VOL
current from RST when
inactive and pin grounded
mA
LOW-level output voltage
HIGH-level output voltage
IOL = 200 µA
IOL = 20 mA
IOH = −200 µA
0
−
−
−
−
−
0.3
V
V
CC − 0.4
VCC
VCC
0.4
V
VOH
0.9VCC
V
I
OH = −20 mA
0
V
tr
tf
rise time
fall time
CL = 100 pF;
VCC = 5 or 3 V
−
0.1
µs
CL = 100 pF;
−
−
0.1
µs
VCC = 5 or 3 V
Clock output to the card (CLK)
Vinact
output voltage in inactive
mode
no load
0
0
0
−
−
−
0.1
0.3
−1
V
I
inact = 1 mA
V
Iinact
VOL
current from CLK when
inactive and pin grounded
mA
LOW-level output voltage
HIGH-level output voltage
IOL = 200 µA
OL = 70 mA
0
−
−
−
−
−
−
−
0.3
VCC
VCC
0.4
16
V
I
V
CC − 0.4
V
VOH
IOH = −200 µA
IOH = −70 mA
CL = 35 pF
0.9VCC
V
0
−
−
1
V
tr
rise time
ns
ns
MHz
tf
fall time
CL = 35 pF
16
fclk
clock frequency
1 MHz Idle
1.5
configuration
operational
0
−
−
−
12
55
−
MHz
%
δ
duty factor (except for XTAL) CL = 35 pF
slew rate (rise and fall) CL = 30 pF
45
0.2
SR
V/ns
Card supply voltage (VCC) (2 ceramic multilayer capacitors with low ESR of minimum 100 nF should be used
in order to meet these specifications)
Vinact
output voltage inactive
no load
0
0
−
−
−
−
0.1
0.3
−1
V
Iinact = 1 mA
V
Iinact
current from VCC when
mA
inactive and pin grounded
2003 Jul 04
47
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
VCC
PARAMETER
output voltage
CONDITIONS
active mode;
MIN.
TYP.
MAX.
5.25
UNIT
4.75
2.78
4.6
5
V
ICC < 55 mA; 5 V card
active mode;
3
3.22
5.4
V
V
I
CC < 55 mA; 3 V card
active mode; current
pulses of 40 nAs with
I < 200 mA; t < 400 ns;
f < 20 MHz; 5 V card
−
active mode; current
pulses of 24 nAs with
I < 200 mA; t < 400 ns;
f < 20 MHz; 3 V card
2.75
−
3.25
V
active mode;
1.64
1.62
1.8
1.96
1.98
V
V
I
CC < 35 mA; 1.8 V card
active mode; current
pulses of 12 nAs with
I < 200 mA; t < 400 ns;
f < 20 MHz; 1.8 V card
−
ICC
output current
5 V card; from 0 to 5 V
3 V card; from 0 to 3 V
−
−
−
−
−
−
−55
−55
−35
mA
mA
mA
1.8 V card; from
0 to 1.8 V
when clock is stopped;
at all VCC values
−
−
−
−10
mA
VCC shorted to ground
−
−120
mA
SR
slew rate
up or down (maximum 0.05
capacitance = 300 nF)
0.16
0.22
V/µs
Vripple(p-p)
ripple voltage on VCC
(peak-to-peak value)
20 kHz < f < 200 MHz
5 V card
3 V card
1.8 V card
−
−
−
−
−
−
350
200
100
mV
mV
mV
Data line (I/O); I/O has an integrated 14 kΩ pull-up resistor at VCC
Vinact
output voltage inactive
no load
inact = 1 mA
0
−
−
−
−
−
0.1
0.3
−1
V
I
V
Iinact
VOL
current from I/O when
inactive and pin grounded
mA
LOW-level output voltage
the I/O is configured as
an output
I
OL = 1 mA
0
−
−
0.3
V
V
IOL = 10 mA
V
CC − 0.4
VCC
2003 Jul 04
48
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
VOH
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HIGH-level output voltage
the I/O is configured as
an output
I
OH < −20 µA
0.8VCC
−
VCC + 0.25
VCC + 0.25
V
I
OH < −40 µA;
0.75VCC
V
5 and 3 V card
OH = −10 mA
I
0
−
−
0.4
V
V
VIL
LOW-level input voltage
HIGH-level input voltage
the I/O is configured as −0.3
+0.8
an input
VIH
IIL
the I/O is configured as 1.5
an input
−
VCC
500
10
V
LOW-level input current on
I/O
VIL = 0
−
−
µA
µA
µs
µs
kΩ
ns
ILIH
ti(tr)
to(tr)
Rpu
tW(pu)
HIGH-level input leakage
current on I/O
VIH = VCC
−
−
input transition times
CL ≤ 60 pF; 5 or 3 V
−
−
1.2
card
output transition times
CL ≤ 60 pF 5 or 3 V
−
−
0.1
card
internal pull-up resistance
between I/O and VCC
11
14
−
17
width of active pull-up pulse the I/O is configured as 2/fXTAL1
3/fXTAL1
an 2/fXTAL1 output;
LOW-to-HIGH
transition
Ipu
current from I/O when active VOH = 0.9VCC
pull-up pulse CL = 60 pF
;
−1
−
−
mA
Auxiliary contacts C4/C8; integrated 10 kΩ pull-up resistor to VCC
Vinact
output voltage inactive
no load
0
−
−
−
−
−
0.1
0.3
−1
V
Iinact = 1 mA
V
Iinact
VOL
current from I/O when
inactive and pin grounded
mA
LOW-level output voltage
C4 and C8 configured
as an output;
IOL = 1 mA
0
−
−
0.3
V
V
VOH
HIGH-level output voltage
C4 and C8 configured
as an output;
0.8VCC
VCC + 0.25
IOH < −40 µA;
5 and 3 V card
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
C4 and C8 configured
as an input
−0.3
−
−
+0.8
VCC
V
V
C4 and C8 configured
as an input
1.5
IIL
VIL = 0
−
−
−
−
500
10
µA
µA
ILIH
HIGH-level input leakage
current
VIH = VCC
2003 Jul 04
49
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
ti(tr)
PARAMETER
CONDITIONS
CL ≤ 60 pF
CL ≤ 60 pF
MIN.
TYP.
MAX.
UNIT
µs
input transition times
output transition times
−
−
8
−
1.2
0.1
12
to(tr)
Rpu
−
µs
internal pull-up resistance
between C4/C8 and VCC
10
kΩ
tW(pu)
width of active pull-up pulse the I/O is configured as
−
200
−
ns
an output;
LOW-to-HIGH
transition
Ipu
current from C4 and C8
when active pull-up
VOH = 0.9VCC
CL = 60 pF
;
−1
−
−
mA
Timing
tact
activation sequence duration
−
−
−
−
160
100
µs
µs
tde
deactivation sequence
duration
Protections and limitations
ICC(sd)
shutdown and limitation
−
−100
−
mA
current at VCC
II/O(lim)
limitation current on I/O
limitation current on pin CLK
limitation current on pin RST
−10
−70
−20
−
−
+10
+70
+20
−
mA
mA
mA
mA
ICLK(lim)
IRST(lim)
IRST(sd)
−
−
shutdown current on pin
RST
−20
Tsd
shutdown temperature
−
−
150
−
°C
Card presence input; pin PRES
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
input leakage current low
input leakage current high
−
−
−
−
0.3VDDD
−
V
0.7VDDD
V
VIN = 0
−
−
±20
µA
µA
IIH
VIN = VDD
±20
General purpose I/Os; pins P0X, P1X, P2X and P3X
VIL
VIH
VOL
VOH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
LOW-level input current
−
−
−
−
−
−
−
0.2VDDD
−
V
0.2VDDD + 0.9
V
IOL = 1.6 mA
IOH = −30 µA
VI = 0.4 V
−
0.4
V
V
DDD − 0.7
−
V
−1
−50
−650
µA
µA
ITL
HIGH-to-LOW transition
current
VI = 2 V
−
Pins ALE and PSEN
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 3.2 mA
−
−
−
0.4
V
V
IOH = −3.2 mA
V
DDD − 0.7
−
2003 Jul 04
50
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pin EA/VPP
VIL
LOW-level input voltage
HIGH-level input voltage
programming voltage
−
−
0.2VDDD
V
VIH
0.2VDDD + 0.9
12.5
−
−
V
V
Vprog
TDA8030
12.75 13
Reset input; pin RESET (active HIGH)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.2VDDD
V
V
0.7VDDD
−
DELATT output pin; optional connection for an external 1.5 kΩ resistor on pin D+
VOH
HIGH-level output voltage
when switched on;
IOH = 2 mA
3.0
−
3.6
10
V
IL
leakage current
when switched off
−
−
µA
Programming input; pin PROG (active HIGH) and Test input; pin TEST (active HIGH)
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.2VDD
V
V
0.7VDD
−
ATX Transceiver
DRIVER CHARACTERISTICS IN FULL-SPEED MODE; PINS D+ AND D−
VOL(stat)
VOH(stat)
Ro(drive)
LOW-level static output
voltage
RL = 1.5 kΩ
−
−
−
−
0.3
3.6
30
V
V
Ω
HIGH-level static output
voltage
2.8
10
driver output resistance
excluding outside
resistors
ttr
transition times
CL = 50 pF
CL = 50 pF
4
−
−
−
20
110
2
ns
%
V
tRFM
Vcross
rise and fall time matching
90
1.3
output signal crossover
voltage
Rint(DP)
integrated resistor on DP
when connected
USB_SOFTCONNECT
active
1.1
−
1.9
kΩ
RECEIVER CHARACTERISTICS IN FULL-SPEED MODE; PINS ATXDP AND ATXDM
Vi(dif)
differential input sensitivity
0.2
0.8
−
−
−
V
V
Vdif(CM)
differential common mode
range in which Vi(dif) applies
2.5
Vth(SE)
single-ended receiver
threshold
0.8
−
2.0
V
2003 Jul 04
51
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g
V
DDD
1
3
4
R1
MICROCOSMOS
BP1
2
0 Ω
C1
100
nF
C2
100
nF
J2
C5I C1I
C6I C2I
C7I C3I
C8I C4I
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
P11
C4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CGND
P10
CARD_READ_CCM0_2251
CLK
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
K1
K2
V
CC
RST
V
DDD
TEST
V
UP
TP18
GND
LX
IC1
STGND
TDA8030
V
DD
V
D1
BAT54
DD
V
EA/V
PP
L1
DDU
V
DDD
UGND
ALE/PROG
PSEN
6.8 µH
+
D
C5
10 µF
(10 V)
C6
100 nF
C3
1 µF
D−
CDELAY
P30/RxD
P27/A15
P26/A14
P25/A13
R2
1.5 kΩ
V
DDU
GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
C7
22 nF
J1
V
R4
NDATA
CC
1
6
4
2
5
3
0 Ω
R3
C12
1
1
2
2
PDATA
0 Ω
22 pF
C13
C8
1 µF
Y1
12 MHz
MGU892
22 pF
V
DDD
Fig.12 Application diagram. (More details in application note AN01013).
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
13 PACKAGE OUTLINE
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
D
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT314-2
136E10
MS-026
2003 Jul 04
53
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
14 SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
14.1 Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA and SSOP-T packages
14.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 Jul 04
54
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
WAVE
REFLOW(2)
not suitable suitable
PACKAGE(1)
BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(5)(6) suitable
not recommended(7)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jul 04
55
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
15 DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16 DEFINITIONS
17 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 04
56
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© Koninklijke Philips Electronics N.V. 2003
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Printed in The Netherlands
613502/01/pp57
Date of release: 2003 Jul 04
Document order number: 9397 750 10125
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