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TDA8034HN/C1 [NXP]

SPECIALTY CONSUMER CIRCUIT, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-1, HVQFN-24;
TDA8034HN/C1
型号： TDA8034HN/C1
厂家： NXP    NXP
描述：

SPECIALTY CONSUMER CIRCUIT, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT616-1, HVQFN-24

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TDA8034HN  
Smart card interface  
Rev. 3.1 — 5 September 2011  
Product data sheet  
1. General description  
The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous  
smart cards operating at 5 V, 3 V or 1.8 V. Using few external components, the  
TDA8034HN provides all supply, protection and control functions between a smart card  
and the microcontroller.  
2. Features and benefits  
Integrated circuit smart card interface in an HVQFN24 package  
5 V, 3 V or 1.8 V smart card supply  
Very low power consumption in Deep Shutdown mode  
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)  
VCC regulation:  
5 V, 3 V or 1.8 V 5 % using two low ESR multilayer ceramic capacitors: one of  
220 nF and one of 470 nF  
current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC =1.8 V) up to  
20 MHz, with controlled rise and fall times and filtered overload detection of  
approximately 120 mA  
Thermal and short-circuit protection for all card contacts  
Automatic activation and deactivation sequences triggered by a short-circuit, card  
take-off, overheating, falling VDD, VDD(INTF) or VDDP  
Enhanced card-side ElectroStatic Discharge (ESD) protection of > 6 kV  
External clock input up to 26 MHz connected to pin XTAL1  
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with  
synchronous frequency changes of fxtal, 12 fxtal, 14 fxtal or 18 fxtal  
Non-inverted control of pin RST using pin RSTIN  
Compatible with ISO 7816, NDS and EMV 4.2 payment systems  
Supply supervisor for killing spikes during power on and off:  
using a fixed threshold  
using an external resistor bridge with threshold adjustment  
Built-in debouncing on card presence contacts (typically 8 ms)  
Multiplexed status signal using pin OFFN  
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
3. Applications  
Pay TV  
Electronic payment  
Identification  
Bank card readers  
4. Quick reference data  
Table 1.  
Quick reference data  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supply  
VDDP  
power supply voltage  
pin VDDP; regulator input  
VCC = 5 V  
4.85  
5
5.5  
V
VCC = 3 V and 1.8 V  
pin VDD  
3
3.3  
5.5  
V
VDD  
supply voltage  
2.7  
3.3  
3.6  
V
VDD(INTF) interface supply voltage  
pin VDD(INTF)  
1.6  
3.3  
VDD + 0.3  
V
IDD  
supply current  
shutdown mode  
deep shutdown mode  
active mode  
-
-
-
-
-
-
-
-
-
-
35  
12  
2
A  
A  
mA  
A  
mA  
IDDP  
power supply current  
shutdown mode; fxtal stopped  
active mode; fCLK = 12 fxtal  
5
;
1.5  
no load  
IDD(INTF)  
interface supply current  
shutdown mode  
active mode  
-
-
-
-
6
2
A  
mA  
[1]  
Card supply voltage: pin VCC  
VCC supply voltage  
active mode; ICC < 65 mA DC  
5 V card  
4.75  
2.85  
1.71  
5.0  
5.25  
3.15  
1.89  
V
V
V
3 V card  
3.05  
1.83  
1.8 V card  
active mode; current pulses of  
40 nA/s at ICC < 200 mA;  
t < 400 ns  
5 V card  
3 V card  
4.65  
2.76  
1.66  
5.0  
5.25  
3.20  
1.94  
V
V
V
-
-
active mode; current pulses of  
15 nA/s at ICC < 200 mA,  
t < 400 ns; 1.8 V card  
Vripple(p-p) peak-to-peak ripple voltage  
from 20 kHz to 200 MHz  
-
-
-
-
350  
65  
mV  
mA  
ICC  
supply current  
VCC = 0 V to 5 V, 3 V or 1.8 V  
General  
tdeact  
Ptot  
deactivation time  
see Figure 8 on page 11  
35  
-
90  
-
250  
0.25  
+85  
s  
W
total power dissipation  
ambient temperature  
Tamb = 25 C to +85 C  
Tamb  
25  
-
C  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
2 of 30  
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
[1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of  
either 100 nF or one 220 nF and one 470 nF.  
5. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
TDA8034HN/C1  
HVQFN24  
plastic thermal enhanced very thin quad flat package; no leads;  
SOT616-1  
24 terminals; body 4 4 0.85 mm  
6. Block diagram  
10 μF  
100 nF  
100 nF  
V
V
DDP  
DD  
GND  
12  
17  
16  
V
DD(INTF)  
R1  
SUPPLY  
INTERNAL  
REFERENCE  
INTERNAL  
OSCILLATOR  
PORADJ 18  
(1)  
R2  
VOLTAGE  
SENSE  
CLKUP  
ALARMN  
EN1  
15  
V
CC  
V
LDO  
CC  
8
PVCC  
PRESN  
RSTIN  
220 nF  
470 nF  
3
SEQUENCER  
14  
13  
EN4  
EN3  
RST  
CLK  
RESET  
GENERATOR  
5
CMDVCCN  
OFFN  
19  
6
CLOCK  
CIRCUIT  
CLOCK  
GENERATOR  
LEVEL  
SHIFTER  
EN2  
CARD  
CONNECTOR  
CLK  
CLKDIV1  
CLKDIV2  
VCC_SEL2  
7
C5 C1  
C6 C2  
C7 C3  
C8 C4  
2
CRYSTAL  
OSCILLATOR  
THERMAL  
PROTECTION  
4
9
10  
11  
I/O  
VCC_SEL1  
I/OUC  
I/O  
20  
TRANSCEIVER  
TDA8034HN  
AUX1  
AUX2  
I/O  
21  
22  
TRANSCEIVER  
AUX1UC  
AUX2UC  
I/O  
TRANSCEIVER  
1
23  
24  
XTAL2  
100 nF  
XTAL1  
V
001aal136  
DD(INTF)  
ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals.  
(1) Optional external resistor bridge, if not required connect pin PORADJ to VDD(INTF)  
Fig 1. Block diagram  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
3 of 30  
 
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
7. Pinning information  
7.1 Pinning  
terminal 1  
index area  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
V
PORADJ  
DD(INTF)  
VCC_SEL2  
RSTIN  
V
V
V
DD  
DDP  
CC  
TDA8034HN  
VCC_SEL1  
CMDVCCN  
CLKDIV1  
RST  
CLK  
Transparent top view  
001aal137  
Fig 2. Pin configuration  
7.2 Pin description  
Table 3.  
Pin description  
Pin Supply Type[1] Description  
Symbol  
VDD(INTF)  
VCC_SEL2  
1
2
VDD(INTF)  
VDD(INTF)  
P
I
interface supply voltage  
5 V or 3 V VCC voltage selection control signal:  
active LOW: VCC = 3 V when pin VCC_SEL1 is HIGH  
active HIGH: VCC = 5 V  
RSTIN  
3
4
VDD(INTF)  
VDD(INTF)  
I
I
microcontroller card reset input; active HIGH  
1.8 V VCC voltage selection control signal:  
active LOW: VCC = 1.8 V  
VCC_SEL1  
active HIGH: disables 1.8 V selection  
microcontroller start activation sequence input; active LOW  
sets the clock frequency on pin CLK in association with pin CLKDIV2; see Table 4  
sets the clock frequency on pin CLK in association with pin CLKDIV1; see Table 4  
card presence contact input; active LOW[2]  
card input/output data line (C7)[3]  
auxiliary card input/output data line (C4)[3]  
auxiliary card input/output data line (C8)[3]  
ground  
CMDVCCN  
CLKDIV1  
CLKDIV2  
PRESN  
I/O  
5
6
7
8
9
VDD(INTF)  
VDD(INTF)  
VDD(INTF)  
VDD(INTF)  
VCC  
I
I
I
I
I/O  
I/O  
I/O  
G
O
O
P
AUX1  
AUX2  
GND  
10 VCC  
11 VCC  
12  
-
CLK  
13 VCC  
14 VCC  
15 VCC  
card clock (C3)  
RST  
card reset (C2)  
VCC  
card supply (C1); decouple to pin GND using one 470 nF capacitor close to pin VCC  
and one 220 nF capacitor close to card socket contact C1 with an ESR < 100 m  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
4 of 30  
 
 
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
Table 3.  
Symbol  
VDDP  
Pin description …continued  
Pin Supply Type[1] Description  
16 VDDP  
P
P
I
low-dropout regulator input supply voltage  
digital supply voltage  
VDD  
17 VDD  
PORADJ  
OFFN  
18 VDD(INTF)  
19 VDD(INTF)  
power-on reset threshold adjustment input using an optional external resistor bridge  
NMOS interrupt to microcontroller[4]; active LOW; see Section 8.10 on page 11  
microcontroller input/output data line[5]  
auxiliary microcontroller input/output data line[5]  
auxiliary microcontroller input/output data line[5]  
crystal connection input  
O
I/OUC  
20 VDD(INTF) I/O  
21 VDD(INTF) I/O  
22 VDD(INTF) I/O  
AUX1UC  
AUX2UC  
XTAL1  
XTAL2  
23 VDD  
24 VDD  
I
O
crystal connection output  
[1] I = input, O = output, I/O = input/output, G = ground and P = power supply.  
[2] If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter  
this, the TDA8034HN has a built-in debouncing timer (typically 8 ms).  
[3] Uses an internal 11 kpull-up resistor connected to pin VCC  
.
[4] Uses an internal 20 kpull-up resistor connected to pin VDD(INTF)  
.
[5] Uses an internal 10kpull-up resistor connected to pin VDD(INTF)  
8. Functional description  
Remark: Throughout this document the ISO 7816 terminology conventions have been  
adhered to and it is assumed that the reader is familiar with these.  
8.1 Power supplies  
The power supply voltage ranges are as follows:  
• VDDP: 4.85 V to 5.5 V when VCC_SEL2 is HIGH (VCC = 5 V)  
• VDDP: 3 V to 5.5 V when VCC_SEL2 is LOW (VCC = 3 V) or when VCC_SEL1 is LOW  
(VCC = 1.8 V)  
• VDD: 2.7 V to 3.6 V  
All interface signals to the system controller are referenced to VDD(INTF). All card contacts  
remain inactive during power up or power down. After powering up the device, pin OFFN  
remains LOW until pin CMDVCCN is set HIGH and pin PRESN is LOW. During power  
down, pin OFFN goes LOW when VDDP falls below the falling threshold voltage (Vth).  
The internal oscillator frequency (fosc(int)) is only used during the activation sequences.  
When the card is not activated (pin CMDVCCN is HIGH), the internal oscillator is in low  
frequency mode to reduce power consumption.  
This device has a Low Drop-Off (LDO) voltage regulator connected to pin VCC, and is  
used instead of a DC-to-DC converter. It ensures a minimum VCC of 4.75 V and that the  
power supply voltage on pin VDDP does not fall below 4.85 V when pin VCC_SEL2 is  
HIGH, for a maximum load current of 65 mA.  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
5 of 30  
 
 
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
8.2 Voltage supervisor  
V
DD(INTF)  
R1  
PORADJ  
R2  
V
DD  
V
REFERENCE  
VOLTAGE  
DD  
V
DDP  
VCC_SEL2  
001aal138  
Fig 3. Voltage supervisor circuit  
The voltage supervisor monitors the voltage of the VDDP, VDD and VDD(INTF) supplies  
providing both Power-On Reset (POR) and supply drop-out detection during a card  
session. The supervisor threshold voltages for VDDP and VDD are set internally, and for  
V
DD(INTF) externally by pin PORADJ. As long as VDD is less than Vth + Vhys, the IC remains  
inactive irrespective of the command line levels. After VDD has reached a level higher than  
Vth + Vhys, the IC remains inactive for the duration of tw. The output of the supervisor is  
sent to a digital controller in order to reset the TDA8034HN. This defined reset pulse of  
approximately 8 ms, i.e. (tw = 1024 1fosc(int)low), is used internally to maintain the IC in  
the Shutdown mode during the supply voltage power on; see Figure 4. A deactivation  
sequence is performed when either VDD, VDDP or VDD(INTF) falls below Vth.  
Remark: fosc(int)low is the low frequency (or inactive) mode of the defined fosc(int)  
parameter.  
V
+ V  
hys  
th  
V
th  
V
DD  
ALARMN  
(internal signal)  
t
t
w
w
power on  
supply dropout  
power off  
001aak993  
Fig 4. Voltage supervisor waveforms  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
6 of 30  
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
8.3 Clock circuits  
The clock signal from pin CLK to the card is either supplied by an external clock signal  
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and  
XTAL2. The TDA8034HN automatically detects if an external clock is connected to  
XTAL1, eliminating the need for a separate pin to select the clock source.  
Automatic clock source detection is performed on each activation command (falling edge  
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is  
checked during a time window defined by the internal oscillator. If a clock is detected, the  
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator  
is started. When an external clock is used, it is mandatory that the clock is applied to pin  
XTAL1 before the falling edge of the signal on pin CMDVCCN.  
DIGITAL  
enclkin  
clkxtal  
MULTIPLEXER  
CRYSTAL  
XTAL1  
XTAL2  
001aak992  
enclkin and clkxtal are internal signal names.  
Fig 5. Basic layout for using an external clock  
The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either fxtal  
12 fxtal or 14 fxtal or 18 fxtal as shown in Table 4.  
,
Remark: The levels on both pins must not be allowed to change simultaneously but  
should be separated by a minimum of 10 ns.  
The frequency change is synchronous and as such during transition, no pulse is shorter  
than 45 % of the smallest period. In addition, only the first and last clock pulse around the  
change has the correct width. When dynamically changing the frequency, the modification  
is only effective after 10 clock periods on pin XTAL1.  
The duty cycle of fxtal on pin CLK should be between 45 % and 55 %. If an external clock  
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.  
When the frequency of the clock signal on pin CLK is either fxtal, 12 fxtal, 14 fxtal or  
18 fxtal, the frequency dividers guarantee a duty cycle between 45 % and 55 %.  
Table 4.  
Clock configuration  
Pin CLKDIV1 level  
Pin CLKDIV2 level  
Pin CLK frequency  
LOW  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
HIGH  
LOW  
18 fxtal  
14 fxtal  
12 fxtal  
fxtal  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
7 of 30  
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
8.4 Input and output circuits  
When pins I/O and I/OUC are pulled HIGH using an 11 kresistor between pins I/O and  
CC and/or between pins I/OUC and VDD(INTF), both lines enter the idle state. Pin I/O is  
V
referenced to VCC and pin I/OUC to VDD(INTF), thus allowing operation at VCC VDD(INTF)  
.
The first side on which a falling edge occurs becomes the master. An anti-latch circuit  
disables falling edge detection on the other line, making it the slave. After a time delay td,  
the logic 0 present on the master-side is sent to the slave-side. When the master-side  
returns logic 1, the slave-side sends logic 1 during time delay (tw(pu)). After this sequence,  
both master and slave sides return to their idle states.  
The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8034HN  
capable of delivering more than 1 mA, up to an output voltage of 0.9VCC, at a load of  
80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the  
internal pull-up resistor value and load current. The current sent to and received from the  
card’s I/O lines is limited to 15 mA at a maximum frequency of 1 MHz.  
8.5 Shutdown mode  
After a power-on reset, if pin CMDVCCN is HIGH, the circuit enters the Shutdown mode,  
ensuring only the minimum number of circuits are active while the TDA8034HN waits for  
the microcontroller to start a session.  
• all card contacts are inactive. The impedance between the contacts and GND is  
approximately 200 .  
• pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 kpull-up  
resistor connected to VDD(INTF)  
• the voltage generators are stopped  
• the voltage supervisor is active  
• the internal oscillator runs at its lowest frequency (fosc(int)low  
)
8.6 Deep shutdown mode  
When the smart card reader is inactive, the TDA8034HN will enter Deep shutdown mode  
if pin CMDVCCN is forced HIGH and pins VCC_SEL1 and VCC_SEL2 are LOW. In Deep  
shutdown mode, all circuits are disabled and pin OFFN follows the status of pin PRESN.  
Changing the status of either pin CMDVCCN, VCC_SEL1 or VCC_SEL2 exits Deep  
shutdown mode; see Figure 6.  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
8 of 30  
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
deactivation  
sequence  
CMDVCCN  
VCC_SEL1  
VCC_SEL2  
shutdown  
shutdown  
shutdown  
activation  
mode  
(internal pin)  
activation  
deep shutdown  
debounce  
OFFN  
PRESN  
V
CC  
001aal139  
Fig 6. Shutdown and Deep shutdown mode activation/deactivation  
8.7 Activation sequence  
The following device activation sequence is applied when using an external clock; see  
Figure 7:  
1. Pin CMDVCCN is pulled LOW (t0).  
2. The internal oscillator is triggered (t0).  
3. The internal oscillator changes to high frequency (t1).  
4. VCC rises from either 0 V to 3 V or 0 V to 5 V on a controlled slope (t2).  
5. Pins I/OUC, AUX1UC and AUX2UC are driven HIGH (t3).  
6. The clock on pin CLK is applied to the C3 contact (t4).  
7. Pin RST is enabled (t5).  
Calculation of the time delays is as follows:  
• t1 = t0 + 384 1fosc(int)low  
• t2 = t1  
• t3 = t1 + 17T / 2  
• t4 = driven by host controller; > t3 and < t5  
• t5 = t1 + 23T / 2  
Remark: The value of period T is 64 times the period interval of the internal oscillator at  
high frequency (1fosc(int)high); t3 is called td(start) and t5 is called td(end)  
.
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
9 of 30  
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
CMDVCCN  
XTAL1  
V
CC  
I/O  
ATR  
CLK  
> 200 ns  
RSTIN  
RST  
I/OUC  
OSCINT  
low frequency  
t0 t1 = t2  
high frequency  
t4  
t
= t  
d(end) act  
t
d(start)  
001aal140  
OSCINT = internal oscillator.  
Fig 7. Activation sequence at t3  
8.8 Deactivation sequence  
When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034HN  
then executes an automatic deactivation sequence by counting the sequencer back to the  
inactive state (see Figure 8) as follows:  
1. Pin RST is pulled LOW (t11).  
2. The clock is stopped, pin CLK is LOW (t12).  
3. Pins I/OUC, AUX1UC and AUX2UC are pulled LOW (t13).  
4. VCC falls to 0 V (t14). The deactivation sequence is completed when VCC reaches its  
inactive state.  
5. VCC < 0.4 V (tdeac  
)
6. All card contacts become low-impedance to GND. However, pins I/OUC, AUX1UC  
and AUX2UC remain pulled up to VDD using the 11 kresistor.  
7. The internal oscillator returns to its low frequency mode.  
Calculation of the time delays is as follows:  
• t11 = t10 + 3T / 64  
• t12 = t11 + T / 2  
• t13 = t11 + T  
• t14 = t11 + 3T / 2  
• tdeac = t11 + 3T / 2 + VCC fall time  
TDA8034HN  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
10 of 30  
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
Remark: The value of period T is 64 times the period interval of the internal oscillator (i.e.  
25 s).  
CMDVCC  
RST  
CLK  
I/O  
V
CC  
XTAL1  
OSCINT  
high frequency  
t10 t11 t12  
low frequency  
t13  
t14  
t
001aak995  
deact  
OSCINT = internal oscillator.  
Fig 8. Deactivation sequence  
8.9 VCC regulator  
The VCC buffer is able to continuously deliver up to 65 mA at VCC = 5 V, 3 V, or 1.8 V.  
The VCC buffer has an internal overload protection with a threshold value of approximately  
120 mA. This detection is internally filtered, enabling spurious current pulses up to  
200 mA with a duration of a few milliseconds to be drawn by the card without causing  
deactivation. However, the average current value must stay below maximum; see Table 8.  
8.10 Fault detection  
The following conditions are monitored by the fault detection circuit:  
• Short-circuit or high current on pin VCC  
• Card removal during transaction  
• VDDP falling  
• VDD falling  
• VDD(INTF) falling  
• Overheating  
Fault detection monitors two different situations:  
• Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in  
the reader and HIGH if the card is in the reader. Any voltage drop on VDD is detected  
by the voltage supervisor. This generates an internal power-on reset pulse but does  
not act upon the pin OFFN signal. The card is not powered-up and short-circuits or  
overheating are not detected.  
TDA8034HN  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
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TDA8034HN  
NXP Semiconductors  
Smart card interface  
• In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault  
detection circuit triggers the automatic emergency deactivation sequence (see  
Figure 9). When the microcontroller resets pin CMDVCCN to HIGH, after the  
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN  
returns to HIGH. This check identifies the fault as either a hardware problem or a card  
removal incident.  
On card insertion or removal, bouncing can occur in the PRESN signal. This depends on  
the type of card presence switch in the connector (normally open or normally closed) and  
the mechanical characteristics of the switch. To correct for this, a debouncing feature is  
integrated in to the TDA8034HN. This feature operates at a typical duration of 8 ms  
(tdeb = 640 (1fosc(int)low). Figure 10 on page 13 shows the operation of the debouncing  
feature.  
On card insertion, pin OFFN goes HIGH after the debounce time has elapsed. When the  
card is extracted, the automatic card deactivation sequence is performed on the first  
HIGH/LOW transition on pin PRESN. After this, pin OFFN goes LOW.  
OFFN  
PRESN  
RST  
CLK  
I/O  
V
CC  
XTAL1  
OSCINT  
high frequency  
low frequency  
t10  
t12  
t
t13  
t14  
001aal141  
deact  
Fig 9. Emergency deactivation sequence after card removal  
TDA8034HN  
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Product data sheet  
Rev. 3.1. — 5 September 2011  
12 of 30  
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
PRESN  
OFFN  
CMDVCCN  
t
t
deb  
deb  
(1)  
(2)  
V
CC  
001aal411  
(1) Deactivation caused by card withdrawal.  
(2) Deactivation caused by short-circuit.  
Fig 10. Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and VCC  
9. Limiting values  
Remark: All card contacts are protected against any short-circuit to any other card  
contact. Stress beyond the levels indicated in Table 5 can cause permanent damage to  
the device. This is a short-term stress rating only and under no circumstances implies  
functional operation under long-term stress conditions.  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDDP  
Parameter  
Conditions  
pin VDDP  
Min  
Max  
+6  
Unit  
V
power supply voltage  
supply voltage  
0.3  
0.3  
0.3  
0.3  
VDD  
pin VDD  
+4.6  
+4.6  
+4.6  
V
VDD(INTF)  
VI  
interface supply voltage  
input voltage  
pin VDD(INTF)  
V
pins CMDVCCN, CLKDIV1, CLKDIV2,  
VCC_SEL1, VCC_SEL2, RSTIN, OFFN,  
PORADJ, XTAL1, XTAL2, I/OUC, AUX1UC,  
AUX1UC  
V
card contact pins PRESN, I/O, RST, AUX1,  
AUX2 and CLK  
0.3  
+6  
V
Tstg  
Ptot  
Tj  
storage temperature  
55  
-
+150  
0.25  
+125  
+85  
+6  
C  
W
total power dissipation  
junction temperature  
Tamb = 25 C to +85 C  
-
C  
C  
kV  
Tamb  
VESD  
ambient temperature  
electrostatic discharge voltage  
25  
6  
Human Body Model (HBM) on card pins I/O,  
RST, VCC, AUX1, AUX2, CLK, PRESN;  
within typical application  
Human Body Model (HBM); all other pins  
Machine Model (MM); all pins  
2  
+2  
kV  
V
200  
500  
+200  
+500  
Field Charged Device Model (FCDM); all  
pins  
V
TDA8034HN  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
13 of 30  
 
 
 
TDA8034HN  
NXP Semiconductors  
Smart card interface  
10. Thermal characteristics  
Table 6.  
Symbol Package name  
Rth(j-a) HVQFN24  
Thermal characteristics  
Parameter  
Conditions  
Typ  
Unit  
thermal resistance from junction to ambient  
in free air  
53  
K/W  
11. Characteristics  
Table 7.  
Characteristics of IC supply voltage  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supply  
VDDP  
power supply voltage  
pin VDDP  
VCC = 5 V  
4.85  
5
5.5  
V
VCC = 3 V or 1.8 V  
pin VDD  
3
3.3  
3.3  
3.3  
-
5.5  
V
VDD  
supply voltage  
2.7  
3.6  
V
VDD(INTF) interface supply voltage pin VDD(INTF)  
1.6  
VDD + 0.3  
V
IDD  
supply current  
shutdown mode  
deep shutdown mode  
active mode  
-
-
-
35  
12  
2
A  
A  
mA  
-
-
IDDP  
power supply current  
shutdown mode  
f
xtal stopped  
-
-
5
A  
active mode  
fCLK = 12 fxtal; no load  
-
-
-
-
1.5  
70  
mA  
mA  
fCLK = 12 fxtal  
;
ICC = 65 mA  
IDD(INTF) interface supply current shutdown mode  
active mode  
-
-
-
-
6
2
A  
mA  
Vth  
threshold voltage  
no external resistors on pin  
PORADJ  
pin VDD falling  
2.30  
3.00  
2.40  
4.10  
2.50  
4.40  
V
V
pin VDDP falling;  
VCC = 5 V  
external resistors on pin  
PORADJ  
1.20  
1.24  
1.29  
V
Vhys  
hysteresis voltage  
no external resistors on pin  
PORADJ  
pin VDD  
50  
100  
200  
8
150  
350  
10.2  
+10  
+1  
mV  
mV  
ms  
A  
A  
pin VDDP; VCC = 5 V  
100  
5.1  
0.1  
1  
tw  
IL  
pulse width  
leakage current  
pin PORADJ < 0.5 V  
pin PORADJ > 1 V  
+4  
-
[1]  
Card supply voltage: pin VCC  
[2]  
Cdec  
decoupling capacitance connected to VCC  
550  
-
830  
nF  
TDA8034HN  
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Product data sheet  
Rev. 3.1. — 5 September 2011  
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TDA8034HN  
NXP Semiconductors  
Smart card interface  
Table 7.  
Characteristics of IC supply voltage …continued  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Shutdown mode  
no load  
Min  
Typ  
Max  
Unit  
Vo  
output voltage  
0.1  
0.1  
-
-
-
-
+0.1  
+0.3  
1  
V
Io = 1 mA  
V
Io  
output current  
supply voltage  
Shutdown mode; pin VCC  
connected to ground  
mA  
VCC  
active mode; ICC < 65 mA  
DC  
5 V card  
3 V card  
1.8 V card  
4.75  
2.85  
1.71  
5.0  
5.25  
3.15  
1.89  
V
V
V
3.05  
1.83  
active mode; current pulses  
of 40 nA/s at ICC < 200 mA;  
t < 400 ns  
5 V card  
3 V card  
4.65  
2.76  
1.66  
5.0  
5.25  
3.20  
1.94  
V
V
V
-
-
active mode; current pulses  
of 15 nA/s at ICC < 200 mA,  
t < 400 ns;1.8 V card  
Vripple(p-p) peak-to-peak ripple  
voltage  
20 kHz to 200 MHz  
-
-
-
-
350  
65  
mV  
mA  
ICC  
supply current  
VCC = 0 V to 5 V, 3 V or  
1.8 V  
V
CC shorted to ground  
90  
120  
150  
0.3  
0.3  
0.3  
mA  
SR  
slew rate  
5 V card  
3 V card  
1.8 V card  
0.055  
0.040  
0.025  
0.18  
0.18  
0.18  
V/s  
V/s  
V/s  
Crystal oscillator: pins XTAL1 and XTAL2  
Cext  
external capacitance  
pins XTAL1 and XTAL2  
(depending on the crystal or  
resonator specification)  
-
-
-
15  
26  
pF  
fxtal  
crystal frequency  
external frequency  
card clock reference; crystal  
oscillator  
2
MHz  
fext  
VIL  
external clock on pin XTAL1  
crystal oscillator  
external clock  
0
-
-
-
-
-
26  
MHz  
V
LOW-level input  
voltage  
0.3  
+0.3VDD  
0.3  
+0.3VDD(INTF)  
VDD + 0.3  
VDD(INTF) + 0.3  
V
VIH  
HIGH-level input  
voltage  
crystal oscillator  
external clock  
0.7VDD  
0.7VDD(INTF)  
V
V
Data lines: pins I/O, I/OUC, AUX1, AUX2, AUXIUC and AUX2UC  
td  
delay time  
falling edge on pins I/O and  
I/OUC or vise versa  
-
-
200  
ns  
tw(pu)  
fio  
pull-up pulse width  
200  
-
-
-
400  
1
ns  
input/output frequency on data lines  
input capacitance on data lines  
-
-
MHz  
pF  
Ci  
10  
TDA8034HN  
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Product data sheet  
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15 of 30  
TDA8034HN  
NXP Semiconductors  
Smart card interface  
Table 7.  
Characteristics of IC supply voltage …continued  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Data lines to the card: pins I/O, AUX1and AUX2[3]  
Vo  
output voltage  
output current  
Shutdown mode  
no load  
0
0
-
-
-
-
0.1  
0.3  
1  
V
Io = 1 mA  
V
Io  
Shutdown mode; pin I/O  
grounded  
mA  
VOL  
LOW-level output  
voltage  
IOL = 1 mA  
0
-
-
-
-
-
-
-
0.3  
V
V
V
V
V
V
V
IOL 15 mA  
VCC 0.4  
0.9VCC  
0.75VCC  
0.75VCC  
0
VCC  
VOH  
HIGH-level output  
voltage  
no DC load  
VCC + 0.1  
VCC + 0.1  
VCC + 0.1  
0.4  
IOH < 40 A; 5 V or 3 V  
IOH < 20 A; 1.8 V  
IOH  15 mA  
VIL  
VIH  
LOW-level input  
voltage  
0.3  
+0.8  
HIGH-level input  
voltage  
VCC = 5 V  
0.6VCC  
-
VCC + 0.3  
V
VCC = 3 V or 1.8 V  
pin I/O  
0.7VCC  
-
VCC + 0.3  
V
Vhys  
IIL  
hysteresis voltage  
-
-
-
50  
-
-
mV  
A  
A  
LOW-level input current pin I/O; VIL = 0 V  
600  
10  
IIH  
HIGH-level input  
current  
pin I/O; VIH = VCC  
-
tr(i)  
tr(o)  
tf(i)  
input rise time  
output rise time  
input fall time  
output fall time  
VIL maximum to  
VIH minimum  
-
-
-
-
-
-
-
-
1.2  
0.1  
1.2  
0.1  
s  
s  
s  
s  
CL 80 pF; 10 % to 90 %;  
0 V to VCC  
VIL maximum to  
VIH minimum  
tf(o)  
CL 80 pF; 10 % to 90 %;  
0 V to VCC  
Rpu  
Ipu  
pull-up resistance  
pull-up current  
connected to VCC  
7
9
11  
k  
VOH = 0.9VCC; C = 80 pF  
8  
6  
4  
mA  
Data lines to the system: pins I/OUC, AUX1UC and AUX2UC[4]  
VOL  
LOW-level output  
voltage  
IOL = 1 mA  
0
-
0.3  
V
VOH  
HIGH-level output  
voltage  
no DC load  
0.9VDD(INTF)  
0.75VDD(INTF)  
0.75VDD(INTF)  
0.3  
-
-
-
-
VDD(INTF) + 0.1  
VDD(INTF) + 0.1  
VDD(INTF) + 0.1  
+0.3VDD(INTF)  
V
V
V
V
IOH 40 A; VDD(INTF) > 2 V  
IOH 20 A; VDD(INTF) < 2 V  
VIL  
VIH  
LOW-level input  
voltage  
HIGH-level input  
voltage  
0.7VDD(INTF)  
-
VDD(INTF) + 0.3  
V
Vhys  
IIH  
hysteresis voltage  
pin I/OUC  
-
-
0.14VDD(INTF)  
-
-
V
HIGH-level input  
current  
VIH = VDD(INTF)  
10  
A  
TDA8034HN  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3.1. — 5 September 2011  
16 of 30  
TDA8034HN  
NXP Semiconductors  
Smart card interface  
Table 7.  
Characteristics of IC supply voltage …continued  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
600  
12  
Unit  
A  
IIL  
LOW-level input current VIL = 0 V  
-
-
Rpu  
tr(i)  
pull-up resistance  
input rise time  
connected to VDD(INTF)  
8
-
10  
-
k  
s  
VIL maximum to  
VIH minimum  
1.2  
tr(o)  
tf(i)  
tf(o)  
Ipu  
output rise time  
input fall time  
output fall time  
pull-up current  
CL 30 pF; 10 % to 90 %;  
0 V to VDD(INTF)  
-
-
-
-
-
0.1  
1.2  
0.1  
-
s  
s  
s  
mA  
VIL maximum to  
VIH minimum  
-
CL 30 pF; 10 % to 90 %;  
0 V to VDD(INTF)  
-
VOH = 0.9VDD; C = 30 pF  
1  
Internal oscillator  
fosc(int) internal oscillator  
frequency  
Reset output to the card: pin RST  
Shutdown mode  
active state  
100  
2
150  
2.7  
200  
3.2  
kHz  
MHz  
Vo  
output voltage  
Shutdown mode  
no load  
0
0
-
-
-
-
0.1  
0.3  
1  
V
Io = 1 mA  
V
Io  
output current  
delay time  
Shutdown mode; pin RST  
grounded  
mA  
td  
between pins RSTIN and  
RST; RST enabled  
-
-
2
s  
VOL  
LOW-level output  
voltage  
IOL = 200 A; VCC = 5 V  
0
0
-
-
0.3  
0.2  
V
V
IOL = 200 A; VCC = 3 V or  
1.8 V  
current limit IOL = 20 mA  
IOH = 200 A  
VCC 0.4  
-
-
-
-
-
VCC  
VCC  
0.4  
V
VOH  
HIGH-level output  
voltage  
0.9VCC  
V
current limit IOH = 20 mA  
CL = 100 pF  
0
-
V
tr  
tf  
rise time  
fall time  
0.1  
s  
s  
CL = 100 pF  
-
0.1  
Clock output to the card: pin CLK  
Vo  
output voltage  
Shutdown mode  
no load  
0
0
-
-
-
-
0.1  
0.3  
1  
V
Io = 1 mA  
V
Io  
output current  
Shutdown mode; pin CLK  
grounded  
mA  
VOL  
LOW-level output  
voltage  
IOL = 200 A  
0
-
-
-
-
-
-
0.3  
VCC  
VCC  
0.4  
16  
V
current limit IOL = 70 mA  
IOH = 200 A  
VCC 0.4  
V
VOH  
HIGH-level output  
voltage  
0.9VCC  
V
current limit IOH = 70 mA  
CL = 30 pF  
0
-
V
[5]  
[5]  
tr  
tf  
rise time  
fall time  
ns  
ns  
CL = 30 pF  
-
16  
TDA8034HN  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
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17 of 30  
TDA8034HN  
NXP Semiconductors  
Smart card interface  
Table 7.  
Characteristics of IC supply voltage …continued  
VDDP = 5 V; VDD = 3.3 V; VDD(INTF) = 3.3 V; fxtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified.  
Symbol Parameter  
fCLK frequency on pin CLK operational  
Conditions  
Min  
0
Typ  
Max  
20  
Unit  
MHz  
%
-
-
[5]  
duty cycle  
slew rate  
CL = 30 pF  
45  
55  
SR  
rise and fall; CL = 30 pF  
VCC = 5 V  
0.2  
-
-
-
-
V/ns  
V/ns  
VCC = 3 V or 1.8 V  
0.12  
Control inputs: pins CLKDIV1, CLKDIV2, RSTIN, VCC_SEL1 and VCC_SEL2[6]  
VIL  
LOW-level input  
voltage  
0.3  
-
-
0.3VDD(INTF)  
V
V
VIH  
HIGH-level input  
voltage  
0.7 VDD(INTF)  
VDD(INTF) + 0.3  
Vhys  
IIL  
hysteresis voltage  
control input  
-
-
-
0.14VDD(INTF)  
-
V
LOW-level input current VIL = 0 V  
-
-
1
1
A  
A  
IIH  
HIGH-level input  
current  
VIH = VDD(INTF)  
Control input: pin CMDVCCN[6]  
VIL  
LOW-level input  
voltage  
0.3  
-
-
0.3VDD(INTF)  
V
V
VIH  
HIGH-level input  
voltage  
0.7VDD(INTF)  
VDD(INTF) + 0.3  
Vhys  
IIL  
hysteresis voltage  
control input  
-
-
-
0.14VDD(INTF)  
-
V
LOW-level input current VIL = 0 V  
-
-
1
1
A  
A  
IIH  
HIGH-level input  
current  
VIH = VDD(INTF)  
fCMDVCCN frequency on pin  
CMDVCCN  
-
-
100  
Hz  
tw  
pulse width  
5 V card  
3 V card  
30  
-
-
-
-
ms  
ms  
15  
Card detection input: pin PRESN[6][7]  
VIL  
LOW-level input  
voltage  
0.3  
-
-
0.3VDD(INTF)  
V
V
VIH  
HIGH-level input  
voltage  
0.7VDD(INTF)  
VDD(INTF) + 0.3  
Vhys  
IIL  
hysteresis voltage  
pin PRESN  
-
-
-
0.14VDD(INTF)  
-
V
LOW-level input current 0 V < VIL < VDD(INTF)  
-
-
5
5
A  
A  
IIH  
HIGH-level input  
current  
0 V < VIH < VDD(INTF)  
OFFN output[8]  
VOL  
VOH  
Rpu  
LOW-level output  
voltage  
IOL = 2 mA  
0
-
0.3  
-
V
HIGH-level output  
voltage  
IOH = 15 A  
0.75VDD(INTF)  
16  
-
V
pull-up resistance  
connected to VDD(INTF)  
20  
24  
k  
TDA8034HN  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
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TDA8034HN  
NXP Semiconductors  
Smart card interface  
[1] To meet these specifications, VCC should be decoupled to pin GND using two ceramic multilayer capacitors of low ESR with values of  
one 220 nF and one 470 nF.  
[2] Using decoupling capacitors of one 220 nF 20 % and one 470 nF 20 %.  
[3] Using the integrated 9 kpull-up resistor connected to VCC  
.
[4] Using the integrated 10 kpull-up resistor connected to VDD(INTF)  
.
[5] The transition time and the duty factor definitions are shown in Figure 11 on page 19; = t1 / (t1 + t2).  
[6] Pins PRESN and CMDVCCN are active LOW; pin RSTIN is active HIGH; see Table 4 for states of pins CLKDIV1 and CLKDIV2.  
[7] Pin PRESN has an integrated current source of 1.25 A to VDD(INTF)  
.
[8] Pin OFFN is an NMOS drain, using an internal 20 kpull-up resistor connected to VDD(INTF)  
.
Table 8.  
Symbol  
IOlim  
Protection characteristics  
Parameter  
Conditions  
pin I/O  
Min  
15  
135  
70  
20  
90  
Typ  
-
Max  
+15  
225  
+70  
+20  
150  
-
Unit  
mA  
mA  
mA  
mA  
mA  
C  
output current limit  
pin VCC  
pin CLK  
pin RST  
pin VCC  
at die  
175  
-
-
Isd  
shutdown current  
120  
150  
Tsd  
shutdown temperature  
-
Table 9.  
Symbol  
tact  
Timing characteristics  
Parameter  
Conditions  
Min  
2090  
35  
Typ  
-
Max  
4160  
250  
Unit  
activation time  
deactivation time  
delay time  
see Figure 7 on page 10  
see Figure 8 on page 11  
s  
s  
tdeact  
td  
90  
CLK sent to card using an external clock  
td(start) = t3; see Figure 7 on page 10  
td(end) = t5; see Figure 7 on page 10  
pin PRESN  
2090  
2120  
3.2  
-
4112  
4160  
6.4  
s  
s  
ms  
-
tdeb  
debounce time  
4.5  
t
t
f
r
V
OH  
90 %  
90 %  
(V  
+ V ) / 2  
OL  
OH  
10 %  
10 %  
V
OL  
t1  
t2  
001aai973  
Fig 11. Definition of output and input transition times  
TDA8034HN  
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12. Application information  
V
MICROCONTROLLER  
DD(INTF)  
V
DD  
R1  
R2  
V
DD(INTF)  
24 23 22 21 20 19  
V
C1  
DD  
V
PORADJ  
DD(INTF)  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
C2  
100 nF  
100 nF VCC_SEL2  
RSTIN  
V
V
V
DD  
DDP  
CC  
TDA8034HN  
VCC_SEL1  
CMDVCCN  
CLKDIV1  
RST  
CLK  
V
DDP  
GND  
C3  
C4  
10 μF  
7
8
9
10 11 12  
100 nF  
C6  
220 nF  
CARD  
CONNECTOR  
C5  
470 nF  
C5 C1  
C6 C2  
C7 C3  
C8 C4  
R4  
0 Ω  
001aal142  
Fig 12. Application diagram  
TDA8034HN  
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13. Package outline  
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;  
24 terminals; body 4 x 4 x 0.85 mm  
SOT616-1  
B
A
D
terminal 1  
index area  
A
A
1
E
c
detail X  
e
1
C
1/2 e  
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12  
w
L
13  
6
e
e
E
h
2
1/2 e  
1
18  
terminal 1  
index area  
24  
19  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
(1)  
(1)  
UNIT  
mm  
A
b
c
E
e
e
e
y
D
D
E
L
v
w
y
1
1
h
1
2
h
0.05 0.30  
0.00 0.18  
4.1  
3.9  
2.25  
1.95  
4.1  
3.9  
2.25  
1.95  
0.5  
0.3  
0.05  
0.1  
1
0.2  
0.5  
2.5  
2.5  
0.1 0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-08-08  
02-10-22  
SOT616-1  
- - -  
MO-220  
- - -  
Fig 13. Package outline SOT616-1 (HVQFN24)  
TDA8034HN  
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14. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
14.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
14.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
• Through-hole components  
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
• Board specifications, including the board finish, solder masks and vias  
• Package footprints, including solder thieves and orientation  
• The moisture sensitivity level of the packages  
• Package placement  
• Inspection and repair  
• Lead-free soldering versus SnPb soldering  
14.3 Wave soldering  
Key characteristics in wave soldering are:  
• Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
• Solder bath specifications, including temperature and impurities  
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14.4 Reflow soldering  
Key characteristics in reflow soldering are:  
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 14) than a SnPb process, thus  
reducing the process window  
• Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 10 and 11  
Table 10. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 11. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 14.  
TDA8034HN  
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maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 14. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
15. Abbreviations  
Table 12. Abbreviations  
Acronym  
EMV  
Description  
Europay MasterCard VISA  
ElectroStatic Discharge  
Equivalent Series Resistor  
Field Charged Device Model  
Human Body Model  
ESD  
ESR  
FCDM  
HBM  
LDO  
Low Drop-Out  
MM  
Machine Model  
NMOS  
POR  
Negative-channel Metal-Oxide Semiconductor  
Power-On Reset  
TDA8034HN  
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16. Revision history  
Table 13. Revision history  
Document ID  
TDA8034HN v.3.1  
Modifications:  
Release date Data sheet status Change notice  
20110905 Product data sheet  
Supersedes  
-
TDA8034HN v.3.0  
• Table 1 “Quick reference data”: values added  
• Table 7 “Characteristics of IC supply voltage”: values added  
• Figure 1 “Block diagram”: Figure note (1) changed  
TDA8034HN v.3.0  
Modifications:  
20110117  
Product data sheet  
-
TDA8034HN v.2.0  
• Table 2 “Ordering information”: type number updated into TDA8034HN/C1  
• Table 3 “Pin description”: Table note [2] corrected  
TDA8034HN v.2.0  
Modifications:  
20101112  
Product data sheet  
-
TDA8034HN_1  
• Table 3 “Pin description”:  
Table note [4] VDD changed into VDD(INTF)  
Table note [5] added  
IOUC, AUX1UC, AUX2UC referenced to new note [5]  
TDA8034HN_1  
20100205  
Product data sheet  
-
-
TDA8034HN  
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17. Legal information  
17.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
17.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
17.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
TDA8034HN  
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Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
non-automotive qualified products in automotive equipment or applications.  
17.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
18. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
TDA8034HN  
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Product data sheet  
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Smart card interface  
19. Tables  
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2  
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3  
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4  
Table 4. Clock configuration . . . . . . . . . . . . . . . . . . . . . .7  
Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13  
Table 6. Thermal characteristics . . . . . . . . . . . . . . . . . .14  
Table 7. Characteristics of IC supply voltage . . . . . . . .14  
Table 8. Protection characteristics . . . . . . . . . . . . . . . .19  
Table 9. Timing characteristics . . . . . . . . . . . . . . . . . . .19  
Table 10. SnPb eutectic process (from J-STD-020C) . . .23  
Table 11. Lead-free process (from J-STD-020C) . . . . . .23  
Table 12. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .24  
Table 13. Revision history . . . . . . . . . . . . . . . . . . . . . . . .25  
TDA8034HN  
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Product data sheet  
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Smart card interface  
20. Figures  
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3  
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4  
Fig 3. Voltage supervisor circuit. . . . . . . . . . . . . . . . . . . .6  
Fig 4. Voltage supervisor waveforms. . . . . . . . . . . . . . . .6  
Fig 5. Basic layout for using an external clock. . . . . . . . .7  
Fig 6. Shutdown and Deep shutdown mode  
activation/deactivation . . . . . . . . . . . . . . . . . . . . . .9  
Fig 7. Activation sequence at t3. . . . . . . . . . . . . . . . . . .10  
Fig 8. Deactivation sequence . . . . . . . . . . . . . . . . . . . .11  
Fig 9. Emergency deactivation sequence after card  
removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Fig 10. Operation of debounce feature with pins OFFN,  
CMDVCCN, PRESN and VCC . . . . . . . . . . . . . . .13  
Fig 11. Definition of output and input transition times . . .19  
Fig 12. Application diagram . . . . . . . . . . . . . . . . . . . . . . .20  
Fig 13. Package outline SOT616-1 (HVQFN24) . . . . . . .21  
Fig 14. Temperature profiles for large and small  
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
TDA8034HN  
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Product data sheet  
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Smart card interface  
21. Contents  
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
7.1  
7.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
8
Functional description . . . . . . . . . . . . . . . . . . . 5  
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6  
Clock circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Input and output circuits . . . . . . . . . . . . . . . . . . 8  
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8  
Deep shutdown mode. . . . . . . . . . . . . . . . . . . . 8  
Activation sequence . . . . . . . . . . . . . . . . . . . . . 9  
Deactivation sequence . . . . . . . . . . . . . . . . . . 10  
VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 11  
8.1  
8.2  
8.3  
8.4  
8.5  
8.6  
8.7  
8.8  
8.9  
8.10  
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13  
Thermal characteristics . . . . . . . . . . . . . . . . . 14  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 14  
Application information. . . . . . . . . . . . . . . . . . 20  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21  
10  
11  
12  
13  
14  
Soldering of SMD packages . . . . . . . . . . . . . . 22  
Introduction to soldering . . . . . . . . . . . . . . . . . 22  
Wave and reflow soldering . . . . . . . . . . . . . . . 22  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23  
14.1  
14.2  
14.3  
14.4  
15  
16  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25  
17  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
17.1  
17.2  
17.3  
17.4  
18  
19  
20  
21  
Contact information. . . . . . . . . . . . . . . . . . . . . 27  
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 5 September 2011  
Document identifier: TDA8034HN  
 

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