TDA8596TH/N1S,118_技术文档

TDA8596

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical

inputs

Rev. 02 — 8 November 2007

Product data sheet

1. General description

The TDA8596 is a quad Bridge Tied Load (BTL) audio power ampliﬁer with symmetrical

inputs, made in BCDMOS technology. It contains four independent ampliﬁer channels in

BTL conﬁguration with complementary (PMOST/NMOST) output stages. Temperature

warning and output signal clipping diagnosis is possible via the I²C-bus and via the

diagnostic pins (DIAG and STB pin). The temperature pre-warning level and clip detection

levels can be programmed via the I²C-bus. The status of each ampliﬁer channel (i.e.

output offset, load connected or not, short circuit condition at the output pins) can be read

out separately.

2. Features

2.1 General

I Operates in legacy mode (non I²C-bus) and I²C-bus mode (3.3 V and 5 V compliant)

I Three hardware-programmable I²C-bus addresses

I Drives 4 Ω or 2 Ω loads

I Balanced/symmetrical inputs

I Speaker fault detection

I Programmable gain (26 dB and 16 dB) also available in legacy mode

I Independent short circuit protection per channel

I Loss of ground and loss of V_Psafe (with 300 mΩ series impedance and a maximum

supply decoupling capacitor of 2200 µF)

I All outputs are short-circuit proof to ground, supply voltage and across the load

I All pins are short circuit proof to ground

I Temperature-controlled gain reduction to prevent audio holes at high junction

temperatures

I Low battery voltage detection

I Qualiﬁed in accordance with AEC-Q100

2.2 I²C-bus mode

I DC load detection: open (no load), normal load, line-driver load

I AC load (tweeter) detection

I Detect which load is connected during start-up to allow the system to be conﬁgured to

select the gain accordingly (e.g. line-driver mode or normal mode).

I Independently selectable soft mute of front (channel 1 and channel 3) and rear

channels (channel 2 and channel 4)

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

I Independently programmable gain (26 dB and 16 dB) of front (channel 1 and channel

3) and rear (channel 2 and channel 4) channels

I Flexible programmable diagnostic levels:

N Programmable clip detect: 2 %, 5 % or 10 %

N Programmable thermal pre-warning

I Selectable information on the DIAG or STB pin:

N The STB pin can be programmed/multiplexed with second clip detection

N Clip information of each channel separately can be directed to the DIAG pin or the

STB pin

N Independent enabling of thermal-, clip- or load fault (short across the load, to V_Por

to ground) available on the DIAG pin

I Offset detection

3. Quick reference data

Table 1.

Quick reference data

Symbol

Parameter

Conditions

R_L= 4 Ω

no load

Min Typ Max Unit

V_P

I_q

supply voltage

quiescent current

output power

8

14.4 18

V

-

270

40

400

mA

W

P_o

R_L= 4 Ω; V_P= 14.4 V;

maximum power; V_i= 2 V

(RMS) square wave

37

-

R_L= 4 Ω; V_P= 14.4 V;

THD = 0.5 %

18

23

58

20

25

64

-

W

R_L= 4 Ω; V_P= 14.4 V;

THD = 10 %

R_L= 2 Ω; V_P= 14.4 V;

maximum power; V_i= 2 V

(RMS) square wave

THD

V_n(o)

total harmonic

distortion

R_L= 4 Ω; f = 1 kHz;

P_o= 1 W to 12 W

-

0.01 0.1

%

noise output voltage

ﬁlter 20 Hz to 22 kHz;

R_S= 1 kΩ

normal mode;

T_amb= 25 °C to 105 °C

-

45

22

65

µV

normal mode;

T_amb= −20 °C to 25 °C

110

29

line driver mode

4. Ordering information

Table 2.

Ordering information

Type number Package

Name

Description

Version

TDA8596TH

HSOP36 plastic, heatsink small outline package; 36 leads; low

stand-off height

SOT851-2

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

2 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

5. Block diagram

ADSEL SDA

28 26

SCL

21

V

P1

19, 20

P2

34, 35

33

DIAG

29

STANDBY/

FAST MUTE

SELECT DIAGNOSTIC/

CLIP DETECT

2

STB

I C-BUS

13

14

IN3+

18

17

OUT3+

26 dB/

16 dB

MUTE

OUT3−

IN3−

PROTECTION/

DIAGNOSTIC

7

6

IN1+

4

2

OUT1+

26 dB/

16 dB

OUT1−

IN1−

PROTECTION/

DIAGNOSTIC

11

12

IN4+

25

23

OUT4+

26 dB/

16 dB

OUT4−

IN4−

PROTECTION/

DIAGNOSTIC

9

8

IN2+

30

32

OUT2+

26 dB/

16 dB

OUT2−

IN2−

PROTECTION/

DIAGNOSTIC

V

P

36

TAB

TDA8596

27

10

SGND

22

GAINSEL

3

31

16

24

001aaf998

SVR

PGND1 PGND2 PGND3

PGND4

Fig 1. Block diagram

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

3 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

6. Pinning information

6.1 Pinning

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

1

2

TAB

n.c.

V

OUT1−

PGND1

OUT1+

n.c.

P2

3

4

DIAG

OUT2−

PGND2

OUT2+

STB

5

6

IN1−

7

IN1+

8

IN2−

9

ADSEL

SVR

IN2+

TDA8596TH

10

11

12

13

14

15

16

17

18

SGND

IN4+

SDA

OUT4+

PGND4

OUT4−

GAINSEL

SCL

IN4−

IN3+

IN3−

n.c.

PGND3

OUT3−

OUT3+

V

P1

V

001aaf999

Fig 2. Pin conﬁguration

6.2 Pin description

Table 3.

Symbol

n.c.

Pin description

1

Description

not connected

OUT1−

PGND1

OUT1+

n.c.

2

channel 1 negative output

power ground channel 1

channel 1 positive output

not connected

3

4

5

IN1−

6

channel 1 negative input

channel 1 positive input

channel 2 negative input

channel 2 positive input

signal ground

IN1+

7

IN2−

8

IN2+

9

SGND

IN4+

10

11

12

13

14

15

channel 4 positive input

channel 4 negative input

channel 3 positive input

channel 3 negative input

not connected

IN4−

IN3+

IN3−

n.c.

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

4 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 3.

Pin description …continued

Symbol

PGND3

OUT3−

OUT3+

V_P1

16

Description

power ground channel 3

channel 3 negative output

channel 3 positive output

supply voltage 1

17

18

19 and 20

21

SCL

I²C-bus clock input

GAINSEL

OUT4−

PGND4

OUT4+

SDA

22

gain select input (legacy mode only)

channel 4 negative output

power ground channel 4

channel 4 positive output

I²C-bus data input/output

half supply ﬁlter capacitor

I²C-bus address select

23

24

25

26

SVR

27

ADSEL

STB

28

29

standby (I²C-bus mode) or mode pin (legacy mode);

programmable second clip indicator

OUT2+

PGND2

OUT2−

DIAG

V_P2

30

channel 2 positive output

31

power ground channel 2

32

channel 2 negative output

33

diagnostic/clip detection output

supply voltage 2

34 and 35

36

TAB

heatsink connection; must be connected to ground

7. Functional description

The TDA8596 is a quad BTL audio power ampliﬁer with symmetrical inputs, made in

BCDMOS technology. It contains four independent ampliﬁer channels in BTL conﬁguration

with complementary (PMOST/NMOST) output stages (see Figure 1). The status of each

ampliﬁer channel (output offset, connected load, short circuit condition at output pins) can

be read out separately via the I²C-bus. The TDA8596 is protected against overvoltage on

the supply pins, short circuits at the output pins, overheating and loss-of-ground or

loss-of-V_Pconditions.

The temperature pre-warning level and the clip detection levels can be programmed via

the I²C-bus. Further, the information that will be available on the diagnostic pins (i.e. DIAG

or STB) can be programmed. Three different I²C-bus addresses can be selected by

connecting a resistor to the ADSEL pin. In case the ADSEL pin is shorted to ground, the

TDA8596 operates in legacy mode. In this mode no I²C-bus is needed and the STB pin

will change from a two level pin (Standby mode and Operating mode) to a three level pin

(Standby, Mute operating and Normal operating mode).

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

5 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

7.1 Output stage

The output stage of each ampliﬁer channel consists of two PMOS power transistors and

two NMOS transistors in BTL conﬁguration. The TDA8596 is manufactured in a BCDMOS

process on an isolated substrate Silicon On Insulator (SOI). Due to the absence of a

doped (bulk) substrate, this process is insensitive to latch-up induced by substrate

coupled parasitic paths.

7.2 Gain selection

The gain of the TDA8596 can be programmed at 16 dB (line driver mode) or 26 dB

(Normal operating mode). This can be done either in I²C-bus mode by means of a bus

command or in legacy mode by using the GAINSEL pin. To allow this, the device must ﬁrst

be put in legacy mode by connecting the ADSEL pin to ground. In case the GAINSEL pin

is connected to ground the 26 dB mode is selected. By leaving the GAINSEL pin open the

16 dB mode is selected. The GAINSEL pin will be ignored in I²C-bus mode.

7.3 Distortion (clip-) detection

If the output of an ampliﬁer channel starts clipping to either the supply voltage or to ground

the output signal will become distorted. When the Total Harmonic Distortion (THD) per

channel exceeds a preselected threshold (2 %, 5 % or 10 %), one of the two diagnostic

pins (DIAG or STB) will be pulled LOW. The clip information of each channel can be

directed separately to one speciﬁc diagnostic pin. This way, it is possible to distinguish

between clipping on the front or rear channels. Redirection of temperature and load

information to the diagnostic pins can be disabled to allow only the clip information to be

present on these pins. In this mode, the temperature and load information is still available

but can only be read out through the I²C-bus.

Note: during mute-to-on or on-to-mute transitions, the clip detection may be activated

even when no output clipping occurs.

7.4 Output protection and short circuit operation

When a short circuit to ground, to V_Por across the load occurs, the concerning ampliﬁer

channel will switch off. After 16 ms of non-operation it will switch on again. If the short

circuit condition is still present the ampliﬁer channel will again return to 16 ms of

non-operation. The 16 ms cycle will reduce the dissipation.

The other ampliﬁer channels (without short circuit condition) will retain functionality. To

prevent audible distortion, the ampliﬁer channel with the short circuit condition can be

disabled via the I²C-bus.

In case the diagnostic pin is selected for load fault information (IB2[D4] = 0), it will be

pulled LOW. Via the I²C-bus it can be read out which channel is shorted by what type of

short circuit (to ground, to V_Por across the load).

In order to detect a shorted load, a signal should be applied to the inputs of the ampliﬁer.

A shorted load is only detected when the output current level on the related output

crosses the deﬁned Safe Operating ARea (SOAR) protection threshold.

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

6 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

7.4.1 SOAR protection

The output transistors are protected by a Safe Operating ARea (SOAR) protection. The

TDA8596 has a two-stage SOAR protection:

• If the differential output voltage across the load (V_o) is less than 1 V, and the current

through the load (I_L) exceeds 4 A, the ampliﬁer channel will be switched off during

16 ms. To prevent spurious switch-off events (which may occur for instance in case of

inductive loads or very high input signals), the fault condition (V_o< 1 V and I_L> 4 A)

must exist for more than 300 µs.

• If the differential output voltage across the load (V_o) is more than 1 V, and the current

through the load (I_L) exceeds 8 A, the ampliﬁer channel will be switched off during

16 ms.

7.4.2 Speaker protection

To prevent damage of the speaker when one side of the speaker is connected to ground, a

missing-current protection is implemented. When the current in the high side power

transistor of one ampliﬁer channel is not equal to the current through the corresponding

low side power transistor, a fault condition is assumed and the concerning channel will be

switched off. The boundary conditions for the activation of this speaker protection are:

• V_o< 1.55 V and I_missing> 1 A for 80 µs

• V_o> 1.55 V and I_missing> 3 A for 80 µs

7.5 Standby and mute operation

The functionality of the STB pin depends on the mode of operation of the device (i.e.

legacy- or I²C-bus mode).

7.5.1 I²C-bus mode

When the STB pin is LOW (< 1 V), the device is in standby condition. The I²C-bus lines

will not be loaded and the quiescent current will be low. When the STB pin is switched

HIGH (> 2.5 V) the TDA8596 switches to operating condition and performs a Power-On

Reset (POR). This will cause the DIAG pin to be pulled LOW. The TDA8596 will start-up

when bit D0 of instruction byte IB1 is set. Bit D0 will also reset the ‘power-on reset

occurred’ bit (DB2[D7]) and releases the DIAG pin.

The soft- and fast-mute functions can be activated by means of I²C-bus instructions. The

soft mute can be activated independently for the front (1 and 3) and rear (2 and 4)

channels, and mutes the audio in 20 ms. The fast mute is activated for all channels

simultaneously and mutes the audio in 0.1 ms. Releasing the mute will always occur via a

soft mute and will take 20 ms.

When the STB pin is switched LOW and the ampliﬁer is in Operating mode, the fast mute

will be activated prior to shut-down. This enables the option to fast mute the ampliﬁer by

means of the STB pin in case of, for instance an engine start, thus preventing audible pop

noise.

7.5.2 Legacy mode (pin ADSEL connected to ground)

In legacy mode, the function of the STB pin changes into a three level (standby, mute and

operating) enable pin and the ampliﬁer will directly start-up when the STB pin is put into

Mute or Normal operating mode. Mute operation is controlled through an internal timer

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

7 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

(20 ms) to minimize mute-to-operating pops. When the STB pins directly switched from

Normal operating to Standby mode, the fast mute (mutes in 0.1 ms) will be activated prior

to shut-down.

7.6 Start-up and shut-down sequence

To prevent the ampliﬁer from producing switch-on and switch-off pop noise, the capacitor

on the SVR pin is used for smooth start-up and shut-down sequences. Larger capacitors

will lead to longer (smoother) start-up and shut-down sequences. Initially the ampliﬁer

outputs are charged to Half Supply Voltage (HVP) minus 1.4 V in mute condition. This is

independent of the I²C-bus mute settings in I²C-bus mode or the pin STB voltage in

legacy mode. The remaining 1.4 V before the outputs reach HVP, is used for mute release

in case the I²C-bus bits (IB2[D2:D0] = 000) have been programmed to mute-off (or

V_STB> 6.5 V in legacy mode). In case the I²C-bus bits have been programmed to maintain

mute condition (IB2[D2:D0] = 111) (or 2.5 V < V_STB< 6.5 V in legacy mode) the ampliﬁer

will stay in mute.

When the STB pin is switched LOW (< 1 V), a fast mute is performed prior to discharging

the capacitor on pin SVR. With a capacitor of 22 µF the device goes into Standby mode

(low quiescent current) within 1 s after switching STB to LOW (see also Figure 3 and

Figure 6).

Start-up and shut-down pop noise can be further reduced by activating the low pop mode.

When this mode is selected (IB2[D3] = 0), the output voltage rising slope will decrease

(resulting in a longer start-up time).

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

8 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

V

P

DIAG

DB2 bit D7

POR

IB1 bit D0

start enable

t

wake

STB

SVR

t

off

amp_on

fast

mute

amplifier

output

t

d(fast_mute)

d(mute_off)

d(soft_mute)

001aad168

Fig 3. Start-up and shut-down timing in I²C-bus mode

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

9 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

V

P

DIAG

DB2 bit D7

POR

IB1 bit D0

start enable

t

wake

STB

SVR

t

load

t

off

amp_on

fast

mute

amplifier

output

t

d(fast_mute)

d(mute_off)

d(soft_mute)

001aad169

Fig 4. Start-up and shut-down timing with DC load active in I²C-bus mode

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

10 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

V

P

DIAG

DB2 bit D7

POR

IB1 bit D0

start enable

t

wake

STB

SVR

t

load

t

off

amp_on

fast

mute

amplifier

output

t

d(fast_mute)

d(mute_off)

d(soft_mute)

001aad170

Fig 5. Start-up and shut-down timing with low pop and DC load activated

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

11 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

V

P

DIAG

STB

on

mute

standby

SVR

t

off

amp_on

soft

mute

fast

mute

amplifier

output

t

d(mute_off)

t

d(fast_mute)

d(soft_mute)

d(mute_on)

001aad171

Fig 6. Start-up and shut-down timing in legacy mode

7.7 Power-on reset and supply voltage spikes

If the supply voltage drops below 5 V in I²C-bus mode (see Figure 8 and 9), the content of

the I²C-bus latches cannot be guaranteed and a power-on reset will be performed. This

will cause all latches to be reset, the ampliﬁer to be switched off and the DIAG pin to be

pulled LOW, indicating that a power-on reset has occurred (see DB2[D7]). When bit

IB1[D0] is set, the power-on ﬂag is reset, the DIAG pin is released and the ampliﬁer will

start-up.

In legacy mode a supply voltage drop below 5 V will switch off the ampliﬁer without pulling

the DIAG pin LOW.

7.8 Engine start and low voltage operation

In steady state, the DC output voltage of an ampliﬁer channel V_Oequals half the supply

voltage (HVP). This voltage is related to the voltage on the SVR pin (refer to Figure 7:

V_O= V_SVR− 1.4 V). An external capacitor has been connected to the SVR pin to suppress

coupling of power supply ripple to the ampliﬁer outputs.

The headroom voltage V_hris deﬁned as the difference between the supply voltage V_Pand

the DC output voltage V_O, i.e. V_hr= V_P− V_O(refer to Figure 7). If the supply voltage drops,

e.g. during an engine start, the outputs will follow slowly due to the capacitor on pin SVR.

However, if the headroom voltage V_hrdrops below the headroom protection threshold of

1.6 V, the headroom protection will be activated to prevent pop noise at the output. This

protection will ﬁrst activate the fast mute and will subsequently discharge the capacitor on

pin SVR to generate more headroom for the ampliﬁer (refer to Figure 8 and 9).

TDA8596_2

Product data sheet

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

When the SVR capacitor has discharged, the ampliﬁer will only start-up again when the

supply voltage V_Pincreases above the low V_Pmute threshold, typically 7.5 V. Below this

threshold, the outputs of the ampliﬁer remain low. In I²C-bus mode, a supply voltage drop

below V_P(reset), typically 5 V will result in setting bit DB2[D7]. In this condition the ampliﬁer

will wait for an I²C-bus command in order to start-up.

The TDA8596 prevents internally induced output pops during engine start. In order to

prevent pops on the output caused by the application (e.g. due to the tuner supply going

out of regulation), the STB pin can be pulled LOW when an engine start is detected. The

STB pin will activate the fast mute within 0.1 ms and consequently all disturbances at the

ampliﬁer inputs will be suppressed.

V

(V)

V

P

14

SVR

(1)

V

hr

8.4

7

(2)

O

V

1.6 V

t (s)

headroom protection

(3)

threshold

001aad172

(1) Headroom voltage V_hr= V_P− V_O.

(2) Steady state output voltage V_O= V_SVR− 1.4 V.

(3) Headroom protection threshold = V_O+ 1.6 V.

Fig 7. Low-headroom protection

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

13 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

2

V

legacy and I C-bus mode

O

(V)

V

P

14.4

output

voltage

(1)

8.8

V

hr

8.6

7.2

(3)

(2)

V

SVR

3.5

output voltage

(3)

t (s)

t

(start-Vo(off))

001aad173

t

(start-SVRoff)

(1) Headroom protection activated:

a) Fast mute.

b) Discharge of SVR.

(2) Low V_Pmute activated.

(3) Low V_Pmute released.

Fig 8. Low V_Pbehavior; legacy and I²C-bus modes

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

14 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

2

V

I C-bus mode only

O

(V)

V

P

14.4

8.8

8.6

7.2

(1)

(2)

5.0

3.5

V

SVR

output voltage

0

POR

IB1 bit D0

DIAG

t (s)

001aad185

(1) Low V_Pmute activated.

(2) V_POR: V_Plevel at which POR is activated.

Fig 9. Low V_Pbehavior; I²C-bus mode only

7.9 Overvoltage and load dump protection

When the supply voltage V_Pexceeds 22 V, all ampliﬁer output stages will be switched to

high-impedance. The TDA8596 is protected against load dump transients up to 50 V.

7.10 Thermal pre-warning and thermal protection

If the average junction temperature reaches the (I²C-bus programmable) pre-warning

level, a thermal pre-warning will be generated, which can be read out on the I²C-bus. If the

TDA8596 is programmed to send thermal warning information to the DIAG pin, the DIAG

pin will be pulled LOW. The default thermal pre-warning detection level (IB3[D4] = 0) is

145 °C typical. In case IB3[D4] = 1, the detection level is modiﬁed to 122 °C typical.

In legacy mode the thermal pre-warning level is ﬁxed at 145 °C typical.

If the junction temperature increases further, the temperature controlled gain reduction will

be activated for all four channels to reduce the output power (see Figure 10). If this still

does not reduce the average junction temperature, all channels will be switched off at the

absolute maximum temperature T_off, typical 175 °C.

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

15 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aad174

30

G

v

(dB)

20

10

0

145

155

165

175

T (°C)

j

Fig 10. Temperature controlled ampliﬁer gain

7.11 Diagnostics

Diagnostic information can be read via the I²C-bus and it can also be made available on

the DIAG pin or STB pin. The information on the DIAG pin is partly ﬁxed, i.e. power-on

reset occurred and low or high battery events. Through I²C-bus commands selectable

information (i.e. load faults, temperature alarms and clip detection) can be made available.

This information will be directed to the DIAG pin through a logical OR function. In case of

any of the above mentioned failures, the DIAG pin will remain LOW so the microcontroller

is triggered to read out the failure information via the I²C-bus (the DIAG pin can be used

as microcontroller interrupt to minimize I²C-bus trafﬁc). As soon as the failure is removed,

the DIAG pin will be released.

The STB pin can be conﬁgured as a second clip detection pin. The clip detection level is

equal for all channels. It is possible to redirect the clip information of all separate channels

to each of the two diagnostic pins DIAG or STB. This option can be used to distinguish

between for instance clipping on the front and rear side channels (i.e. by redirecting the

front channels to one diagnostic output and the rear channels to the second diagnostic

output).

Table 4 shows the diagnostic options for the DIAG pin and STB pin for both I²C-bus and

legacy mode:

Table 4.

Diagnostic information per pin for various modes

I²C-bus mode

Diagnostic

Legacy mode

Pin DIAG

no

information

Pin DIAG

Pin STB

Power-on reset

after power-on reset;

pin DIAG will remain

LOW until ampliﬁer has

been started

no

Low battery

yes

no

yes

Clip detection

can be enabled per

channel

can be enabled per

channel

yes; ﬁxed level for all

channels on 2 %

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

16 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 4.

Diagnostic information per pin for various modes …continued

Diagnostic

information

I²C-bus mode

Legacy mode

Pin DIAG

Pin STB

Temperature pre-

warning

can be enabled

no

yes; pre-warning level

is 145 °C

Short

can be enabled

no

yes

Speaker protection

(missing current)

Offset detection

Load detection

Overvoltage

no

yes

7.12 Offset detection

Offset detection can be performed either with or without input signal (for instance when

the DSP is in mute after a start-up). Assume the ampliﬁer is in I²C-bus mode. When an

I²C-bus read of the output offset is performed the DBx[D2] latch will be set. When the

ampliﬁer BTL output voltage crosses the 1.55 V window threshold within 1 s after a read is

performed, the DBx[D2] latch is reset and setting is disabled. After a certain delay, the

next read can be performed.

Example: in case the offset bits are still set when a successive read is performed more

than 1 s after the previous read, the output signal has not been within the offset window

thresholds for at least 1 s. This could either indicate an output signal with a frequency

below 1 Hz or the presence of an output offset above 1.55 V (see Figure 11).

2

V

= V

− V

OUT+ OUT−

O

I C-bus mode only

offset

threshold

t

reset:

t = 1 s:

setting

disabled

read = no offset

DB1 bit D2 reset

V

= V

− V

OUT+ OUT−

O

offset

threshold

t

read = set bit

t = 1 s:

read = offset

DB1 bit D2 set

001aad175

Fig 11. Offset detection

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

17 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

7.13 DC load detection

When the DC load detection is enabled (IB1[D1] = 1), a DC offset is slowly applied at the

outputs of the ampliﬁers during the start-up sequence (see Figure 4 and Figure 5) and the

load currents as a result of the applied offset are measured. Based on this measurement

the load impedance can be determined to differentiate between normal, line driver and no

load (see Figure 12).

LOAD

NORMAL

LINE DRIVER MODE

OPEN-CIRCUIT

DETECTION

LEVEL

20 Ω 100 Ω

800 Ω 5 kΩ

001aad176

Fig 12. DC load detection levels

When the ampliﬁer is used in line driver mode and the external booster has an input

impedance between 100 Ω and 800 Ω (DC-coupled), the DC load bits will be set at

DBx[D5:D4] = 10 independent of the selected gain setting (see Table 5).

Table 5.

DC load detection translation table

DC load bits

Load indication^[1]

DBx[D5]

DBx[D4]

0

1

0

1

normal load

line driver load

open load

not valid

[1] Only when IB1[D2] = 0.

By reading the I²C-bus bits the microprocessor can determine after the start-up of the

ampliﬁer whether a speaker or an external booster is connected and initiate the proper

selection of the ampliﬁer gain, i.e. 26 dB for normal mode or 16 dB for line driver mode.

Gain selection will occur without audible pop noise when the ampliﬁer is in mute.

The DC load bit DBx[D4] is shared with the AC load detection. This implies that Table 5 is

only valid when AC load detection is disabled (IB1[D2] = 0). When the AC load detection is

enabled (IB1[D2] = 1) the bits DBx[D4] will show the result of the AC load detection. After

disabling the AC load detection data bit DBx[D4] will show the result of the DC load

measurement, which was stored during the AC load measurement.

7.14 AC load detection

When AC load detection is enabled (IB1[D2] = 1), AC coupled speakers (e.g. tweeters)

can be detected during the assembly process. The detection is performed by means of

applying an audible input sine wave (e.g. 19 kHz) to the inputs of the ampliﬁer. The AC

current into the load is measured with a 460 mA peak current detector to detect the

presence of an AC load. In order to prevent spurious AC load detection (e.g. due to

ampliﬁer on/off switching), the AC load detection bit will only be set when the peak current

threshold is triggered at least three times. Besides the 460 mA peak current threshold, a

secondary threshold level at 230 mA is present. In case this level is not triggered, a high

ohmic DC load (e.g. line driver) is assumed (also refer to Figure 13).

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

18 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Example: at an AC output voltage of 2 V peak the total impedance must be less than 4 Ω

to detect an AC coupled load or above 9 Ω to guarantee the detection of a DC load. Refer

to Table 6 for the interpretation AC load detection bits.

Table 6.

AC load detection translation table

Normal DC load bit

DBx[D5]

Line driver DC load bit

DBx[D4]

Load indication

Don’t care

0

1

no AC load detected

AC load detected

The AC load detection can only be performed when the ampliﬁer has completed its

start-up sequence. Consequently it will not conﬂict with the DC load detection.

001aad177

20

|Z

|

th(load)

(Ω)

16

12

8

(1)

(2)

4

0

1

2

3

4

5

V

(V)

oM

(1) I_oM< 230 mA (no load detection level).

(2) I_oM> 460 mA (load detection level).

Fig 13. AC load impedance versus output signal

7.15 I²C-bus diagnostic bits read out

The diagnostic information of the ampliﬁer can be read out via the I²C-bus. The I²C-bus

data bits are set in case a failure event occurs and are not reset until an I²C-bus read

command is given. This implies that even when the failure mode is removed before

reading out the I²C-bus, the microcontroller will still be able to read out what kind of failure

has occurred. A consequence of this procedure is that during the I²C-bus read cycle old

information is read. When actual information is required, it is recommended to perform

two successive read actions.

The DIAG pin will give actual diagnostic information (when selected), however it does not

distinguish between the various failure modes. The DIAG pin can be used to trigger an

I²C-bus read out of the data bits to retrieve actual diagnostic information. When a failure is

no longer present, the DIAG pin will be released instantly, independently of the I²C-bus

latches.

TDA8596_2

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

8. I²C-bus speciﬁcation

Table 7.

Pin ADSEL

Open

TDA8596 ADDRESS with hardware address select

A6

A5

A4

A3

A2

A1

A0

R/W

1

0

1

0

0 = write to TDA8596

1 = read from TDA8596

0 = write to TDA8596

1 = read from TDA8596

0 = write to TDA8596

1 = read from TDA8596

51 kΩ to ground

10 kΩ to ground

Ground

1

0

1

0

1

no I²C-bus; legacy mode

SDA

SCL

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 14. START and STOP conditions

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 15. Bit transfer

TDA8596_2

Product data sheet

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

2

I C-BUS WRITE

SCL

1

2

7

8

9

1

2

7

8

9

MSB − 1

MSB MSB − 1

LSB + 1

LSB

MSB

LSB + 1

ACK

SDA

S

A

P

ADDRESS

WRITE DATA

W

To stop the transfer, after the last acknowledge (A)

a STOP condition (P) must be generated

2

I C-BUS READ

SCL

SDA

1

2

7

8

9

1

2

7

8

9

MSB MSB − 1

LSB + 1

MSB MSB − 1

LSB + 1

LSB

ACK

A

ACK

NA

P

S

R

READ DATA

ADDRESS

To stop the transfer, the last byte must not be acknowledged

and a STOP condition (P) must be generated

: generated by master (microcontroller)

: generated by slave

: START

001aac649

S

P

: STOP

A

: acknowledge

NA

: not acknowledge

R/W : read / write

Fig 16. I²C-bus read and write modes

8.1 Instruction bytes

I²C-bus mode:

• If R/W bit = 0, the TDA8596 expects 3 instruction bytes: IB1, IB2 and IB3

• After a power-on reset, all instruction bits are set to logic 0

Legacy mode:

• The settings are equal to the condition with all instruction bits set to logic 0 (see

Table 8), with the exception of IB1[D0] bit that is ignored in legacy mode.

Table 8.

Bit

Instruction byte IB1

Description

D7

don’t care

D6

channel 3 clip information on DIAG or STB pin

0 = clip information on DIAG pin

1 = clip information on STB pin

channel 1 clip information on DIAG or STB pin

0 = clip information on DIAG pin

1 = clip information on STB pin

D5

TDA8596_2

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 8.

Instruction byte IB1 …continued

Bit

Description

D4

channel 4 clip information on DIAG or STB pin

0 = clip information on DIAG pin

1 = clip information on STB pin

D3

D2

D1

D0

channel 2 clip information on DIAG or STB pin

0 = clip information on DIAG pin

1 = clip information on STB pin

AC load detection enable

0 = AC load detection disabled

1 = AC load detection enabled; DBx[D4] bits not available for DC load detection

DC load detection enable

0 = DC load detection disabled

1 = DC load will be detected

ampliﬁer start enable; (clear power-on reset ﬂag, DB2[D7])

0 = ampliﬁer not enabled, DIAG pin will remain LOW

1 = ampliﬁer will start-up, power-on occurred (DB2[D7]) will be reset and DIAG

pin will be released

Table 9.

Bit

Instruction byte IB2

Description

D7 and D6

clip detection level

00 = clip detection level 2 %

01 = clip detection level 5 %

10 = clip detection level 10 %

11 = clip detection level disabled

temperature information on DIAG pin

0 = temperature information on DIAG pin

1 = no temperature information on DIAG pin

load fault information (shorts, missing current) on DIAG pin

0 = fault information on DIAG pin

1 = no fault information on DIAG pin

low pop (slow start) enable

0 = low pop enabled

D5

D4

D3

D2

D1

1 = low pop disabled

soft mute channel 1 and channel 3 (mute delay 20 ms)

0 = no mute

1 = mute

soft mute channel 2 and channel 4 (mute delay 20 ms)

0 = no mute

1 = mute

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 9.

Instruction byte IB2 …continued

Bit

Description

D0

fast mute all ampliﬁer channels (mute delay 100 µs)

0 = no mute

1 = mute

Table 10. Instruction byte IB3

Bit

D7

D6

Description

don’t care

ampliﬁer channel 1 and channel 3 gain select

0 = 26 dB

1 = 16 dB

D5

D4

D3

D2

D1

D0

ampliﬁer channel 2 and channel 4 gain select

0 = 26 dB

1 = 16 dB

temperature pre-warning level

0 = warning level on 145 °C

1 = warning level on 122 °C

disable channel 3

0 = channel 3 enabled

1 = channel 3 disabled

disable channel 1

0 = channel 1 enabled

1 = channel 1 disabled

disable channel 4

0 = channel 4 enabled

1 = channel 4 disabled

disable channel 2

0 = channel 2 enabled

1 = channel 2 disabled

8.2 Data bytes

I²C-bus mode:

• If R/W = 1, the TDA8596 will send four data bytes to the microprocessor: DB1, DB2,

DB3, and DB4

• All bits are latched

• All bits are reset after a read operation except D4 and D5. D2 is set after a read

operation, refer to the offset detection described in Section 7.12

• For explanation of AC and DC load detection bits, refer to Section 7.13 and

Section 7.14

TDA8596_2

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 11. Data byte DB1

Bit

Description

D7

temperature pre-warning

0 = no warning

1 = junction temperature too high

speaker fault channel 2 (missing current)

0 = no missing current

D6

1 = missing current

D5 and D4

channel 2 DC load or AC load detection

if bit IB1[D2] = 1, AC load detection is enabled, bit D5 and bit D4 are available for

AC load detection

00 = no AC load

01 = AC load detected

10 = no AC load

11 = AC load detected

if bit IB1[D2] = 0, DC load detection is enabled, bits D5 and bit D4 are available

for DC load detection

00 = normal load

01 = not valid

10 = line driver load

11 = open load

D3

D2

D1

D0

channel 2 shorted load

0 = not shorted load

1 = shorted load

channel 2 output offset

0 = no output offset

1 = output offset

channel 2 short to V_P

0 = no short to V_P

1 = short to V_P

channel 2 short to ground

0 = no short to ground

1 = short to ground

Table 12. Data byte DB2

Bit

Description

D7

power-on reset occurred/ampliﬁer status

0 = ampliﬁer on

1 = power-on reset has occurred; ampliﬁer off

speaker fault channel 4 (missing current)

0 = no missing current

D6

1 = missing current

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 12. Data byte DB2 …continued

Bit

Description

D5 and D4

channel 4 DC load or AC load detection

if bit IB1[D2] = 1, AC load detection is enabled, bit D5 and bit D4 are available for

AC load detection

00 = no AC load

01 = AC load detected

10 = no AC load

11 = AC load detected

if bit IB1[D2] = 0, DC load detection is enabled, bits D5 and bit D4 are available

for DC load detection

00 = normal load

01 = not valid

10 = line driver load

11 = open load

D3

D2

D1

D0

channel 4 shorted load

0 = not shorted load

1 = shorted load

channel 4 output offset

0 = no output offset

1 = output offset

channel 4 short to V_P

0 = no short to V_P

1 = short to V_P

channel 4 short to ground

0 = no short to ground

1 = short to ground

Table 13. Data byte DB3

Bit

Description

D7

maximum temperature protection

0 = no protection

1 = maximum temperature protection

speaker fault channel 1 (missing current)

0 = no missing current

D6

1 = missing current

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 13. Data byte DB3 …continued

Bit

Description

D5 and D4

channel 1 DC load or AC load detection

if bit IB1[D2] = 1, AC load detection is enabled, bit D5 and bit D4 are available for

AC load detection

00 = no AC load

01 = AC load detected

10 = no AC load

11 = AC load detected

if bit IB1[D2] = 0, DC load detection is enabled, bits D5 and bit D4 are available

for DC load detection

00 = normal load

01 = not valid

10 = line driver load

11 = open load

D3

D2

D1

D0

channel 1 shorted load

0 = not shorted load

1 = shorted load

channel 1 output offset

0 = no output offset

1 = output offset

channel 1 short to V_P

0 = no short to V_P

1 = short to V_P

channel 1 short to ground

0 = no short to ground

1 = short to ground

Table 14. Data byte DB4

Bit

D7

D6

Description

reserved

speaker fault channel 3 (missing current)

0 = no missing current

1 = missing current

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 14. Data byte DB4 …continued

Bit

Description

D5 and D4

channel 3 DC load or AC load detection

if bit IB1[D2] = 1, AC load detection is enabled, bit D5 and bit D4 are available for

AC load detection

00 = no AC load

01 = AC load detected

10 = no AC load

11 = AC load detected

if bit IB1[D2] = 0, DC load detection is enabled, bits D5 and bit D4 are available

for DC load detection

00 = normal load

01 = not valid

10 = line driver load

11 = open load

D3

D2

D1

D0

channel 3 shorted load

0 = not shorted load

1 = shorted load

channel 3 output offset

0 = no output offset

1 = output offset

channel 3 short to V_P

0 = no short to V_P

1 = short to V_P

channel 3 short to ground

0 = no short to ground

1 = short to ground

9. Limiting values

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

operating

Min

Max

18

Unit

V

V_P

supply voltage

-

non operating

−1

-

+50

50

V

load dump protection;

duration 50 ms; rise time

> 2.5 ms

V

V_P(r)

I_OSM

reverse supply voltage

10 minutes maximum

-

−2

V

A

non-repetitive peak

output current

13

I_ORM

repetitive peak output

current

repetitive

-

8

A

T_j

junction temperature

storage temperature

-

150

°C

T_stg

−55

+150

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

27 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 15. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

T_amb

Parameter

Conditions

Min

−40

-

Max

+105

V_P

Unit

°C

ambient temperature

protection voltage

V_(prot)

AC and DC short circuit

voltage of output pins

and across the load

V

V_x

voltage on pin x

SCL and SDA

0

-

6.5

13

V

W

V

inputs, SVR and DIAG

STB

[1]

24

P_tot

total power dissipation

T_case= 70 °C

80

V_esd

electrostatic discharge

voltage

human body model;

C = 100 pF; R_s= 1.5 kΩ

-

2000

machine model;

C = 200 pF; R_s= 10 Ω;

L = 0.75 µH

-

200

V

[1] 10 kΩ series resistance if connected to V_P.

10. Thermal characteristics

Table 16. Thermal characteristics

Symbol

R_th(j-c)

Parameter

Conditions

Typ

1

Unit

thermal resistance from junction to case

thermal resistance from junction to ambient

K/W

R_th(j-a)

35

11. Characteristics

Table 17. Characteristics

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltage behavior

V_P

supply voltage

R_L= 4 Ω

R_L= 2 Ω

no load

8

14.4

270

4

18

16

400

15

7.2

8

V

[1]

8

V

I_q

quiescent current

standby current

output voltage

-

mA

µA

V

I_stb

V_STB= 0.4 V

-

V_O

6.7

6.9

6.3

0.1

7

V_P(low)(mute)

low supply voltage

mute

with rising supply voltage

with falling supply voltage

7.5

6.8

0.7

V

7.4

1

V

∆V_P(low)(mute)

V_th(ovp)

V_hr

low supply voltage

mute hysteresis

V

overvoltage protection

threshold voltage

18

20

22

V

headroom voltage

when headroom protection is activated;

see Figure 7

1.1

1.6

2.0

TDA8596_2

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TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 17. Characteristics …continued

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_POR

power-on reset

voltage

see Figure 9

4.1

5.0

5.8

V

V_O(offset)

output offset voltage

ampliﬁer on

−95

−25

−40

0

+95

+25

+40

mV

ampliﬁer mute

line driver mode

Mode select pin STB/second clip detection pin

V_STB

voltage on pin STB

Standby mode

I²C-bus mode

-

1

V

legacy mode (I²C-bus off)

Mute operating mode

legacy mode (I²C-bus off)

Operating mode

2.5

-

4.5

V

I²C-bus mode

legacy mode (I²C-bus off)

2.5

6.5

-

V_P

V

[2]

LOW voltage on pin STB when pulled

down during clipping

I_STB= 150 µA

I_STB= 500 µA

5.6

6.1

-

6.1

7.4

V

I_STB

current on pin STB

0 V < V_STB< 8.5 V

clip detection not active; I²C-bus

mode

-

4

30

70

µA

legacy mode

10

Start-up, shut-down and mute timing

t_wake

wake-up time

time after wake-up via STB pin before

ﬁrst I²C-bus transmission is recognized;

see Figure 3

-

300

-

500

10

µs

I_LO(SVR)

output leakage

µA

current on pin SVR

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

29 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 17. Characteristics …continued

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_{d(mute_off)}

mute off delay time

mute to 10 % of output signal;

I_LO(SVR)= 0 µA

[3]

I²C-bus mode (IB1[D0]); with

295

465

795

ms

I_LO(SVR)= 10 µA → +15 ms; no

DC load (IB1[D1] = 0); low pop

disabled (IB2[D3] = 1); see Figure 3

I²C-bus mode (IB1[D0]); with

500

640

430

640

830

650

940

ms

I_LO(SVR)= 10 µA → +20 ms; DC load

active (IB1[D1] = 1); low pop disabled

(IB2[D3] = 1); see Figure 4

I²C-bus mode (IB1[D0]); with

1190

1030

I_LO(SVR)= 10 µA → +20 ms; DC load

active (IB1[D1] = 0); low pop enabled

(IB2[D3] = 0); see Figure 5

legacy mode; with I_LO(SVR)= 10 µA →

+20 ms; V_STB= 7 V; R_ADSEL= 0 Ω;

see Figure 6

t_{amp_on}

ampliﬁer on time

ampliﬁer from mute to 90 % of output

signal; I_LO(SVR)= 0 µA

[3]

I²C-bus mode (IB1[D0]); with

360

565

710

510

520

695

890

720

870

ms

I_LO(SVR)= 10 µA → +30 ms; no

DC load (IB1[D1] = 0); low pop

disabled (IB2[D3] = 1); see Figure 3

I²C-bus mode (IB1[D0]); with

1015

1270

1120

I_LO(SVR)= 10 µA → +35 ms; DC load

active (IB1[D1] = 1); low pop disabled

(IB2[D3] = 1); see Figure 4

I²C-bus mode (IB1[D0]); with

I_LO(SVR)= 10 µA → +30 ms; DC load

active (IB1[D1] = 0); low pop enabled

(IB2[D3] = 0); see Figure 5

legacy mode; with I_LO(SVR)= 10 µA →

+20 ms; V_STB= 7 V; R_ADSEL= 0 Ω;

see Figure 6

t_off

ampliﬁer switch-off

time

time to DC output voltage < 0.1 V;

I²C-bus mode (IB1[D0]); I_LO(SVR)= 0 µA

[3]

with I_LO(SVR)= 10 µA → +0 ms; low

pop enabled (IB2[D3] = 0); see

Figure 4

120

245

280

20

530

620

40

ms

with I_LO(SVR)= 10 µA → +0 ms; low

pop disabled (IB2[D3] = 1); see

Figure 5

140

t_d(mute-on)

mute to on delay time from 10 % to 90 % of output signal;

IB2[D1] = 1 to 0; V_i= 50 mV; see

Figure 6

-

t_{d(soft_mute)}

soft mute delay time

from 10 % to 90 % of output signal;

IB2[D1] = 0 to 1; V_i= 50 mV; see

Figure 6

20

40

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

30 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 17. Characteristics …continued

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_{d(fast_mute)}

fast mute delay time

from 10 % to 90 % of output signal;

-

0.1

1

ms

V_STBfrom 8 V to 1.3 V; V_i= 50 mV; see

Figure 6

t_{(start-Vo(off))}

t_{(start-SVRoff)}

engine start to output V_Pfrom 14.4 V to 7 V; V_o< 0.5 V; see

-

0.1

40

1

ms

off time

Figure 8

engine start to SVR

off time

V_Pfrom 14.4 V to 7 V; V_SVR< 2 V; see

Figure 8

75

I²C-bus interface^[4]

V_IL

LOW-level input

voltage

pins SCL and SDA

pin SDA; I_L= 5 mA

-

1.5

5.5

0.4

V

V_IH

V_OL

HIGH-level input

voltage

2.3

-

LOW-level output

voltage

f_SCL

SCL clock frequency

-

400

-

kHz

kΩ

R_ADSEL

resistance on pin

ADSEL

I²C-bus address A[6:0] = 110 1100

I²C-bus address A[6:0] = 110 1101

I²C-bus address A[6:0] = 110 1111

legacy mode

155

42

7

-

51

10

-

57

15

0.5

-

Gain select pin

R_GAINSEL

resistance on pin

GAINSEL

legacy mode (I²C-bus off)

26 dB gain; normal mode

16 dB gain; line driver mode

-

5

-

kΩ

20

Diagnostic

V_OL(DIAG)

LOW-level output

voltage on pin DIAG

fault condition; I_DIAG= 1 mA

-

0.3

V

V_{O(offset_det)}

THD_clip

output voltage at

offset detection

±1.3

±1.55

± 2.0

total harmonic

distortion clip

detection level

V_P> 10 V

IB2[D7:D6] = 10; level 10 %

IB2[D7:D6] = 01; level 5 %

5

3

10

5

16

7

%

IB2[D7:D6] = 00; level 2 %

1

2

4

3

8

%

∆THD_clip

total harmonic

distortion clip

detection level

variation

between IB2[D7:D6] = 10 and

IB2[D7:D6] = 01 (level between 10 %

and 5 %)

between IB2[D7:D6] = 01 and

IB2[D7:D6] = 00 (level between 5 % and

2 %)

1

3.5

6

%

T_j(AV)(pwarn)

pre-warning average IB3[D4] = 0

135

112

150

145

122

155

132

160

°C

junction temperature

IB3[D4] = 1

T_{j(AV)(G(−0.5dB))}average junction

temperature for 0.5 dB

gain reduction

V_i= 0.05 V

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

31 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 17. Characteristics …continued

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

∆T_{j(pw-G(−0.5dB))}prewarning to 0.5 dB

gain reduction

7

10

13

°C

junction temperature

difference

∆T_{j(G(−0.5dB)-of)}junction temperature

difference between

10

-

15

20

-

°C

0.5 dB gain reduction

and off

∆G_{(th_fold)}

gain reduction of

thermal foldback

dB

Z_th(load)

load detection

I²C-bus mode

threshold impedance

normal load detection

line driver load detection

I²C-bus mode

-

20

800

-

Ω

100

5000

Z_th(open)

open load detection

threshold impedance

I_{th(o)det(load)AC}AC load detection

output threshold

I²C-bus mode

AC load bit is set

AC load bit is not set

460

-

mA

current

230

Ampliﬁer

P_o

output power

R_L= 4 Ω; V_P= 14.4 V; THD = 0.5 %

R_L= 4 Ω; V_P= 14.4 V; THD = 10 %

18

23

37

20

25

40

-

W

R_L= 4 Ω; V_P= 14.4 V; maximum power;

V_i= 2 V (RMS) square wave

R_L= 4 Ω; V_P= 15.2 V; maximum power;

41

45

-

W

V_i= 2 V (RMS) square wave

R_L= 2 Ω; V_P= 14.4 V; THD = 0.5 %

R_L= 2 Ω; V_P= 14.4 V; THD = 10 %

29

37

58

32

41

64

-

W

R_L= 2 Ω; V_P= 14.4 V; maximum power;

V_i= 2 V (RMS) square wave

THD

total harmonic

distortion

P_o= 1 W to 12 W; f = 1 kHz; R_L= 4 Ω

P_o= 1 W to 12 W; f = 10 kHz

-

0.01

0.09

0.14

0.02

0.1

0.3

%

P_o= 1 W to 12 W; f = 20 kHz

0.4

line driver mode; V_o= 1 V (RMS) and

5 V (RMS); f = 20 Hz to 20 kHz

0.05

α_cs

channel separation

f = 1 kHz; R_S= 1 kΩ

f = 10 kHz; R_S= 1 kΩ

65

60

55

80

65

70

-

dB

PSRR

power supply rejection f = 100 Hz to 10 kHz; R_S= 1 kΩ

ratio

CMRR

common mode

rejection ratio

normal mode; V_cm= 0.3 V (p-p);

f = 1 kHz to 3 kHz; R_S= 1 kΩ

45

-

65

-

dB

V

V_cm(max)(rms)

maximum common

mode voltage (RMS

value)

f = 1 kHz

0.6

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

32 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

Table 17. Characteristics …continued

Refer to test circuit (see Figure 29) at V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz; R_S= 0 Ω; normal mode; unless otherwise speciﬁed.

Tested at T_amb= 25 °C; guaranteed for T_amb= −40 °C to +105 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_n(o)

noise output voltage

ﬁlter 20 Hz to 22 kHz; R_S= 1 kΩ

mute mode

-

19

22

45

26

µV

line driver mode

29

normal mode; T_amb= 25 °C to 105 °C

normal mode; T_amb= −20 °C to 25 °C

differential in; differential out

normal mode

65

110

G_v

R_i

voltage gain

25.5

15.5

44

26

16

60

26.5

16.5

100

dB

kΩ

line driver mode

[5]

input resistance

mute attenuation

symmetrical input; C_i= 470 nF; see

Figure 29

α_mute

V_o/ V_o(mute); V_i= 50 mV

80

-

92

25

-

dB

V_o(mute)(RMS)

RMS mute output

voltage

V_i= 1 V (RMS); ﬁlter 20 Hz to 22 kHz

µV

B_p

power bandwidth

−1 dB

-

20 to

-

Hz

20000

[1] Operation above 16 V with a 2 Ω reactive load can trigger the ampliﬁer protection. The ampliﬁer switches off and will restart after 16 ms

resulting in an ‘audio hole’.

[2] V_STBdepends on the current into the STB pin: minimum = (1429 × I_STB) + 5.4 V, maximum = (3143 × I_STB) + 5.6 V.

[3] The times are speciﬁed without a leakage current. For a leakage current of 10 µA on the SVR pin, the delta time is speciﬁed. If the

capacitor value on the SVR pin changes with ±30 %, the speciﬁed time will also change with ±30 %. The speciﬁed time includes an ESR

of the capacitor on the SVR pin of up to 15 Ω.

[4] Standard I²C-bus spec: maximum LOW level = 0.3 × V_DD, minimum HIGH-level = 0.7 × V_DD. To comply with 5 V and 3.3 V logic the

maximum LOW level is deﬁned with V_DD= 5 V and the minimum HIGH-level with V_DD= 3.3 V.

[5] R_iis the total differential input resistance. f_−3dBcut-off frequency is deﬁned as

1

=

= 19 Hz assuming worst-case low input resistance and 20 % spread in C_i.

------------------------------------

2π × R_i× C_i⁄ 2

------------------------------------------------------------------

2π × 44 kΩ × 235 nF × 0.8

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

33 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

12. Performance diagrams

001aad139

2

10

THD

(%)

10

1

−1

10

(1)

−2

10

(2)

(3)

−3

10

−2

−1

2

10

1

10

P

(W)

o

V_P= 14.4 V.

(1) f = 10 kHz.

(2) f = 1 kHz.

(3) f = 100 Hz.

Fig 17. Total harmonic distortion as a function of output power; 4 Ω load

001aad140

2

10

THD

(%)

10

1

(1)

−1

10

(2)

(3)

−2

10

−3

−2

−1

2

10

1

10

P

(W)

o

V_P= 14.4 V.

(1) f = 10 kHz.

(2) f = 1 kHz.

(3) f = 100 Hz.

Fig 18. Total harmonic distortion as a function of output power; 2 Ω load

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

34 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aad141

28

(1)

P

o

(W)

26

24

22

20

18

(2)

−2

−1

2

10

1

10

f (kHz)

V_P= 14.4 V.

(1) THD = 10 %.

(2) THD = 0.5 %.

Fig 19. Output power as a function of frequency; 4 Ω load

001aad142

55

P

o

(W)

45

(1)

(2)

35

25

−2

−1

2

10

1

10

f (kHz)

V_P= 14.4 V.

(1) THD = 10 %.

(2) THD = 0.5 %.

Fig 20. Output power as a function of frequency; 2 Ω load

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

35 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aad143

60

P

o

(W)

(1)

40

(2)

(3)

20

0

5

10

15

20

V

(V)

P

f = 1 kHz.

(1) P_o(max)

.

(2) THD = 10 %.

(3) THD = 0.5 %.

Fig 21. Output power as a function of supply voltage; 4 Ω load

001aad144

100

P

o

(W)

80

(1)

60

40

20

0

(2)

(3)

5

10

15

20

V

(V)

P

f = 1 kHz.

(1) P_o(max)

.

(2) THD = 10 %.

(3) THD = 0.5 %.

Fig 22. Output power as a function of supply voltage; 2 Ω load

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

36 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aad145

1

THD

(%)

−1

−2

−3

10

(1)

(2)

−2

−1

2

10

1

10

f (kHz)

V_P= 14.4 V; R_L= 4 Ω.

(1) P_o= 1 W.

(2) P_o= 10 W.

Fig 23. Total harmonic distortion as a function of frequency; normal mode

001aag000

−1

10

THD

(%)

(1)

−2

10

(2)

(3)

−3

10

−2

−1

2

10

1

10

f (kHz)

V_P= 14.4 V; R_L= 600 Ω.

(1) V_o= 5 V; front channel.

(2) V_o= 1 V.

(3) V_o= 5 V; rear channel.

Fig 24. Total harmonic distortion as a function of frequency; line driver mode

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

37 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aag001

−40

PSRR

(dB)

−50

−60

−70

−80

−90

(1)

(2)

2

3

4

5

10

f (Hz)

V_P= 14.4 V; R_L= 4 Ω; V_ripple= 2 V (p-p).

(1) front channel.

(2) rear channel.

Fig 25. Powers supply ripple rejection ratio as a function of frequency

001aag002

−50

α

cs

(dB)

−60

−70

−80

−90

−100

2

3

4

5

10

f (Hz)

V_P= 14.4 V; R_L= 4 Ω; P_o= 4 W.

Fig 26. Channel separation as a function of frequency

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

38 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

001aag003

50

P

tot

(W)

40

30

20

10

0

10

20

30

40

P

(W)

o

V_P= 14.4 V; R_L= 4 Ω; f = 1 kHz.

Fig 27. Power dissipation as a function of output power; 4 Ω load

001aag004

100

P

tot

(W)

80

60

40

20

0

20

40

60

80

P

(W)

o

V_P= 14.4 V; R_L= 2 Ω; f = 1 kHz.

Fig 28. Power dissipation as a function of output power; 2 Ω load

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

39 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

13. Application information

(2)

R

+8.5 V

ADSEL

SDA

26

SCL

21

V

P1

19, 20

P2

ADSEL

+5 V

28

34, 35

10 kΩ

STB 29

33 DIAG

STANDBY/

FAST MUTE

SELECT DIAGNOSTIC/

CLIP DETECT

2

I C-BUS

C

i

R /2

i

R

s

/ 2

IN3+ 13

V / 2

i

(1)

18 OUT3+

470 nF

26 dB/

16 dB

MUTE

17 OUT3−

R /2

i

C

i

IN3− 14

R

/ 2

s

V / 2

i

PROTECTION/

DIAGNOSTIC

470 nF

C

i

R /2

i

s

IN1+

7

6

V / 2

i

4

2

OUT1+

470 nF

26 dB/

16 dB

OUT1−

R /2

i

C

i

IN1−

R

/ 2

s

V / 2

i

PROTECTION/

DIAGNOSTIC

470 nF

C

i

R /2

i

s

IN4+ 11

V / 2

i

25 OUT4+

470 nF

26 dB/

16 dB

23 OUT4−

R /2

i

C

i

IN4− 12

R

/ 2

s

V / 2

i

PROTECTION/

DIAGNOSTIC

470 nF

C

i

R /2

i

s

IN2+

9

8

V / 2

i

30 OUT2+

470 nF

26 dB/

16 dB

32 OUT2−

R /2

i

C

i

IN2−

R

s

/ 2

V / 2

i

PROTECTION/

DIAGNOSTIC

470 nF

V

cm

V

P

36 TAB

TDA8596

27

10

SGND

22

GAINSEL

3

31

16

24

PGND4

SVR

(2)

PGND1 PGND2 PGND3

22 µF

001aag005

(1) A capacitor of 10 nF may be added between every ampliﬁer output and ground for EMC reasons.

(2) The SVR capacitor and R_ADSELresistor should ﬁrst be connected to SGND before connecting to PGND.

Fig 29. Test and application information

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

40 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

8.5 V

5.6 kΩ

4.7 kΩ

18 kΩ

10 kΩ

3.3 V

MICRO-

CONTROLLER

STB

29

TDA8596

switch

001aag009

Fig 30. Circuit for combined STB and clip detection function on pin STB

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

41 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

13.1 PCB schematic and layout

2200 µF/

16 V

220

nF

220

nF

V

P

V

P2

P1

19, 20

34, 35

3 31 16 24 36

470 nF

IN1+

n.c.

7

1

IN1−

5

6

15

470 nF

IN2+

IN2−

9

OUT1+

OUT1−

OUT2+

OUT2−

OUT3+

OUT3−

OUT4+

OUT4−

4

2

8

SGND

10

30

32

18

17

25

23

TDA8596

470 nF

IN3+

13

14

IN3−

470 nF

IN4+

IN4−

SVR

11

12

27

4.7 kΩ

28 29 33 21 26 22

22 µF

on/standby

(SW1)

16 dB gain

open

26 dB gain

10 kΩ

BC859

1

2

3

4

SDA

+5V

GND

SCL

DZ

8.2 V

18 kΩ

2 kΩ

BAW62

10 kΩ

2

I C-bus

supply

unmute

22 kΩ

10 kΩ

legacy

mode

clip 2

1

2

3

4

8

7

6

5

V

p

SW2

mute

10 µF

SW3

TDA3664

1 µF

2

I C-bus

2

1

address

select

dip switch

3

4

12 kΩ

51 kΩ

diag

001aag006

Fig 31. Evaluation board; schematic

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

42 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

SVR

Sense

22 µF

C13

Vp

Gnd

top

−OUT1+ −OUT2+

+OUT4− +OUT3−

address

TDA8596TH

I2C

select

Clip2

/stb

J5

D8 (00)

I2C supply

enable

SCL

Gnd

+5V

SDA

C15 C14

DA (01)

DE (11)

SW5

mode

1 µF

10 µF

2200 µF/16 V

C2

SW2

on

SW1

stby

C6 C5 C8 C7 C11 C12 C9 C10

D1

26 dB

gain

diag

16 dB

I2C

mute

SW3

unmute

8 x 470 nF

−IN2+ +IN4−

Sgnd

R6

10 kΩ

−IN1+

+IN3−

Legacy

DZ1

8.2 V

Vp Gnd

SRK

ver. 2

NXP Semiconductors

001aag007

Fig 32. Evaluation board layout; top view

bottom

C3

C1

220 nF

TDA8596TH

ID

IC1

BC859

2 kΩ

R8 R6

1

18

R4

R5

R2

4

1

10 kΩ

TDA3664

12 kΩ 51 kΩ

R3

R7

18 kΩ

22 kΩ

R1

4.7 kΩ

001aag008

Fig 33. Evaluation board layout; bottom view

Rev. 02 — 8 November 2007

TDA8596_2

Product data sheet

43 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

14. Test information

14.1 Quality information

This product has been qualiﬁed in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Stress test qualiﬁcation for integrated circuits, and is suitable for

use in automotive applications.

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

44 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

15. Package outline

HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height

SOT851-2

D

E

A

x

c

y

X

E

2

M

H

E

v

A

D

1

D

2

1

18

pin 1 index

Q

A

2

E

1

(A )

3

A

4

θ

L

p

detail X

36

19

z

M

w

b

p

e

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

UNIT

mm

A

4

b

c

D

1

D

E

e

H

L

p

Q

v

w

x

y

Z

θ

2

3

p

2

1

2

E

max.

+0.08 0.38 0.32

−0.04 0.25 0.23

3.5

3.2

16.0 13.0 1.1 11.1 6.2 2.9

15.8 12.6 0.9 10.9 5.8 2.5

14.5 1.1 1.7

13.9 0.8 1.5

2.55

2.20

8°

0°

0.65

3.5

0.35

0.25 0.12 0.03 0.07

Notes

1. Limits per individual lead.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

SOT851-2

04-05-04

Fig 34. Package outline SOT851-2 (HSOP36)

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

45 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

16. Abbreviations

Table 18. Abbreviations

Acronym

Description

BCDMOS

CMOS

DMOS

DSP

Bipolar CMOS/DMOS

Complementary Metal-Oxide Semiconductor

Double-diffused Metal-Oxide Semiconductor

Digital Signal Processor

ESR

Equivalent Series Resistance

NMOS

NMOST

PMOS

PMOST

SOAR

Negative-channel Metal-Oxide Semiconductor

Negative-channel Metal-Oxide Semiconductor Transistor

Positive-channel Metal-Oxide Semiconductor

Positive-channel Metal-Oxide Semiconductor Transistor

Safe Operating ARea

17. Revision history

Table 19. Revision history

Document ID

TDA8596_2

Release date

20071108

Data sheet status

Change notice

Supersedes

Product data sheet

-

TDA8596_1

Modiﬁcations:

• Figure 30: Value of base-emitter resistor changed from 10 kΩ to 5.6 kΩ

• Section 14: Quality information reference updated

TDA8596_1

20070705

Preliminary data sheet

-

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

46 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

18.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

TDA8596_2

Product data sheet

Rev. 02 — 8 November 2007

47 of 48

TDA8596

NXP Semiconductors

I²C-bus controlled 4 × 45 W power ampliﬁer with symmetrical inputs

20. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

18

Legal information . . . . . . . . . . . . . . . . . . . . . . 47

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 47

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47

18.1

18.2

18.3

18.4

2

2.1

2.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

I²C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

4

5

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

19

20

Contact information . . . . . . . . . . . . . . . . . . . . 47

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.2

7.3

Functional description . . . . . . . . . . . . . . . . . . . 5

Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Gain selection. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Distortion (clip-) detection. . . . . . . . . . . . . . . . . 6

Output protection and short circuit operation . . 6

SOAR protection. . . . . . . . . . . . . . . . . . . . . . . . 7

Speaker protection . . . . . . . . . . . . . . . . . . . . . . 7

Standby and mute operation. . . . . . . . . . . . . . . 7

I²C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Legacy mode

7.4

7.4.1

7.4.2

7.5

7.5.1

7.5.2

(pin ADSEL connected to ground) . . . . . . . . . . 7

Start-up and shut-down sequence . . . . . . . . . . 8

Power-on reset and supply voltage spikes . . . 12

Engine start and low voltage operation. . . . . . 12

Overvoltage and load dump protection. . . . . . 15

Thermal pre-warning and thermal protection . 15

Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Offset detection. . . . . . . . . . . . . . . . . . . . . . . . 17

DC load detection . . . . . . . . . . . . . . . . . . . . . . 18

AC load detection . . . . . . . . . . . . . . . . . . . . . . 18

I²C-bus diagnostic bits read out . . . . . . . . . . . 19

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

8

8.1

8.2

I²C-bus speciﬁcation . . . . . . . . . . . . . . . . . . . . 20

Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 21

Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

Thermal characteristics. . . . . . . . . . . . . . . . . . 28

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 28

Performance diagrams . . . . . . . . . . . . . . . . . . 34

Application information. . . . . . . . . . . . . . . . . . 40

PCB schematic and layout . . . . . . . . . . . . . . . 42

Test information. . . . . . . . . . . . . . . . . . . . . . . . 44

Quality information . . . . . . . . . . . . . . . . . . . . . 44

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 45

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 46

10

11

12

13

13.1

14

14.1

15

16

17

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 November 2007

Document identifier: TDA8596_2


型号：	TDA8596TH/N1S,118
厂家：	NXP
描述：	TDA8596 - I2C-bus controlled 4 x 45 W power amplifier with symmetrical inputs SOIC 36-Pin 放大器光电二极管商用集成电路
文件：	总48页 (文件大小：268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA8596TH/N1S,118 [NXP]

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