TDA8706AM [NXP]
6-bit analog-to-digital converter with multiplexer and clamp; 6比特的模拟 - 数字转换器，多路转换器和钳
| 型号： | TDA8706AM |
| 厂家： | 
NXP |
| 描述： | 6-bit analog-to-digital converter with multiplexer and clamp |
| 文件： | 总20页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8706A
6-bit analog-to-digital converter
with multiplexer and clamp
1996 Jul 30
Product specification
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
FEATURES
APPLICATIONS
• 6-bit resolution
• General purpose video applications
• R, G and B signals
• Binary 3-state CMOS outputs
• CMOS compatible digital inputs
• 3 multiplexed video inputs
• Automotive (car navigation)
• LCD systems
• R, G and B clamps on code 0
• Frame grabber.
• Single 6-bit ADC operation allowed up to 40 MSPS
• External control of clamping level
• Internal reference voltage (external reference allowed)
• Power dissipation only 36 mW (typical)
• Operating temperature of −40 to +85 °C
• Operating between 2.7 and 5.5 V.
GENERAL DESCRIPTION
The TDA8706A is a 6-bit analog-to-digital converter (ADC)
with 3 analog multiplexed inputs. Each input has an analog
clamp on code 0 for RGB video processing. Clamping
level can also be adjusted externally up to code 20. It can
also be used as a single 6-bit ADC.
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
2.7
TYP.
3.0
MAX.
5.5
UNIT
V
VDDD
VDDO
IDDA
IDDD
IDDO
INL
2.7
2.7
−
3.0
3.0
7
5.5
5.5
10
V
output stages supply voltage
analog supply current
digital supply current
V
mA
mA
mA
LSB
−
4
6
output stages supply current
integral non-linearity
fclk = 40 MHz; ramp input
−
1
1.5
±0.6
fclk = 40 MHz; ramp input;
−
±0.25
Tamb = 25 °C
DNL
differential non-linearity
f
clk = 40 MHz; ramp input;
−
±0.20
±0.5
LSB
MHz
Tamb = 25 °C
fclk(max)
Ptot
maximum clock frequency
total power dissipation
40
−
−
fclk = 40 MHz; ramp input
3 V supplies
−
−
36
−
mW
mW
5.5 V supplies
−
96
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8706AM
SSOP24
plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1996 Jul 30
2
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
BLOCK DIAGRAM
V
V
V
CLK
24
CLPR
CLPB
12
CLPG
13
11
20
19
18
17
16
15
D5
D4
D3
D2
D1
D0
CLAMP
4
CLP
8
digital
voltage
outputs
RED
6-BIT
ADC
CMOS
OUTPUTS
MULTIPLEXER
9
GREEN
10
BLUE
TDA8706A
22
V
SSD
V
REGULATOR
6
DDA
21
DDO
5
1
2
3
7
14
23
MGD133
V
V
V
V
SR SG SB
V
DDA
DDD
RB
V
SSO
SSA
select
inputs
Fig.1 Block diagram.
1996 Jul 30
3
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
PINNING
SYMBOL PIN
DESCRIPTION
select input RED
SR
1
2
3
4
5
6
7
8
9
SG
select input GREEN
select input BLUE
SB
CLP
VDDA
VRB
clamping pulse input (positive pulse)
analog supply voltage
reference voltage BOTTOM input
analog ground
handbook, halfpage
SR
SG
1
2
24 CLK
23
22
21
20
19
18
17
16
15
14
13
V
V
V
DDD
SSD
DDO
VSSA
RED
GREEN
BLUE
VCLPR
VCLPB
VCLPG
VSSO
D0
3
SB
RED input
4
CLP
GREEN input
5
V
D5
D4
D3
D2
D1
D0
V
DDA
10 BLUE input
6
V
RB
11 RED clamping voltage level input
12 BLUE clamping voltage level input
13 GREEN clamping voltage level input
14 digital output ground
TDA8706A
7
V
SSA
8
RED
9
GREEN
BLUE
15 digital voltage output; bit 0 (LSB)
16 digital voltage output; bit 1
17 digital voltage output; bit 2
18 digital voltage output; bit 3
19 digital voltage output; bit 4
20 digital voltage output; bit 5
21 supply voltage for output stage
22 digital ground
10
11
12
D1
V
CLPR
SSO
D2
V
V
CLPB
CLPG
D3
MGD132
D4
D5
VDDO
VSSD
VDDD
CLK
23 digital supply voltage
Fig.2 Pin configuration.
24 clock input
1996 Jul 30
4
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
PARAMETER
MIN.
−0.3
MAX.
+7.0
UNIT
analog supply voltage
digital supply voltage
supply voltage difference
V
V
VDDD
−0.3
+7.0
∆VDD
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−1.0
−1.0
−1.0
−0.3
−
+1.0
+1.0
+1.0
+7.0
10
V
V
V
V
VI
input voltage
IO
output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
−55
−40
−
+150
+85
operating ambient temperature
junction temperature
+150
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
119
K/W
1996 Jul 30
5
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
CHARACTERISTICS
VDDA = V5 to V7 = 2.7 to 5.5 V; VDDD = V23 to V22 = 2.7 to 5.5 V; VDDO = V21 to V14 = 2.7 to 5.5 V;
VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = −40 to +85 °C; typical values measured at
VDDA = VDDD = VDDO = 3 V and Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
VDDD
VDDO
analog supply voltage
digital supply voltage
2.7
2.7
2.7
3.0
3.0
3.0
5.5
V
5.5
5.5
V
V
output stages supply
voltage
∆VDD
supply voltage difference
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−0.3
−0.3
−0.3
−
−
−
−
7
4
1
+0.3
+0.3
+0.3
10
V
V
V
IDDA
IDDD
IDDO
analog supply current
digital supply current
mA
mA
mA
−
6
output stages supply current fclk = 40 MHz; ramp input
−
1.5
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); note 1
VIL
LOW level input voltage
0
0
−
−
−
−
0
2
4
3
V
DDD × 0.3 V
DDD × 0.2 V
VDDD < 3.3 V
V
VIH
HIGH level input voltage
V
DDD × 0.7
DDD × 0.8
VDDD
VDDD
+1
10
−
V
VDDD < 3.3 V
V
V
IIL
IIH
Zi
LOW level input current
HIGH level input current
input impedance
Vclk = VDDD × 0.2
Vclk = VDDD × 0.8
fclk = 40 MHz
−1
−
µA
µA
kΩ
pF
−
CI
input capacitance
fclk = 40 MHz
−
−
INPUTS SR, SG, SB, CLP (REFERENCED TO VSSD
)
VIL
LOW level input voltage
0
0
−
−
−
−
−
−
V
DDD × 0.3 V
DDD × 0.2 V
VDDD < 3.3 V
V
VIH
HIGH level input voltage
V
DDD × 0.7
DDD × 0.8
VDDD
VDDD
−
V
VDDD < 3.3 V
V
V
IIL
LOW level input current
HIGH level input current
VIL = VDDD × 0.2
VIH = VDDD × 0.8
−1
µA
µA
IIH
−
+1
INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2
VCLP
ICLP
input voltage for clamping
input current
Vcode −9
−
−
Vcode 20
30
V
−
µA
1996 Jul 30
6
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ANALOG INPUTS RED, GREEN AND BLUE; see Table 1
Vi(p-p)
input voltage amplitude
(peak-to-peak value)
VDDA = VDDD = 3 V;
Tamb = 25 °C
0.665
0.70
0.735
V
VDDA = VDDD = 5 V;
0.625
0.66
0.695
V
Tamb = 25 °C
Ii
input current
−
−
10
µA
Cclamp
clamp coupling capacitance
1
10
100
nF
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM VDDA = 3 V
VDDA = 5 V
−
−
−
V
DDA − 1.19
DDA − 1.13
−
−
−
V
V
V
∆TVRB
Outputs
temperature variation on
VRB
Tamb = 0 to 50 °C
0.7
mV/°C
DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD
)
VOL
VOH
LOW level output voltage
HIGH level output voltage
IO = 1 mA
0
−
0.5
V
V
IO = −1 mA
V
DDO − 0.5 −
VDDO
Switching characteristics
CLOCK INPUT CLK; see Fig.3; note 1
fclk(max)
maximum clock frequency
40
20
−
−
−
−
MHz
MHz
fmux(max) maximum multiplexer
frequency
tCPH
tCPL
tr
clock pulse width HIGH
clock pulse width LOW
clock rise time
8
8
−
−
−
−
−
ns
ns
ns
−
10% to 90%; fclk ≤ 25 MHz;
10
LOW = VSSD, HIGH = VDDD
tf
clock fall time
90% to 10%; fclk ≤ 25 MHz;
−
−
10
ns
LOW = VSSD, HIGH = VDDD
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input;
Tamb = 25 °C
−
−
±0.25
±0.20
±0.6
±0.5
LSB
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input;
Tamb = 25 °C
EFFECTIVE BITS; note 2
EB
effective bits
f
clk = 40 MHz; fi = 4.43 MHz −
5.8
−
bits
1996 Jul 30
7
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (fclk = 40 MHz; CL = 20 pF); Tamb = 25 °C; see Fig.3
OUTPUT DATA; note 3
tds
th
sampling delay time
output hold time
−
5
−
−
−
−
7
ns
−
−
ns
ns
ns
ns
td
output delay time
VDDO = 4.75 V
VDDO = 3.15 V
VDDO = 2.70 V
12
17
18
15
20
21
SELECT INPUT SIGNALS SR, SG, SB AND CLP
tsu
set-up time SR, SG and SB with no overlap; see Fig.3
10
−
−
ns
ns
ns
ns
ns
with overlap
10% to 90%
90% to 10%
see Fig.4
tr
rise time SR, SG and SB
fall time SR, SG and SB
4
4
0
6
6
−
−
−
−
tf
tover
R, G and B (active) overlap see Fig.4
time with respect to select
signals SR, SG and SB
tCLPP
tMH
clamp pulse time
CCLP = 10 nF
−
3
−
−
µs
multiplexer hold time
SR, SG and SB
9
−
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time of td.
1996 Jul 30
8
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Table 1 Output coding and input voltage (typical values)
Vi(p-p) (V)
DDA = VDDD = 3 V VDDA = VDDD = 5 V
<VDDA − 1.1 <VDDA − 1.06
BINARY OUTPUT BITS
STEP
V
D5
D4
D3
D2
D1
D0
Underflow
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
V
DDA − 1.1
VDDA − 1.06
1
.
.
.
.
.
.
.
.
62
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
63
V
DDA − 0.4
V
DDA − 0.4
Overflow
>VDDA − 0.4
>VDDA − 0.4
Table 2 Clamping input level (VCLPR, VCLPG and VCLPB
CLPR, VCLPG AND VCLPB
)
V
CLAMPING LEVEL
Open-circuit(1)
code 0
Vcode −9 to Vcode 20
code −9 to code 20
Note
1. Use capacitor ≥10 pF to VSSA
.
Table 3 Clamp and inputs RED, GREEN and BLUE; VDDA = VDDD = VDDO = 3 V
SR or SG or SB
CLAMP
VCLPR, VCLPG or VCLPB
Vi RED or GREEN or BLUE
DIGITAL OUTPUTS
open
VCLP
open
VCLP
V
DDA − 1.1 V
VCLP
0
X(1)
1
V
DDA − 1.1 V
VCLP
0
1
code (VCLP
)
Note
1. Where X = don’t care.
Table 4 Clamping characteristic related to TV signals
PARAMETER
Clamping time per line (signal active)
Input signals clamped to correct level
MIN.
TYP.
MAX.
UNIT
2.2
3.0
3
−
µs
lines
−
10
1996 Jul 30
9
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
t
CLK
CPH
t
CPL
t
SU
t
MH
SR
SG
SB
CLAMP
t
CLPP
OUTPUT
DATA
GREEN
t
BLUE
RED
GREEN
MBE859
t
d
h
Fig.3 AC characteristics select signals, clamp and output data.
1996 Jul 30
10
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
CLK
SR
SG
SB
t
over
RED
ACTIVE
t
over
GREEN
ACTIVE
t
t
over
su
BLUE
ACTIVE
MBE860
Fig.4 Anti-overlap system for analog multiplexer.
RED, GREEN, BLUE
(SR, SG, SB inputs)
digital outputs
= 000000
1
0
CLAMP
input
MBE861
Fig.5 AC characteristics select signals; clamp and data.
11
1996 Jul 30
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
V
DDA
handbook, halfpage
V
DDO
R
LAD
REGULATOR
V
RB
D5 to D0
V
SSO
MGD134
V
SSA
MBE967
Fig.6 CMOS data outputs.
Fig.7 VRB.
V
DDD
handbook, halfpage
1
/ V
2
CLK
DDD
V
SSD
MLC860
Fig.8 CLK input.
1996 Jul 30
12
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
APPLICATION INFORMATION
SR
SG
CLK
V
1
2
3
4
5
6
7
8
9
24
23
DDD
V
V
SB
SSD
DDO
22
CLP
21
V
DDA
(1)
D5
D4
D3
D2
D1
20
V
RB
19
100
nF
TDA8706A
V
SSA
18
RED
V
SSA
17
GREEN
16
BLUE
(2)
D0
V
10
11
12
15
V
CLPR
SSO
14
100
nF
(2)
(2)
V
V
CLPB
CLPG
13
100
nF
100
nF
V
SSA
MBE969
V
V
SSA
SSA
The analog and digital supplies should be separated and decoupled.
VRB must not be connected to VCLPR, VCLPB or VCLPG pins.
For applications where the black level is clamped to code 0, VCLPR, VCLPB and VCLPG must be left open-circuit with their respective decoupling
capacitors. In that event, they may also be connected together in order to use only one single decoupling capacitor.
(1) VRB is decoupled to VSSA. Eventually an external regulator can be connected to VRB
.
(2) VCLPR, VCLPB and VCLPG are decoupled to VSSA. Eventually external voltages can be forced on VCLPR, VCLPB and VCLPG
.
Fig.9 Application diagram.
1996 Jul 30
13
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
PACKAGE OUTLINE
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT340-1
MO-150AG
1996 Jul 30
14
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SOLDERING
Introduction
SSOP
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Reflow soldering
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
Reflow soldering techniques are suitable for all SO and
SSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
METHOD (SO AND SSOP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
SO
Repairing soldered joints
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1996 Jul 30
15
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jul 30
16
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
NOTES
1996 Jul 30
17
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
NOTES
1996 Jul 30
18
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
NOTES
1996 Jul 30
19
Philips Semiconductors – a worldwide company
Argentina: see South America
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Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Portugal: see Spain
Romania: see Italy
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Hungary: see Austria
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Indonesia: see Singapore
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Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
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Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
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Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/30/01/pp20
Date of release: 1996 Jul 30
Document order number: 9397 750 00991
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