TDA8706AMDB-T [NXP]
IC 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24, PLASTIC, SOT-340-1, SSOP-24, Analog to Digital Converter;
| 型号： | TDA8706AMDB-T |
| 厂家： | 
NXP |
| 描述： | IC 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24, PLASTIC, SOT-340-1, SSOP-24, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总17页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8706A
6-bit analog-to-digital converter
with multiplexer and clamp
Product specification
2003 Jul 21
Supersedes data of 1996 Jul 30
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
FEATURES
APPLICATIONS
• 6-bit resolution
• General purpose video applications
• R, G and B signals
• Binary CMOS compatible outputs
• CMOS compatible digital inputs
• TLL clock input
• Automotive (car navigation)
• LCD systems
• Three multiplexed video inputs
• R, G and B clamps on code 0
• Frame grabber.
GENERAL DESCRIPTION
• Single 6-bit Analog-to-Digital Converter (ADC) operation
allowed up to 40 MSPS
The TDA8706A is a 6-bit ADC with three analog
multiplexed inputs. Each input has an analog clamp on
code 0 for RGB video processing. Clamping level can also
be adjusted externally up to code 20. It can also be used
as a single 6-bit ADC.
• External control of clamping level
• Internal reference voltage (external reference allowed)
• Power dissipation only 36 mW (typical)
• Operating temperature of −40 to +85 °C
• Operating between 2.7 and 3.6 V
• Sine wave clock allowed.
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
CONDITIONS
MIN.
2.7
TYP. MAX. UNIT
analog supply voltage
digital supply voltage
3.3
3.3
3.3
6.4
4.4
−
3.6
3.6
3.6
10
V
VDDD
VDDO
IDDA
2.7
2.7
−
V
output stage supply voltage
analog supply current
digital supply current
V
mA
mA
mA
LSB
IDDD
IDDO
INL
−
8.5
1.8
output stage supply current
integral non-linearity
fclk = 40 MHz; ramp input
−
f
clk = 40 MHz; ramp input
−
±0.20 ±0.5
DNL
fclk(max)
Ptot
differential non-linearity
maximum clock frequency
total power dissipation
fclk = 40 MHz; ramp input
−
±0.10 ±0.35 LSB
40
−
−
−
MHz
mW
fclk = 40 MHz; ramp input
36
73
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8706AM
SSOP24
plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
2003 Jul 21
2
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
BLOCK DIAGRAM
V
V
V
CLK
24
CLPR
CLPB
12
CLPG
13
11
20 D5
19 D4
CLAMP
4
CLP
18 D3
digital
8
9
RED
GREEN
BLUE
voltage
6-BIT
ADC
CMOS
OUTPUTS
MULTIPLEXER
outputs
17 D2
16 D1
15 D0
10
22
TDA8706A
V
SSD
V
REGULATOR
6
DDA
21
DDO
5
1
2
3
7
14
23
MGD133
V
V
V
DDD
SR SG SB
V
DDA
V
V
SSO
RB
SSA
select
inputs
Fig.1 Block diagram.
2003 Jul 21
3
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
PINNING
SYMBOL PIN
DESCRIPTION
select input RED
SR
1
2
3
4
5
6
7
8
9
SG
select input GREEN
select input BLUE
SB
CLP
VDDA
VRB
clamping pulse input (positive pulse)
analog supply voltage
reference voltage BOTTOM output
analog ground
handbook, halfpage
SR
SG
1
2
24 CLK
23
22
21
20
19
18
17
16
15
14
13
V
V
V
DDD
SSD
DDO
VSSA
RED
GREEN
BLUE
VCLPR
VCLPB
VCLPG
VSSO
D0
3
SB
RED input
4
CLP
GREEN input
5
V
D5
D4
D3
D2
D1
D0
V
DDA
10 BLUE input
6
V
RB
11 RED clamping voltage level input
12 BLUE clamping voltage level input
13 GREEN clamping voltage level input
14 output stage ground
TDA8706AM
7
V
SSA
8
RED
9
GREEN
BLUE
15 digital voltage output; bit 0 (LSB)
16 digital voltage output; bit 1
17 digital voltage output; bit 2
18 digital voltage output; bit 3
19 digital voltage output; bit 4
20 digital voltage output; bit 5
21 output stage supply voltage
22 digital ground
10
11
12
D1
V
CLPR
SSO
D2
V
V
CLPB
CLPG
D3
MGD132
D4
D5
VDDO
VSSD
VDDD
CLK
23 digital supply voltage
Fig.2 Pin configuration.
24 clock input
2003 Jul 21
4
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VDDA
PARAMETER
MIN.
−0.3
MAX.
+7.0
UNIT
analog supply voltage
digital supply voltage
V
V
VDDD
−0.3
+7.0
∆VDD
supply voltage difference
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−1.0
−1.0
−1.0
−0.3
−
+1.0
+1.0
+1.0
+7.0
10
V
V
V
V
VI
input voltage
IO
output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
−40
−
+150
+85
150
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to
ambient
119
K/W
CHARACTERISTICS
VDDA = 2.7 to 3.6 V; VDDD = 2.7 to 3.6 V; VDDO = 2.7 to 3.6 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V;
amb = −40 to +85 °C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C; unless otherwise
T
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDA
analog supply voltage
digital supply voltage
2.7
2.7
2.7
3.3
3.3
3.3
3.6
3.6
3.6
V
VDDD
V
V
VDDO
output stage supply
voltage
∆VDD
supply voltage difference
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−0.3
−0.3
−0.3
−
−
+0.3
+0.3
+0.3
10
V
−
V
−
V
IDDA
IDDD
IDDO
analog supply current
digital supply current
6.4
4.4
−
mA
mA
mA
−
8.5
output stage supply
current
fclk = 40 MHz; ramp input
−
1.8
2003 Jul 21
5
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SYMBOL
Ptot
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
total power dissipation
−
36
73
mW
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); note 1
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
0
−
−
0
2
4
3
0.8
V
2.0
−1
−
VDDD
+1
10
−
V
Vclk = 0.8 V
Vclk = 2.0 V
fclk = 40 MHz
fclk = 40 MHz
µA
µA
kΩ
pF
IIH
Zi
−
Ci
input capacitance
−
−
INPUTS SR, SG, SB AND CLP (REFERENCED TO VSSD
)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
V
DDD × 0.3
V
V
DDD × 0.7
VDDD
−
V
VIL = VDDD × 0.2
VIH = VDDD × 0.8
−1
µA
µA
IIH
−
+1
INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2
VCLP
ICLP
input voltage for clamping
input current
Vcode(−9)
−
−
−
Vcode(20)
30
V
−
µA
LSB
ACLP
clamp accuracy
between inputs RED,
GREEN and BLUE of each
device; Tamb = 25 °C
−1
+1
ANALOG INPUTS RED, GREEN AND BLUE; see Table 1
Vi(p-p)
input voltage amplitude
(peak-to-peak value)
0.63
0.70
0.77
V
Ii
input current
−
−
10
µA
Cclamp
clamp coupling
capacitance
1
10
100
nF
Reference voltages for the resistor ladder; see Table 1
VRB
BOTTOM reference
voltage
VDDA − 1.29 VDDA − 1.21 VDDA − 1.13 V
Outputs
DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD
)
VOL
VOH
LOW-level output voltage IO = 1 mA
HIGH-level output voltage IO = −1 mA
0
−
−
0.5
V
V
V
DDO − 0.5
VDDO
Switching characteristics
CLOCK INPUT CLK; see Fig.3; note 1
fclk(max)
maximum clock frequency
40
20
−
−
−
−
MHz
MHz
fmux(max)
maximum multiplexer
frequency
tCPH
tCPL
clock pulse width HIGH
clock pulse width LOW
9
9
−
−
−
−
ns
ns
2003 Jul 21
6
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SYMBOL
PARAMETER
clock rise time
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ns
tr
10% to 90%;fclk ≤ 40 MHz;
LOW = 0.8 V,
HIGH = 2.0 V
−
−
−
−
7
7
tf
clock fall time
90% to 10%;fclk ≤ 40 MHz;
LOW = 0.8 V,
ns
HIGH = 2.0 V
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input
−
−
±0.20
±0.10
±0.5
LSB
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input
±0.35
EFFECTIVE BITS; note 2
EB
effective bits
fclk = 40 MHz;
fi = 4.43 MHz
5.5
5.8
−
bits
Timing (fclk = 40 MHz; CL = 10 pF); see Fig.3
OUTPUT DATA; note 3
tds
th
sampling delay time
output hold time
−
−
7
ns
ns
ns
6.5
−
9.0
12
−
td
output delay time
19
SELECT INPUT SIGNALS SR, SG, SB AND CLP
tsu
set-up time SR, SG and
SB
with no overlap; see Fig.3 10
−
−
6
6
−
−
−
−
−
−
ns
ns
ns
ns
ns
with overlap; see Fig.4
−
4
4
0
tr
rise time SR, SG and SB 10% to 90%
tf
fall time SR, SG and SB
90% to 10%
see Fig.4
tover
RED, GREEN and BLUE
(active) overlap time with
respect to select signals
SR, SG and SB
tCLPP
tMH
clamp pulse time
CCLP = 10 nF
−
3
−
−
µs
multiplexer hold time SR,
SG and SB
9
−
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns. A sine wave with specified amplitude is also allowed.
2. Effective bits are derived from a Fast Fourier Transform (FFT) processing taking 2K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time td.
2003 Jul 21
7
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Table 1 Output coding and input voltage (typical values); VDDA = VDDD = 3.3 V
BINARY OUTPUT BITS
STEP
Vi (V)
D5
D4
D3
D2
D1
D0
Underflow
<VDDA − 1.12
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
V
DDA − 1.12
1
.
.
.
.
62
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
63
V
DDA − 0.42
Overflow
>VDDA − 0.42
Table 2 Clamping input level (VCLPR, VCLPG and VCLPB
)
V
CLPR, VCLPG, VCLPB
CLAMPING LEVEL
Open-circuit(1)
code 0
Vcode(−9) to Vcode(20)
code −9 to code 20
Note
1. Use capacitor ≥10 pF to VSSA
.
Table 3 Clamp and inputs RED, GREEN and BLUE; VDDA = VDDD = VDDO = 3.3 V
SR or SG or SB
CLAMP
V
CLPR, VCLPG or VCLPB
Vi RED or GREEN or BLUE
DIGITAL OUTPUTS
open
VCLP
open
VCLP
V
DDA − 1.12 V
VCLP
0
don’t care
0
1
V
DDA − 1.12 V
VCLP
1
code (VCLP
)
2003 Jul 21
8
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
t
CLK
CPH
t
CPL
1.4 V
t
SU
t
MH
SR
SG
SB
CLAMP
t
CLPP
OUTPUT
DATA
GREEN
t
BLUE
RED
GREEN
MBE859
t
d
h
Fig.3 AC characteristics select signals, clamp and output data.
2003 Jul 21
9
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
CLK
SR
SG
SB
t
over
RED
ACTIVE
t
over
GREEN
ACTIVE
t
t
over
su
BLUE
ACTIVE
MBE860
Fig.4 Anti-overlap system for analog multiplexer.
RED, GREEN, BLUE
(SR, SG, SB inputs)
digital outputs
= 000000
1
0
CLAMP
input
MBE861
Fig.5 AC characteristics select signals; clamp and data.
10
2003 Jul 21
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
V
handbook, halfpage
DDA
V
DDO
R
LAD
REGULATOR
V
RB
D5 to D0
V
SSO
V
SSA
MGD134
MBE967
Fig.6 CMOS data outputs pins D0 to D5.
Fig.7 Output pin VRB.
V
handbook, halfpage
DDD
1.4 V
CLK
V
SSD
MGX350
Fig.8 Input pin CLK.
11
2003 Jul 21
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
APPLICATION INFORMATION
SR
SG
CLK
V
1
2
3
4
5
6
7
8
9
24
23
(3)
(3)
DDD
V
V
100 nF
100 nF
SB
SSD
DDO
22
CLP
21
V
DDA
(1)
D5
D4
D3
D2
D1
20
V
RB
19
TDA8706A
V
SSA
100 nF
18
100
V
RED
17
nF
SSA
GREEN
BLUE
16
D0
V
10
11
12
15
(2)
V
V
CLPR
SSO
14
(2)
(2)
V
CLPB
CLPG
100 nF
V
13
100 nF
SSA
100 nF
MBE969
SSA
V
V
SSA
The analog and digital supplies should be separated and decoupled.
VDDO should be well decoupled with its capacitor in order to be as close as possible to its pin.
VRB must not be connected to VCLPR, VCLPB or VCLPG pins.
For applications where the black level is clamped to code 0, VCLPR, VCLPB and VCLPG must be left open-circuit with their respective decoupling
capacitors. In that event, they may also be connected together in order to use only one single decoupling capacitor.
(1) VRB is decoupled to VSSA. An external regulator can also be connected to VRB
.
(2) VCLPR, VCLPB and VCLPG are decoupled to VSSA. External voltages can also be forced on VCLPR, VCLPB and VCLPG
.
(3) VDDO and VDDO can be shorted together but the decoupling capacitors should remain as close as possible to its pin.
Fig.9 Application diagram.
2003 Jul 21
12
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
PACKAGE OUTLINE
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A
X
v
c
H
M
A
y
E
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.8
0.4
mm
2
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT340-1
MO-150
2003 Jul 21
13
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Jul 21
14
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Jul 21
15
Philips Semiconductors
Product specification
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jul 21
16
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp17
Date of release: 2003 Jul 21
Document order number: 9397 750 10878
相关型号：
©2020 ICPDF网 联系我们和版权申明