TDA8754HL/27/C1,55 [NXP]

IC 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144, Analog to Digital Converter;


型号：	TDA8754HL/27/C1,55
厂家：	NXP
描述：	IC 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, SOT-486-1, LQFP-144, Analog to Digital Converter 转换器
文件：	总61页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

TDA8754

Triple 8-bit video ADC up to

270 Msps

Product speciﬁcation

2004 May 19

Supersedes data of 2003 Sept 30

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

CONTENTS

9.8

Phase register

9.9

PLL divider registers

Horizontal sync registers

Coast register

Horizontal sync selection register

Vertical sync selection register

Clamp register

FEATURES

9.10

9.11

9.12

9.13

9.14

9.15

9.16

9.17

9.18

9.19

9.20

9.21

9.22

9.23

9.24

9.25

9.26

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

Inverter register

Output register

Output enable register 1

Output enable register 2

Clock output register

Internal oscillator register

Power management register

Read register

PINNING

7.1

7.2

LQFP144 package

LBGA208 package

FUNCTIONAL DESCRIPTION

8.1

Power management

Standby mode

Power-down mode

Analog video input

Analog multiplexers

Activity detection

ADC

Version register

8.1.1

8.1.2

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.3

8.4

8.5

8.6

8.7

Sign detection register

Activity detection register 1

Activity detection register 2

16.1

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

TIMING

Clamp

AGC

HSOSEL, DEO and SCHCKREFO

PLL

Sync-on-green

Programmable coast

Data enable

APPLICATION INFORMATION

PACKAGE OUTLINES

SOLDERING

Introduction to soldering surface mount

packages

8.8

8.9

Sync separator

3-level

16.2

16.3

16.4

16.5

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for

wave and reflow soldering methods

I²C-BUS REGISTER DESCRIPTION

I²C-bus formats

Write 1 register

Write all registers

9.1

9.1.1

9.1.2

9.1.3

9.2

9.3

9.4

Read register

DATA SHEET STATUS

DEFINITIONS

I²C-bus registers overview

Offset registers (R, G and B)

Coarse registers (R, G and B)

Fine registers (R, G and B)

SOG register

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

9.5

9.6

9.7

PLL control

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

FEATURES

• 3.3 V power supply

• Triple 8-bit ADC:

– 0.25 LSB differential non-linearity (DNL)

– 0.6 LSB integral non-linearity (INL).

• Analog sampling rate from 12 Msps up to 270 Msps

• Maximum data rate:

• IC control via I²C-bus serial interface

• Power-down mode

• LQFP144 and LBGA208 package:

– Single port mode: 140 MHz

– Dual port mode: 270 MHz

– LBGA208 package pin to pin compatible with

TDA8756.

– 3.3 V LV-TTL outputs.

• PLL control via I²C-bus:

APPLICATIONS

– 390 ps PLL jitter peak to peak at 270 MHz

• RGB/YUV high-speed digitizing

• LCD panels drive

– Low PLL drift with temperature (2 phase steps

maximum)

• LCD projection system

• New TV concept.

– PLL generates the ADC sampling clock which can be

locked on the line frequency from 15 kHz to 150 kHz

– Integrated PLL divider

GENERAL DESCRIPTION

– Programmable phase clock adjustment cells.

• Three clamp circuits for programming a clamp code

from −24 to +136 by steps of 1 LSB (mid-scale clamping

for YUV signal)

The TDA8754 is a complete triple 8-bit ADC with an

integrated PLL running up to 270 Msps and analog

preprocessing functions (clamp and PGA) optimized for

capturing RGB/YUV graphic signals.

• Internal generation of clamp signal

• Three independent blanking functions

• Input:

The PLL generates a pixel clock from inputs HSYNC and

COAST.

The TDA8754 offers full sync processing for

sync-on-green applications. A clamp signal may be

generated internally or provided externally.

– 700 MHz analog bandwidth

– Two independent analog inputs selectable via

I²C-bus

The clamp levels, gains and other settings are controlled

via the I²C-bus interface.

– Analog input from 0.5 V to 1 V (p-p) to produce a

full-scale ADC input of 1 V (p-p)

– Three controllable amplifiers: gain control via I²C-bus

to produce full-scale peak-to-peak output with a half

LSB resolution.

This IC supports display resolutions up to QXGA

(2048 × 1536) at 85 Hz.

• Synchronisation:

– Frame and field detection for interlaced video signal

– Parasite synchronization pulse detection and

suppression

– Sync processing for composite sync, 3-level sync and

sync-on-green signals

– Polarity and activity detection.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

QUICK REFERENCE DATA

SYMBOL

V_CCA

PARAMETER

CONDITIONS

MIN.

3.0

TYP.

3.3

MAX.

3.6

UNIT

analog supply voltage

digital supply voltage

output supply voltage

analog PLL frequency

effective number of bits

integral non-linearity

differential non-linearity

power dissipation

V_CCD

V_CCO

f_PLL

3.0

−

3.3

−

3.6

270

−

MHz

bits

LSB

ENOB

INL

f_clk= 270 MHz; f_i= 10 MHz

7.6

±0.6

±0.25

−

±1.3

±0.6

1.3

DNL

P_tot

−

ORDERING INFORMATION

PACKAGE

TYPE

SAMPLING

NUMBER

FREQUENCY

NAME

DESCRIPTION

VERSION

TDA8754HL/11

TDA8754HL/14

TDA8754HL/17

TDA8754HL/21

TDA8754HL/27

TDA8754EL/11

TDA8754EL/14

TDA8754EL/17

TDA8754EL/21

TDA8754EL/27

LQFP144

plastic low proﬁle quad ﬂat package;

144 leads; body 20 × 20 × 1.4 mm

SOT486-1

110 MHz

140 MHz

170 MHz

210 MHz

270 MHz

110 MHz

140 MHz

170 MHz

210 MHz

270 MHz

LBGA208⁽¹⁾

plastic low proﬁle ball grid array package;

208 balls; body 17 × 17 × 1.05 mm

SOT774-1

Note

1. Values are not yet guaranteed.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

BLOCK DIAGRAM

handbook, full pagewidth

3×

RGB

output A

LV-TTL

BUFFERS

3×

RGB1

input

CLAMP

AGC

DMX

ADC

RGB2

input

RGB

output B

LV-TTL

BUFFERS

ACTIVITY

DETECTION

HPDO

TDA8754

SOGIN1

SOGIN2

CKDATA

DEO

SYNC

SEPARATOR

HSYNC1

CLKDMX

HCOUNTER

CHSYNC1

HSYNC2

CHSYNC2

COAST

POWER

MANAGEMENT

PLL

VSYNC1

VSYNC2

I C-BUS

SLAVE

MGU895

VSYNCO

HSYNCO

CKEXT CKREFO SDA SCL A0

FIELDO

Fig.1 Block diagram.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

PINNING

LQFP144 package

7.1

SYMBOL

DESCRIPTION

GNDD(TTL)

V_CCD(TTL)

HSYNC2

CHSYNC2

V_CCA(PLL)

HSYNC1

CHSYNC1

GNDA(PLL)

TTL input digital ground

TTL input digital supply voltage

horizontal synchronization pulse input 2

composite horizontal synchronization pulse input 2

PLL analog supply voltage

horizontal synchronization pulse input 1

composite horizontal synchronization pulse input 1

PLL analog ground

PLL ﬁlter input

GNDA(CPO)

CPO analog ground

PLL ﬁlter input

PMO

phase measurement output (test)

SUB analog ground

GNDA(SUB)

CAPSOGIN1

CAPSOGO

CAPSOGIN2

GNDA(SOG)

SOGIN1

V_CCA(SOG)

SOGIN2

V_CCA(R)

decoupling SOG input 1

decoupling SOG output

decoupling SOG input 2

SOG analog ground

sync-on-green input 1

SOG analog supply voltage

sync-on-green input 2

red channel analog supply voltage

red channel analog input 1

RIN1

GNDA(R1)

RIN2

red channel 1 analog ground

red channel analog input 2

GNDA(R2)

DEC

red channel 2 analog ground

main regulator decoupling input

red channel ladder decoupling input

red channel clamp capacitor input

green channel analog supply voltage

green channel analog input 1

green channel 1 analog ground

green channel analog input 2

green channel 2 analog ground

green channel ladder decoupling input

green channel clamp capacitor input

blue channel analog supply voltage

blue channel analog input 1

blue channel 1 analog ground

RBOT

RCLPC

V_CCA(G)

GIN1

GNDA(G1)

GIN2

GNDA(G2)

GBOT

GCLPC

V_CCA(B)

BIN1

GNDA(B1)

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

BIN2

DESCRIPTION

blue channel analog input 2

blue channel 2 analog ground

GNDA(B2)

BBOT

BCLPC

AGCO

GNDD(ADC)

V_CCD(ADC)

GNDD(SUB)

PWD

blue channel ladder decoupling input

blue channel clamp capacitor input

AGC output

ADC digital ground

ADC digital supply voltage

SUB digital ground

power-down control input

TEST

BB0

test input; must be connected to ground

blue channel ADC output B bit 0

blue channel ADC output B bit 1

blue channel ADC output B bit 2

blue channel ADC output B bit 3

blue channel ADC output B bit 4

blue channel ADC output B bit 5

blue channel ADC output B bit 6

blue channel ADC output B bit 7

blue channel B output supply voltage

blue channel B output ground

blue channel ADC output bit out of range

blue channel ADC output A bit 0

blue channel ADC output A bit 1

blue channel ADC output A bit 2

blue channel ADC output A bit 3

blue channel ADC output A bit 4

blue channel ADC output A bit 5

blue channel ADC output A bit 6

blue channel ADC output A bit 7

blue channel A output supply voltage

blue channel A output ground

green channel ADC output B bit 0

green channel ADC output B bit 1

green channel ADC output B bit 2

green channel ADC output B bit 3

green channel ADC output B bit 4

green channel ADC output B bit 5

green channel ADC output B bit 6

green channel ADC output B bit 7

green channel B output supply voltage

green channel B output ground

BB1

BB2

BB3

BB4

BB5

BB6

BB7

V_CCO(BB)

GNDO(BB)

BOR

BA0

BA1

BA2

BA3

BA4

BA5

BA6

BA7

V_CCO(BA)

GNDO(BA)

GB0

GB1

GB2

GB3

GB4

GB5

GB6

GB7

V_CCO(GB)

GNDO(GB)

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

GOR

DESCRIPTION

green channel ADC output bit out of range

GA0

green channel ADC output A bit 0

green channel ADC output A bit 1

green channel ADC output A bit 2

green channel ADC output A bit 3

green channel ADC output A bit 4

green channel ADC output A bit 5

green channel ADC output A bit 6

green channel ADC output A bit 7

green channel A output supply voltage

green channel A output ground

red channel ADC output B bit 0

red channel ADC output B bit 1

red channel ADC output B bit 2

red channel ADC output B bit 3

red channel ADC output B bit 4

red channel ADC output B bit 5

red channel ADC output B bit 6

red channel ADC output B bit 7

red channel B output supply voltage

red channel B output ground

GA1

GA2

GA3

GA4

GA5

GA6

GA7

V_CCO(GA)

GNDO(GA)

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

V_CCO(RB)

GNDO(RB)

ROR

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

red channel ADC output bit out of range

red channel ADC output A bit 0

red channel ADC output A bit 1

red channel ADC output A bit 2

red channel ADC output A bit 3

red channel ADC output A bit 4

red channel ADC output A bit 5

red channel ADC output A bit 6

red channel ADC output A bit 7

red channel A output supply voltage

red channel A output ground

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

V_CCO(RA)

GNDO(RA)

V_CCO(CLK)

CKDATA

GNDO(CLK)

GNDD(I2C)

V_CCD(I2C)

clock output digital supply voltage

data clock output

clock output digital ground

I²C-bus lines digital ground

I²C-bus lines digital supply voltage

I²C-bus address control input

I²C-bus serial data input and output

I²C-bus serial clock input

SDA

SCL

DIS

I²C-bus disable control input

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

TDO

DESCRIPTION

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

scan test output

TCK

scan test mode input; must be connected to ground

clamp pulse input

CLP

STBYDIV

GNDD(MCF)

V_CCD(MCF)

HSYNCO

DEO

DVI standby output

MCF digital ground

MCF digital supply voltage

horizontal synchronization pulse output

data enable output

HPDO

hot plug detector output

GNDO(TTL)

V_CCO(TTL)

VSYNCO

FIELDO

CLPO

TTL output digital ground

TTL output digital supply voltage

vertical synchronization pulse output

ﬁeld information output

clamp output

CKREFO

CSYNCO

ACRX2

reference output clock; re-synchronized horizontal negative pulse

composite synchronization output

test pin; should be connected to ground

SLC digital ground

ACRX1

GNDD(SLC)

V_CCD(SLC)

CKEXT

SLC output digital supply voltage

external clock input

COAST

PLL coast control input

VSYNC2

VSYNC1

vertical synchronization pulse input 2

vertical synchronization pulse input 1

108

handbook, halfpage

109

TDA8754HL

144

MGU896

Fig.2 Pin configuration LQFP144 package.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

7.2

LBGA208 package

SYMBOL

SOGIN1

BALL

DESCRIPTION

sync-on-green input 1

PLL analog ground

sync-on-green input 2

PLL analog ground

GNDA(PLL)

SOGIN2

GNDA(PLL)

HSYNC2

CHSYNC2

COAST

CSYNCO

FIELDO

HSYNCO

SCL

horizontal synchronization pulse input 2

composite horizontal synchronization pulse input 2

PLL coast control input

composite synchronization output

ﬁeld information output

A10

A11

A12

A13

A14

A15

A16

horizontal synchronization pulse output

I²C-bus serial clock input

not connected

n.c.

not connected

DIS

I²C-bus disable control input

I²C-bus address control input

data clock output

CKDATA

GNDA(PLL)

PMO

PLL analog ground

phase measurement output (test)

PLL analog ground

GNDA(PLL)

V_CCA(PLL)

CLP

PLL analog ground

PLL analog supply voltage

clamp pulse input

CKEXT

CKREFO

VSYNCO

DEO

external clock input

reference output clock; re-synchronized horizontal negative pulse

vertical synchronization pulse output

data enable output

B10

B11

B12

B13

B14

B15

B16

SDA

I²C-bus serial data input and output

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDO(CLK)

V_CCO(CLK)

RIN1

clock output digital ground

clock output digital supply voltage

red channel analog input 1

analog ground

GNDA

CAPSOGIN1

CAPSOGIN2

CAPSOGO

HSYNC1

VSYNC1

CLPO

decoupling SOG input 1

decoupling SOG input 2

decoupling SOG output

horizontal synchronization pulse input 1

vertical synchronization pulse input 1

clamp output

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

n.c.

BALL

DESCRIPTION

C10

C11

C12

C13

C14

C15

C16

not connected

n.c.

not connected

TCK

scan test mode input

scan test output

I²C-bus lines digital supply voltage

not connected

TDO

V_CCD(I2C)

n.c.

not connected

n.c.

not connected

GNDA

analog ground

PLL ﬁlter input

GNDA(CPO)

CHSYNC1

VSYNC2

HPDO

n.c.

CPO analog ground

composite horizontal synchronization pulse input 1

vertical synchronization pulse input 2

hot plug detector output

not connected

n.c.

D10

D11

D12

D13

D14

D15

D16

not connected

V_CCO(TTL)

GNDO(TTL)

GNDD(I2C)

n.c.

TTL output digital supply voltage

TTL output digital ground

I²C-bus lines digital ground

not connected

n.c.

not connected

n.c.

not connected

RIN2

red channel analog input 2

analog ground

GNDA

GNDD(TTL)

V_CCD(TTL)

GNDD(SLC)

V_CCD(SLC)

n.c.

analog ground

TTL input digital ground

TTL input digital supply voltage

SLC digital ground

E10

E13

E14

E15

E16

SLC output digital supply voltage

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

RBOT

GNDA

n.c.

analog ground

red channel ladder decoupling input

analog ground

F13

not connected

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

n.c.

BALL

DESCRIPTION

F14

F15

F16

not connected

n.c.

not connected

n.c.

not connected

GIN1

GNDA

DEC

V_CCA

n.c.

green channel analog input 1

analog ground

main regulator decoupling input

analog supply voltage

not connected

G12

G13

G14

G15

G16

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

RCLPC

V_CCA

n.c.

analog ground

red channel clamp capacitor input

analog supply voltage

not connected

H12

H13

H14

H15

H16

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GIN2

GNDA

GBOT

GNDA

GCLPC

n.c.

green channel analog input 2

analog ground

green channel ladder decoupling input

analog ground

green channel clamp capacitor input

not connected

J12

J13

J14

J15

J16

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

BCLPC

V_CCA

n.c.

analog ground

blue channel clamp capacitor input

analog supply voltage

not connected

K12

K13

K14

n.c.

not connected

n.c.

not connected

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

n.c.

BALL

DESCRIPTION

K15

K16

not connected

n.c.

not connected

BIN1

GNDA

BBOT

V_CCA

n.c.

blue channel analog input 1

analog ground

blue channel ladder decoupling input

analog supply voltage

not connected

L13

L14

L15

L16

M10

M13

M14

M15

M16

n.c.

not connected

n.c.

not connected

n.c.

not connected

GNDA

AGCO

TEST

V_CCO

GNDO

n.c.

analog ground

AGC output

test input

data output digital supply voltage

data output digital ground

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

BIN2

GNDA

GNDD(ADC)

BA2

blue channel analog input 2

analog ground

ADC digital ground

blue channel ADC output A bit 2

data output digital supply voltage

green channel ADC output B bit 4

green channel ADC output B bit 0

green channel ADC output A bit 4

green channel ADC output A bit 0

data output digital ground

power-down control input

not connected

V_CCO

GB4

GB0

GA4

GA0

N10

N11

N12

N13

N14

N15

N16

GNDO

PWD

n.c.

not connected

n.c.

not connected

n.c.

not connected

V_CCD(ADC)

BB1

ADC digital supply voltage

blue channel ADC output B bit 1

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

BA6

BALL

DESCRIPTION

blue channel ADC output A bit 6

blue channel ADC output A bit 3

BA3

BOR

GB5

GB1

GA5

GA1

RB6

RB3

RB0

RA5

RA2

ROR

BB6

BB4

BB2

BA7

BA4

BA0

GB6

GB2

GA6

GA2

RB7

RB4

RB1

RA6

RA3

RA0

BB7

BB5

BB3

BB0

BA5

BA1

GB7

GB3

GA7

GA3

GOR

RB5

blue channel ADC output bit out of range

green channel ADC output B bit 5

green channel ADC output B bit 1

green channel ADC output A bit 5

green channel ADC output A bit 1

red channel ADC output B bit 6

red channel ADC output B bit 3

red channel ADC output B bit 0

red channel ADC output A bit 5

red channel ADC output A bit 2

red channel ADC output bit out of range

blue channel ADC output B bit 6

blue channel ADC output B bit 4

blue channel ADC output B bit 2

blue channel ADC output A bit 7

blue channel ADC output A bit 4

blue channel ADC output A bit 0

green channel ADC output B bit 6

green channel ADC output B bit 2

green channel ADC output A bit 6

green channel ADC output A bit 2

red channel ADC output B bit 7

red channel ADC output B bit 4

red channel ADC output B bit 1

red channel ADC output A bit 6

red channel ADC output A bit 3

red channel ADC output A bit 0

blue channel ADC output B bit 7

blue channel ADC output B bit 5

blue channel ADC output B bit 3

blue channel ADC output B bit 0

blue channel ADC output A bit 5

blue channel ADC output A bit 1

green channel ADC output B bit 7

green channel ADC output B bit 3

green channel ADC output A bit 7

green channel ADC output A bit 3

green channel ADC output bit out of range

red channel ADC output B bit 5

P10

P11

P12

P13

P14

P15

P16

R10

R11

R12

R13

R14

R15

R16

T10

T11

T12

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

RB2

BALL

DESCRIPTION

T13

T14

T15

T16

red channel ADC output B bit 2

red channel ADC output A bit 7

red channel ADC output A bit 4

red channel ADC output A bit 1

RA7

RA4

RA1

MBL890

handbook, halfpage

TDA8754EL

11 13 15

10 12 14 16

Fig.3 Pin configuration LBGA208 package.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

FUNCTIONAL DESCRIPTION

8.2.1

ANALOG MULTIPLEXERS

This triple high-speed 8-bit ADC is designed to convert

RGB/YUV signals coming from an analog source into

digital data used by a LCD driver (pixel clock up to

270 MHz with analog source) or projections systems.

The TDA8754 has two analog inputs (RGB input 1 and

RGB input 2) selectable via the I²C-bus.

The sync management can be achieved in several ways:

• Choice between two analog inputs HSYNC and two

analog inputs VSYNC

8.1

Power management

• Choice between two analog inputs CHSYNC

• Choice between two analog inputs SOG.

It is possible to put the TDA8754 in standby mode by

setting bit STBY = 1 or to put the whole device in power-

down mode by setting pin PWD to HIGH level.

8.2.2

ACTIVITY DETECTION

8.1.1

STANDBY MODE

When a signal is connected or disconnected on

pins HSYNC1(2), CHSYNC1(2), VSYNC1(2) and

SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is

set to HIGH to advise the user of a change. Bit HPDO is

set to logic 0 and pin HPDO is set to LOW when register

ACTIVITY2 has been read.

In standby mode, the status of the blocks is as follows:

• Activity detection, I²C-bus slave, sync separator and

SOG are still active

• Pixel counter, ADCs, demultiplexers, AGC and clamp

cells are inactive

When the synchronization pulse on pin SOG is 3-level, the

system will automatically be able to detect that a 3-level

sync is present and will force bit 3LEVEL to logic 1. It is

possible to disable this function with bit FTRILEVEL.

• Output buffers to the RGB block (RGB 0 to 7, CKDATA,

DEO, HSYNCO and VSYNCO) are in high-impedance

state

• Output HPDO is still active

When an interlaced signal is detected, bit ACFIELD is set

to logic 1. When the signal detected is progressive, this bit

is set to logic 0. Any change in this bit results into setting

bit HPDO = 1 and pin HPDO = HIGH.

• Output buffers (ROR, BOR, GOR, CKREFO, CSYNCO,

CLPO and FIELDO) are in a LOW-level state.

8.1.2

POWER-DOWN MODE

A field detection unit is available on pin FIELDO which

output is given by the sync separator. The field identity is

given by pin FIELDO. This pin gives the field of interlaced

signal input.

In power-down mode the status of the blocks is as follows:

• All digital inputs and outputs are in high-impedance

state

• All blocks are inactive (I²C-bus, activity detection, ADCs,

etc.)

An automatic polarity detection is also available on

pins HSYNC1(2), VSYNC1(2) and CHSYNC1(2). The

output on pin HPDO is not affected by the change of

polarity of these inputs.

• Analog output is left uncontrolled

• I²C-bus is left in high-impedance state.

8.2.3

ADC

8.2

Analog video input

The three ADCs are designed to convert R, G and B

(or Y, U and V) signals at a maximum frequency of

270 Msps. The ADC input range is 1 V (p-p) full-scale and

the pipeline delay is 2 ADC clock cycles from the input

sampling to the data output.

The RGB/YUV video inputs are externally AC coupled and

are internally DC polarized. The synchronization signals

are also used by the device as input for the internal PLL

and the automatic clamp.

The reference ladders regulators are integrated.

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8.2.4

CLAMP

properly in order to create the correct HSYNCO and DEO

output signals (see Figs.5 and 6), which is depending on

video standard. Output signal DEO should be used to

determine the first active pixel.

Three independent parallel clamping circuits are used to

clamp the video input signals on programmable black

levels. The clamp levels may be set from

−24 to +136 LSBs in steps of 1 LSB. They are controlled

by three 9-bit I²C-bus registers (OFFSETR, OFFSETG

and OFFSETB).

The demultiplexed mode should be used (bit DMX = 1)

and the output flow is alternated between port A and port B

in case the sampling frequency is over 140 Msps (clock

frequency). It is necessary, in order to warrant that the

outputs HSYNCO and DEO are always changing on

CKDATA output rising edge (see Fig.7), that the values

HSYNCL, HBACKL and HDISPL (see Fig.5) are even

value. If an odd value is entered the outputs HSYNCO and

DEO can change state during falling edge, which is not

compliant with the t_h(o)and t_d(o)specified output timing.

The clamp pulse can be generated internally (based on the

PLL clock reference) or can be externally applied on

pin CLP.

By setting correctly the I²C-bus bits, it is possible to inhibit

the clamp request with the Vsync signal. This inhibition will

be effected by forcing logic 0 on the clamp request output.

It should be noted that the clamp period can start on the

falling edge of the clamp request and that the high level of

the clamp request sets the ADC outputs in the blanking

mode. This means that by forcing the clamp signal request

to logic 0 by using Vsync, a falling edge may happen on

the clamp request if this signal was at logic 1 before

enforcing the inhibition. To avoid this, the user has to

guarantee that the Vsync signal used for the clamp

inhibition will not be set during a high level of the clamp

request signal.

Bit SCHCKREFO is used if in demultiplexed mode one

pixel shift is needed in the DEO signal (to move the screen

one vertical line). By setting bit SCHCKREFO from a

logic 0 to a logic 1 a left move is obtained, also the timing

relationship between HSYNCO, DEO and CKDATA stays

unchanged. An even number of pixel moves is done by

changing the value of HBACKL and HSYNCL. The correct

combination of bits HBACKL, HSYNCL and SCHCKREFO

places the first active pixel at the beginning of the screen

with always the correct phase relationship between

outputs DEO, HSYNCO and CKDATA.

Remark: If signal Vsync is coming from the external

pin VSYNC, this signal may be used to coast the PLL.

In order to properly do the coast, the edge of signal Vsync

(COAST) must not appear at the same time as the edge of

signal Hsync. This condition is similar to the pin CLP

inhibition condition.

Bit HSOSEL should be set to a logic 0 only after the PLL is

stable, so only after the video standard has been found

and correct PLL parameters have been set in the

TDA8754. Bit HSOSEL should be set to a logic 1 to have

a stable HSYNCO signal during the video recognition. The

video standard can be recognized by using the signals

FIELDO, VSYNCO and HSYNCO. The phase relation

between CKDATA and HSYNCO (or DEO) is undefined if

bit HSOSEL = 1.

8.2.5

AGC

Three independent variable gain amplifiers are used to

provide, for each channel, a full-scale input signal to the

8-bit ADC. The gain adjustment range is designed in such

a way that for an input range varying from 0.5 to 1 V (p-p),

the output signal corresponds to the ADC full-scale input

of 1 V (p-p).

8.4

PLL

The ADCs are clocked by either the internal PLL locked to

the reference clock (Hsync from input or Hsync from sync

separator) or to an external clock connected to

pin CKEXT. This selection is performed via the I²C-bus by

setting bit CKEXT. To use the external clock, bit CKEXT

must be reset to logic 1.

8.3

HSOSEL, DEO and SCHCKREFO

Bit HSOSEL allows to have a full correlation phase

behaviour between outputs CKDATA and HSYNCO when

bit HSOSEL = 0 (Hsync from counter). If HSOSEL = 0 and

bits PA4 to PA0 of register PHASE are changed to chose

the best sampling time, the phase relationship between

outputs CKDATA and HSYNCO will stay unchanged. After

the video standard is determined, bit HSOSEL must be set

to a logic 0 for normal operation mode.

The PLL phase frequency detector can be disconnected

during the frame flyback (vertical blanking) or the

unavailability of the Ckref signal by using the coast

function. The coast signal can be derived from the

VSYNC1(2) input, from the Vsync extracted by the sync

separator or from the coast input. The coast function can

be disabled with bit COE.

To use the Hsync from the counter the registers HSYNCL,

HBACKL, HDISPLMSB and HDISPLLSB should be set

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The coast signal may be active either HIGH or LOW by

setting bit COS.

HSYNCO output of the sync separator is always a mostly

low signal, whatever is the polarity of the composite sync

input. The VSYNCO output signal of the sync separator is

also mostly low signal. It is at a high state during the

vertical blanking.

It is possible to control the phase of the ADC clock via the

I²C-bus with the included digital phase-shift controller. The

phase register (5 bits) enables to shift the phase by steps

of 11.25 deg.

8.5

Sync-on-green

The PLL also provides a CKDATA clock. This clock is

synchronized with the data outputs whatever the output

mode is.

When the SOG input is selected (bit SOGSEL = 1), the

SOG charge pump current bits SOGI[1:0] should be

programmed in function of the input signal; see Table 1.

It is possible to delay the CKDATA clock with a constant

delay (t = 2 ns compared to the outputs) by setting

bit CKDD = 1. Moreover, it is possible to invert this output

by setting bit CKDATINV = 1.

A hum remover is implemented in the SOG. It removes

completely the hum perturbation on the first or second

edge of the horizontal sync pulse for digital video input like

VESA, and on the second edge only for analog video input

signal like TV or HDTV.

When the PLL reference signal comes from the separator,

the PLL rising edge must be preferably used in order to not

use the PLL coast mode. It should be noted that the

The maximum hum perturbation is 250 mV (p-p) at 60 Hz

to have a correct SOG functionality.

Table 1 Charge pump current programming; note 1

MAXIMUM VALUE

∆Tvideo / ∆Tline

MAXIMUM VALUE

∆Tsync / ∆Tline

BITS SOGI[1:0]

STANDARD

83.5 %

86.0 %

14.8 %

12.6 %

8.6 %

TV standards and non-VESA standards

all TV, HDTV and VESA standards

90.5 %

HDTV standards or non-VESA standards

test mode

Note

1. Definitions:

∆Tvideo = total time in 2 frames when video signal is strictly superior to black level.

∆Tline = total time of 2 frames.

∆Tsync = total time in 2 frames when the video signal is strictly inferior to black level.

8.6

Programmable coast

8.7

Data enable

When the values of PRECOAST[2:0] = 0 and

POSTCOAST[4:0] = 0, the coast pulse equals the Vsync

input.

This signal qualifies the active data period on the

horizontal line. Pin DEO = HIGH during the active display

time and LOW during the blank time. The start of this

signal can be adjusted with bits HSYNCL[9:0] and

HBACKL[9:0]. The length of this signal can be adjusted

with bits HDISPL[11:0].

When an interlaced signal is used, the regenerated coast

pulse width may vary from one frame to another of one

Hsync pulse. In that case, the programmed value of

PRECOAST[2:0] needs to be increased by one compared

to the expected minimum number of Hsync coast pulses

before the vertical sync signal.

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8.8

Sync separator

This function is able to get rid of the additional

synchronization pulses in vertical blanking like

equalization or serration pulses.

The sync separator is compatible with TV, HDTV and

VESA standards.

If the green video signal has composite sync on it

(sync-on-green), the SOG function allows to separate the

Chsync and the active video part. The Chsync signal

coming from this SOG function is accessible through

pin CSYNCO.

8.9

3-level

When the synchronization pulse of the input of the SOG is

3-level, the system will be able to detect that a 3-level sync

is present and will advise the customer if a change is

observed by setting bit HPDO = 1 and pin HPDO = HIGH.

It is possible to disable this function with bit FTRILEVEL.

When this automatic function is disabled, the manual

mode will only influence the separator circuitry.

It is possible to extract the Hsync and the Vsync signals by

using the sync separator from this (C)Hsync signal coming

from SOG or coming from the (C)Hsync input.

I²C-BUS REGISTER DESCRIPTION

I²C-bus formats

9.1

9.1.1

WRITE 1 REGISTER

Each register is programmed independently by giving its subaddress and its data content.

Table 2 I²C-bus sequence for writing 1 register

SDA LINE

DESCRIPTION

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

Byte 2

master transmits programming mode and subregister address to write to

slave generates an acknowledge

Byte 3

master transmits data 1

slave generates an acknowledge

master generates a stop condition

Table 3 Byte format for writing 1 register

BIT

Byte 1

R/W

−

device address

Byte 2

Byte 3

programming mode

−

MODE

SA4

SA3

SA2

SA1

SA0

−

data 1

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Table 4 Write format bit description

BIT

Byte 1

SYMBOL

DESCRIPTION

7 to 1

A[6:0]

R/W

Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level

on pin A0.

Write command bit. If R/W = 0, then write action.

Byte 2

7 to 6

−

not used

MODE

SA[4:0]

Mode selection bit. If MODE = 0, then each register can be written independently.

4 to 0

Byte 3

7 to 0

D[7:0]

Data 1. This value is written in the selected register.

9.1.2

WRITE ALL REGISTERS

All registers are programmed one after the other, by giving this initial condition (XX11 1111) as the subaddress state;

thus, the registers are charged following the predefined sequence of 32 bytes (from subaddress 0 0000 to 1 1111).

Table 5 I²C-bus sequence for writing all registers

SDA LINE

DESCRIPTION

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

Byte 2

master transmits programming mode and subregister address to start writing to

slave generates an acknowledge

Byte 3

master transmits data 1

slave generates an acknowledge

Byte 34

master transmits data 32

slave generates an acknowledge

master generates a stop condition

Table 6 Byte format for writing all registers

BIT

Byte 1

device address

R/W

−

Byte 2

programming mode

−

MODE

SA4

SA3

SA2

SA1

SA0

Byte (2 + n)

data n

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Table 7 Write format bit description

BIT

Byte 1

SYMBOL

DESCRIPTION

7 to 1

A[6:0]

R/W

Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level

on pin A0.

Write command bit. If R/W = 0, then write action.

Byte 2

7 to 6

−

not used

MODE

SA[4:0]

Mode selection bit. If MODE = 1, then all registers can be written one after the other.

4 to 0

Byte (2 + n)

7 to 0

D[7:0]

Data n. This value is written in register 00h + n.

9.1.3

READ REGISTER

Table 8 I²C-bus sequence for reading one register

SDA LINE

DESCRIPTION

master starts with a start condition

Byte 1

master transmits device address (7 bits) plus write command bit (R/W = 0)

slave generates an acknowledge

Byte 2

master transmits programming mode and subregister address to read from

slave generates an acknowledge

Byte 3

master transmits read register subaddress

slave generates an acknowledge

Byte 4

master transmits device address (7 bits) plus read command bit (R/W = 1)

slave generates an acknowledge

Byte 5

slave transmits data to master

master generates an not-acknowledge after reading the data byte

master generates a stop condition

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Table 9 Byte format for reading register

BIT

Byte 1

device address

R/W

−

Byte 2

Byte 3

Byte 4

Byte 5

programming mode

−

MODE

SA4

SA3

SA2

SA1

SA0

read subaddress

−

RA1

RA0

−

device address

R/W

−

data 1

Table 10 Read format bit description

BIT

Byte 1

SYMBOL

DESCRIPTION

7 to 1

A[6:0]

R/W

Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level

on pin A0.

Write command bit. If R/W = 0, then write action.

Byte 2

7 to 6

−

not used

MODE

SA[4:0]

Mode selection bit. If MODE = 0, then each register can be written independently.

4 to 0

Byte 3

7 to 0

Byte 4

7 to 1

RA[1:0]

Read address. This is the value of the read register to be selected.

A[6:0]

R/W

Device address. The TDA8754 address is 1001 10X. Bit A0 relates with the voltage level

on pin A0.

Read command bit. If R/W = 1, then read action.

Byte 5

7 to 0

D[7:0]

Data 1. The value from read register is sent from the slave to the master.

2004 May 18

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9.2

I²C-bus registers overview

Table 11 I²C-bus analog write registers

MSB

BIT

LSB

DEFAULT

VALUE

ADDR

NAME

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

OFFSETR

COARSER

FINER

OR7

OR8

−

OR6

CR6

−

OR5

CR5

−

OR4

CR4

−

OR3

OR2

CR2

FR2

OG2

CG2

FG2

OB2

CB2

FB2

OR1

CR1

FR1

OG1

CG1

FG1

OB1

CB1

FB1

OR0

0000 0000

0100 0110

XXXX X000

0000 0000

0100 0110

XXXX X000

0000 0000

0100 0110

XXXX X000

0000 0001

0101 1100

0000 0101

0000 0110

CR3

−

CR0

FR0

OFFSETG

COARSEG

FINEG

OG7

OG8

−

OG6

CG6

−

OG5

CG5

−

OG4

CG4

−

OG3

CG3

−

OG0

CG0

FG0

OB0

CB0

FB0

OFFSETB

COARSEB

FINEB

OB7

OB8

−

OB6

CB6

−

OB5

CB5

−

OB4

CB4

−

OB3

CB3

−

SOG

FTRILEVEL STRILEVEL CKREFS

SOGSEL

DR2

SOGI1

DR1

SOGI0

DR0

VCO0

DI8

PLLCTRL

PHASE

IP1

IP0

PA3

PA4

CKEXT

PA2

EPSI1

PA1

EPSI0

PA0

DI11

VCO2

DI10

VCO1

DI9

DIVMSB

SCH

CKREFO

0Dh

0Eh

0Fh

10h

11h

12h

DIVLSB

HSYNCL

HBACKL

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

1001 1000

0010 0100

0000 1111

1000 0101

0000 0000

HSYNCL9 HSYNCL8 HSYNCL7

HSYNCL1 HSYNCL0 HBACKL9

HSYNCL6

HBACKL8

HBACKL0

HDISPL4

HSYNCL5

HBACKL7

HDISPL11

HDISPL3

HSYNCL4 HSYNCL3

HBACKL6 HBACKL5

HDISPL10 HDISPL9

HSYNCL2

HBACKL4

HDISPL8

HDISPL0

HDISPLMSB HBACKL3 HBACKL2 HBACKL1

HDISPLLSB

COAST

HDISPL7 HDISPL6 HDISPL5

PRE PRE PRE

COAST2 COAST1 COAST0

HDISPL2

HDISPL1

POST

COAST4

POST

COAST3

POST

COAST2

POST

COAST1

POST

COAST0

13h

14h

15h

16h

HSYNCSEL

VSYNCSEL

CLAMP

−

TESTCNT

BYSEPA

VSS

HSSEL

COSSEL2

ICLP

HSS

XXX X0100

XXX0 0000

X010 0000

X000 0000

TSTCOAST COE

COSSEL1

CLPT

HSOSEL CLPSEL2

CLPSEL1

CLPH

CLPENL

INVERTER

COS

CLPS

CKREFO

INV

DEO

INVRGB

HSO

INVRGB

VSO

INVRGB

FIELDO

INV

17h

18h

OUTPUT

RGBSEL TEN

AGCSEL1

AGCSEL0

BLKEN

DMXRGB ODDARGB

SHIFTRGB 0000 0000

OUTPUTEN1

−

BOENRGB AOENRGB

OROEN TOUTERGB TOUTSRGB XXX1 1100

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MSB

BIT

LSB

DEFAULT

VALUE

ADDR

NAME

19h

OUTPUTEN2 CKROEN CSOEN

DEOEN

RGB

HSOEN

RGB

HPDOEN

VSOEN

RGB

CLPOEN

FIELDOEN

1111 1111

XXX0 0001

XXXX XX00

1Ah

1Bh

CLKOUTPUT

INTOSC

−

CKSEL

RGB

DLYCLK

RGB

CKDAT

INV

OUT

OSCILL

CKOEN

RGB

−

SWITCH

OSC

INTOSC

OFF

1Ch

1Dh

1Eh

1Fh

reserved

PWRMGT

READADDR

−

SHCKDMX

SHCKADC STBY

DVIRGB

ADDR0

XXXX 0000

XXXX XX00

−

ADDR1

Table 12 I²C-bus analog read registers; note 1

MSB

BIT

LSB

DEFAULT

VALUE

ADDR

NAME

VER0

VERSION

SIGN

−

VER3

VER2

VER1

XXXX 0000

XX00 0000

0000 0000

X000 0000

POLVS2

ACSOG2

3LEVEL

POLVS1

ACSOG1

ACFIELD

POLCHS2

ACCHS2

HPDO

POLCHS1 POLHS2

ACCHS1 ACHS2

ACVSSEP ACRXC1

POLHS1

ACHS1

ACRXC0

ACTIVITY1

ACTIVITY2

ACVS2

ACVS1

ASD

−

Note

1. The read register address is specified with bits ADDR1 and ADDR0 of register READADDR.

Philips Semiconductors

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9.3

Offset registers (R, G and B)

The offset registers contain a 9-bit value which controls the clamp level for the RGB channels. The 8 LSBs are in the

offset registers and the 1 MSB is in the coarse gain control register. The relationship between the programming code and

the level of the clamp code is given in Table 15. The default value is: clamp code = 0 and ADC output = 0.

Table 13 Offset registers (00h, 03h, 06h) bit allocation

OFFSETR (00h)

OFFSETG (03h)

OFFSETB (06h)

Default

OR7

OG7

OB7

OR6

OG6

OB6

OR5

OG5

OB5

OR4

OG4

OB4

OR3

OG3

OB3

OR2

OG2

OB2

OR1

OG1

OB1

OR0

OG0

OB0

Table 14 Offset registers (00h, 03h, 06h) bit description

BIT SYMBOL

OFFSETR (address: 00h)

7 to 0 OR[7:0]

OFFSETG (address: 03h)

7 to 0 OG[7:0]

OFFSETB (address: 06h)

7 to 0 OB[7:0]

DESCRIPTION

offset R channel; LSB in this register and MSB bit OR8 in register COARSER

offset G channel; LSB in this register and MSB bit OG8 in register COARSEG

offset B channel; LSB in this register and MSB bit OB8 in register COARSEB

Table 15 Coding for clamp level and ADC output

OR8 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0

HEX

VALUE

CLAMP CODE

(DECIMAL)

ADC OUTPUT

(CODE TRANSITION)

OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0

OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0

1 E9

1 EA

−24

−23

−24/−23

−23/−22

−1/0

0/1

1 FF

0 00

0 01

−1

1/2

0 3F

0 40

63/64

64/65

0 78

0 79

120

121

120/121

121/122

0 80

128

128/129

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OR8 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0

HEX

CLAMP CODE

(DECIMAL)

ADC OUTPUT

(CODE TRANSITION)

OG8 OG7 OG6 OG5 OG4 OG3 OG2 OG1 OG0

VALUE

OB8 OB7 OB6 OB5 OB4 OB3 OB2 OB1 OB0

0 86

0 87

134

135

134/135

135/136

9.4

Coarse registers (R, G and B)

The coarse gain of the AGC is controlled with 7 bits. The code gain can vary from 32 to 95; see Table 18.

Table 16 Coarse gain registers (01h, 04h, 07h) bit allocation

COARSER (01h)

COARSEG (04h)

COARSEB (07h)

Default

OR8

OG8

OB8

CR6

CG6

CB6

CR5

CG5

CB5

CR4

CG4

CB4

CR3

CG3

CB3

CR2

CG2

CB2

CR1

CG1

CB1

CR0

CG0

CB0

Table 17 Coarse gain registers (01h, 04h, 07h) bit description

BIT SYMBOL

COARSER (address: 01h)

DESCRIPTION

OR8

offset R channel; MSB bit of offset value

6 to 0

CR[6:0]

coarse gain of the AGC for R channel

COARSEG (address: 04h)

OG8

offset G channel; MSB bit of offset value

coarse gain of the AGC for G channel

6 to 0

CG[6:0]

COARSEB (address: 07h)

OB8

offset B channel; MSB bit of offset value

coarse gain of the AGC for B channel

6 to 0

CB[6:0]

Table 18 Coarse register

CR6 CR5 CR4 CR3 CR2 CR1 CR0

DECIMAL

VALUE

CG6 CG5 CG4 CG3 CG2 CG1 CG0 V_iTO BE FULL-SCALE

CB6 CB5 CB4 CB3 CB2 CB1 CB0

GAIN ADC

1.000

0.992

1.000

1.008

0.753

0.746

0.738

1.328

1.340

1.355

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CR6 CR5 CR4 CR3 CR2 CR1 CR0

DECIMAL

VALUE

CG6 CG5 CG4 CG3 CG2 CG1 CG0 V_iTO BE FULL-SCALE

GAIN ADC

CB6 CB5 CB4 CB3 CB2 CB1 CB0

0.706

0.698

1.416

1.432

0.500

2.000

9.5

Fine registers (R, G and B)

Fine gain control is done with 3 bits allowing 8 intermediate values between two values of consecutive coarse gain.

Table 19 Fine gain registers (02h, 05h, 08h) bit allocation

FINER (02h)

−

FR2

FG2

FB2

FR1

FG1

FB1

FR0

FG0

FB0

FINEG (05h)

FINEB (08h)

Default

Table 20 Fine gain registers (02h, 05h, 08h) bit description

BIT SYMBOL

FINER (address: 02h)

DESCRIPTION

7 to 3

2 to 0

−

not used

FR[2:0]

ﬁne gain of the AGC for R channel

FINEG (address: 05h)

7 to 3

2 to 0

−

not used

FG[2:0]

ﬁne gain of the AGC for G channel

FINEB (address: 08h)

7 to 3

2 to 0

−

not used

FB[2:0]

ﬁne gain of the AGC for B channel

Table 21 Fine gain control bits (example for coarse register value 32)

FR2 FR1 FR0

DECIMAL VALUE

FG2 FG1 FG0

FB2 FB1 FB0

FINE STEPS OF GAIN ADC

1.000

1.001

1.002

1.003

1.004

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FR2 FR1 FR0

DECIMAL VALUE

FG2 FG1 FG0

FB2 FB1 FB0

FINE STEPS OF GAIN ADC

1.005

1.006

1.007

9.6

SOG register

Table 22 SOG (09h) bit allocation

BIT

Symbol

Default

FTRILEVEL

STRILEVEL

CKREFS

SOGSEL

SOGI1

SOGI0

Table 23 SOG (09h) bit description

BIT SYMBOL

DESCRIPTION

test bit for forcing charge pump current down

0 = default value

1 = forcing down

test bit for forcing charge pump current up

0 = default value

1 = forcing up

FTRILEVEL

STRILEVEL

CKREFS

SOGSEL

SOGI[1:0]

deﬁnes the 3-level function mode

0 = automatic 3-level

1 = level selection with bit STRILEVEL

forces the state of 3-level function

0 = not 3-level mode

1 = 3-level mode

enables the PLL Ckref signal to be selected

0 = same as input

1 = input inverted

enables the reference PLL between HSYNC input and SOG input to be selected

0 = HSYNC input

1 = SOG input

1 to 0

deﬁnes the SOG charge pump current; values are given in % of sync pulse/line length

00 = 14.8 % maximum (TV standards) and non-VESA standards

01 = 12.6 % maximum (all standards)

10 = 8.6 % maximum (HDTV standards) and non-VESA standards

11 = 0 test mode

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9.7

PLL control

Table 24 PLLCTRL (0Ah) bit allocation

BIT

Symbol

Default

IP1

IP0

DR2

DR1

DR0

Table 25 PLLCTRL (0Ah) bit description

BIT

SYMBOL

DESCRIPTION

7 to 6

IP[1:0]

charge pump current value to increase the bandwidth of the PLL

00 = 800 µA

01 = 1200 µA

10 = 1600 µA

11 = 2000 µA

5 to 3

Z[2:0]

internal resistance value for the VCO ﬁlter to be selected

000 = not used

001 = 1.56 kΩ

010 = 1.25 kΩ

011 = 1.00 kΩ

100 = 0.80 kΩ

101 = 0.64 kΩ

110 = 0.51 kΩ

111 = 0.41 kΩ

3 to 0

DR[2:0]

PLL temperature phase drift to be compensated. The optimized value of this register is 001.

These bits add a delay on the clock reference input of the PLL as a function of the

temperature of the die.

000 = +1.75 step phase

001 = −0.3 step phase

010 = −4.3 step phase

011 = −6.2 step phase

100 = −2.2 step phase

9.8

Phase register

Table 26 PHASE (0Bh) bit allocation

BIT

Symbol

Default

PA4

PA3

PA2

PA1

PA0

VCO2

VCO1

VCO0

Table 27 PHASE (0Bh) bit description

BIT

SYMBOL

DESCRIPTION

7 to 4

3 to 0

PA[4:0]

phase shift value for the clock pixel. See Table 28.

VCO gain control. See Table 29.

VCO[2:0]

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Table 28 Phase registers bits

PA4

PA3

PA2

PA1

PA0

PHASE SHIFT (deg)

11.25

337.50

348.75

Table 29 VCO gain control

VCO GAIN

(MHz/V)

PIXEL CLOCK FREQUENCY

(MHz)

VCO2

VCO1

VCO0

12 to 22

22 to 45

45 to 62

62 to 85

85 to 120

120 to 176

176 to 270

−

105

135

no oscillation

9.9

PLL divider registers

Table 30 DIVMSB (0Ch) bit allocation

BIT

Symbol

CKEXT

SCH

EPSI1

EPSI0

DI11

DI10

DI9

DI8

CKREFO

Default

Table 31 DIVMSB (0Ch) bit description

BIT

SYMBOL

DESCRIPTION

CKEXT

external clock selection

0 = internal PLL

1 = external clock

SCH

shift of pixel counter reference (Ckref) with one clock pixel period

CKREFO

0 = not active

1 = active

5 to 4

3 to 0

EPSI[1:0]

DI[11:8]

enables the resynchronization edge of CKREFO to be selected; they are test bits

00 = default value for proper operation

PLL divider ratio. These are the 4 MSBs of the 12-bit value. See Table 34.

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Table 32 DIVLSB (0Dh) bit allocation

BIT

Symbol

Default

DI7

DI6

DI5

DI4

DI3

DI2

DI1

Table 33 DIVLSB (0Dh) bit description

BIT

7 to 0

SYMBOL

DESCRIPTION

DI[7:0]

PLL divider ratio. These are the 8 LSBs of the 12-bit value. See Table 34.

Table 34 PLL divider ratio

DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

PLL DIVIDER RATIO

100

4095

9.10 Horizontal sync registers

Remark: The sum of HSYNCL[9:0] + HBACKL[9:0] + HDISPL[9:0] + 16 needs to be smaller than the PLL divider.

Table 35 HSYNCL, HBACKL and HDISPL bits allocation

BIT

Symbol

Default

HSYNCL9 HSYNCL8 HSYNCL7 HSYNCL6 HSYNCL5 HSYNCL4 HSYNCL3 HSYNCL2

Symbol

Default

HSYNCL1 HSYNCL0 HBACKL9 HBACKL8 HBACKL7 HBACKL6 HBACKL5 HBACKL4

Symbol

Default

HBACKL3 HBACKL2 HBACKL1 HBACKL0 HDISPL11 HDISPL10 HDISPL9

HDISPL8

Symbol

Default

HDISPL7

HDISPL6

HDISPL5

HDISPL4

HDISPL3

HDISPL2

HDISPL1

HDISPL0

Table 36 Sync registers (0Eh to 11h) bit description

BIT SYMBOL

HSYNCL[9:0]

DESCRIPTION

−

length of the Hsync signal; in number of pixel clock cycles; minimum value

is 16

HBACKL[9:0]

HDISPL[11:0]

interval between the Hsync active edge and the ﬁrst active pixel; in number of

pixels; minimum value is 16

number of active pixels for one line; length of the data enable signal; minimum

value is 16

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9.11 Coast register

Remark: When POSTCOAST[4:0] = PRECOAST[2:0] = 0, then the coast pulse equals the VSYNC input.

Table 37 COAST (12h) bit allocation

BIT

Symbol

PRE

POST

COAST2

COAST1

COAST0

COAST4

COAST3

COAST2

COAST1

COAST0

Default

Table 38 COAST (12h) bit description

BIT SYMBOL

7 to 5 PRE

DESCRIPTION

programs the length (in numbers of pixel clocks) of the coast pulse before the edge of the

COAST[2:0] vertical sync signal

4 to 0

POST

programs the length (in numbers of pixel clocks) of the coast pulse after the edge of the

COAST[4:0] vertical sync signal

9.12 Horizontal sync selection register

Table 39 HSYNCSEL (13h) bit allocation

BIT

Symbol

Default

−

TESTCNT

BYSEPA

HSSEL

HSS

Table 40 HSYNCSEL (13h) bit description

BIT SYMBOL

7 to 4

DESCRIPTION

−

not used

TESTCNT

BYSEPA

HSSEL

HSS

this bit is used to test the pixel counter

0 = normal mode

1 = test mode

enables the sync separator for the PLL reference to be bypassed

0 = Hsync from the separator

1 = bypass of the sync separator

enables either the HSYNC or CHSYNC input signal to be selected

0 = HSYNC input

1 = CHSYNC input

enables either the HSYNC or CHSYNC input signal to be inverted

0 = non-inverted

1 = inverted

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9.13 Vertical sync selection register

Table 41 VSYNCSEL (14h) bit allocation

BIT

Symbol

Default

−

TSTCOAST

COE

VSS

COSSEL2

COSSEL1

Table 42 VSYNCSEL (14h) bit description

BIT

SYMBOL

DESCRIPTION

7 to 5

−

not used

TSTCOAST switches a multiplexer to select the output signal on pin VSYNCO

0 = output of the separator function

1 = output of the coast function

COE

enables coast mode

0 = coast mode

1 = no coast mode

VSS

enables VSYNC input signal to be inverted

0 = non-inverted

1 = inverted

COSSEL2

COSSEL1

selects signal for coast PLL mode

0 = signal selected with bit COSSEL1

1 = pin coast

can be used for the coast PLL mode; see bit COSSEL2

0 = VSYNC input

1 = VSYNC from the sync separator

9.14 Clamp register

Table 43 CLAMP (15h) bit allocation

BIT

−

HSOSEL

CLPSEL2

CLPSEL1

CLPH

CLPENL

ICLP

CLPT

Symbol

Default

Table 44 CLAMP (15h) bit description

BIT SYMBOL

DESCRIPTION

−

not used

HSOSEL

deﬁnes the signal on the output HSYNCO; see Section 8.3

0 = Hsync from the Hcounter

1 = Ckref is reference of the PLL

CLPSEL2

can be used to select the clamp signal

0 = Hsync signal generated by the pixel counter

1 = signal selected with bit CLPSEL1

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BIT

SYMBOL

DESCRIPTION

CLPSEL1

can be used to select the clamp signal; see bit CLPSEL2

0 = PLL reference signal

1 = clamp input

CLPH

inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 42)

0 = clamp inhibited during Vsynco

1 = clamp active during Vsynco

CLPENL

deﬁnes if clamp input works on edge or on level

0 = on edge; for all frequencies (must be preferably chosen)

1 = on level; only for frequencies below 45 MHz to have proper clamp function

dedicated for test mode; should be forced to logic 0

deﬁnes if the test mode of the clamp is active

0 = not active

ICLP

CLPT

1 = active

9.15 Inverter register

Table 45 INVERTER (16h) bit allocation

BIT

Symbol

−

COS

CLPS

CKREFO

INV

DEOINV

RGB

HSOINV

RGB

VSOINV

RGB

FIELDO

INV

Default

Table 46 INVERTER (16h) bit description

BIT SYMBOL

DESCRIPTION

−

not used

COS

enables the COAST input signal to be inverted

0 = non-inverted

1 = inverted

CLPS

enables the CLAMP input signal to be inverted

0 = non-inverted

1 = inverted

CKREFOINV

DEOINVRGB

HSOINVRGB

enables the output CKREFO to be inverted

0 = non-inverted

1 = inverted

enables the output DEO to be inverted

0 = non-inverted

1 = inverted

enables the output HSYNCO to be inverted

0 = non-inverted

1 = inverted

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BIT

SYMBOL

DESCRIPTION

enables the output VSYNCO to be inverted

VSOINVRGB

0 = non-inverted

1 = inverted

FIELDOINV

enables the output FIELDO to be inverted

0 = non-inverted

1 = inverted

9.16 Output register

Table 47 OUTPUT (17h) bit allocation

BIT

Symbol

Default

RGBSEL

TEN

AGCSEL1

AGCSEL0

BLKEN

DMXRGB ODDARGB SHIFTRGB

Table 48 OUTPUT (17h) bit description

BIT SYMBOL

RGBSEL

DESCRIPTION

deﬁnes which RGB input will be used

0 = input 1

1 = input 2

TEN

enables the track and hold operating mode to be selected

0 = mode enable; must be set to logic 0 for proper operation

1 = mode disable

deﬁne the output on pin AGCO

00 = RAGC

5 to 4

AGCSEL[1:0]

01 = GAGC

10 = BAGC

11 = not used

BLKEN

inhibits the blanking mode during clamp

0 = blanking active; during the blanking period, the RGB outputs of the ADC are fixed at

the values of registers OFFSETR, OFFSETG and OFFSETB if these values are greater

or equal to 0, or forced to 0 if these values are negative.

1 = blanking not active

DMXRGB

determines whether all pixels go to port A or if pixels go alternately to port A and B. The

maximum data rate for single port mode is 140 MHz and it is 270 MHz in dual port mode.

0 = port A

1 = port A and B

ODDARGB

SHIFTRGB

deﬁnes the parity of the pixels

0 = even pixel on port A

1 = odd pixel on port A

deﬁnes output on port A and B

0 = synchronous

1 = interleaved

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9.17 Output enable register 1

Table 49 OUTPUTEN1 (18h) bit allocation

BIT

Symbol

Default

−

BOENRGB AOENRGB

OROEN

TOUTERGB TOUTSRGB

Table 50 OUTPUTEN1 (18h) bit description

BIT

SYMBOL

DESCRIPTION

7 to 5

−

not used

BOENRGB

AOENRGB

OROEN

enables output port B to be set to high-impedance

0 = active signal

1 = high-impedance

enables output port A to be set to high-impedance

0 = active signal

1 = high-impedance

enables outputs Out Of Range to be set to high-impedance

0 = active signal

1 = high-impedance

TOUTERGB

TOUTSRGB

deﬁnes if the test mode of the output buffer is active or not

0 = mode normal

1 = mode test

deﬁnes the state of the output in test mode

0 = forces output to LOW

1 = forces output to HIGH

9.18 Output enable register 2

Table 51 OUTPUTEN2 (19h) bit allocation

BIT

CKROEN

Symbol

Default

CSOEN DEOENRGB HSOENRGB HPDOEN VSOENRGB CLPOEN FIELDOEN

Table 52 OUTPUTEN2 (19h) bit description

BIT SYMBOL

CKROEN

DESCRIPTION

enables the output CKREFO to be set to high-impedance

0 = active signal

1 = high-impedance

CSOEN

enables the output CSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

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BIT

SYMBOL

DESCRIPTION

enables the output DEO to be set to high-impedance

0 = active signal

DEOENRGB

1 = high-impedance

HSOENRGB

HPDOEN

enables the output HSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

enables the output HPDO to be set to high-impedance

0 = active signal

1 = high-impedance

VSOENRGB

CLPOEN

enables the output VSYNCO to be set to high-impedance

0 = active signal

1 = high-impedance

enables the output CLPO to be set to high-impedance

0 = active signal

1 = high-impedance

FIELDOEN

enables the output FIELDO to be set to high-impedance

0 = active signal

1 = high-impedance

9.19 Clock output register

Table 53 CLKOUTPUT (1Ah) bit allocation

BIT

−

Symbol

Default

CKSELRGB DLYCLKRGB CKDATINV OUTOSCILL CKOENRGB

Table 54 CLKOUTPUT (1Ah) bit description

BIT

7 to 5

SYMBOL

DESCRIPTION

−

not used

CKSELRGB

DLYCLKRGB

CKDATINV

enables the selection of the signal on the pin CKDATA

0 = clock of output buffers; signal Ckdata

1 = pixel clock of the converter; signal Ckadco

enables a delay of 2 ns to be added to the clock Ckdata

0 = no delay

1 = 2 ns delay

enables the polarity of the output CKDATA to be inverted

0 = non-inverted

1 = inverted

OUTOSCILL

enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the

internal oscillator on the output

0 = Ckdata

1 = for test

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BIT

SYMBOL

DESCRIPTION

CKOENRGB

enables the output CKDATA to be set to high-impedance

0 = active signal

1 = high-impedance

9.20 Internal oscillator register

Table 55 INTOSC (1Bh) bit allocation

BIT

Symbol

Default

−

SWITCHOSC INTOSCOFF

Table 56 INTOSC (1Bh) bit description

BIT

7 to 2

SYMBOL

DESCRIPTION

−

not used

SWITCHOSC

enables a multiplexer to be switched; signal insertion on the input of the separator and

coast block, between the internal oscillator and pin CKEXT

0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the

coast, activity detection and sync separator is done

1 = test mode

INTOSCOFF

disables the internal oscillator for the separator function, the coast gate and activity

detection

0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast,

activity detection and sync separator is done

1 = disabled

9.21 Power management register

Table 57 PWRMGT (1Eh) bit allocation

BIT

Symbol

Default

−

SHCKDMX SHCKADC

STBY

DVIRGB

Table 58 PWRMGT (1Eh) bit description

BIT

SYMBOL

DESCRIPTION

7 to 4

−

not used

test bits; should be set to logic 0 for proper operation

test bits; should be set to logic 1 for better performances

SHCKDMX

SHCKADC

STBY

enables the RGB block to be forced into the standby mode, except activity detection,

I²C-bus registers. In the standby mode, all outputs are in high-impedance state, except

pin HPDO which is still active. If the IC is in the power-down mode, this bit has no effect

0 = IC active

1 = standby mode

DVIRGB

this bit must be set to logic 0 for proper operation

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9.22 Read register

Table 59 READADDR (1Fh) bit allocation

BIT

Symbol

Default

−

ADDR1

ADDR0

Table 60 READADDR (1Fh) bit description

BIT

SYMBOL

DESCRIPTION

7 to 2

1 to 0

−

not used

ADDR[1:0]

00 = read register 0

01 = read register 1

10 = read register 2

11 = read register 3

9.23 Version register

Table 61 VERSION (01h) bit allocation

BIT

−

VER3

VER2

VER1

VER0

Symbol

Default

Table 62 VERSION (01h) bit description

BIT

7 to 4

3 to 0

SYMBOL

DESCRIPTION

−

not used

VER[3:0]

version of the IC

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9.24 Sign detection register

The sign bits are set at logic 0 when the input is a mostly low input signal.

Table 63 SIGN bit allocation

BIT

Symbol

Default

−

POLVS2

POLVS1

POLCHS2 POLCHS1

POLHS2

POLHS1

Table 64 SIGN bit description

BIT

SYMBOL

DESCRIPTION

7 to 6

−

not used

POLVS2

POLVS1

POLCHS2

POLCHS1

POLHS2

POLHS1

sign of VSYNC2 input

0 = non inverted

1 = inverted

sign of VSYNC1 input

0 = non inverted

1 = inverted

sign of CHSYNC2 input

0 = non inverted

1 = inverted

sign of CHSYNC1 input

0 = non inverted

1 = inverted

sign of HSYNC2 input

0 = non inverted

1 = inverted

sign of HSYNC1 input

0 = non inverted

1 = inverted

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9.25 Activity detection register 1

Table 65 ACTIVITY1 bit allocation

BIT

Symbol

Default

ACVS2

ACVS1

ACSOG2

ACSOG1

ACCHS2

ACCHS1

ACHS2

ACHS1

Table 66 ACTIVITY1 bit description

BIT SYMBOL

DESCRIPTION

ACVS2

activity of VSYNC2 input

0 = not active

1 = active

ACVS1

activity of VSYNC1 input

0 = not active

1 = active

ACSOG2

ACSOG1

ACCHS2

ACCHS1

ACHS2

activity of SOGIN2 input

0 = not active

1 = active

activity of SOGIN1 input

0 = not active

1 = active

activity of CHSYNC2 input

0 = not active

1 = active

activity of CHSYNC1 input

0 = not active

1 = active

activity of HSYNC2 input

0 = not active

1 = active

ACHS1

activity of HSYNC2 input

0 = not active

1 = active

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9.26 Activity detection register 2

It should be noted that activity, sign and polarity detection will be correctly set after a maximum delay of:

6 frame periods + 50 ms.

Table 67 ACTIVITY2 bit allocation

BIT

Symbol

Default

−

ASD

3LEVEL

ACFIELD

HPDO

ACVSSEP

ACRXC1

ACRXC0

Table 68 ACTIVITY2 bit description

BIT SYMBOL

DESCRIPTION

−

not used

ASD

indicates if parasite sync pulses have been detected

0 = not detected

1 = detected

3LEVEL

ACFIELD

HPDO

state of the sync separator input

0 = Hsync

1 = 3-level Hsync

activity of the sync separator FIELDO output

0 = not active

1 = active

copy of the HPDO output state

0 = stable state on input

1 = new input

ACVSSEP

activity of the sync separator (Vsync output)

0 = not active

1 = active

ACRXC1

ACRXC0

test bit

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10 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL

V_CC

PARAMETER

supply voltage

CONDITIONS

MIN.

−0.5

MAX.

UNIT

∆V_CC

V_i

supply voltage differences

input voltage

I²C-bus input voltage

−0.5

−

+0.5

+4.5

+6.5

referred to GNDA

V_i(SCL,SDA)

I_o

referred to GNDD

output current

°C

T_stg

storage temperature

ambient temperature

junction temperature

electrostatic discharge voltage

−55

+150

T_amb

T_j

−

150

V_esd

HBM, LQFP144 package

−3000

+3000

11 THERMAL CHARACTERISTICS

SYMBOL

R_th(j-a)

PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

thermal resistance from junction in free air

to ambient, JEDEC4L

LQFP144 package

LBGA208 package

−

°C/W

R_th(j-c)

thermal resistance from junction

to case

LQFP144 package

−

8.1

8.5

°C/W

12 CHARACTERISTICS

Typical values are measured at V_CCA= V_CCA(SOG)to GNDA(SOG) or V_CCA(R)to GNDA(R) or V_CCA(G)to GNDA(G)

or V_CCA(B)to GNDA(B) = 3.3 V; V_CCD= V_CCD(TTL)to GNDD(TTL) or V_CCD(ADC)to GNDD(ADC)

or V_CCD(I2C)to GNDD(I2C) or V_CCD(MCF)to GNDD(MCF) or V_CCD(TTL)to GNDD(TTL)

or V_CCD(SLC)to GNDD(SLC) = 3.3 V; V_CCO= V_CCO(BB)to GNDO(BB) or V_CCO(BA)to GNDO(BA)

or V_CCO(GB)to GNDO(GB) or V_CCO(GA)to GNDO(GA) or V_CCO(RB)to GNDO(RB) or V_CCO(RA)to GNDO(RA)

or V_CCO(CLK)to GNDO(CLK) = 3.3 V; T_amb= 25 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

V_CCA

V_CCD

V_CCO

I_CCA

analog supply voltage

digital supply voltage

output stage supply voltage

analog supply current

digital supply current

output stage supply current

supply voltage difference

V_CCAto V_CCD

3.0

3.3

180

125

3.6

−

3.0

−

I_CCD

−

I_CCO

∆V_CC

−

−100

−165

−

+100 mV

+165 mV

V_CCOto V_CCD

V_CCAto V_CCO

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

P_tot

PARAMETER

total power dissipation

power dissipation

CONDITIONS

MIN.

TYP. MAX. UNIT

−

1.0

1.3

−

power-down mode

standby mode

−

120

−

R, G and B ampliﬁers

RGB INPUTS: PINS RIN1, GIN1, BIN1, RIN2, GIN2 AND BIN2

V_i(p-p)

input voltage range

(peak-to-peak value)

0.5

−

1.0

I_i

input current

−40

−

+40

−

µA

kΩ

C_i

R_i

input capacitance

input resistance

−

AMPLIFIERS

bandwidth

−3 dB; T_amb= 25 °C

−

700

−

MHz

G_c

coarse gain

minimum coarse gain; code = 32

maximum coarse gain;

code = 95

∆G/∆T

ampliﬁer gain stability variation

with temperature

minimum coarse gain; code = 32

−

G_E(rms)

full-scale channel-to-channel

matching (RMS value)

minimum coarse gain; code = 32

−

2.5

R, G and B clamp

N_clamp

clamp level accuracy

f_CLK= 25MHz, clamp code = 20

f_clk= 270 MHz; DR = 2160

−

LSB

Phase-Locked Loop (PLL)

PLL; see Table 69

J_PLL(p-p)

long term PLL phase jitter

−

390

480

(peak-to-peak value)

divider ratio

100

−

4095

270

150

f_PLL

f_ref

output clock frequency

reference clock frequency

phase drift

−

MHz

kHz

step

deg

−

∆ϕ_step

ϕ_step

−

phase shift step

−

11.25

−

Analog-to-Digital Converters (ADCs); minimum coarse gain

f_s(max)

INL

maximum sampling frequency

integral non-linearity

differential non-linearity

effective number of bits

crosstalk

270

−

MHz

LSB

bits

f_clk= 270 MHz; f_i= 10 MHz

f_clk= 270 MHz

±0.6

±1.3

DNL

ENOB

α_ct

−

±0.25 ±0.6

−

7.6

−

−45

−

S/N

signal-to-noise ratio

f_clk= 270 MHz; f_i= 10 MHz

−

-55

SFDR

THD

spurious free dynamic range

total harmonic distortion

−

−48

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

Data timing; 10 pF load; see Fig.4

t_d(o)

t_h(o)

t_su(o)

output delay

−

5.2

−

output hold time

output setup time

1.9

−

LV-TTL digital inputs and outputs

INPUT PINS CKEXT, COAST, VSYNC1, VSYNC2, HSYNC1, HSYNC2, CHSYNC1, CHSYNC2, PWD, A0, DIS, TCK

AND CLP

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

−

0.8

2.0

V_CCD

OUTPUT PINS RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, CKDATA, TDO, DEO, HPDO,

HSYNCO, VSYNCO, FIELDO, CLPO, CKREFO AND CSYNCO

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_OH= 1 mA

−

0.4

I_OL= −1 mA

2.4

−

Data clock output

OUTPUT PIN CKDATA

f_CKDATA(max)

maximum buffer frequency

−

140

−

MHz

Data outputs

OUTPUT PINS RA[7:0], RB[7:0], GA[7:0], GB[7:0], BA[7:0], BB[7:0], ROR, BOR, GOR, DEO, HSYNCO AND CSYNCO

f_data(max)

maximum buffer frequency

−

MHz

Hsync inputs

INPUT PINS HSYNC1, HSYNC2, CHSYNC1 AND CHSYNC2

t_{W(Hsync)(min)}minimum pulse width

250

−

t_{W(Hsync)(max)}maximum pulse width

in % of total horizontal line

−

SOG inputs

INPUT PINS SOGIN1 AND SOGIN2

V_sync(G)

sync-on-green pulse amplitude

150

−

high/low differential amplitude of

3-level pulse

−

I²C-bus (fast mode; 5 V tolerant)

PINS SCL AND SDA

f_SCL

V_IL

V_IH

C_b

clock frequency

−

400

0.8

5.5

400

kHz

LOW-level input voltage

HIGH-level input voltage

capacitive load

2.0

−

Thermal characteristics

R_th(j-c)

thermal resistance from junction LQFP144 package

to case

−

8.1

8.5

°C/W

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

Table 69 Examples of PLL settings and performance

V_CCA= V_CCD= V_CCO= 3.3 V; T_amb= 25 °C; note 1.

LONG-TERM TIME

JITTER

f_ref

(kHz)

f_clk

(MHz)

K_O

C_Z

C_P

I_P

VIDEO STANDARD

(MHz/V) (nF) (pF) (µA) (Ω)

RMS (ps)

p-p (ps)

VGA 60 Hz

31.469

48.08

60.02

63.98

80.00

75.00

93.75

106.25

25.175

800

220 680 1200 510

220 680 1600 640

220 680 1600 510

220 680 1600 640

220 680 2000 640

220 680 1600 800

220 680 2000 640

500

3000

VESA: 640 × 480

SVGA 72 Hz

1040

1312

1688

2160

370

220

185

145

135

1980

1320

1110

870

VESA: 800 × 600

XGA 75 Hz

78.75

108

VESA: 1024 × 768

SXGA 60 Hz

105

135

VESA: 1280 × 1024

SXGA 75 Hz

135

VESA: 1280 × 1024

UXGA 60 Hz

162

810

VESA: 1600 × 1200

UXGA 75 Hz

202.5

229.5

570

VESA: 1600 × 1200

UXGA 85 Hz

510

VESA: 1600 × 1200

Note

1. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.

50 %

CKDATA

sample N

sample N + 1

sample N + 2

RGB input

h(o)

d(o)

RGB outputs

A7 to A0, B7 to B0,

DEO,

DATA

N − 2

DATA

N − 1

DATA

N + 1

50 %

HSYNCO,

CKREFO

mce410

Fig.4 Data timing diagram.

2004 May 18

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R,G,B in

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

ckdivo

ckphi

ckrefin

possibility to add a clock period with bit SCHCKREFO

HBACKL

HDISPL

HSYNCL

hcount

hsyncin

dein

hs hs−1 hs−2

hb hb−1

hd hd−1 hd−2

ckadco

ADC out

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

MDB107

HSYNCL, HBACKL and HDISPL must be long 16 (minimum value in number of pixel clock cycles).

Fig.5 Timing diagram.

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

handbook, full pagewidth

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

RGB outputs

10 11 12 13 14 15 16 17 18 19 20

A7 to A0

MDB201

HSCYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin.

CKREFO is LOW during 8 clock pulses.

Fig.6 Output format port A.

handbook, full pagewidth

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 0

RGB outputs

A7 to A0

RGB outputs

B7 to B0

bit SHIFTRGB = 1

RGB outputs

A7 to A0

RGB outputs

B7 to B0

MDB108

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin.

CKREFO is LOW during 8 clock pulses.

Fig.7 Output formats ports A and B; even pixels port A and odd pixels port B.

2004 May 18

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Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

handbook, full pagewidth

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 0

RGB outputs

A7 to A0

RGB outputs

B7 to B0

MDB200

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin.

CKREFO is LOW during 8 clock pulses.

Fig.8 Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 0.

handbook, full pagewidth

ckrefin

HSYNCO

CKREFO

DEO

CKDATA

bit SHIFTRGB = 1

RGB outputs

A7 to A0

RGB outputs

B7 to B0

MCE411

HSYNCO, DEO, CKREFO and RGB outputs A7 to A0 are referred to the rising edge of ckrefin.

CKREFO is LOW during 8 clock pulses.

Fig.9 Output formats ports A and B; odd pixels port A; bit SHIFTRGB = 1.

2004 May 18

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Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

14 APPLICATION INFORMATION

CCD

SCL SDA

CCD

handbook, full pagewidth

R21

4.7 kΩ

R20

4.7 kΩ

V V

CCO CCO

CCD

CCO

CCD

GNDD(TTL)

RA6

108

107

106

105

104

103

102

101

100

out red A

CCD(TTL)

RA5

CCD

HSYNC2

RA4

CHSYNC2

RA3

CCA(PLL)

RA2

CCA

HSYNC1

CHSYNC1

GNDA(PLL)

RA1

RA0

ROR

GNDO(RB)

220 nF

GNDA(CPO)

CCO(RB)

CCO

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

C2 680 pF

PMO

GNDA(SUB)

CAPSOGIN1

CAPSOGO

CAPSOGIN2

GNDA(SOG)

SOGIN1

C3 1 µF

C4 1 µF

C5 330 pF

C6 330 pF

C7 1 µF

C8 1 µF

out red B

SOGIN1

SOGIN2

TDA8754HL

CCA(SOG)

GNDO(GA)

SOGIN2

CCO(GA)

CCO

CCA(R)

GA7

CCA

RIN1

GNDA(R1)

RIN2

GA6

RIN1

GA5

GA4

RIN2

out green A

GNDA(R2)

DEC

GA3

C9 100 nF

C10 100 nF

C11 4.7 nF

GA2

RBOT

GA1

RCLPC

GA0

CCA(G)

GOR

GNDO(GB)

CCA

C12 1 µF

C13 1 µF

GIN1

GNDA(G1)

GIN2

GIN1

CCO(GB)

CCO

GB7

GB6

GB5

GB4

GB3

GIN2

GNDA(G2)

GBOT

C14 100 nF

C15 4.7 nF

GCLPC

out green B

CCA(B)

CCA

MDB109

out blue B

out blue A

C16

1 µF

C17

1 µF

C19

4.7

CCO

C18

CCD

CCO

100 nF

BIN1 BIN2

Fig.10 Application diagram.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

15 PACKAGE OUTLINES

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm

SOT486-1

108

109

(A )

pin 1 index

detail X

144

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 20.1

0.17 0.09 19.9 19.9

22.15 22.15

21.85 21.85

0.75

0.45

1.4

1.1

1.4

1.1

1.6

0.25

0.2 0.08 0.08

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-03-14

03-02-20

SOT486-1

136E23

MS-026

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

LBGA208: plastic low profile ball grid array package; 208 balls; body 17 x 17 x 1.05 mm

SOT774-1

ball A1

index area

detail X

1/2

ball A1

index area

10 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

max.

0.45 1.20 0.55 17.2 17.2

0.35 0.95 0.45 16.8 16.8

mm 1.65

0.12 0.35

0.25

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

02-05-14

SOT774-1

- - -

MO-192

- - -

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

16 SOLDERING

To overcome these problems the double-wave soldering

method was specifically developed.

16.1 Introduction to soldering surface mount

packages

If wave soldering is used the following conditions must be

observed for optimal results:

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

16.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Driven by legislation and environmental forces the

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 270 °C depending on solder paste material. The

top-surface temperature of the packages should

preferably be kept:

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250 °C or 265 °C, depending on solder

material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

• below 225 °C (SnPb process) or below 245 °C (Pb-free

process)

– for all BGA, HTSSON-T and SSOP-T packages

16.4 Manual soldering

– for packages with a thickness ≥ 2.5 mm

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

– for packages with a thickness < 2.5 mm and a

volume ≥ 350 mm³so called thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free

process) for packages with a thickness < 2.5 mm and a

volume < 350 mm³so called small/thin packages.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

Moisture sensitivity precautions, as indicated on packing,

must be respected at all times.

16.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

16.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE⁽¹⁾

WAVE

not suitable

REFLOW⁽²⁾

BGA, HTSSON..T⁽³⁾, LBGA, LFBGA, SQFP, SSOP..T⁽³⁾, TFBGA,

USON, VFBGA

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN, HVSON, SMS

PLCC⁽⁵⁾, SO, SOJ

not suitable⁽⁴⁾

suitable

LQFP, QFP, TQFP

not recommended⁽⁵⁾⁽⁶⁾suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L⁽⁸⁾, PMFP⁽⁹⁾, WQCCN..L⁽⁸⁾

not recommended⁽⁷⁾

suitable

not suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature

exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar

soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

17 DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18 DEFINITIONS

19 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2004 May 18

Philips Semiconductors

Product speciﬁcation

Triple 8-bit video ADC up to 270 Msps

TDA8754

20 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2004 May 18

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R78/05/pp57

Date of release: 2004 May 18

Document order number: 9397 750 13199

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TDA8754HL/27/C1,55 [NXP]

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