TDA8757HL [NXP]
Triple 8-bit ADC 170 Msps; 三重8位ADC 170 Msps的
| 型号： | TDA8757HL |
| 厂家： | 
NXP |
| 描述： | Triple 8-bit ADC 170 Msps |
| 文件： | 总37页 (文件大小：820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8757
Triple 8-bit ADC 170 Msps
Rev. 07 — 28 February 2002
Preliminary data
1. General description
The TDA8757 is a triple 8-bit ADC for the digitizing of large bandwidth RGB/YUV
signals at a sampling rate up to 170 Msps.
The IC supports display resolutions up to 1600 × 1200 (UXGA) at 60 Hz.
The IC also includes a PLL that can be locked to the horizontal line frequency and
generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics
applications. An external clock signal can also be used to clock the ADC.
The outputs are available either on one port up to 110 Msps or on two ports up to
170 Msps. The operating mode is selectable with the serial interface to for either
I2C-bus or 3-wire serial bus (3W-bus) operation.
The clamp level, the gain and the other settings are controllable through the serial
interface.
2. Features
■ Triple 8-bit ADC
■ Sampling rate up to 170 Msps
■ IC controllable by a serial interface which can be I2C-bus or 3W-bus, selected by a
TTL input pin
■ Three clamps for programming a clamping code from −63.5 to +64 in steps of
1⁄2 LSB (RGB) and from +120 to +136 in steps of 1⁄2 LSB (YUV)
■ Three controllable amplifiers: gain controlled by the serial interface to produce a
full-scale resolution of 1⁄2 LSB peak-to-peak
■ Amplifier bandwidth of 250 MHz
■ Low gain variation with temperature
■ PLL controllable through the serial interface to generate the ADC clock which can
be locked to any line frequency of 15 to 150 kHz
■ Integrated PLL divider
■ Programmable phase clock adjustment cells
■ Internal voltage regulators
■ TTL compatible digital inputs and outputs
■ Outputs on one port or demultiplexed on two ports; selectable with the serial
interface
■ Chip enable, high-impedance ADC output
■ Power-down mode
■ 1.5 W power dissipation
■ Sync on green extractor.
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
3. Applications
■ RGB/YUV high-speed digitizing
■ LCD panels drive
■ LCD projection systems
■ VGA to UXGA (1600 × 1200 at 60 Hz) modes.
4. Quick reference data
Table 1: Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCCA
analog supply voltage for PLL
and the RGB channels
4.75
5.0
5.25
V
VDDD
logic supply voltage for I2C-bus
and 3W-bus
4.75
5.0
5.25
V
VCCD
VCCO
digital supply voltage
4.75
4.75
5.0
5.0
5.25
5.25
V
V
output stages supply voltage
for PLL and the RGB channels
VCCA(PLL)
VCCO(PLL)
ICCA
analog PLL supply voltage
output PLL supply voltage
4.75
4.75
−
5.0
5.0
135
5.25
5.25
−
V
V
analog supply current for the
RGB channels
mA
IDDD
logic supply current for I2C-bus
and 3W-bus
−
1
−
mA
ICCD
digital supply current
output stages supply current
analog PLL supply current
clock frequency
−
95
80
34
−
−
mA
ICCO
−
−
mA
ICCA(PLL)
fclk
−
−
mA
normal (Dmx = 0)
−
110
170
150
170
±1.5
MHz
MHz
kHz
MHz
LSB
de-multiplexed (Dmx = 1)
−
−
fref(PLL)
fPLL
PLL reference clock frequency
output clock frequency range
DC integral non-linearity
15
10
−
−
−
INL
from analog input to
digital output; full-scale;
sinusoidal input;
±0.5
fclk = 170 MHz
DNL
DC differential non-linearity
from analog input to
digital output; full-scale;
sinusoidal input;
−
−
±0.4
±1
LSB
fclk = 170 MHz
∆Gamp/∆T
amplifier gain stability variation Vref = 2.5 V with
325
−
ppm/°C
with temperature
100 ppm/°C maximum
B
amplifier bandwidth
−3 dB; Tamb = 25 °C
250
−
−
−
MHz
ns
tset(ADC+AGC)
settling time of the block
ADC + AGC
input signal settling
time <1 ns; settling to
1%; fi = 85 MHz
−
4
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
2 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 1: Quick reference data…continued
Symbol
DRPLL
Ptot
Parameter
Conditions
Min
100
−
Typ
−
Max
4095
−
Unit
PLL divider ratio
total power dissipation
fclk = 170 MHz;sinusoidal
input
1.5
W
jPLL(max)(p-p)
maximum PLL phase jitter
(peak-to-peak value)
fclk = 170 MHz
−
360
−
ps
5. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
Version
TDA8757HL
HLQFP144 plastic, heatsink low profile quad flat package; 144 leads;
SOT612-1
body 20 × 20 × 1.4 mm
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
3 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
6. Block diagram
CLP
131
CLP
R
AGC
R
5
8
6
7
GAINC
R
BOT
R
11
IN
R
CLAMP
114 to 121
8
8
9
A0 to A7
R
B0 to B7
R
DEC
R
R
R
100 to 107
113
OUTPUT
MUX
ADC
OR
R
3
VREF
RED CHANNEL
GREEN CHANNEL
BLUE CHANNEL
129
18
OE
CLP
G
15
AGC
G
16
17
GAINC
G
BOT
G
92 to 99
79 to 86
91
8
8
A0 to A7
G
21
G
IN
G
B0 to B7
G
19
G
DEC
G
OR
G
26
29
27
AGC
B
CLP
B
28
GAINC
B
BOT
B
8
8
71 to 78
58 to 65
70
A0 to A7
32
B
B
B
IN
B
B0 to B7
B
30
DEC
B
OR
B
HSYNCI
23
IN
SOG
CKADC
SYNCHRO
EXTRACTOR
24
SOG
O
123
124
TDA8757
CKDATA
38
39
43
47
44
42
37
A1
A2
SEN
SCL
SDA
DIS
CKREFO
1-bit
(Hlevel)
SERIAL
134
133
135
136
INTERFACE
CKEXT
INV
COAST
PLL
2
I C-BUS
REGULATOR
or
CKREF
2
3W-BUS
I C-bus
2
I C/3W
132
4
2
130
141
CZ
140
CP
FCE694
HSYNC DEC1 DEC2 PD
Fig 1. Block diagram.
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
4 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
CLP
OE
AGC
α
CKDMX
CLP
α
CLAMP
CONTROL
DAC
8
8
2
I C-bus:
A0 to A7
V
P
α
α
8 bits
(Oα)
CKADC
ADC
8
150
kΩ
OUTPUTS A
&
OUTPUTS B
B0 to B7
REGISTER
α
α
IN
α
MUX
AGC
OR
α
VREF
2
I C-bus:
3 bits
DAC
(Dmx, Odda, Shift, Blk)
8
D
R
D R
5
8
7
BOT
α
1
2
I C-bus:
2
1
5 bits
REGISTER
FINE GAIN ADJUST
REGISTER
COARSE GAIN ADJUST
I C-bus: 7 bits
(Cα)
(Fα)
SERIAL
2
I C-BUS
FCE695
GAINC
α
SDA SCL
HSYNC
Fig 2. Channel diagram (where α stands for R, G or B).
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
C
C
2
Z
P
COAST
CKEXT
INV
2
I C-bus: 1 bit
(Vlevel)
I C-bus: 3 bits
(Z)
+/−
Z
CKADC
2
CKREF
I C-bus: 5 bits
(P)
0/180
MUX
PHASE
VCO
PHASE
FREQUENCY
DETECTOR
2
I C-bus:
1 bit
CKDMX
2
I C-bus:
1 bit
2
2
I C-bus: 5 bits
(Edge)
I C-bus: 2 bits
2
I C-bus: 1 bit
(Odda)
(Ip, Up, Do)
(Vco)
(Ckext)
+/−
τ
CKDATA
MUX
2
I C-bus: 2 bits
(Ckdd, Ckdp)
DIV N (100 to 4095)
÷ 2
2
2
I C-bus: 12 bits
I C-bus:
(Di)
1 bit (Dmx)
SYNCHRO
MUX
+/−
CKREFO
2
I C-bus: 1 bit
(Ckrp)
2
I C-bus: 1 bit
(Ckrs)
MBL365
(1)
OE
(1) Enable of CKDATA and CKREFO by OE. Available in C3 version only.
Fig 3. PLL diagram.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
6 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
7. Pinning information
7.1 Pinning
n.c.
n.c.
B7
1
108
107
DEC2
2
R
3
106 B6
105 B5
VREF
DEC1
R
R
R
R
R
R
R
G
G
G
G
G
G
G
G
4
5
104
AGC
R
BOT
R
GAINC
R
CLP
R
B4
103 B3
102
6
7
B2
101 B1
100
8
DEC
R
9
B0
99 A7
A6
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CCA(R)
98
97 A5
96
IN
R
n.c.
AGND
R
A4
n.c.
95 A3
94 A2
93 A1
92 A0
AGC
G
BOT
G
GAINC
G
91 OR
CLP
G
DEC
G
G
TDA8757HL
V
90
89
88
87
CCO(G)
OGND
V
G
CCA(G)
V
IN
G
CCO(G)
OGND
G
AGND
G
IN
86 B7
G
G
G
G
G
G
G
G
B
B
B
B
B
B
SOG
SOG
B6
B5
85
84
O
n.c.
83 B4
82 B3
81 B2
AGC
B
BOT
B
GAINC
B
CLP
B
B1
B0
A7
A6
80
79
78
77
DEC
B
V
CCA(B)
IN
B
AGND
76 A5
75 A4
74 A3
B
n.c.
n.c.
n.c.
73
A2
GND
DP
FCE697
Fig 4. Pin configuration.
7.2 Pin description
Table 3: Pin description
Symbol
n.c.
Pin
1
Description
not connected
DEC2
VREF
DEC1
2
main regulator decoupling input 2
gain stabilizer voltage reference input
main regulator decoupling input 1
3
4
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© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
7 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 3: Pin description…continued
Symbol
Pin
5
Description
AGCR
BOTR
GAINCR
CLPR
DECR
VCCA(R)
INR
red channel AGC output
6
red channel ladder decoupling input (BOT)
red channel gain capacitor input
red channel clamp capacitor input
red channel regulator decoupling input
red channel analog supply voltage
red channel analog input
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
n.c.
not connected
AGNDR
n.c.
red channel gain analog ground
not connected
AGCG
BOTG
GAINCG
CLPG
DECG
VCCA(G)
ING
green channel AGC output
green channel ladder decoupling input (BOT)
green channel gain capacitor input
green channel clamp capacitor input
green channel regulator decoupling input
green channel analog supply voltage
green channel analog input
green channel gain analog ground
sync on green channel input
composite sync output
AGNDG
INSOG
SOGO
n.c.
not connected
AGCB
BOTB
GAINCB
CLPB
DECB
VCCA(B)
INB
blue channel AGC output
blue channel ladder decoupling input (BOT)
blue channel gain capacitor input
blue channel clamp capacitor input
blue channel regulator decoupling input
blue channel analog supply voltage
blue channel analog input
AGNDB
n.c.
blue channel gain analog ground
not connected
n.c.
not connected
n.c.
I2C/3W
not connected
selection input between I2C-bus (active HIGH) and 3W-bus
(active LOW)
A1
38
39
40
41
42
I2C-bus address control input 1
I2C-bus address control input 2
scan test mode input (active HIGH)
scan test output
I2C-bus and 3W-bus disable control input (disable at HIGH
level)
A2
TCK
TDO
DIS
SEN
43
select enable input for 3W-bus
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Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 3: Pin description…continued
Symbol
Pin
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Description
I2C-bus/3W-bus serial data input
logic I2C-bus/3W-bus digital supply voltage
logic I2C-bus/3W-bus digital ground 1
I2C-bus/3W-bus serial clock input
not connected
SDA
VDDD
VSSD1
SCL
n.c.
n.c.
not connected
n.c.
not connected
n.c.
not connected
VCCD2
DGND2
n.c.
digital supply voltage 2
digital ground 2
not connected
VSSD2
VSSD3
n.c.
logic I2C-bus/3W-bus digital ground 2
logic I2C-bus/3W-bus digital ground 3
not connected
B0B
blue channel ADC output B bit 0 (LSB)
blue channel ADC output B bit 1
blue channel ADC output B bit 2
blue channel ADC output B bit 3
blue channel ADC output B bit 4
blue channel ADC output B bit 5
blue channel ADC output B bit 6
blue channel ADC output B bit 7 (MSB)
blue channel ADC output B ground
blue channel ADC output B supply voltage
blue channel ADC output A ground
blue channel ADC output A supply voltage
blue channel ADC output bit out of range
blue channel ADC output A bit 0 (LSB)
blue channel ADC output A bit 1
blue channel ADC output A bit 2
blue channel ADC output A bit 3
blue channel ADC output A bit 4
blue channel ADC output A bit 5
blue channel ADC output A bit 6
blue channel ADC output A bit 7 (MSB)
green channel ADC output B bit 0 (LSB)
green channel ADC output B bit 1
green channel ADC output B bit 2
green channel ADC output B bit 3
green channel ADC output B bit 4
green channel ADC output B bit 5
B1B
B2B
B3B
B4B
B5B
B6B
B7B
OGNDB
VCCO(B)
OGNDB
VCCO(B)
ORB
A0B
A1B
A2B
A3B
A4B
A5B
A6B
A7B
B0G
B1G
B2G
B3G
B4G
B5G
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 3: Pin description…continued
Symbol
Pin
85
Description
B6G
green channel ADC output B bit 6
B7G
86
green channel ADC output B bit 7 (MSB)
green channel ADC output B ground
green channel ADC output B supply voltage
green channel ADC output A ground
green channel ADC output A supply voltage
green channel ADC output bit out of range
green channel ADC output A bit 0 (LSB)
green channel ADC output A bit 1
green channel ADC output A bit 2
green channel ADC output A bit 3
green channel ADC output A bit 4
green channel ADC output A bit 5
green channel ADC output A bit 6
green channel ADC output A bit 7 (MSB)
red channel ADC output B bit 0 (LSB)
red channel ADC output B bit 1
red channel ADC output B bit 2
red channel ADC output B bit 3
red channel ADC output B bit 4
red channel ADC output B bit 5
red channel ADC output B bit 6
red channel ADC output B bit 7 (MSB)
not connected
OGNDG
VCCO(G)
OGNDG
VCCO(G)
ORG
87
88
89
90
91
A0G
92
A1G
93
A2G
94
A3G
95
A4G
96
A5G
97
A6G
98
A7G
99
B0R
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
B1R
B2R
B3R
B4R
B5R
B6R
B7R
n.c.
OGNDR
VCCO(R)
OGNDR
VCCO(R)
ORR
red channel ADC output B ground
red channel ADC output B supply voltage
red channel ADC output A ground
red channel ADC output A supply voltage
red channel ADC output A bit out of range
red channel ADC output A bit 0 (LSB)
red channel ADC output A bit 1
red channel ADC output A bit 2
red channel ADC output A bit 3
red channel ADC output A bit 4
red channel ADC output A bit 5
red channel ADC output A bit 6
red channel ADC output A bit 7 (MSB)
PLL digital ground
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
OGNDPLL
CKDATA
CKREFO
TESTO
output data clock
output horizontal pulse synchronized to pixel clock
output reserved for test
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Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 3: Pin description…continued
Symbol
Pin
126
127
128
129
Description
VCCO(PLL)
n.c.
PLL output supply voltage
not connected
DGND1
OE
digital ground 1
output enable; active LOW (when OE is HIGH, the outputs are
high-impedance)
PD
130
power-down control input (IC is in Power-down mode when
this pin is HIGH)
CLP
131
132
133
134
135
136
137
138
139
140
141
142
143
144
clamp pulse input (clamp active HIGH)
horizontal synchronization pulse input
PLL clock output inverter control input (invert when HIGH)
external clock input
HSYNC
INV
CKEXT
COAST
CKREF
VCCD1
n.c.
PLL coast control input
PLL reference clock input
digital supply voltage 1
not connected
AGNDPLL
CP
PLL analog ground
PLL filter input
CZ
PLL filter input
AGNDPLL
VCCA(PLL)
n.c.
PLL analog ground
PLL analog supply voltage
not connected
GNDDP
exposed die pad connection
8. Functional description
This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming
from an analog source, into digital data used by a LCD driver (pixel clock up to
170 MHz).
8.1 Analog video inputs
The RGB/YUV video inputs are externally AC coupled and are internally
DC polarized.
The synchronization signals are also used for the internal PLL and the gain
calibration.
If the green video signal has composite sync (sync on green), it is possible to extract
this composite sync by connecting the green signal to pin INSOG (AC coupled). When
the sync pulse amplitude is below 300 mV, the I2C-bus bit ‘Slevel’ has to be set to
logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV.
The composite sync is available at pin SOGO (TTL level compatible signal).
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
blank level
300 mV
to
600 mV
150 mV comparison level
set by I C-bus bit Slevel = 0
2
blank level
150 mV
to
300 mV
80 mV comparison level
set by I C-bus bit Slevel = 1
2
005aaa009
Fig 5. Sync level diagram.
If this function is not used, pin INSOG should be connected to the analog power
supply. In this event, pin SOGO is at LOW-level TTL.
8.2 Clamps
Three independent parallel clamping circuits are used to clamp the video input
signals on several black levels. The clamping levels may be set from
−63.5 to +64 LSBs (RGB) and from +120 to +136 LSBs in steps of 1⁄2 LSB (YUV).
They are controlled by changing the values in three 8-bit registers: OFFSETR,
OFFSETG and OFFSETB (see Table 5). Each clamp must be able to correct an
offset from ±100 mV to ±10 mV within 300 ns, and correct the total offset in 10 lines.
The clamping is done using the following principle: On the incoming of a TTL positive
going pulse supplied on pin CLP, three external capacitors are loaded independently
by the device in order to change the voltage level of each analog RGB input. The
capacitors are connected to pins CLPR, CLPG and CLPB.
video signal
255
constant level
ADC
Clamp
+
128
=
Clamp
+
64
=
clamp
0
programming
Clamp
= 0
constant level
Clamp
−
63.5
=
FCE698
CLP
Fig 6. Clamp definition.
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Preliminary data
Rev. 07 — 28 February 2002
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TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
8.2.1 Variable gain amplifiers
Three independent variable gain amplifiers are used to provide a full-scale input
signal to the 8-bit ADC for each channel. The gain adjustment range is designed so
that for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds
to the ADC full-scale input of 1 V (p-p).
To ensure that the gain does not vary over the whole operating temperature range, a
reference voltage Vref = 2.5 V (DC) with a maximum variation of 100 ppm/°C, is
supplied externally on pin VREF.
The calibration of the gains is done using the following principle: On the incoming of a
pulse supplied to pin HSYNC, an internal multiplexer switches from the RGB video
signals to a reference voltage (1⁄16Vref). The ADCs inputs become this reference
signal and the three corresponding outputs are compared to pre-set values loaded in
three 7-bit registers: COARSER, COARSEG and COARSEB. Depending on the
result of the comparisons, the three gains are adjusted such that the ADC outputs
become equal to the pre-set values in the registers. The three gains are simply
controlled by changing the values in the COARSE registers.
The signal supplied on pin HSYNC, may be selected active HIGH or active LOW. The
choice is done through the serial interface by setting bit ‘Hlevel’ in the control register
(active HIGH when bit Hlevel = 0).
This active part of the signal has to occur during the blanking period of the signal in
order not to interrupt the active video. Normally the horizontal synchronization signal,
provided by the video source, is connected to pin HSYNC.
The values loaded in the gain registers (COARSER, COARSEG, COARSEB) are
chosen among 68 values (see Table 6).
A fine correction is also used to finely tune the gain on the three channels and to
compensate the channel-to-channel gain mismatch. The fine correction is done using
the following principle: the three binary codes, stored in the three 5-bit registers
(FINER, FINEG and FINEB) are converted into three analog voltages (with three
DACs) and are independently added to the reference voltage (1⁄16Vref). Thus, three
different reference voltages are used for the gain calibration of the three channels.
When the COARSE registers are set at full-scale, the resolution of the fine registers
corresponds to 1⁄2 LSB peak-to-peak (see Equation 3).
8.2.2 Important recommendations
The clamping and the gain calibration requires two external signals (pulses). One
signal is connected to pin CLP and the other is connected to pin HSYNC. It is very
important that:
The active part of these two signals occur during the blanking of the video signal,
in order not to interrupt or disturb the active video.
•
•
The active part of these two signals does not overlap on each other, in order to
perform correctly the gain calibration and the clamping. Normally the clamp pulse
is sent after the end of the horizontal synchronization pulse.
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Triple 8-bit ADC 170 Msps
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8.2.3 ADCs
Three ADCs convert analog signals into three series of 8-bit codes, with a maximum
clock frequency of 170 Msps. The ADCs input range is 1 V (p-p) full-scale and the
pipeline delay is 1 clock cycle from the sampling to the data output. The reference
ladder regulators are integrated.
8.2.4 Data outputs
ADC outputs are straight binary. Pin OE switches the output status between active
and high-impedance (OE = HIGH). It is possible to force the outputs with a maximum
10 pF capacitive load. The timing must be checked very carefully if the capacitive
loads are more than 10 pF.
It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC
pulse) and during the clamping (CLP pulse). This mode is activated through the serial
interface by setting bit ‘Blk’ to logic 1 in register DEMUX.
The TDA8757 provides outputs either on one port (port A) or on two ports (ports A
and B). The selection is made with the serial interface by setting bit ‘Dmx’ to logic 0 or
logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports
are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select
the port that would provide the odd pixel by setting bit ‘Odda’ to logic 1 or logic 0 in
register DEMUX; when this bit is logic 1, the odd pixel is output on port A.
One out-of-range bit exists per channel (ORR, ORG and ORB). It will be at logic 1
when the signal is out-of-range of the ADC voltage ladder.
Finally, two configurations are possible: either the port A outputs and the port B
outputs are both synchronous or they are interleaved. The selection is done by
setting bit ‘Shift’ to logic 0 or logic 1 in register DEMUX.
CKREF
CKADC
CKREFO
OUT A
XXX
XXX
ODD
EVEN
FCE708
Fig 7. Definition of odd and even pixels; Edge = 0, Dmx = 0 and Ckrp = 1.
8.2.5 PLL
The ADCs are clocked by either the internal PLL locked to the reference clock
CKREF or an external clock connected to pin CKEXT. All parts of the PLL are on-chip
except the loop filter capacitance. The selection is performed via the serial interface
by setting bit ‘Ckext’ in register PHASE (Ckext = 1 when the external clock is used).
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Triple 8-bit ADC 170 Msps
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The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 170 MHz. The
gain of the VCO part can be controlled through the serial interface, depending on the
frequency range to which the PLL is locked.
Moreover, the PLL may be locked either on the rising or on the falling edge of the
CKREF signal pulses. This choice is made through the serial interface by setting
bit ‘Edge’ in register CONTROL (rising edge when bit ‘Edge’ = 0).
The charge pump current (Icp) enables an increase of PLL bandwidth. It is
programmable through the serial interface by setting bits ‘Ip2’, ‘Ip1’ and ‘Ip0’ in the
control register (see Table 8).
Different resistance values (R) for the filter can also be programmed through the
serial interface by setting the bits ‘Z2’, ‘Z1’ and ‘Z0’ in register VCO (see Table 9).
To have optimal PLL performance, R and Icp must be chosen so that:
The result of the product ‘R × I ’ is smaller than a determined limit (Lim)
•
•
cp
The result of the product ‘R × I ’ is as close as possible to this limit (Lim).
cp
0.3π × DRPLL × f ref
Lim =
(1)
--------------------------------------------------
K0
where:
DRPLL = the divider ratio, which is the ratio between the pixel frequency and the
horizontal line frequency of the incoming signal. The setting of this parameter is
•
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
f
ref = the frequency of the signal.
•
•
K = the VCO gain, which depends on the pixel frequency ranges given in
Table 10.
0
In the event that several combinations of R and Icp give the same result, a calculation
of the damping factor (ξ) for each combination becomes necessary.
The combination of R and Icp whose damping factor is the closest to 1.5, generates
the optimal PLL performance.
K0 Icp
R CZ
ξ =
----------------------------------------------
(2)
--------------
DRPLL (CZ + CP)
2
where CZ and CP are the external capacitors of the PLL loop filter. The recommended
values are: CZ = 68 nF and CP = 150 pF.
The COAST signal is used to disconnect the PLL phase frequency detector during
the frame flyback (vertical blanking) or during the unavailability of the CKREF signal.
This signal can normally be derived from the VSYNC signal.
COAST may be set either active HIGH or active LOW by setting bit ‘Vlevel’ in the
control register through the serial interface (Vlevel = 0 when HIGH).
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Triple 8-bit ADC 170 Msps
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It is possible to control the phase of the ADC clock (CKADC) through the serial
interface with the included digital phase-shift controller. The phase register (5 bits)
enables the phase to shift by steps of 11.25 °.
The CKREF signal is re-synchronized by the synchro-block on the CKADC clock. The
new reference is available on pin CKREFO. This synchronization may be done with
the CKREF signal directly, or with the output of the divider in the PLL (see Figure 3).
The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register
(Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO
is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX
(positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles.
The PLL also provides a CKDATA clock. This clock is synchronized on the data
outputs whatever the output mode.
It is possible to delay the CKDATA clock with a constant time (τ = 3 ns, compared to
the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. It is also possible to
reverse the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in
register DEMUX.
The maximum capacitive load for each clock output is 10 pF, and pin OE switches the
output status between active and high impedance (OE = HIGH).
If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and
bit ‘Ckrs’ in the phase register have to be set at logic 1, and it is also important to
disconnect the internal PLL by using the following settings:
Set bit ‘Do’ in the control register to logic 1.
•
•
Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0.
CKREF
t
CKAO
CKADC
t
CKREFO
CKREFO
Ckrp = 0
8 clock periods
CKREFO
Ckrp = 1
FCE699
Fig 8. Timing diagram; CKREFO; Dmx = 0.
There is a delay between the input signal on pin CKREF and the corresponding
output on pin CKREFO; see Figure 8. This delay is tCKREFO
:
tCKREFO = either tCKAO (if clock phase >01000) or tCKAO + TCLK(pixel) (if phase <01000)
tCKAO = tCLK(buffer) + tphase selector
phase
2π
tCLK(buffer) = tbf and tphase selector
=
TCLK(pixel)
---------------
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Triple 8-bit ADC 170 Msps
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9. I2C-bus and 3W-bus interfaces
9.1 Register definitions
The configuration of the registers is given in Table 4.
Table 4: I2C-bus and 3W-bus registers
Function Subaddress
name
Bit definition
Default
value
A7 A6 A5 A4 A3 A2 A1 A0 MSB
LSB
SUBADDR
OFFSETR
X
X
X
Mode Sa3
Sa2
Or2
Cr2
Fr2
Sa1 Sa0
Or1 Or0
XXX1 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0000 0111
1011 1011
0100 1100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Or7
Or8
X
Or6
Cr6
X
Or5
Cr5
X
Or4
Cr4
Fr4
Or3
Cr3
Fr3
COARSER X
Cr1
Fr1
Cr0
Fr0
FINER
X
X
OFFSETG
Og7
Og8
X
Og6
Cg6
X
Og5
Cg5
Og4
Cg4
Og3
Cg3
Fg3
Ob3
Cb3
Fb3
Do
Og2
Cg2
Fg2
Ob2
Cb2
Fb2
Ip2
Og1 Og0
Cg1 Cg0
Fg1 Fg0
Ob1 Ob0
Cb1 Cb0
Fb1 Fb0
COARSEG X
FINEG
X
X
Slevel Fg4
OFFSETB
Ob7
Ob8
X
Ob6
Cb6
X
Ob5
Cb5
X
Ob4
Cb4
Fb4
COARSEB X
FINEB
CONTROL X
X
Vlevel Hlevel Edge Up
Ip1
Ip0
VCO
X
X
Z2
Z1
Z0
Vco1 Vco0 Di11 Di10 Di9
DIVIDER
(LSB)
Di8
Di7
Di6
Di5
Di4
Di3
Di2
Di1
PHASE
DEMUX
X
X
X
X
X
X
X
X
1
1
1
1
0
0
0
1
Di0
Blk
Ckrs Ckext P4
P3
P2
P1
P0
0000 0000
Cken Ckrp Ckdp Ckdd Shift Odda Dmx 1000 0111
9.1.1 Subaddress
All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I2C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
each register.
Bit Mode, used only with the I2C-bus, allows two modes for the programming:
Mode 0
Mode 1
Each register is programmed independently, by giving its subaddress
and its content.
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predefined sequence of 16 bytes (from
subaddress 0000 to 1101).
The default values correspond to a VESA 1280 × 1024 at 75 Hz graphic mode.
9.1.2 Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in Table 5.
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Triple 8-bit ADC 170 Msps
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Table 5: Coding
Programmed code
Clamp code
ADC output
0
−63.5
−63
−62.5
...
1
underflow
2
...
127
...
0
0
...
...
254
255
256
...
63.5
64
63 or 64
64
120
...
120
...
287
136
136
The default programmed value is:
Programmed code = 127
Clamp code = 0
•
•
•
ADC output = 0.
9.1.3 Coarse and Fine registers
These two registers enable the gain control: the AGC gain with the coarse register,
and the reference voltage with the fine register. The coarse register programming
equation is as follows:
NCOARSE + 1
N
COARSE + 1
------------------------------------------------
ref .(512 – NFINE
1
GAIN =
×
=
× 32
(3)
-----------------------------------------------
-----
16
V
)
NFINE
Vref 1 –
-----------------
32 × 16
Where: Vref = 2.5 V.
The gain correspondence is given in Table 6. The gain is linear with reference to the
programming code (NFINE = 0).
Table 6: Typical gain correspondence (COARSE)
NCOARSE
32
Gain
0.825
2.5
Vi to be full-scale (V)
1.212
0.4
99
The default programmed value is as follows:
N
COARSE = 32
•
•
•
Gain = 0.825
V to be full-scale = 1.212.
i
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Triple 8-bit ADC 170 Msps
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To modulate this gain, the fine register is programmed using the above equation. With
a full-scale ADC input, the fine register resolution is a 1⁄2 LSB peak-to-peak (see
Table 7 for NCOARSE = 32).
Table 7: Typical gain correspondence (FINE)
NFINE
0
Gain
0.825
0.878
Vi to be full-scale (V)
1.212
1.139
31
The default programmed value is: NFINE = 0.
9.1.4 Control register
COAST and HSYNC signals can be derived by setting the I2C-bus control bits ‘Vlevel’
and ‘Hlevel’ respectively. When bits ‘Vlevel’ and ‘Hlevel’ are set to zero, COAST and
HSYNC are active HIGH.
Bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It will
be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1.
Bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These bits
have to be logic 0 during normal use.
Bit ‘Cken’ is used for the test to check the CKADC internal signal. This bit has to be
logic 0 during normal use.
Bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the bandwidth of
the PLL, as shown in Table 8.
Table 8: Charge pump current control
Ip2
0
Ip1
0
Ip0
0
Current (µA)
6.25
12.5
25
0
0
1
0
1
0
0
1
1
50
1
0
0
100
200
400
700
1
0
1
1
1
0
1
1
1
The default programmed value is as follows:
Charge pump current = 700 µA
•
•
•
•
Bits ‘Up’ and ‘Do’ are used for testing, normally they are set to logic 0
Rising edge of CKREF: bit ‘Edge’ at logic 0
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
9.1.5 VCO register
Bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be selected.
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Triple 8-bit ADC 170 Msps
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Table 9: VCO register bits
Z2
0
Z1
0
Z0
0
Resistance (kΩ)
high-impedance
0
0
1
9
0
1
0
6.4
4.5
3.2
2.25
1.6
1.1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Bits ‘Vco1’ and ‘Vco0’ control the VCO gain.
Table 10: VCO gain control
Vco1
Vco0
VCO gain (MHz/V)
Pixel clock
frequency range
(MHz)
0
0
1
1
0
1
0
1
12
20
40
70
10 to 20
20 to 40
40 to 85
85 to 170
The default programmed value is as follows:
Internal resistance = 2.25 kΩ
•
•
VCO gain = 70 MHz/V.
9.1.6 Divider register
This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The
default programmed value is 0110 1001 1000 = 1688.
The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed
before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for
the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be
noted that if the I2C-bus programming is done in mode 1 and the bit ‘Di0’ has to be
toggled, then the registers have to be loaded twice to update the divider ratio.
9.1.7 Phase register
Bit ‘Ckext’ is logic 0 when the PLL clock is used, and logic 1 when the external clock
is used.
Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see Figure 3).
Bits ‘P4’ to ‘P0’ are used to program the phase shift for the clock pixel.
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Triple 8-bit ADC 170 Msps
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Table 11: Phase registers bits
P4
0
P3
0
P2
0
P1
0
P0
0
Phase shift (deg)
0
0
0
0
0
1
11.25
...
...
1
...
1
...
1
...
1
...
0
337.5
348.75
1
1
1
1
1
The default programmed value is as follows:
No external clock: bit ‘Ckext’ is logic 0
Phase shift for CKDATA is 0 degrees.
•
•
9.1.8 DEMUX register
The default programming is:
Outputs forced to logic 0 during CLP and HSYNC pulses: bit ‘Blk’ = 1
CKREFO with positive polarity: bit ‘Ckrp’ = 0
CKDATA not reversed: bit ‘Ckdp’ = 0
•
•
•
•
•
•
•
CKDATA not delayed: bit ‘Ckdd’ = 0
De-multiplexed outputs: bit ‘Dmx’ = 1
Interleaved outputs: bit ‘Shift’ = 1
Odd pixels on port A: bit ‘Odda’ = 1.
9.1.9 Power-down mode
When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
•
•
When the device is in Power-down mode (pin PD = HIGH), the previously
programmed register values remain unaffected.
9.2 I2C-bus protocol
Table 12: Register format
A6
A5
A4
A3
A2
A1
A0
RW
1
0
0
1
1
A2
A1
0
The address of the circuit for the I2C-bus is 1001 1XX0.
Bits ‘A1’ and ‘A0’ are fixed by the potential on pins A2 and A1. Bit ‘RW’ must always
be equal to logic 0 because it is not possible to read the data in the register. The
timing and protocol for the I2C-bus are standard. Two sequences are available;
see Table 13 and 14.
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Triple 8-bit ADC 170 Msps
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Table 13: Address sequence for mode 0
S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition.
S
IC ADDRESS
A
SUBADDRESS A
REGISTER1
DATA
REGISTER1
(see Table 4)
A
SUBADDRESS
REGISTER2
A
A
...
...
P
P
Table 14: Address sequence for mode 1
S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition.
S
IC ADDRESS
A
SUBADDRESS A
XX11 1111
DATA
REGISTER1
(see Table 4)
A
DATA
REGISTER2
9.3 3W-bus protocol
For the 3W-bus, the first byte refers to the register address which is programmed. The
second byte refers to the data to be sent to the chosen register (see Table 4).
Using a 3W-bus interface, an indefinite number of ICs can operate on the same
system. Pin SEN is used to validate the circuits.
t
= 600 ns
r3W
100 ns
SEN
1
9
x
1
9
SCL
SDA
x
x
x
x
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
x
FCE707
t
= 100 ns
t
= 100 ns
h3W
s3W
Fig 9. 3W-bus protocol.
10. Limiting values
Table 15: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCCA
Parameter
Conditions
Min
Max
+7.0
+7.0
+7.0
+7.0
Unit
V
analog supply voltage
logic supply voltage
digital supply voltage
output stages supply voltage
−0.3
−0.3
−0.3
−0.3
VDDD
V
VCCD
V
VCCO
V
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Triple 8-bit ADC 170 Msps
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Table 15: Limiting values…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
∆VCC
supply voltage differences
V
V
V
V
V
V
CCA − VCCD
CCO − VCCD
CCO − VDDD
CCA − VDDD
CCD − VDDD
CCA − VCCO
−1.0
−1.0
−1.0
−1.0
−1.0
−1.0
−0.3
+1.0
+1.0
+1.0
+1.0
+1.0
+1.0
+7.0
V
V
V
V
V
V
V
Vi(RGB)
RGB input voltage range
referenced
to AGND
Io
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
0
+150
70
−
150
11. Thermal characteristics
Table 16: Typical thermal characteristics
Symbol
Parameter
Conditions
Value
Unit
Rth(j-a)
thermal resistance from junction to in free air
ambient
30
K/W
12. Characteristics
Table 17: Characteristics
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VCCA(PLL)
VCCA(R)
VCCA(G)
VCCA(B)
VDDD
,
analog supply voltage for PLL and
the RGB channels
4.75
5.0
5.25
V
,
,
logic supply voltage for I2C-bus
and 3W-bus
4.75
5.0
5.25
V
VCCD
VCCO(PLL)
VCCO(R)
VCCO(G)
VCCO(B)
digital supply voltage
4.75
4.75
5.0
5.0
5.25
5.25
V
V
,
output stages supply voltage for
PLL and the RGB channels
,
,
ICCA(PLL)
analog PLL supply current
−
34
−
mA
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Triple 8-bit ADC 170 Msps
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Table 17: Characteristics…continued
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise
specified.
Symbol
ICCA(R)
ICCA(G)
ICCA(B)
IDDD
Parameter
Conditions
Min
Typ
Max
Unit
,
,
analog supply current for the
RGB channels
−
135
−
mA
logic supply current for I2C-bus
and 3W-bus
−
1
−
mA
ICCD
ICCO(R)
ICCO(G)
ICCO(B)
digital supply current
−
−
95
80
−
−
mA
mA
,
,
,
output stages supply current for
the RGB channels and PLL
sinusoidal input
ICCO(PLL)
∆VCC
supply voltage difference
V
V
V
V
V
V
CCA − VCCD
CCO − VCCD
CCO − VDDD
CCA − VDDD
CCD − VDDD
CCA − VCCO
−0.25
−0.25
−0.25
−0.25
−0.25
−0.25
−
−
+0.25
+0.25
+0.25
+0.25
+0.25
+0.25
−
V
−
V
−
V
−
V
−
V
−
V
Ptot
Ppd
total power dissipation
sinusoidal input
1.5
55
W
mW
power dissipation in Power-down
mode
−
−
R, G and B amplifiers
B
bandwidth
−3 dB; Tamb = 25 °C
250
−
−
−
MHz
ns
tset(ADC+AGC)
settling time of the block
ADC + AGC
full-scale (black to white)
transition; input signal
settling time <1 ns; settling
to within 2 LSB
−
4
GCOARSE
coarse gain range
minimum coarse gain;
code = 32
−
−
−
−
−
−1.67
8
−
−
−
−
−
dB
maximum coarse gain;
code = 99
dB
GFINE
fine gain correction range
minimum fine input
code = 0
0
dB
maximum fine input
code = 31
−0.5
325
dB
∆Gamp/∆T
amplifier gain stability variation
with temperature
Vref with 100 ppm/°C
maximum variation
ppm/°C
IGC
gain current
−
−
±20
−
−
µA
tstab
amplifier gain adjustment speed HSYNC active; capacitors
from minimum to maximum gain on pins 8, 16 and 24 are
22 nF
25
mdB/µs
Vref
amplifier reference voltage
−
2.5
−
V
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
24 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 17: Characteristics…continued
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Iref
amplifier reference voltage
current
−
50
−
µA
Vi(p-p)
input voltage
(peak-to-peak value)
corresponding to full-scale
input at high gain
−
−
0.4
−
V
V
corresponding to full-scale
output at low gain
−
1.212
Ci
input capacitance
−
−
10
1
−
−
pF
%
GE(rms)
channel-to-channel gain
matching (RMS value)
maximum coarse gain;
Tamb = 25 °C
minimum coarse gain;
Tamb = 25 °C
−
−
5
−
−
%
Clamps
PCLP
precision
maximum black level noise
on RGB channels = 10 mV;
Tamb = 25 °C
0.5
LSB
tW(CLP)
CLPE
clamp pulse width
500
−
2000
ns
channel-to-channel clamp
matching
−
0.5
−
LSB
Aoff
code clamp reference
clamp register input
code = 0
−
−
−
−
−63.5
+64
−
−
−
−
LSB
LSB
LSB
LSB
clamp register input
code = 255
clamp register input
code = 256
+120
+135.5
clamp register input
code = 287
Phase-locked loop (PLL)
jPLL(max)(p-p)
long term PLL phase jitter
fclk = 170 MHz
−
360
−
ps
(peak-to-peak value)
DR
divider ratio
100
15
10
−
−
4095
150
170
2
−
fref
reference clock frequency
output clock frequency
phase drift[1]
−
kHz
MHz
step
deg
fPLL
∆Φstep
Φstep
ADCs
fs
−
standard at 160 Msps
−
phase shift step
Tamb = 25 °C
−
11.25
−
maximum sampling frequency
DC integral non-linearity
170
−
−
MHz
LSB
INL
from IC analog input to
digital output; sinusoidal
input; fclk = 170 MHz
−
±0.5
±1.5
DNL
DC differential non-linearity
from IC analog input to
digital output; sinusoidal
input; fclk = 170 MHz
−
±0.4
±1
LSB
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
25 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 17: Characteristics…continued
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ENOB[2]
effective number of bits
−
7.4
−
bits
Signal-to-noise ratio
S/N
signal-to-noise ratio
fclk = 170 MHz
fclk = 170 MHz
−
−
46
57
−
−
dB
dB
Spurious free dynamic range
SFDR
spurious free dynamic range
Clock timing output (CKDATA)
ηext
ADC clock duty factor
maximum clock frequency
45
50
55
%
fclk(max)
−
−
170
MHz
Clock timing input (CKEXT)
fclk(max) maximum clock frequency
tCPH
−
−
−
−
170
−
MHz
ns
clock pulse width HIGH
clock pulse width LOW
2.5
2.5
tCPL
−
ns
Data timing[3]
td(s)
sampling delay time
output data set-up time
output hold time
all times referenced to 50% of
the rising edge of CKDATA; see
Figure 10
−
−
−
−7.5
−7
1
−
−
−
ns
ns
ns
tsu(d)(o)
th(o)
3-state output delay time
tdZH
tdZL
tdHZ
tdLZ
output enable HIGH
−
−
−
−
15
18
13
10
−
−
−
−
ns
ns
ns
ns
output enable LOW
output disable HIGH
output disable LOW
Data and sync outputs
VOL
VOH
IOL
LOW-level output voltage
Io = 1 mA
−
−
0.4
−
V
HIGH-level output voltage
LOW-level output current
HIGH-level output current
load capacitance
Io = 1 mA
2.4
−
−
V
VOL = 0.2 V
VOH = 3.4 V
0.2
0.3
10
−
mA
mA
pF
IOH
−
−
CL
−
−
TTL digital inputs (CKREF, COAST, INV, HSYNC, CLP, PD, DIS, I2C/3W, OE, CKEXT)
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input impedance
−
−
0.8
−
V
2.0
−
−
V
400
35
tbf
tbf
−
µA
µA
kΩ
pF
IIH
Zi
−
−
−
−
Ci
input capacitance
−
−
Sync on green input
Vsync(G)
sync on green pulse amplitude[4] Slevel = 0; see Figure 5
300
150
−
−
600
300
mV
mV
Slevel = 1; see Figure 5
9397 750 09457
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Preliminary data
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26 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 17: Characteristics…continued
VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V
(referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together;
Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise
specified.
Symbol
3W-bus
trst
Parameter
Conditions
Min
Typ
Max
Unit
reset time of the chip before
3-wire communication
−
−
−
600
100
100
−
−
−
ns
ns
ns
tsu
th
data set-up time for 3-wire
communication
data hold time for 3-wire
communication
I2C-bus[5]
VIL
LOW-level input voltage
HIGH-level input voltage
for SCL and SDA
−
−
−
0.3VDD
V
V
VIH
for SCL and SDA;
VPU = 5 V
3
−
for SCL and SDA;
VPU = 3 V
0.7VDD
−
−
fSCL
tBUF
clock frequency
0
−
−
100
kHz
time the bus must be free before
new transmission can start
4.7
−
µs
tHD;STA
tSU;STA
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
start condition hold time
start condition set-up time
LOW-level clock period
HIGH-level clock period
data set-up time
4.0
4.7
4.7
4.0
250
0
−
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
ns
ns
µs
ns
µs
pF
repeated start
−
−
−
−
data hold time
−
SDA and SCL rise time
SDA and SCL fall time
stop condition set-up time
bus line capacitive loading
fSCL = 100 kHz
fSCL = 100 kHz
−
1.0
300
−
tf
−
tSU;STO
Cb
4.0
−
400
[1] From 25 to 70 °C, the edge of the clock CKDATA has a shift of 1 phase compared to CKREF.
[2] Effective bits are obtained from a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency).
Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
[3] Output data acquisition: the output data is available after the maximum sampling delay time td(s). All the timings are given for a 10 pF
capacitive load.
[4] Pulse relative to the blank level.
[5] The I2C-bus timings are given for use of the bus at a frequency of 100 kbit/s (100 kHz). This bus could be used at a frequency of
400 kbit/s (400 kHz).
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
27 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Table 18: Examples of PLL settings and performance
VCCA = VDDD = VCCD = VCCO = 5 V; Tamb = 25 °C.
Video standards
fref
fclk
N
KO
CZ
CP
IP
Z
Long-term time jitter[1]
(kHz) (MHz)
(MHz/V) (nF) (nF) (µA) (kΩ)
RMS-value
(ps)
peak-to-peak
value (ps)
VGA: 640 × 480
31.469 25.175 800
20
68
68
0.15 200 4.5 242
1452
1350
VESA: 800 × 600
(SVGA 72 Hz)
48.08 50 1040 40
0.15 700 1.6 225
0.15 400 4.5 120
0.15 400 3.2 98
0.15 400 4.5 70
0.15 400 4.5 65
VESA: 1024 × 768
(XGA 75 Hz)
60.02 78.75 1312 40
68
68
68
68
720
588
420
390
VESA: 1280 × 1024
(SXGA 60 Hz)
63.98 108
80.00 135
75.00 162
1688 70
1688 70
2160 70
VESA: 1280 × 1024
(SXGA 75 Hz)
VESA: 1600 × 1200
(UXGA 60 Hz)
[1] PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
t
t
CPL
CPH
n
50%
CKDATA
DATA
t
su(d)(o)
2.4 V
0.4 V
I
I
I
n+1
n−1
n
t
h(o)
t
d(s)
V
in
Sample n+2
Sample n+1
Sample n+3
Sample n
FCE700
Fig 10. Data timing; Dmx = 0; n = even pixel.
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
RGBIN
CKADC
CKDATA
OUT A
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
FCE701
Fig 11. Timing diagram; single port mode; Dmx = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
28 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
RGBIN
CKADC
CKDATA
OUT A
OUT B
n-2
n
n+2
n+4
n-1
n+1
n+3
FCE702
Fig 12. Timing diagram; dual port mode, interleaved outputs, even pixels on port A; Dmx = 1, Shift = 1, Odda = 0,
Ckdd = 0, Ckdp = 0; n = even pixel.
RGBIN
CKADC
CKDATA
OUT A
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n-1
n+1
n+3
OUT B
n-2
n
n+2
n+4
FCE703
Fig 13. Timing diagram; dual port mode, interleaved outputs, odd pixels on port A; Dmx = 1, Shift = 1, Odda = 1,
Ckdd = 0, Ckdp = 0; n = even pixel.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
29 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
RGBIN
CKADC
CKDATA
n-4
n-3
n-2
n-1
n
n+2
n+3
OUT A
OUT B
n+1
FCE704
Fig 14. Timing diagram; dual port mode, synchronized outputs, even pixels on port A; Dmx = 1, Shift = 0,
Odda = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-1
n-2
n+1
n
n+3
n+2
n+5
n+4
OUT B
FCE705
Fig 15. Timing diagram; dual port mode, synchronized outputs, odd pixels on port A; Dmx = 1, Shift = 0, Odda = 1,
Ckdd = 0, Ckdp = 0; n = even pixel.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
30 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
13. Application information
150 pF
68 nF
n.c.
108
n.c.
1
10 nF
B7
DEC2
R
B6
R
2
107
VREF
3
10 nF
106
B5
DEC1
R
4
105
AGC
R
B4
R
5
104
10 nF
BOT
R
B3
R
6
103
22 nF
GAINC
R
B2
R
7
102
4.7 nF
CLP
B1
R
R
R
8
101
10 nF
DEC
B0
R
9
100
V
A7
CCA(R)
IN
R
G
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
99
100 nF
A6
G
RIN
98
n.c.
A5
G
97
AGND
R
A4
G
75 or 50Ω
96
A3
n.c.
G
95
AGC
G
A2
G
94
10 nF
BOT
A1
G
G
93
22 nF
10 nF
GAINC
G
A0
G
OR
92
4.7 nF
CLP
G
G
G
91
TDA8757HL
V
DEC
CCO(G)
OGND
90
V
G
CCA(G)
IN
G
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
100 nF
V
CCO(G)
GIN
GIN
AGND
IN
OGND
G
G
B7
G
B6
75 or 50Ω
470 nF
SOG
SOG
G
O
B5
G
B4
n.c.
AGC
B
B
B
B
B
G
10 nF
BOT
B3
G
B2
22 nF
10 nF
GAINC
G
4.7 nF
CLP
DEC
B1
G
B0
G
V
A7
B
A6
CCA(B)
100 nF
IN
B
B
BIN
AGND
B
A5
B
A4
n.c.
n.c.
n.c.
75 or 50Ω
B
A3
B
A2
B
GND
DP
(tbf)
10
kΩ
10
kΩ
005aaa010
V
V
PU
PU
For interfacing the 5 V digital outputs of TDA8757 to devices with 3 V compliant inputs, a resistor bridge (220 Ω in series,
820 Ω to ground) should be applied to each digital output.
Fig 16. Application diagram.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
31 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
14. Package outline
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 x 20 x 1.4 mm; exposed die pad
SOT612-1
y
X
A
D
h
108
109
73
72
Z
E
e
E
H
A
E
2
h
A
E
(A )
3
A
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
37
144
1
36
v
M
A
Z
w M
D
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
D
E
E
e
H
H
E
L
L
v
w
y
Z
Z
θ
1
2
3
p
h
h
D
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 20.1 7.1 20.1 7.1
0.17 0.09 19.9 6.9 19.9 6.9
22.15 22.15
21.85 21.85
0.75
0.45
1.4
1.1
1.4
1.1
mm
1.6
0.25
1
0.2 0.08 0.08
0.5
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-03-22
02-01-25
SOT612-1
MS-026
Fig 17. Package outline.
9397 750 09457
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Preliminary data
Rev. 07 — 28 February 2002
32 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe, it is desirable to take normal precautions appropriate
to handling integrated circuits.
16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface
temperature of the packages should preferable be kept below 220 °C for thick/large
packages, and below 235 °C small/thin packages.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
•
•
For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
9397 750 09457
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Preliminary data
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33 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
•
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the
need for removal of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
16.5 Package related soldering information
Table 19: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package
Soldering method
Wave
Reflow[1]
suitable
suitable
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
not suitable[2]
HBCC, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, SMS
PLCC[3], SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
suitable
not recommended[3][4]
not recommended[5]
[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[2] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
34 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
17. Revision history
Table 20: Revision history
Rev Date
CPCN
-
Description
07 20020228
Preliminary data (9397 750 09457); seventh version
9397 750 09457
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 — 28 February 2002
35 of 37
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
18. Data sheet status
[1]
[2]
Data sheet status
Product status
Definition
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
19. Definitions
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a short-form specification is
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
21. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
20. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
36 of 37
9397 750 09457
Preliminary data
Rev. 07 — 28 February 2002
TDA8757
Triple 8-bit ADC 170 Msps
Philips Semiconductors
Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
20
21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Functional description . . . . . . . . . . . . . . . . . . 11
Analog video inputs . . . . . . . . . . . . . . . . . . . . 11
Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Variable gain amplifiers . . . . . . . . . . . . . . . . . 13
Important recommendations. . . . . . . . . . . . . . 13
ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
9.1
I2C-bus and 3W-bus interfaces. . . . . . . . . . . . 17
Register definitions . . . . . . . . . . . . . . . . . . . . . 17
Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Offset register . . . . . . . . . . . . . . . . . . . . . . . . . 17
Coarse and Fine registers . . . . . . . . . . . . . . . 18
Control register . . . . . . . . . . . . . . . . . . . . . . . . 19
VCO register. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Divider register . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase register. . . . . . . . . . . . . . . . . . . . . . . . . 20
DEMUX register . . . . . . . . . . . . . . . . . . . . . . . 21
Power-down mode . . . . . . . . . . . . . . . . . . . . . 21
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21
3W-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
9.2
9.3
10
11
12
13
14
15
16
16.1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal characteristics. . . . . . . . . . . . . . . . . . 23
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 23
Application information. . . . . . . . . . . . . . . . . . 31
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32
Handling information. . . . . . . . . . . . . . . . . . . . 33
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 33
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 33
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 34
Package related soldering information . . . . . . 34
16.2
16.3
16.4
16.5
17
18
19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 35
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 28 February 2002
Document order number: 9397 750 09457
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