TDA8755 [NXP]
YUV 8-bit video low-power analog-to-digital interface; YUV的8位视频低功耗模拟 - 数字接口
| 型号： | TDA8755 |
| 厂家： | 
NXP |
| 描述： | YUV 8-bit video low-power analog-to-digital interface |
| 文件： | 总20页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8755
YUV 8-bit video low-power
analog-to-digital interface
1995 Mar 09
Product specification
Supersedes data of June 1994
File under Integrated Circuits, IC02
Philips Semiconductors
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
FEATURES
APPLICATIONS
• 8-bit resolution
• High speed analog-to-digital conversion for video signal
digitizing
• Sampling rate up to 20 MHz
• TTL compatible digital inputs
• 3-state TTL outputs
• 100 Hz improved definition TV (IDTV).
GENERAL DESCRIPTION
• U, V two's complement outputs
• Y binary output
The TDA8755 is a bipolar 8-bit video low-power
analog-to-digital conversion (ADC) interface for YUV
signals. The device converts the YUV analog input signal
into 8-bit coded digital words in a 4 : 1 : 1 format at a
sampling rate of 20 MHz. The U/V signals are converted in
a multiplexed manner. All analog signal inputs are digitally
clamped and a fast precharge is provided for start-up.
All digital inputs and outputs are TTL compatible. Frame
synchronization is supported in a multiplexed manner.
• Power dissipation of 550 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• High signal-to-noise ratio over a large analog input
frequency range
• Track-and-hold included
• Clamp functions included
• UV multiplexed ADC
• 4 : 1 : 1 output data encoder
• Stable voltage regulator included.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
analog supply voltage
CONDITIONS
MIN.
4.75
TYP.
5.0
MAX.
5.25
UNIT
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
INL
V
V
V
digital supply voltage
4.75
4.75
−
5.0
5.0
46
5.25
5.25
55
output stages supply voltage
analog supply current
digital supply current
mA
−
55
66
mA
output stages supply current
DC integral non-linearity
DC differential non-linearity
effective bits
−
9
12
mA
fclk = 2 MHz
fclk = 2 MHz
−
±0.4
±0.3
7.1
−
±1
LSB
LSB
bits
MHz
mW
DNL
EB
−
±0.5
−
−
fclk(max)
Ptot
maximum clock frequency
total power dissipation
20
−
−
550
700
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
SOT287-1
TDA8755T
32
SO32L
plastic
1995 Mar 09
2
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
BLOCK DIAGRAM
LMA73-41
b o o k , f u l l p a g e w i d t h
1995 Mar 09
3
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
PINNING
SYMBOL PIN
DESCRIPTION
not connected
n.c.
1
2
REG1
decoupling input (internal
stabilization loop decoupling)
INY
3
4
Y analog voltage input
REG2
decoupling input (internal
stabilization loop decoupling)
CLPY
VCCA
5
6
Y clamp capacitor connection
analog positive supply voltage
(+5 V)
handbook, halfpage
V
INU
7
8
U analog voltage input
1
2
32
31
n.c.
REG1
INY
CCD
SDN
stabilizer decoupling node and
analog reference voltage (+3.35 V)
D7
3
30 D6
29 D5
INV
9
V analog voltage input
REG2
4
AGND
CLPU
CLPV
REG3
10 analog ground
5
CLPY
28
27
D4
D3
11 U clamp capacitor connection
12 V clamp capacitor connection
V
CCA
6
13 decoupling input (internal
stabilization loop decoupling)
INU
SDN
INV
7
26 D2
25 D1
8
CE
14 chip enable input (TTL level input
active LOW)
TDA8755
9
24 D0
V
23
10
AGND
CCO
CLP
HREF
CLK
DGND
D'0
15 clamp control input
16 horizontal reference signal
17 clock input
CLPU 11
12
22 D'3
21 D'2
CLPV
REG3 13
18 digital ground
D'1
20
19
18
19 V data output; bit 0 (n−1)
20 V data output; bit 1 (n)
21 U data output; bit 0 (n−1)
22 U data output; bit 1 (n)
14
15
D'0
CE
D'1
CLP
DGND
D'2
HREF 16
17 CLK
D'3
MLA728 - 1
VCCO
23 positive supply voltage for output
stages (+5 V)
D0
D1
D2
D3
D4
D5
D6
D7
VCCD
24 Y data output; bit 0 (LSB)
25 Y data output; bit 1
26 Y data output; bit 2
27 Y data output; bit 3
28 Y data output; bit 4
29 Y data output; bit 5
30 Y data output; bit 6
31 Y data output; bit 7 (MSB)
32 digital positive supply voltage (+5 V)
Fig.2 Pin configuration.
1995 Mar 09
4
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
+7.0
+7.0
+1.0
+1.0
+1.0
+5.0
VCCD
+6
UNIT
V
VCCD
digital supply voltage
−0.3
−0.3
−1.0
−1.0
−1.0
−
V
VCCO
output stages supply voltage
V
∆VCC
supply voltage difference between VCCA and VCCD
supply voltage difference between VCCO and VCCD
supply voltage difference between VCCA and VCCO
input voltage
V
V
V
VI
referenced to AGND
V
Vclk(p-p)
IO
AC input voltage for switching (peak-to-peak value) referenced to DGND
−
V
output current
−
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
−
+150
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
70
K/W
1995 Mar 09
5
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
CHARACTERISTICS
VCCA = V6 to V10 = 4.75 to 5.25 V; VCCD = V32 to V18 = 4.75 to 5.25 V; VCCO = V23 to V18 = 4.75 to 5.25 V;
AGND and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V;
VCCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and
Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
4.75
5.0
5.25
V
V
V
4.75
4.75
−
5.0
5.0
46
55
9
5.25
5.25
55
output stages supply voltage
analog supply current
digital supply current
mA
mA
mA
ICCD
−
66
ICCO
output stages supply current
−
12
Inputs
CLK (PIN 17)
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
input impedance
0
−
0.8
VCCD
−
V
2.0
−400
−
−
V
Vclk = 0.4 V
−
µA
µA
kΩ
pF
IIH
ZI
Vclk = 2.7 V
fclk = 20 MHz
fclk = 20 MHz
−
100
−
−
4
CI
input capacitance
−
4.5
−
CE, CLP AND HREF (PINS 14 TO 16)
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−400
−
V
Vclk = 0.4 V
Vclk = 2.7 V
µA
µA
IIH
100
CLPY (PIN 5)
V5
I5
clamp voltage for 16 output code
clamp output current
−
−
3.725
−
−
V
±50
µA
CLPU AND CLPV (PINS 11 AND 12)
V11, 12 clamp voltage for 128 output code
I11, 12
−
−
3.30
−
−
V
clamp output current
±50
µA
INY (PIN 3)
VI(p-p)
input voltage, full range
(peak-to-peak value)
fi = 4.43 MHz
0.93
1.0
1.07
V
ZI
input impedance
input capacitance
fi = 6 MHz
fi = 6 MHz
−
−
30
1
−
−
kΩ
CI
pF
1995 Mar 09
6
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
INU AND INV (PINS 7 AND 9)
VI(p-p)
input voltage, full range
fi = 1.5 MHz
0.93
1.03
1.13
V
(peak-to-peak value)
ZI
input impedance
fi = 2 MHz
fi = 2 MHz
−
−
30
1
−
−
kΩ
CI
input capacitance
pF
INPUTS ISOLATION
αct
crosstalk between Y, U and V
−
−55
−50
dB
Outputs
SDN (PIN 8)
Vref
VREG
IL
reference voltage
line regulation
load current
−
3.32
4.0
−
−
−
−
V
4.75 V ≤ VCCA ≤ 5.25 V
−
mV
mA
−2
DIGITAL OUTPUTS D0 TO D7 AND D’0 TO D’3 (PINS 24 TO 31 AND 19 TO 22)
VOL
LOW level output voltage
IO = 0.4 mA
0
−
−
−
−
0.4
V
IO = 1.5 mA
0
0.5
V
VOH
IOZ
HIGH level output voltage
IO = −0.4 mA
0.4 V < VO < VCCD
2.4
−20
VCCD
+20
V
output current in 3-state mode
µA
Switching characteristics
fclk(max)
fclk(min)
tCPH
maximum clock frequency
20
−
−
−
−
−
−
MHz
MHz
ns
minimum clock frequency
clock pulse width HIGH
clock pulse width LOW
2.0
−
20
20
tCPL
−
ns
Analog signal processing (fclk = 20 MHz; 50% clock duty factor)
Gdiff
ϕdiff
f1
differential gain
note 1; see Fig.8
note 1; see Fig.8
−
−
−
−
2
−
−
0
−
%
differential phase
3
deg
dB
dB
fundamental harmonics (full-scale) note 2
−
fall
harmonics (full-scale),
all components
note 2; see Fig.10
−54
SVRR1
SVRR2
supply voltage ripple rejection 1
supply voltage ripple rejection 2
note 3
note 3
−
−
−40
−
−
dB
1.0
%/V
Transfer function (50% clock duty factor)
INL
DC integral non-linearity
DC differential non-linearity
AC integral non-linearity
effective bits
fclk = 2 MHz
fclk = 2 MHz
note 4
−
−
−
−
±0.4
±0.3
±1.0
7.1
±1.0
±0.5
±2.0
−
LSB
LSB
LSB
bits
DNL
AILE
EB
note 5; Fig.10
1995 Mar 09
7
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (fclk = 20 MHz); note 6; see Figs 3 to 7
tds
th
sampling delay time
output hold time
−
7
−
−
−
−
−
3
3
7
3
−
−
3
1
−
−
ns
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
td
output delay time
33
10
10
8
42
14
14
11
6
tdZH
tdZL
tdHZ
tdLZ
tr
3-state output delay time
3-state output delay time
3-state output delay time
3-state output delay time
clock rise time
enable-to-HIGH
enable-to-LOW
disable-to-HIGH
disable-to-LOW
4
5
−
tf
clock fall time
5
−
tsu
th
HREF set-up time
−
−
HREF hold time
−
−
tr
data output rise time
data output fall time
minimum time for active clamp
12
16
−
−
tf
−
tCLP
note 7; see Fig.9
−
Notes
1. Low frequency ramp signal (VI(p-p) = full-scale and 64 µs period) combined with a sinewave input voltage
(VI(p-p) = 0.25 full-scale, fi = maximum permitted frequency) at the input.
2. The input conditions are related as follows:
a) Y channel: VI(p-p) = 1.0 V; fi = 4.43 MHz
b) U/V channel: VI(p-p) = 1.0 V; fi = 1.5 MHz.
3. Supply voltage ripple rejection:
a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation
of 0.5 V:
∆VI (127)
SVRR1 = 20 log
----------------------
∆VCCA
b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:
∆ (VI (0) – VI (255)
)
1
SVVR2 =
×
------------------------------------------------ -----------------
VI (0) – VI (255) ∆ V CCA
4. Full-scale sinewave (fi = 4.43 MHz for Y and fi = 1.5 MHz for U and V; fclk = 20 MHz).
5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input
frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform
(FFT) treatment taking 4 × Tclk (clock periods) acquisition points per period. The calculation takes into account all
harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
6. Output data acquisition is available after the maximum delay time of td.
7. U and V output data is not valid during tCLP
.
1995 Mar 09
8
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
Table 1 Mode selection
CE
D7 TO D0; D’3 TO D’0
1
0
high impedance
active; binary
Table 2 Output data coding
OUTPUT PORT
BIT
OUTPUT DATA
Y
D7
D6
D5
D4
D3
D2
D1
D0
D’3
D’2
D’1
D’0
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
U
V
t
t
CPL
CPH
1.4 V
CLK
sample N
sample N
1
sample N
2
sample N
3
sample N
4
sample N 5
V
l
t
h
t
ds
2.4 V
DATA
DATA
DATA
DATA
DATA
N
DATA
N 1
1.4 V
0.4 V
D0 to D7
N
4
N
3
N
2
N
1
t
d
MSA646
Fig.3 Timing diagram (INY signal).
9
1995 Mar 09
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
V
CCD
n
CE
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
TEST
tdLZ
S1
LOW
10 %
VCCD
VCCD
GND
GND
V
tdZL
tdHZ
tdZH
CCD
3.3 kΩ
15 pF
S1
TDA8755
MBD874
CE
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
handbook, halfpage
TDA8755
test probe
TEK P6201
D0 to D7
15 pF
MLA733 - 1
Fig.5 Load circuit for the 3-state output timing
measurement.
1995 Mar 09
10
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
CLK
sample N
1
sample N
5
4
4
2
3
HREF
output
sample N
t
t
su
h
output data valid
MLA732 - 1
N
4
N
3
N
2
N
1
N
data
The output data is valid 4 clock periods after HREF goes HIGH.
Fig.6 Timing definition for set-up and hold times (HREF signal).
4 clock periods (T
clk
)
sample N
sample N 4 x T
clk
CLK
HREF
sample N 4 (T
clk
1)
output data valid
output
data
N
4
N
3
N 3
MLA731 - 1
When the HREF period is a multiple of 4 clock periods, the output data is valid without any clock delay.
The internal circuit always gives an internal delay of 4 clock periods as illustrated in Fig.6.
Fig.7 Timing diagram (HREF signal).
1995 Mar 09
11
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
0.3 V
Y, U and V
channel
1.2 V
0.3 V
MSA644
64 µs
Y channel = 4.43 MHz sinewave.
U, V channel = 1.5 MHz sinewave.
Fig.8 Input test signal for differential gain and phase measurements.
digital
MSA645
output
level
255
black-level
clamping
Y : 16
U,V : 128
0
time
t
CLP
CLP
Fig.9 Clamping control timing.
12
1995 Mar 09
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
MBD873
0
amplitude
(dB)
20
40
60
80
100
120
0
1.25
2.50
3.75
5.00
6.25
7.50
8.75
10.00
f (MHz)
Effective bits: 7.30; THD = −53.35 dB.
Harmonic levels (dB): 2nd = −58.38; 3rd = −60.03; 4th = −57.30; 5th = −69.38; 6th = −67.09.
Fig.10 Fast Fourier Transform (fclk = 20 MHz; fi = 4.43 MHz).
1995 Mar 09
13
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
APPLICATION INFORMATION
V
n.c.
REG1
INY
CCD
a
1
2
3
4
32
31
5 V
10 nF
10 nF
D7
D6
D5
D4
D3
D2
D1
AGND
DGND
30
29
(3)
4.7 µF
REG2
CLPY
AGND
AGND
220 nF
(1)
5
6
28
27
V
CCA
5 V
10 nF
INU
SDN
7
8
26
25
(3)
4.7 µF
4.7 µF
+ 3.35 V
(2)
10 nF
(3)
TDA8755
INV
D0
V
9
24
23
AGND
CLPU
CLPV
REG3
CE
CCO
10
5 V
10 nF
D'3
AGND
11
22
(1)
(1)
DGND
D'2
AGND
AGND
12
13
21
20
D'1
220 nF
D'0
14
15
19
18
17
CLP
DGND
CLK
HREF
16
MLA735 - 1
The analog and digital supplies should be separated and decoupled.
(1) Clamp capacitors must be determined in accordance with the application; recommended values are CLPY = 18 nF, CLPU and CLPV = 33 nF.
(2) It is possible to use the reference output voltage pin SDN to drive other analog circuits under the limits indicated in Chapter “Characteristics”.
(3) Input signal pins have a high bandwidth. It is necessary to take special care on PCB layout to avoid any interaction from other signals (digital clocks
for example).
Fig.11 Application diagram.
1995 Mar 09
14
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
aY
SAA7158
Y
12
12
12
12
12
VDRAM
1 x TMS4C2970
SAA4940
NOISE
REDUCTION
INCLUDING
CROSS-COLOUR
REDUCTION
to
video
processor
U
V
U
TDA8755
VIDEO
ENHANCEMENT,
LFR
PROCESSING
AND DACs
VDRAM
1 x TMS4C2970
V
2
2
12
12/13.5/16/18 MHz
control
32/36 MHz
VCO2A
VCO1
H2, V2
MEMORY
(32 kHz/100 Hz)
VSYNC
SC1
CONTROLLER
SAA4951
to
deflection
processor
27 MHz
VCO2B
data
8
control
2
2
µC bus
2
I
C
MICROCONTROLLER
PCB83C652
MSA642
Fig.12 Block diagram of a full-options Improved Picture Quality (IPQ) module.
1995 Mar 09
15
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
aY
Y
VIDEO
ENHANCEMENT
AND
to
video
processor
VDRAM
1 x
TMS4C2970
12
12
U
U
V
DACs
TDA8755
SAA7165
2
V
2
I C bus
12/13.5/16/18 MHz
control
32/36 MHz
VCO1
VCO2A
H2, V2
(32 kHz/100 Hz)
MEMORY
CONTROLLER
SAA4951
VSYNC
to
deflection
processor
SC1
27 MHz
VCO2B
data
8
control
2
MSA643
2
I
C
MICROCONTROLLER
PCB83C652
Fig.13 Block diagram of an economic Improved Picture Quality (IPQ) module.
1995 Mar 09
16
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
PACKAGE OUTLINE
SO32:plasticsmall outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.086
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.42
0.39
0.043 0.047
0.016 0.039
0.037
0.022
inches 0.10
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-25
SOT287-1
1995 Mar 09
17
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
Several techniques exist for reflowing; for example,
SOLDERING
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Plastic small outline packages
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 Mar 09
18
Philips Semiconductors
Product specification
YUV 8-bit video low-power
analog-to-digital interface
TDA8755
NOTES
1995 Mar 09
19
Philips Semiconductors – a worldwide company
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
Internet: http://www.semiconductors.philips.com/ps/
Tel. (01)640 000, Fax. (01)640 200
Italy: PHILIPS SEMICONDUCTORS S.r.l.,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5028, Fax. (03)3740 0580
Korea: (Republic of) Philips House, 260-199 Itaewon-dong,
SCD38
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
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Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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Tel. (09)849-4160, Fax. (09)849-7811
533061/30/03/pp20
Date of release: 1995 Mar 09
9397 750 00027
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
Document order number:
Philips Semiconductors
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