TDA8761 [NXP]
9-bit analog-to-digital converter for digital video; 9位模拟 - 数字转换器，用于数字视频
| 型号： | TDA8761 |
| 厂家： | 
NXP |
| 描述： | 9-bit analog-to-digital converter for digital video |
| 文件： | 总20页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8761
9-bit analog-to-digital converter for
digital video
1995 Mar 20
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
FEATURES
APPLICATIONS
• 9-bit resolution
Analog-to-digital conversion for:
• Sampling rate up to 30 MHz
• DC sampling allowed
• Video data digitizing
• Digital Video Broadcasting (DVB)
• Cable TV.
• One clock cycle conversion only
• High signal-to-noise ratio over a large analog input
frequency range (8.5 effective bits at 10 MHz full-scale
input at fclk = 30 MHz)
GENERAL DESCRIPTION
The TDA8761 is a 9-bit analog-to-digital converter (ADC)
for professional video and digital video set box
• No missing codes guaranteed
• In range (IR) 3-state TTL output
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
30 MHz. Its linearity performance ensures the required
conversion accuracy in case of 256QAM demodulator
concept and for all symbol frequencies. All digital inputs
and outputs are TTL compatible, although a low-level sine
wave clock input signal is allowed.
• TTL compatible digital inputs and outputs
• Low-level AC clock input signal allowed
• External reference voltage regulator
• Power dissipation only 360 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
TYP. MAX. UNIT
4.75
4.75
4.4
−
5.0
5.0
5.0
30
5.25
5.25
5.25
tbf
V
VCCD
VCCO
ICCA
V
output stages supply voltage
analog supply current
digital supply current
V
mA
mA
mA
LSB
LSB
LSB
LSB
MHz
mW
ICCD
ICCO
AINL
−
22
tbf
output stages supply current
AC integral non-linearity
−
22
tbf
note 1; full scale input sine wave
−
±0.75 tbf
note 1; 50% full scale input sine wave
−
±0.5
±0.5
±0.3
−
tbf
tbf
tbf
−
ADNL
AC differential non-linearity note 1; full scale input sine wave
note 1; 50% full scale input sine wave
maximum clock frequency
−
−
fclk(max)
Ptot
30
−
total power dissipation
360
tbf
Note
1. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
ORDERING INFORMATION
PACKAGE
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
TYPE
NUMBER
NAME
VERSION
TDA8761M
SSOP28
SOT341-1
1995 Mar 20
2
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
BLOCK DIAGRAM
V
3
CLK
V
CCD
CE
10
CCA
1
11
2
CLOCK DRIVER
TC
TDA8761
V
RT
9
25 D8
24 D7
23 D6
22 D5
21 D4
20 D3
19 D2
18 D1
17 D0
MSB
V
I
8
7
ANALOG -TO - DIGITAL
CONVERTER
analog
voltage input
LATCHES
TTL OUTPUTS
data outputs
V
RM
LSB
V
CCO1
13
V
RB
6
28
26
V
CCO2
IR
IN RANGE LATCH
TTL OUTPUT
output
12
27
4
5
14
AGND1 AGND2 DGND
OGND1 OGND2
MGC355
analog grounds digital ground
output grounds
Fig.1 Block diagram.
1995 Mar 20
3
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
PINNING
SYMBOL PIN
DESCRIPTION
CLK
TC
1
2
3
4
5
6
7
8
9
clock input
two’s complement input (active LOW)
analog supply voltage (+5 V)
analog ground 1
VCCA
AGND1
AGND2
VRB
analog ground 2
handbook, halfpage
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
V
CLK
TC
1
2
28
CCO2
VRM
VI
27 OGND2
IR
V
3
26
CCA
VRT
reference voltage TOP input
AGND1
AGND2
4
25 D8
24 D7
23 D6
22 D5
CE
10 chip enable input (TTL level input,
active LOW)
5
VCCD
11 digital supply voltage (+5 V)
12 digital ground
V
6
RB
DGND
VCCO1
V
7
RM
13 supply voltage for output stages 1
(+5 V)
TDA8761
V
I
D4
8
21
20 D3
D2
V
OGND1
n.c.
n.c.
D0
14 output ground 1
15 not connected
9
RT
CE
10
11
19
16 not connected
V
18 D1
17 D0
16 n.c.
15 n.c.
CCD
17 data output; bit 0 (LSB)
18 data output; bit 1
19 data output; bit 2
20 data output; bit 3
21 data output; bit 4
22 data output; bit 5
23 data output; bit 6
24 data output; bit 7
25 data output; bit 8 (MSB)
26 in range data output
27 output ground 2
DGND 12
D1
V
13
CCO1
D2
OGND1 14
D3
MGC356
D4
D5
D6
D7
D8
IR
OGND2
VCCO2
28 supply voltage for output stages 2
(+5 V)
Fig.2 Pin configuration.
1995 Mar 20
4
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
output stages supply voltage
supply voltage differences between
VCCA and VCCD
note 1
note 1
−0.3
−0.3
+7.0
+7.0
−1.0
−1.0
−1.0
−0.3
−
+1.0
+1.0
+1.0
+7.0
VCCD
V
V
V
V
V
VCCO and VCCD
VCCA and VCCO
VI
input voltage
referenced to AGND
referenced to DGND
Vi(p-p)
AC input voltage for switching
(peak-to-peak value)
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
0
+150
+70
+150
−
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided the difference
between VCCA, VCCD and VCCO is between −1 and +1 V.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
110
K/W
1995 Mar 20
5
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
CHARACTERISTICS
VCCA = V3 to V4 and V5 = 4.75 to 5.25 V; VCCD = V11 to V12 = 4.75 to 5.25 V; VCCO = V13 and V28 to V14 and
V27 = 4.4 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at
VCCA = VCCD = VCCO = 5 V; Vi(p-p) = 1.5 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
∆VCC
analog supply voltage
4.75
4.75
4.4
5.0
5.25
V
digital supply voltage
output stages supply voltage
supply voltage differences between
VCCA and VCCD
5.0
5.0
5.25
5.25
V
V
−0.25
−0.4
−0.4
−
−
+0.25
+0.4
+0.4
tbf
V
VCCA and VCCO
−
V
VCCD and VCCO
−
V
ICCA
ICCD
ICCO
analog supply current
digital supply current
output stages supply current
30
22
22
mA
mA
mA
−
tbf
−
tbf
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
input impedance
0
−
−
0
−
2
2
0.8
VCCD
+1
20
−
V
2.0
−1
−
V
Vclk = 0.4 V
µA
µA
kΩ
pF
IIH
ZI
Vclk = 2.7 V
fclk = 30 MHz
fclk = 30 MHz
−
CI
input capacitance
−
−
INPUT CE (REFERENCED TO DGND); see Table 2
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−400
−
V
VIL = 0.4 V
VIH = 2.7 V
µA
µA
IIH
20
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL
IIH
ZI
LOW level input current
HIGH level input current
input impedance
VI = 1.3 V
VI = 3.8 V
fi = 10 MHz
fi = 10 MHz
−
−
−
−
0
−
−
−
−
µA
µA
kΩ
pF
70
5
CI
input capacitance
8
1995 Mar 20
6
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reference voltages for the resistor ladder; see Table 1
VRB
VRT
Vdiff
reference voltage BOTTOM
reference voltage TOP
1.2
1.3
−
V
−
3.3
2.0
V
CCA − 0.8 V V
differential reference voltage
1.8
3.0
V
V
RT − VRB
Iref
reference current
resistor ladder
−
30
−
mA
Ω
RLAD
TCRLAD
−
85
−
temperature coefficient of the resistor
ladder
−
1.86
158
250
250
1.5
−
ppm
mΩ/K
mV
mV
V
−
−
VosB
VosT
Vi(p-p)
offset voltage BOTTOM
offset voltage TOP
note 2
note 2
note 3
−
−
−
−
analog input voltage
(peak-to-peak value)
1.3
2.5
Outputs
DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)
VOL
VOH
LOW level output voltage
HIGH level output voltage
IO = 1 mA
0
−
−
−
−
−
0.4
V
IO = 0 mA
2.7
2.7
2.4
−20
V
V
V
CCO − 0.5
V
IO = −0.4 mA
IO = −1 mA
CCO − 1.3
CCO − 1.4
V
V
IOZ
output current in 3-state mode
0.4 V < VO < VCCO
+20
µA
Switching characteristics
CLOCK INPUT CLK; see Fig.3; note 1
fclk(max)
tCPH
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
30
10
10
−
−
−
−
−
−
MHz
ns
tCPL
ns
Analog signal processing
LINEARITY
AINL
AC integral non-linearity
note 5; full scale input
sine wave
−
−
−
−
−
−
±0.75 tbf
LSB
LSB
LSB
LSB
LSB
%
note 5; 50% full scale
input sine wave
±0.5
±0.5
±0.3
±1
tbf
tbf
tbf
−
ADNL
AC differential non-linearity
note 5; full scale input
sine wave
note 5; 50% full scale
input sine wave
OFER
GER
offset error
middle code;
VRB = 1.3 V; VRT = 3.3 V
gain error (from device to device)
VRB = 1.3 V;
±0.1
−
VRT = 3.3 V; note 4
1995 Mar 20
7
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BANDWIDTH (fclk = 30 MHz)
B
analog bandwidth
full-scale sine wave;
note 6
−
40
−
−
−
MHz
75% full-scale sine
wave; note 6
−
−
55
MHz
MHz
small signal at
mid-scale;
700
VI = ±10 LSB at
code 256; note 6
tSTLH
tSTHL
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.5; note 7
−
−
2.0
2.5
tbf
tbf
ns
ns
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.5; note 7
HARMONICS (fclk = 30 MHZ)
THD
total harmonic distortion
fi = 10 MHz
−
−64
−
−
dB
dB
SIGNAL-TO-NOISE RATIO; see Fig.7; note 8
S/N
signal-to-noise ratio (full scale)
without harmonics;
53
55
f
clk = 30 MHz;
fi = 10 MHz
EFFECTIVE BITS; see Fig 6; note 8
EB effective bits
fclk = 30 MHz;
fi = 10 MHz
−
8.5
−
bits
dB
TWO-TONE; note 9
TTIR
two-tone intermodulation rejection
fclk = 30 MHz
−
−
−64
−
−
BIT ERROR RATE
BER
bit error rate
fclk = 30 MHz;
fi = 10 MHz;
VI = ±16 LSB at
code 256
10−13
times/
sample
DIFFERENTIAL GAIN; note 10
Gdiff
differential gain
fclk = 30 MHz;
PAL modulated ramp
−
−
tbf
tbf
−
−
%
DIFFERENTIAL PHASE; note 10
ϕdiff
differential phase
fclk = 30 MHz;
deg
PAL modulated ramp
Timing (fclk = 30 MHz; CL = 15 pF); see Fig.3; note 11
tds
th
sampling delay time
output hold time
−
5
−
−
−
2
ns
ns
ns
pF
−
−
td
output delay time
digital output load
10
15
14
40
CL
1995 Mar 20
8
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
3-state output delay times; see Fig.4
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
tbf
tbf
tbf
tbf
tbf
ns
−
−
−
tbf
tbf
tbf
ns
ns
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at Tamb = 25 °C.
(VRT – VRB) × 8
3. Analog input voltage range can be derived from VRT − VRB difference. It is
(V511 – V0) – 1.5 V
-------------------------------------------
9
4. GER =
× 100
---------------------------------------------------
1.5 V
5. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No
glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of td.
1995 Mar 20
9
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.3 V)
BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
STEP VI(p-p) IR
U/F
0
<1.55
0
1
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
1.55
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
510
511
O/F
.
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
3.05
>3.05
Table 2 Mode selection
TC
X
CE
D8 TO D0
IR
1
0
0
high impedance
high impedance
active
0
active; two’s complement
active; binary
1
active
t
CPL
t
CPH
1.4 V
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
2.4 V
1.4 V
0.4 V
DATA
D0 to D8
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
t
d
MGC357
Fig.3 Timing diagram.
10
1995 Mar 20
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
V
CCD
CE
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
CCD
t
t
t
t
V
dLZ
dZL
dHZ
dZH
CCD
3.3 kΩ
15 pF
V
CCD
S1
TDA8761
GND
GND
CE
MGC358
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
1995 Mar 20
11
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
t
t
STLH
STHL
50 %
code 511
V
I
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
MGC359
0.5 ns
0.5 ns
Fig.5 Analog input settling-time diagram.
MGC360
0
amplitude
(dB)
20
40
60
80
100
120
0
1.88
3.75
5.63
7.50
9.37
11.3
13.1
15.0
f (MHz)
Effective bits: 8.58; THD = −61.80 dB.
Harmonic levels (dB): 2nd = −64.77; 3rd = −79.30; 4th = −71.90; 5th = −66.12; 6th = −82.29.
Fig.6 Fast Fourier Transform (fclk = 30 MHz; fi = 10 MHz).
12
1995 Mar 20
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
INTERNAL PIN CONFIGURATIONS
V
CCO2
handbook, halfpage
handbook, halfpage
V
V
CCO1
CCA
D8 to D0
O/UF
V
I
OGND1
AGND
MGC040
MGC361
Fig.7 TTL data and in-range outputs.
Fig.8 Analog inputs.
dbook, halfpage
V
CCO1
V
CCA
handbook, halfpage
V
V
RT
RM
CE
R
(TC)
LAD
V
RB
MEA050
AGND
OGND2
MGC041
Fig.9 CE (TC) 3-state input.
Fig.10 VRB, VRM and VRT.
1995 Mar 20
13
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
V
CCD
V
(1.3 V)
CLK
ref
DGND
MGC042
Fig.11 CLK input.
1995 Mar 20
14
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
APPLICATION INFORMATION
V
handbook, halfpage
CLK
TC
CCO2
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
OGND2
IR
V
CCA
3
AGND1
D8
4
AGND2
(1)
D7
5
V
RB
D6
6
(1)
100 nF
AGND
100 nF
V
RM
D5
7
TDA8761
V
I
D4
8
(1)
V
RT
D3
9
AGND
100 nF
CE
D2
10
11
12
13
14
AGND
V
D1
CCD
DGND
D0
(2)
V
n.c.
CCO1
(2)
OGND1
n.c.
15
MGC362
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor.
For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal
(pin 8) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder
(e.g. R = 5 kΩ and C = 100 nF).
(1) VRB, VRM and VRT are decoupled to AGND.
(2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence.
Fig.12 Application diagram.
1995 Mar 20
15
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
D
E
A
X
c
H
v
M
A
y
E
Z
28
15
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.1
0.7
mm
2.0
0.65
1.25
0.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-09-08
95-02-04
SOT341-1
MO-150AH
1995 Mar 20
16
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
Several techniques exist for reflowing; for example,
SOLDERING
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Plastic small outline packages
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 Mar 20
17
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
NOTES
1995 Mar 20
18
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
NOTES
1995 Mar 20
19
Philips Semiconductors – a worldwide company
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SCD39
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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The information presented in this document does not form part of any quotation
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533061/1500/01/pp20
Date of release: 1995 Mar 20
9397 750 00112
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Document order number:
Philips Semiconductors
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