TDA8790 [NXP]
8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter; 8位， 40 Msps的2.7〜 5.5 V，通用模拟 - 数字转换器
| 型号： | TDA8790 |
| 厂家： | 
NXP |
| 描述： | 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter |
| 文件： | 总20页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8790
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
1996 Feb 21
Product specification
Supersedes data of 1995 May 08
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
FEATURES
APPLICATIONS
• 8-bit resolution
High-speed analog-to-digital conversion for:
• Video data digitizing
• Camera
• Operation between 2.7 and 5.5 V
• Sampling rate up to 40 MHz
• DC sampling allowed
• Camcorder
• High signal-to-noise ratio over a large analog input
frequency range (7.3 effective bits at 4.43 MHz
full-scale input at fclk = 40 MHz)
• Radio communication.
GENERAL DESCRIPTION
• CMOS/TTL compatible digital inputs and outputs
• External reference voltage regulator
The TDA8790 is an 8-bit universal analog-to-digital
converter (ADC) for video and general purpose
• Power dissipation only 30 mW (typical)
applications. It converts the analog input signal from
2.7 to 5.5 V into 8-bit binary-coded digital words at a
maximum sampling rate of 40 MHz. All digital inputs and
outputs are CMOS/TTL compatible. A sleep mode allows
reduction of the device power consumption down to 4 mW.
• Low analog input capacitance, no buffer amplifier
required
• Sleep mode (4 mW)
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
2.7
TYP.
3.3
MAX.
5.5
UNIT
V
VDDD
VDDO
∆VDD
2.7
2.5
3.3
3.3
5.5
5.5
V
V
output stages supply voltage
supply voltage difference
V
DDA − VDDD
DDD − VDDO
−0.2
−0.2
−
−
−
4
5
1
+0.2
V
V
+2.25
V
IDDA
IDDD
IDDO
analog supply current
digital supply current
6
8
2
mA
mA
mA
−
output stages supply current
fclk = 40 MHz; CL = 20 pF;
ramp input
−
INL
integral non-linearity
fclk = 40 MHz; ramp input
−
±0.5
±0.25
−
±0.75
±0.5
−
LSB
LSB
MHz
mW
DNL
fclk(max)
Ptot
differential non-linearity
maximum clock frequency
total power dissipation
fclk = 40 MHz; ramp input
−
40
−
VDDA = VDDD = VDDO = 3.3 V
30
53
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8790M
SSOP20
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
1996 Feb 21
2
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
BLOCK DIAGRAM
V
5
V
DDD
CLK
1
DDA
3
2
CLOCK DRIVER
SLEEP
TDA8790
V
RT 10
19 D7
18 D6
17 D5
16 D4
15 D3
14 D2
13 D1
MSB
R
LAD
V
I
9
8
CMOS
OUTPUTS
ANALOG -TO - DIGITAL
CONVERTER
analog
voltage input
LATCHES
data outputs
V
RM
12
20
D0
LSB
V
V
RB
7
DDO
6
11
V
4
V
V
MBE502
SSA
SSO
SSD1
analog
ground
output
ground
digital
ground
Fig.1 Block diagram.
1996 Feb 21
3
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
PINNING
SYMBOL PIN
DESCRIPTION
CLK
SLEEP
VDDD
VSSD
VDDA
VSSA
VRB
VRM
VI
1
2
3
4
5
6
7
8
9
clock input
sleep mode input
digital supply voltage (2.7 to 5.5 V)
digital ground
V
1
2
20
19
CLK
DDO
analog supply voltage (2.7 to 5.5 V)
analog ground
SLEEP
D7
V
3
18 D6
DDD
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
V
4
17
16
15
D5
D4
D3
SSD
V
5
DDA
TDA8790
V
6
VRT
VSSO
D0
10 reference voltage TOP input
11 digital output ground
12 data output; bit 0 (LSB)
13 data output; bit 1
SSA
V
7
14 D2
D1
RB
V
8
13
RM
D1
V
I
9
12 D0
V
11
D2
14 data output; bit 2
V
10
SSO
RT
D3
15 data output; bit 3
MBE501
D4
16 data output; bit 4
D5
17 data output; bit 5
D6
18 data output; bit 6
D7
19 data output; bit 7 (MSB)
VDDO
20 positive supply voltage for output
stage (2.7 to 5.5 V)
Fig.2 Pin configuration.
1996 Feb 21
4
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
PARAMETER
CONDITIONS
note 1
MIN.
−0.3
MAX.
+7.0
UNIT
analog supply voltage
V
V
V
VDDD
VDDO
∆VDD
digital supply voltage
note 1
note 1
−0.3
−0.3
+7.0
+7.0
output stages supply voltage
supply voltage difference
V
V
V
DDA − VDDD
DDA − VDDO
DDD − VDDO
−1.0
−1.0
−1.0
−0.3
−
+4.0
+4.0
+4.0
+7.0
VDDD
V
V
V
V
V
VI
input voltage
referenced to VSSA
referenced to VSSD
Vclk(p-p)
AC input voltage for switching
(peak-to-peak value)
IO
output current
−
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
−55
−20
−
+150
+75
+150
Note
1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply
voltage ∆VDD remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
120
K/W
1996 Feb 21
5
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
CHARACTERISTICS
VDDA = V5 to V6 = 3.3 V; VDDD = V3 to V4 = 3.3 V; VDDO = V20 to V11 = 3.3 V; VSSA, VSSD and VSSO shorted together;
Vi(p-p) = 1.84 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA
VDDD
VDDO
∆VDD
analog supply voltage
2.7
2.7
2.5
3.3
5.5
V
digital supply voltage
3.3
3.3
5.5
5.5
V
V
output stages supply voltage
supply voltage difference
V
V
DDA − VDDD
DDD − VDDO
−0.2
−0.2
−
−
−
4
5
1
+0.2
V
+2.25
V
IDDA
IDDD
IDDO
analog supply current
digital supply current
6
8
2
mA
mA
mA
−
output stages supply current
fclk = 40 MHz; ramp input;
CL = 20 pF
−
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1
VIL
VIH
LOW level input voltage
HIGH level input voltage
0
−
−
−
0
−
4
3
0.3VDDD
V
0.7VDDD
VDDD
VDDD
+1
5
V
V
DDD ≤ 3.6 V
0.6VDDD
V
IIL
IIH
ZI
LOW level input current
HIGH level input current
input impedance
Vclk = 0.3VDDD
Vclk = 0.7VDDD
fclk = 40 MHz
fclk = 40 MHz
−1
−
µA
µA
kΩ
pF
−
−
CI
input capacitance
−
−
INPUT SLEEP (REFERENCED TO VSSD); see Table 2
VIL
VIH
LOW level input voltage
HIGH level input voltage
0
−
−
−
−
−
0.3VDDD
VDDD
VDDD
−
V
0.7VDDD
0.6VDDD
−1
V
V
DDD ≤ 3.6 V
V
IIL
LOW level input current
HIGH level input current
VIL = 0.3VDDD
VIH = 0.7VDDD
µA
µA
IIH
−
+1
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA
)
IIL
IIH
ZI
LOW level input current
HIGH level input current
input impedance
VI = VRB
VI = VRT
−
−
−
−
0
−
−
−
−
µA
µA
kΩ
pF
9
fi = 1 MHz
fi = 1 MHz
20
2
CI
input capacitance
Reference voltages for the resistor ladder; see Table 1
VRB
VRT
Vdiff
reference voltage BOTTOM
reference voltage TOP
1.1
2.7
1.5
1.2
3.3
2.1
−
V
V
V
VTOP ≤ VDDA
VDDA
2.7
differential reference voltage
V
RT − VRB
Iref
reference current
−
0.95
−
mA
1996 Feb 21
6
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
SYMBOL
PARAMETER
resistor ladder
CONDITIONS
MIN.
TYP.
2.2
MAX.
UNIT
kΩ
RLAD
−
−
−
−
−
−
TCRLAD
temperature coefficient of the
resistor ladder
−
1860
4092
170
ppm
mΩ/K
mV
mV
V
−
VosB
VosT
Vi(p-p)
offset voltage BOTTOM
offset voltage TOP
note 2
note 2
−
−
170
analog input voltage (peak-to-peak note 3
value)
1.4
1.76
2.4
Outputs
DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO VSSD
)
VOL
VOH
IOZ
LOW level output voltage
HIGH level output voltage
output current in 3-state mode
IO = 1 mA
0
−
−
−
0.5
V
IO = −1 mA
V
DDO − 0.5
VDDO
+20
V
0.4 V < VO < VDDO
−20
µA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
tCPH
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
40
9
−
−
−
−
−
−
MHz
ns
tCPL
9
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input;
see Fig.6
−
−
±0.5
±0.75
LSB
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input;
see Fig.7
±0.25 ±0.5
BANDWIDTH (fclk = 40 MHz)
analog bandwidth
B
full-scale sine wave;
note 4
−
−
−
−
10
−
−
−
−
MHz
MHz
MHz
MHz
75% full-scale sine wave;
note 4
13
50% full-scale sine wave;
note 4
20
small signal at mid scale;
Vi = ±10 LSB at
350
code 128; note 4
INPUT SET RESPONSE (fclk = 40 MHz; see Fig.8; note 5)
tSTLH
analog input settling time
LOW-to-HIGH
full-scale square wave
−
−
3
3
5
5
ns
ns
tSTHL
analog input settling time
HIGH-to-LOW
full-scale square wave
HARMONICS; (fclk = 40 MHZ; see Fig.9; note 6)
THD
total harmonic distortion
fi = 4.43 MHz
−
−50
−
dB
1996 Feb 21
7
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
SYMBOL
SIGNAL-TO-NOISE RATIO; see Fig.9; note 6
S/N signal-to-noise ratio (full scale)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
without harmonics;
fclk = 40 MHz;
−
47
−
dB
fi = 4.43 MHz
EFFECTIVE BITS; see Fig.9; note 6
EB effective bits
fclk = 40 MHz
fi = 300 kHz
fi = 4.43 MHz
−
−
7.8
7.3
−
−
bits
bits
DIFFERENTIAL GAIN; see note 7
Gdiff
differential gain
fclk = 40 MHz;
PAL modulated ramp
−
−
1.5
−
−
%
DIFFERENTIAL PHASE; see note 7
ϕdiff
differential phase
fclk = 40 MHz;
0.25
deg
PAL modulated ramp
Timing (fclk = 40 MHz; CL = 20 pF); see Fig.4; note 8
tds
th
sampling delay time
output hold time
−
5
8
8
8
−
5
ns
ns
ns
ns
ns
−
−
td
output delay time
VDDO = 4.75 V
12
17
18
15
20
21
VDDO = 3.15 V
DDO = 2.7 V
V
3-state sleep mode delay times; see Fig.5
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
14
16
16
14
18
20
20
18
ns
ns
ns
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 0 up to and including 256:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb = 25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to 256 at Tamb = 25 °C.
1996 Feb 21
8
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 255 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
V
RT – VRB
a) The current flowing into the resistor ladder is IL
=
and the full-scale input range at the converter,
-----------------------------------------
R
OB + RL + ROT
R L
to cover code 0 to code 255, is V = R × I =
× (VRT – VRB ) = 0.838 × (VRT – VRB )
-----------------------------------------
i
L
L
R
OB + RL + ROT
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
RL
will be kept reasonably constant from part to part. Consequently variation of the output codes
-----------------------------------------
OB + RL + ROT
R
at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation is observed in the reconstructed signal.
5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
7. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a DAC.
8. Output data acquisition: the output data is available after the maximum delay time of td.
handbook, halfpage
9
V
RT
R
OT
code 255
R
L
7
V
I
L
RM
R
LAD
code 0
R
OB
6
V
RB
MGD284
Fig.3 Explanation of note 3.
1996 Feb 21
9
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
Table 1 Output coding and input voltage (typical values; referenced to VSSA
)
BINARY OUTPUT BITS
VI(p-p)
(V)
STEP
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<1.37
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1.37
1
.
.
.
.
.
.
.
.
.
.
.
.
.
254
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
255
3.13
>3.13
Overflow
Table 2 Sleep mode selection
SLEEP
D7 TO D0
I
DDA + IDDD (typ.)
1
0
high impedance
active
1.2 mA
9 mA
t
CPL
t
CPH
50 %
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
V
DDO
DATA
D0 to D7
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
50 %
0 V
t
d
MSA670
Fig.4 Timing diagram.
1996 Feb 21
10
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
V
DDD
SLEEP
50 %
dZH
t
t
dHZ
HIGH
90 %
output
data
50 %
LOW
t
t
dZL
dLZ
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
DDD
t
t
t
t
V
DDD
dLZ
dZL
dHZ
dZH
3.3 kΩ
20 pF
V
DDD
GND
GND
S1
TDA8790
SLEEP
MBE503
fSLEEP = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
1996 Feb 21
11
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
MBE548
0.291
A
(LSB)
0.178
0.065
−0.047
−0.160
−0.272
0
34
68
102
136
170
204
238
255
codes
Fig.6 Typical integral non-linearity (INL) performance.
MBE549
0.150
A
(LSB)
0.091
0.032
−0.025
−0.84
−0.143
0
34
68
102
136
170
204
238
255
codes
Fig.7 Typical differential non-linearity (DNL) performance.
12
1996 Feb 21
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
t
t
STLH
STHL
50 %
code 255
V
I
50 %
code 0
5 ns
5 ns
CLK
50 %
50 %
MBE504
2 ns
2 ns
Fig.8 Analog input settling-time diagram.
MBE550
0
20
40
60
80
A
(dB)
100
120
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20
f (MHz)
Effective bits: 7.32; THD = 51.08 dB.
Harmonic levels (dB): 2nd = −68.99; 3rd = −51.62; 4th = −66.05; 5th = −63.23; 6th = −72.79.
Fig.9 Typical Fast Fourier Transform (fclk = 40 MHz; fi = 4.43 MHz).
13
1996 Feb 21
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
INTERNAL PIN CONFIGURATIONS
andbook, halfpage
handbook, halfpage
V
V
DDO
DDA
D7 to D0
V
I
V
V
SSO
SSA
MBE505
MLC857
Fig.11 Analog inputs.
Fig.10 CMOS data outputs.
handbook, halfpage
V
V
DDO
DDA
V
V
RT
R
LAD
RM
SLEEP
V
RB
V
V
SSA
SSO
MLC859
MBE506
Fig.12 SLEEP 3-state input.
Fig.13 VRB, VRM and VRT.
1996 Feb 21
14
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
V
DDD
handbook, halfpage
1
/ V
2
CLK
DDD
V
SSD
MLC860
Fig.14 CLK input.
APPLICATION INFORMATION
V
CLK
DDO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D7
D6
D5
D4
D3
D2
D1
SLEEP
V
DDD
V
SSD
V
DDA
TDA8790
V
SSA
(1)
V
RB
(1)
V
100
nF
RM
V
100
nF
D0
V
I
(1)
V
V
SSA
SSO
RT
V
SSA
100
nF
MBE507
V
SSA
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupled capacitor.
(1) VRB, VRM and VRT are decoupled to VSSA
.
Fig.15 Application diagram.
15
1996 Feb 21
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
D
E
A
X
c
y
H
v
M
A
E
Z
11
20
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0
1.4
1.2
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.5
0.65
1.0
0.2
0.25
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-04-05
95-02-25
SOT266-1
1996 Feb 21
16
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering SSOP
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds at between 270 and
320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration:
45 minutes at 45 °C.
Wave soldering SSOP
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Feb 21
17
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Feb 21
18
Philips Semiconductors
Product specification
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
TDA8790
NOTES
1996 Feb 21
19
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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825
Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415
SCDS47
© Philips Electronics N.V. 1996
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SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880
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All rights are reserved. Reproduction in whole or in part is prohibited without the
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Fax. (021)577035/5874546
537021/1100/03/pp20
Date of release: 1996 Feb 21
9397 750 00677
Document order number:
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