TDA8932T [NXP]
IC 25 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO32, 7.50 MM , PLASTIC, MO-119, SOT287-1, SOP-32, Audio/Video Amplifier;![TDA8932T](http://pdffile.icpdf.com/pdf2/p00269/img/icpdf/TDA8932T_1613986_icpdf.jpg)
型号: | TDA8932T |
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描述: | IC 25 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO32, 7.50 MM , PLASTIC, MO-119, SOT287-1, SOP-32, Audio/Video Amplifier 放大器 光电二极管 商用集成电路 |
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TDA8932
Class-D audio amplifier
Rev. 02 — 12 December 2006
Preliminary data sheet
1. General description
The TDA8932 is a high efficiency class-D amplifier with low power dissipation.
The typical output power is 2 × 15 W in stereo half-bridge application (RL = 4 Ω) or
1 × 30 W typical in full-bridge application (RL = 8 Ω). Due to the low power dissipation the
device can be used without any external heat sink when playing music. If proper cooling
via the printed-circuit board is implemented, a continuous output power of 2 × 15 W is
feasible. Due to the implementation of thermal foldback, even for high supply voltages
and/or lower load impedances, the device remains operating with considerable music
output power without the need for an external heat sink.
The device has two full-differential inputs driving two independent outputs. It can be used
as mono full-bridge configuration (BTL) or as stereo half-bridge configuration (SE).
2. Features
I Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical
I Mono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) application
I Application without heatsink using thermally enhanced small outline package
I High efficiency and low-power dissipation
I Thermally protected and thermal foldback
I Current limiting to avoid audio holes
I Full short-circuit proof across load and to supply lines (using advanced current
protection)
I Switchable internal or external oscillator (master-slave setting)
I No pop noise
I Full-differential inputs
3. Applications
I Flat panel television sets
I Flat panel monitor sets
I Multimedia systems
I Wireless speakers
I Mini and micro systems
I Home sound sets
TDA8932
NXP Semiconductors
Class-D audio amplifier
4. Quick reference data
Table 1.
Quick reference data
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Supplies
Conditions
Min
Typ
Max Unit
VP
supply voltage
supply current
asymmetrical supply
Sleep mode; no load
10
-
22
0.6
40
36
1
V
IP
mA
mA
Iq(tot)
total quiescent
current
Operating mode; no load, no
snubbers and no filter
connected
-
80
Stereo SE channel; Rs < 0.1 Ω[1][2]
Po(RMS) RMS output power continuous time output power
per channel;
THD+N = 10 %; fi = 1 kHz
RL = 4 Ω; VP = 22 V
RL = 8 Ω; VP = 30 V
14
14
15
15
-
-
W
W
short time output power per
channel; THD+N = 10 %;
fi = 1 kHz
RL = 4 Ω; VP = 29 V
23
25
-
W
Mono BTL; Rs < 0.1 Ω[1][2]
Po(RMS) RMS output power continuous time output power;
THD+N = 10 %; fi = 1 kHz
RL = 4 Ω; VP = 12 V
RL = 8 Ω; VP = 22 V
14
28
15
30
-
-
W
W
short time output power;
THD+N = 10 %; fi = 1 kHz
RL = 8 Ω; VP = 29 V
47
50
-
W
[1] Output power is measured indirectly; based on RDSon measurement.
[2] Rs is the series resistance of inductor of low-pass LC filter in the application.
5. Ordering information
Table 2.
Ordering information
Type number Package
Name
Description
Version
TDA8932T
SO32
plastic small outline package; 32 leads;
body width 7.5 mm
SOT287-1
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
2 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
6. Block diagram
OSCREF OSCIO
V
DDA
8
10
31
28
BOOT1
OSCILLATOR
29
2
V
DDP1
IN1P
DRIVER
HIGH
27
26
PWM
MODULATOR
OUT1
V
SSD
CTRL
DRIVER
LOW
V
SSP1
3
IN1N
INREF
IN2P
21
20
22
23
12
15
MANAGER
BOOT2
V
DDP2
DRIVER
HIGH
PWM
MODULATOR
OUT2
CTRL
DRIVER
LOW
V
SSP2
14
4
IN2N
DIAG
PROTECTIONS:
OVP, OCP, OTP,
UVP, TF, WP
V
DDA
25
24
18
STABILIZER 11 V
STAB1
STAB2
DREF
V
SSP1
V
DDA
STABILIZER 11 V
V
7
6
CGND
SSP2
POWERUP
REGULATOR 5 V
V
SSD
MODE
5
ENGAGE
11
30
19
V
V
DDA
HVPREF
HVP1
SSA
TDA8932
13
TEST
HVP2
HALF SUPPLY VOLTAGE
9
1, 16, 17, 32
001aad757
V
V
SSD(HW)
SSA
Fig 1. Block diagram
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
3 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
7. Pinning information
7.1 Pinning
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
SSD(HW)
SSD(HW)
IN1P
OSCIO
HVP1
3
IN1N
DIAG
4
V
DDP1
5
ENGAGE
POWERUP
CGND
BOOT1
OUT1
6
7
V
SSP1
8
V
STAB1
STAB2
DDA
TDA8932T
9
V
SSA
V
10
11
12
13
14
15
16
OSCREF
HVPREF
INREF
TEST
SSP2
OUT2
BOOT2
V
DDP2
IN2N
HVP2
DREF
IN2P
V
V
SSD(HW)
SSD(HW)
001aad756
Fig 2. Pin configuration SO32
7.2 Pin description
Table 3.
Symbol
VSSD(HW)
IN1P
Pin description
Pin
1
Description
negative digital supply voltage and handle wafer connection
positive audio input for channel 1
2
IN1N
3
negative audio input for channel 1
DIAG
4
diagnostic output; open-drain
ENGAGE
POWERUP
CGND
VDDA
5
engage input to switch between Mute mode and Operating mode
power-up input to switch between Sleep mode and Mute mode
control ground; reference for POWERUP, ENGAGE and DIAG
positive analog supply voltage
6
7
8
VSSA
9
negative analog supply voltage
OSCREF
HVPREF
INREF
TEST
10
11
12
13
14
15
16
17
18
input internal oscillator setting (only master setting)
decoupling of internal half supply voltage reference
decoupling for input reference voltage
test signal input; for testing purpose only
IN2N
negative audio input for channel 2
IN2P
positive audio input for channel 2
VSSD(HW)
VSSD(HW)
DREF
negative digital supply voltage and handle wafer connection
negative digital supply voltage and handle wafer connection
decoupling of internal (reference) 5 V regulator for logic supply
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
4 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 3.
Pin description …continued
Symbol
Pin
Description
HVP2
19
half supply output voltage 2 for charging single-ended capacitor for
channel 2
VDDP2
BOOT2
OUT2
VSSP2
STAB2
STAB1
VSSP1
OUT1
BOOT1
VDDP1
HVP1
20
21
22
23
24
25
26
27
28
29
30
positive power supply voltage for channel 2
bootstrap high-side driver channel 2
PWM output channel 2
negative power supply voltage for channel 2
decoupling of internal 11 V regulator for channel 2 drivers
decoupling of internal 11 V regulator for channel 1 drivers
negative power supply voltage for channel 1
PWM output channel 1
bootstrap high-side driver channel 1
positive power supply voltage for channel 1
half supply output voltage 1 for charging single-ended capacitor for
channel 1
OSCIO
31
32
oscillator input in slave configuration or oscillator output in master
configuration
VSSD(HW)
negative digital supply voltage and handle wafer connection
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
5 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
8. Functional description
8.1 General
The TDA8932 is a mono full-bridge or stereo half-bridge audio power amplifier using
class-D technology. The audio input signal is converted into a Pulse Width Modulated
(PWM) signal via an analog input stage and PWM modulator. To enable the output power
Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM
signal is applied to a control and handshake block and driver circuits for both the high side
and low side. A 2nd-order low-pass filter converts the PWM signal to an analog audio
signal across the loudspeakers.
The TDA8932 contains two independent half-bridges with full differential input stages. The
loudspeakers can be connected in the following configurations:
• Mono full-bridge: Bridge Tied Load (BTL)
• Stereo half-bridge: Single-Ended (SE)
The TDA8932 contains common circuits to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. The following
protections are built-in: thermal foldback, temperature, current and voltage protections.
8.2 Mode selection and interfacing
The TDA8932 can be switched in three operating modes using pins POWERUP and
ENGAGE:
• Sleep mode: with low supply current.
• Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the Vl-converter input stages. The capacitors on
pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical
supply only).
• Operating mode: the amplifiers are fully operational with output signal.
• Fault mode.
Both pins POWERUP and ENGAGE refer to pin CGND.
Table 4 shows the different modes as a function of the voltages on the POWERUP and
ENGAGE pins.
Table 4.
Mode
Mode selection
Pin
POWERUP
ENGAGE
< 0.8 V
< 0.8 V[1]
3 V to 6.0 V[1]
don’t care
DIAG
Sleep
< 0.8 V
don’t care
> 2 V
Mute
2 V to 6.0 V[1]
2 V to 6.0 V[1]
2 V to 6.0 V[1]
Operating
Fault
> 2 V
< 0.8 V
[1] In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never
exceed the supply voltage (VDDA, VDDP1 or VDDP2).
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
6 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
If the transition between Mute mode and Operating mode is controlled via a time constant,
the start-up will be pop free since the DC output offset voltage is applied gradually to the
output between Mute mode and Operating mode. The bias current setting of the
VI-converters is related to the voltage on pin ENGAGE:
• Mute mode: the bias current setting of the VI-converters is zero (VI-converters
disabled)
• Operating mode: the bias current is at maximum
The time constant required to apply the DC output offset voltage gradually between Mute
mode and Operating mode can be generated by applying a decoupling capacitor on pin
ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF.
V
P
POWERUP
DREF
HVPREF
HVP1, HVP2
0.43V
ENGAGE
0.3V
ENGAGE
ENGAGE
0.17V
ENGAGE
AUDIO
AUDIO
AUDIO
PWM
audio
OUT1, OUT2
PWM
PWM
DIAG
OSCIO
operating
mute
operating
fault
operating
sleep
001aae788
Fig 3. Start-up sequence
8.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of
approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an
analog audio signal across the loudspeaker. The PWM switching frequency can be set by
an external resistor Rosc connected between pins OSCREF and VSSD(HW). The carrier
frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ,
the carrier frequency is set to an optimized value of 320 kHz (see Figure 4).
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
7 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
If two or more TDA8932 devices are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices. This can be realized
by connecting all pins OSCIO together and configure one of the TDA8932 in the
application as clock master, while the other TDA8932 devices are configured in slave
mode.
Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as
oscillator output and in slave mode as oscillator input. Master mode is enabled by applying
a resistor while slave mode is entered by connecting pin OSCREF directly to pin VSSD(HW)
(without any resistor).
The value of the resistor also sets the frequency of the carrier which can be estimated by
the following formula:
12.45 × 109
f osc
=
(1)
---------------------------
Rosc
Where:
fosc = oscillator frequency
Rosc = oscillator resistor (on pin OSCREF)
001aad758
550
f
osc
(kHz)
450
350
250
25
30
35
40
45
Rosc (kΩ)
Fig 4. Oscillation frequency as a function of resistor Rosc
Table 5 summarizes how to configure the TDA8932 in master or slave configuration.
For device synchronization see Section 14.6 “Device synchronization”.
Table 5.
Master or slave configuration
Configuration
Pin
OSCREF
OSCIO
output
input
Master
Slave
Rosc > 25 kΩ to VSSD(HW)
Rosc = 0 Ω; shorted to VSSD(HW)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
8 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
8.4 Protection
The following protection is included in the TDA8932:
• Thermal Foldback (TF)
• OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protection:
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• ESD
The reaction of the device to the different fault conditions differs per protection.
8.4.1 Thermal Foldback (TF)
If the junction temperature of the TDA8932 exceeds the threshold level (Tj > 140 °C) the
gain of the amplifier is decreased gradually to a level where the combination of dissipation
(P) and the thermal resistance from junction to ambient [Rth(j-a)] results in a junction
temperature around the threshold level.
This means that the device will not completely switch off, but remains operational at lower
output power levels. Especially with music output signals this feature enables high peak
output power while still operating without any external heat sink other than the
printed-circuit board area.
If the junction temperature still increases due to external causes, the OTP shuts down the
amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 °C, then the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
When the loudspeaker terminals are short-circuited or if one of the demodulated outputs
of the amplifier is short-circuited to one of the supply lines, this will be detected by the
OCP.
If the output current exceeds the maximum output current (IO(ocp) > 4 A), this current will
be limited by the amplifier to 4 A while the amplifier outputs remain switching (the amplifier
is not shut down completely). This is called current limiting.
The amplifier can distinguish between an impedance drop of the loudspeaker and a
low-ohmic short-circuit across the load or to one of the supply lines. This impedance
threshold depends on the supply voltage used:
• In case of a short-circuit across the load, the audio amplifier is switched off completely
and after approximately 100 ms it will try to restart again. If the short-circuit condition
is still present after this time, this cycle will be repeated. The average dissipation will
be low because of this low duty cycle.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
9 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
• In case of a short to one of the supply lines, this will trigger the OCP and the amplifier
will be shut down. During restart the window protection will be activated. As a result
the amplifier will not start until 100 ms after the short to the supply lines is removed.
• In case of impedance drop (e.g. due to dynamic behavior of the loudspeaker) the
same protection will be activated. The maximum output current is again limited to 4 A,
but the amplifier will not switch off completely (thus preventing audio holes from
occurring). The result will be a clipping output signal without any artifacts.
8.4.4 Window Protection (WP)
The WP checks the PWM output voltage before switching from Sleep mode to Mute mode
(outputs switching) and is activated:
• During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1
,
VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8932 waits for
open-circuit outputs. Because the check is done before enabling the power stages, no
large currents will flow in the event of a short-circuit.
• When the amplifier is completely shut down due to activation of the OCP because a
short-circuit to one of the supply lines is made, then during restart (after 100 ms) the
window protection will be activated. As a result the amplifier will not start until the
short-circuit to the supply lines is removed.
8.4.5 Supply voltage protection
If the supply voltage drops below 10 V, the UnderVoltage Protection (UVP) circuit is
activated and the system will shut down directly. This switch-off will be silent and without
pop noise. When the supply voltage rises above the threshold level, the system is
restarted again after 100 ms.
If the supply voltage exceeds 36 V the OverVoltage Protection (OVP) circuit is activated
and the power stages will shut down. It is re-enabled as soon as the supply voltage drops
below the threshold level. The system is restarted again after 100 ms.
It should be noted that supply voltages > 40 V may damage the TDA8932. Two conditions
should be distinguished:
1. If the supply voltage is pumped to higher values by the TDA8932 application itself
(see also Section 14.3), the OVP is triggered and the TDA8932 is shut down. The
supply voltage will decrease and the TDA8932 is protected against any overstress.
2. If a supply voltage > 40 V is caused by other or external causes, then the TDA8932
will shut down, but the device can still be damaged since the supply voltage will
remain > 40 V in this case. The OVP protection is not a supply voltage clamp.
An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the
voltage difference between them exceeds a certain level. This level depends on the sum
of both supply voltages. The unbalance threshold levels can be defined as follows:
• LOW-level threshold: VP(th)(ubp)l < 8⁄5 × VHVPREF
• HIGH-level threshold: VP(th)(ubp)h > 8⁄3 × VHVPREF
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
10 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is
within 6 % of its starting value.
Table 6 shows an overview of all protection and the effect on the output signal.
Table 6.
Protection overview
Restart
Protection
When fault is removed
Every 100 ms
OTP
OCP
WP
no
yes
no
yes
yes
no
no
UVP
OVP
UBP
yes
yes
yes
no
no
8.5 Diagnostic input and output
Whenever a protection is triggered, except for TF, pin DIAG is activated to LOW level (see
Table 6). An internal reference supply will pull-up the open-drain DIAG output to
approximately 2.4 V. This internal reference supply can deliver approximately 50 µA.
Pin DIAG refers to pin CGND. The diagnostic output signal during different short
conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the
device into Fault mode.
V
V
o
o
2.4 V
2.4 V
amplifier
restart
no restart
0 V
0 V
≈ 50 ms ≈ 50 ms
short to
shorted load
supply line
001aad759
Fig 5. Diagnostic output for different short-circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and a maximum of flexibility in the application,
the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of
one of the two channels can be inverted, so that the amplifier can operate as a mono BTL
amplifier. The input configuration for a mono BTL application is illustrated in Figure 6.
In SE configuration it is also recommended to connect the two differential inputs in
anti-phase. This has advantages for the current handling of the power supply at low signal
frequencies and minimizes supply pumping (see also Section 14.8).
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
11 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
IN1P
IN1N
OUT1
audio
input
IN2P
IN2N
OUT2
001aad760
Fig 6. Input configuration for mono BTL application
8.7 Output voltage buffers
When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on
in asymmetrical supply configuration. The start-up will be pop free since the device starts
switching when the capacitor on pin HVPREF and the SE capacitors are completely
charged.
Output voltage buffers:
• Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half supply voltage output is disabled when the TDA8932 is used in a
symmetrical supply application.
• Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
• Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF. Pin INREF applies the bias voltage for the inputs.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
12 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
9. Internal circuitry
Table 7.
Internal circuitry
Pin
1
Symbol
VSSD(HW)
VSSD(HW)
VSSD(HW)
VSSD(HW)
Equivalent circuit
1, 16,
17, 32
V
V
DDA
16
17
32
SSA
001aad784
2
IN1P
IN1N
INREF
IN2N
IN2P
V
DDA
3
2 kΩ
± 20 %
12
14
15
2, 15
V/I
48 kΩ
± 20 %
12
HVPREF
48 kΩ
± 20 %
2 kΩ
± 20 %
3, 14
V/I
V
SSA
001aad785
4
DIAG
V
2.4 V
DDA
50 µA
4
5 kΩ
± 20 %
V
V
CGND 001aad786
SSA
5
ENGAGE
4.6 V
DDA
I
= 20 µA
ref
5
226 kΩ
± 20 %
V
SSA
CGND
001aad787
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
13 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
Equivalent circuit
6
POWERUP
V
DDA
6
V
CGND
001aad788
SSA
7
CGND
V
DDA
7
V
SSA
001aad789
8
VDDA
8
V
V
SSA
SSD
001aad790
9
VSSA
V
DDA
9
V
SSD
001aad791
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
14 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
Symbol
Equivalent circuit
10
OSCREF
V
DDA
I
ref
10
V
001aad792
SSA
11
HVPREF
V
DDA
11
V
SSA
001aad793
DDA
13
TEST
V
13
V
SSA
001aad795
18
DREF
V
DD
18
V
SSD
001aad796
19
30
HVP2
HVP1
V
DDA
19, 30
V
001aad797
SSA
20
23
26
29
VDDP2
VSSP2
VSSP1
VDDP1
20, 29
23, 26
001aad798
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
15 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 7.
Internal circuitry …continued
Pin
21
Symbol
BOOT2
BOOT1
Equivalent circuit
21, 28
28
OUT1, OUT2
001aad799
22
27
OUT2
OUT1
V
V
DDP1,
DDP2
22, 27
V
SSP1,
V
SSP2
001aad800
24
25
STAB2
STAB1
V
DDA
24, 25
V
SSP1,
V
SSP2
001aad801
31
OSCIO
DREF
31
V
SSD
001aad802
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
16 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
[1]
VP
Vx
supply voltage
asymmetrical supply
−0.3
+40
V
voltage on pin x
[2]
[3]
[4]
IN1P, IN1N, IN2P, IN2N
OSCREF, OSCIO, TEST
−5
+5
6
V
V
V
VSSD(HW) − 0.3 5
POWERUP, ENGAGE,
DIAG
VCGND − 0.3
[5]
[6]
all other pins
VSS − 0.3
4
VDD + 0.3 V
IORM
repetitive peak output
current
maximum output
current limiting
-
A
Tj
junction temperature
storage temperature
ambient temperature
power dissipation
-
150
+150
+85
5
°C
°C
°C
W
Tstg
Tamb
P
−55
−40
-
[1] VP = VDDP1 − VSSP1 = VDDP2 − VSSP2
.
[2] Measured with respect to pin INREF; Vx < VDD + 0.3 V.
[3] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V.
[4] Measured with respect to pin CGND; Vx < VDD + 0.3 V.
[5] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2.
[6] Current limiting concept.
11. Thermal characteristics
Table 9.
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
Rth(j-a)
thermal resistance from
junction to ambient
free air natural convection
JEDEC test board
[1]
[2]
-
-
-
41
44
-
44
-
K/W
K/W
K/W
2 layer application board
Ψj-lead
thermal characterization
parameter from junction
to lead
30
Ψj-top
thermal characterization
parameter from junction
to top of package
-
-
8
K/W
[1] Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural
convection.
[2] Strongly depends on where you measure on the package.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
17 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
12. Static characteristics
Table 10. Static characteristics
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Supply
VP
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
asymmetrical supply
symmetrical supply
Sleep mode; no load
10
±5
-
22
36
±18
1
V
±11
0.6
40
V
IP
supply current
mA
mA
Iq(tot)
total quiescent current
Operating mode; no load, no
-
80
snubbers and no filter connected
Series resistance output power switches
RDSon
drain-source on-state
resistance
Tj = 25 °C
-
-
150
234
-
-
mΩ
mΩ
Tj = 125 °C
Power-up input: pin POWERUP[1]
VI
input voltage
0
-
-
6.0
20
V
II
input current
VI = 3 V
1
-
µA
V
VIL
LOW-level input voltage
0
2
0.8
6.0
VIH
HIGH-level input voltage
-
V
Engage input: pin ENGAGE[1]
VO
VI
output voltage
4.2
0
4.6
5.0
6.0
40
V
input voltage
-
V
IO
output current
VI = 3 V
-
20
-
µA
V
VIL
LOW-level input voltage
0
0.8
6.0
VIH
HIGH-level input voltage
3
-
V
Diagnostic output: pin DIAG[1]
VO output voltage
protection activated; see Table 6
Operating mode
-
-
0.8
3.3
V
V
2
2.5
Bias voltage for inputs: pin INREF
VO(bias) bias output voltage
with respect to pin VSSA
-
2.1
-
V
Half supply voltage
Pins HVP1 and HVP2
VO
output voltage
half supply voltage to charge SE
capacitor
0.5VP − 0.5VP
0.2
0.5VP +
0.2
V
IO
output current
output voltage
VHVP1 = VO − 1 V;
-
50
-
mA
VHVP2 = VO − 1 V
Pin HVPREF
VO
half supply reference voltage in
Mute mode
0.5VP − 0.5VP
0.2
0.5VP +
0.2
V
V
Reference voltage for internal logic: pin DREF
VO
output voltage
4.5
4.8
5.1
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
18 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 10. Static characteristics …continued
VP = 22 V; fosc = 320 kHz; Tamb = 25 °C; unless otherwise specified.
Symbol
Amplifier outputs: pins OUT1 and OUT2
|VO(offset) output offset voltage
Parameter
Conditions
Min
Typ
Max
Unit
|
SE; with respect to pin HVPREF
Mute mode
-
-
-
-
15
mV
mV
Operating mode
BTL
100
Mute mode
-
-
-
-
20
mV
mV
Operating mode
150
Stabilizer output: pins STAB1 and STAB2
VO output voltage
Mute mode and Operating mode;
with respect to pins VSSP1 and
VSSP2
10
11
12
V
Voltage protection
VP(uvp)
undervoltage protection
supply voltage
8.0
36
-
9.5
10
40
18
-
V
V
V
V
VP(ovp)
overvoltage protection
supply voltage
38.5
VP(th)(ubp)l
VP(th)(ubp)h
low unbalance protection
threshold supply voltage
VHVPREF = 11 V
VHVPREF = 11 V
-
-
high unbalance protection
threshold supply voltage
29
Current protection
IO(ocp) overcurrent protection
output current
Temperature protection
Tact(th_prot) thermal protection activation
current limiting
4
5
-
A
155
140
-
-
160
150
°C
°C
temperature
Tact(th_fold)
thermal foldback activation
temperature
Oscillator reference; pin OSCIO[2]
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
4.0
0
-
-
-
-
-
5
V
V
V
V
VIL
0.8
5
VOH
4.0
0
VOL
0.8
-
Nslave(max)
maximum number of slaves driven by one master
12
[1] Measured with respect to pin CGND.
[2] Measured with respect to pin VSSD(HW)
.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
19 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
13. Dynamic characteristics
Table 11. Switching characteristics
VP = 22 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Internal oscillator
Conditions
Min
Typ
Max
Unit
fosc
oscillator frequency
Rosc = 39 kΩ
-
320
-
-
kHz
kHz
range
300
500
Timing PWM output: pins OUT1 and OUT2
tr
rise time
IO = 0 A
IO = 0 A
IO = 0 A
-
-
-
10
10
80
-
-
-
ns
ns
ns
tf
fall time
tw(min)
minimum pulse width
Table 12. SE characteristics
VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Po(RMS) RMS output power
Conditions
Min
Typ
Max
Unit
[2]
continuous time output power per
channel
RL = 4 Ω; VP = 22 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 8 Ω; VP = 30 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
short time output power per channel
RL = 4 Ω; VP = 29 V
THD+N = 0.5 %
11
-
12
12
15
15
-
-
-
-
W
W
W
W
14
-
11
-
12
12
15
15
-
-
-
-
W
W
W
W
14
-
[2]
[3]
19
23
20
25
-
-
W
W
THD+N = 10 %
THD+N
total harmonic distortion-plus-
noise
Po = 1 W
fi = 1 kHz
-
0.015
0.08
30
0.05
0.10
31
1
%
fi = 6 kHz
-
%
Gv(cl)
|∆Gv|
αcs
closed-loop voltage gain
voltage gain difference
channel separation
Vi = 100 mV; no load
29
-
dB
dB
dB
0.5
Po = 1 W; fi = 1 kHz
Operating mode
fi = 100 Hz
70
80
-
[4]
SVRR
supply voltage ripple rejection
-
60
-
dB
dB
kΩ
µV
µV
fi = 1 kHz
40
70
-
50
-
|Zi|
input impedance
differential
100
100
70
-
[5]
[5]
Vn(o)
noise output voltage
Operating mode; Rs = 0 Ω
Mute mode
150
100
-
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
20 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 12. SE characteristics …continued
VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VO(mute)
mute output voltage
Mute mode; Vi = 1 V (RMS) and
fi = 1 kHz
-
100
-
µV
CMRR
common mode rejection ratio
output power efficiency
Vi(cm) = 1 V (RMS)
Po = 15 W
56
75
-
dB
ηpo
VP = 22 V; RL = 4 Ω
VP = 30 V; RL = 8 Ω
90
91
92
93
-
-
%
%
[1] Rs is the series resistance of inductor of low-pass LC filter in the application.
[2] Output power is measured indirectly; based on RDSon measurement.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] Maximum Vripple = 2 V (p-p); Rs = 0 Ω.
[5] B = 20 Hz to 20 kHz, AES17 brick wall.
Table 13. BTL characteristics
VP = 22 V; RL = 8 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Po(RMS) RMS output power
Conditions
Min
Typ
Max
Unit
[2]
continuous time output power
RL = 4 Ω; VP = 12 V
THD+N = 0.5 %; fi = 1 kHz
THD+N = 0.5 %; fi = 100 Hz
THD+N = 10 %; fi = 1 kHz
THD+N = 10 %; fi = 100 Hz
RL = 8 Ω; VP = 22 V
THD+N = 0.5 %; fi = 1 kHz
THD+N = 0.5 %; fi = 100 Hz
THD+N = 10 %; fi = 1 kHz
THD+N = 10 %; fi = 100 Hz
short time output power
RL = 4 Ω; VP = 15 V
THD+N = 0.5 %
11
-
12
12
15
15
-
-
-
-
W
W
W
W
14
-
23
-
24
24
30
30
-
-
-
-
W
W
W
W
28
-
[2]
19
23
20
25
-
-
W
W
THD+N = 10 %
RL = 8 Ω; VP = 29 V
THD+N = 0.5 %
38
47
40
50
-
-
W
W
THD+N = 10 %
[3]
THD+N
total harmonic distortion-plus-
noise
Po = 1 W
fi = 1 kHz
-
0.04
0.04
36
0.1
0.1
37
%
fi = 6 kHz
-
%
Gv(cl)
closed-loop voltage gain
35
dB
[4]
[4]
SVRR
supply voltage ripple rejection
Operating mode
fi = 100 Hz
-
75
75
80
-
-
-
dB
dB
dB
fi = 1000 Hz
70
-
sleep; fi = 100 Hz
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
21 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Table 13. BTL characteristics …continued
VP = 22 V; RL = 8 Ω; fi = 1 kHz; fosc = 320 kHz; Rs < 0.1 Ω[1]; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
differential
Min
Typ
Max
Unit
|Zi|
input impedance
35
50
-
kΩ
Vn(o)
noise output voltage
Rs = 0 Ω
[5]
[5]
Operating mode
Mute mode
-
-
-
100
70
150
100
-
µV
µV
µV
VO(mute)
mute output voltage
Mute mode; Vi = 1 V (RMS) and
fi = 1 kHz
100
CMRR
common mode rejection ratio
output power efficiency
Vi(cm) = 1 V (RMS)
56
88
90
75
90
92
-
-
-
dB
%
ηpo
Po = 15 W; VP = 12 V and RL = 4 Ω
Po = 30 W; VP = 22 V and RL = 8 Ω
%
[1] Rs is the series resistance of inductor of low-pass LC filter in the application.
[2] Output power is measured indirectly; based on RDSon measurement.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] Maximum Vripple = 2 V (p-p); Rs = 0 Ω.
[5] B = 20 Hz to 20 kHz, AES17 brick wall.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
22 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL
configuration can be estimated using Equation 2 and Equation 3.
SE configuration:
2
RL
× (1 – tw(min) × f osc) × VP
----------------------------------------------------------
RL + RDSon + Rs + RESR
------------------------------------------------------------------------------------------------------------------------------------------
8 × RL
Po(0.5%)
=
(2)
(3)
BTL configuration:
2
RL
-----------------------------------------------------
RL + 2 × (RDSon + Rs)
-------------------------------------------------------------------------------------------------------------------------------------
2 × RL
× (1 – tw(min) × f osc) × VP
Po(0.5%)
=
Where:
VP = supply voltage VDDP1 − VSSP1 [V] or VDDP2 − VSSP2 [V]
RL = load impedance [Ω]
RDSon = on-resistance power switch [Ω]
Rs = series resistance output inductor [Ω]
RESR = equivalent series resistance SE capacitor [Ω]
tw(min) = minimum pulse width [s]; 80 ns typical
fosc = oscillator frequency [Hz]; 320 kHz typical with Rosc = 39 kΩ
The output power Po at THD+N = 10 % can be estimated by:
Po(10%) = 1.25 × Po(0.5%)
(4)
Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at
different load impedances. The output power is calculated with: RDSon = 0.15 Ω (at
Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 4 A (minimum).
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
23 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
001aad768
001aad769
40
40
P
o
(W)
R
L
= 4 Ω
P
(W)
o
R
L
= 4 Ω
30
30
6 Ω
8 Ω
6 Ω
8 Ω
20
10
0
20
10
0
10
20
30
40
10
20
30
40
V
(V)
V
(V)
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
Fig 7. SE output power as a function of supply voltage
001aad770
001aad771
80
80
R
L
= 8 Ω
6 Ω
P
(W)
P
(W)
o
o
R
L
= 8 Ω
60
60
6 Ω
4 Ω
4 Ω
40
20
0
40
20
0
10
20
30
40
10
20
30
40
V
(V)
V (V)
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
Fig 8. BTL output power as a function of supply voltage
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
24 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
14.2 Output current limiting
The peak output current IO(max) is internally limited above a level of 4 A (minimum). During
normal operation the output current should not exceed this threshold level of 4 A
otherwise the output signal is distorted. The peak output current in SE or BTL
configurations can be estimated using Equation 5 and Equation 6.
SE configuration:
0.5 × VP
IO(max)
≤
≤ 4 A
(5)
(6)
----------------------------------------------------------
RL + RDSon + Rs + RESR
BTL configuration:
VP
IO(max)
≤
≤ 4 A
-----------------------------------------------------
RL + 2 × (RDSon + Rs)
Where:
VP = supply voltage VDDP1 − VSSP1 [V] or VDDP2 − VSSP2 [V]
RL = load impedance [Ω]
RDSon = on-resistance power switch [Ω]
Rs = series resistance output inductor [Ω]
RESR = equivalent series resistance SE capacitor [Ω]
Example:
A 4 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V without
running into current limiting. Current limiting (clipping) will avoid audio holes but it causes
a comparable distortion like voltage clipping.
14.3 Speaker configuration and impedance
For a flat frequency response (second-order Butterworth filter) it is necessary to change
the low-pass filter components Llc and Clc according to the speaker configuration and
impedance. Table 14 shows the practical required values.
Table 14. Filter component values
Configuration
RL (Ω)
Llc (µH)
22
Clc (nF)
680
SE
4
6
8
4
6
8
33
470
47
330
BTL
10
1500
1000
680
15
22
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency
response will roll-off with 20 dB per decade below f-3dB (3 dB cut-off frequency).
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
25 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
The 3 dB cut-off frequency is equal to:
1
f –3dB
=
(7)
----------------------------------
2π × RL × Cse
Where:
-3dB = 3 dB cut-off frequency [Hz]
f
RL = load impedance [Ω]
Cse = single-ended capacitance [F]; see Figure 28
Table 15 shows an overview of the required SE capacitor values in case of 60 Hz, 40 Hz
or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values
Impedance (Ω)
Cse (µF)
f-3dB = 60 Hz
680
f-3dB = 40 Hz
1000
f-3dB = 20 Hz
2200
4
6
8
470
680
1500
330
470
1000
14.5 Gain reduction
The gain of the TDA8932 is internally fixed at 30 dB for SE (or 36 dB for BTL). The gain
can be reduced by a resistive voltage divider at the input (see Figure 9).
R1
R2
470 nF
470 nF
100
kΩ
R3
audio in
001aad762
Fig 9. Input configuration for reducing gain
When applying a resistive divider, the total closed-loop gain Gv(tot) can be calculated by
Equation 8 and Equation 9:
REQ
Gv(tot) = Gv(cl) + 20log
(8)
-----------------------------------------
REQ + (R1 + R2)
Where:
Gv(tot) = total closed-loop voltage gain [dB]
Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE [dB]
REQ = equivalent resistance, R3 and Zi [Ω]
R1 = series resistor [Ω]
R2 = series resistor [Ω]
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
26 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
R3 × Zi
REQ
=
(9)
------------------
R3 + Zi
Where:
REQ = equivalent resistance [Ω]
R3 = parallel resistor [Ω]
Zi = internal input impedance
Example:
Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9
results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8932 devices are used in one application it is recommended that all
devices are synchronized running at the same switching frequency to avoid beat tones.
Synchronization can be realized by connecting all OSCIO pins together and configure one
of the TDA8932 devices as master, while the other TDA8932 devices are configured as
slaves (see Figure 10).
A device is configured as master by connecting a resistor between pins OSCREF and
VSSD(HW) setting the carrier frequency. Pin OSCIO of the master is then configured as an
oscillator output for synchronization. The OSCREF pins of the slave devices should be
shorted to VSSD(HW) configuring pin OSCIO as an input.
master
slave
IC1
IC2
TDA8932
TDA8932
OSCREF
OSCIO
OSCIO
OSCREF
V
SSD
C
R
osc
39 kΩ
osc
100 nF
V
SSD
001aad761
Fig 10. Master slave concept in two chip application
14.7 Thermal behavior (printed-circuit board considerations)
The heatsink in the application with the TDA8932 is made with the copper on the
Printed-Circuit Board (PCB). The TDA8932 uses the four corner leads (pins 1, 16, 17 and
32) for heat transfer from the die to the PCB. The thermal foldback will limit the maximum
junction temperature to 140 °C.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
27 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Equation 10 shows the relation between the maximum allowable power dissipation P and
the thermal resistance from junction to ambient.
T j(max) – Tamb
Rth( j – a)
=
(10)
-----------------------------------
P
Where:
Rth(j-a) = thermal resistance from junction to ambient
Tj(max) = maximum junction temperature
Tamb = ambient temperature
P = power dissipation which is determined by the efficiency of the TDA8932
The power dissipation is shown in Figure 20 (SE) and Figure 27 (BTL).
The thermal resistance as a function of the PCB area (35 µm copper) is shown in
Figure 11.
001aae336
80
R
th(j-a)
(K/W)
60
(1)
(2)
40
20
0
2000
4000
6000
8000
10000
2
PCB area (mm )
(1) Single layer FR2 PCB; copper plane at device side (100 % coverage).
(2) Double layer FR4 PCB; copper plane on both sides (100 % coverage).
Fig 11. Thermal resistance as a function of the PCB area
Example 1
• At VP = 30 V and Po = 2 × 15 W into 8 Ω (THD+N = 10 % continuous), the power
dissipation P = 2.3 W at Po = 15 W (see Figure 20).
• Tj(max) = 125 °C and Tamb = 25 °C.
The required thermal resistance Rth(j-a) = 100 / 2.3 = 43 K/W.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
28 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
Example 2
In case of music output power at 25 % of the rated power, the Tj(max) is much lower.
• At VP = 30 V and Po = 2 × (0.25 × 15) = 2 × 3.75 W into 8 Ω, the power dissipation
P = 1.6 W at Po = 3.75 W (see Figure 20)
• Rth(j-a) = 43 K/W
The maximum junction temperature Tj(max) = 25 + 1.6 × 43 = 93.8 °C.
14.8 Pumping effects
When the amplifier is used in a SE configuration, a so-called 'pumping effect' can occur.
During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of
that energy is delivered back to the other supply line (e.g. VSSP1) and visa versa. When
the power supply cannot sink energy, the voltage across the output capacitors of that
power supply will increase.
The voltage increase caused by the pumping effect depends on:
• Speaker impedance
• Supply voltage
• Audio signal frequency
• Value of decoupling capacitors on supply lines
• Source and sink currents of other channels
The pumping effect should not cause a malfunction of either the audio amplifier and/or the
power supply. For instance, this malfunction can be caused by triggering of the
undervoltage or overvoltage protection of the amplifier.
Pumping effects in a SE configuration can be minimized by connecting audio inputs in
anti-phase and change the polarity of one speaker. This is illustrated in Figure 12.
IN1P
OUT1
audio
in1
IN1N
IN2N
OUT2
audio
in2
IN2P
001aad763
Fig 12. SE application for reducing pumping effects
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
29 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
14.9 SE curves measured in reference design
001aad772
001aad773
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
(1)
−1
(1)
−1
10
10
(2)
(3)
(2)
(3)
−2
−2
10
10
−3
−3
10
10
−2
−1
2
−2
−1
2
10
10
1
10
10
10
10
1
10
10
P
(W)
P (W)
o
o
a. VP = 22 V; RL = 2 × 4 Ω
b. VP = 30 V; RL = 2 × 8 Ω
(1) fi = 6 kHz
(2) fi = 100 Hz
(3) fi = 1 kHz
Fig 13. Total harmonic distortion-plus-noise as a function of output power
001aad774
001aad775
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
(1)
(2)
(1)
(2)
−1
−1
10
10
−2
−2
10
10
−3
−3
10
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
a. VP = 22 V; RL = 2 × 4 Ω
b. VP = 30 V; RL = 2 × 8 Ω
(1) Po = 10 W
(2) Po = 1 W
Fig 14. Total harmonic distortion-plus-noise as a function of frequency
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
30 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
001aad776
001aad777
40
0
SVRR
(dB)
G
v
(dB)
−20
30
−40
−60
(1)
(2)
(1)
(2)
20
10
−80
−100
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
Vi = 100 mV (RMS); Ri = 0 Ω; Cse = 1000 µF
(1) VP = 30 V; RL = 2 × 8 Ω
Vripple = 500 mV (RMS) referenced to ground;
Ri = 0 Ω (shorted input)
(1) VP = 30 V; RL = 2 × 8 Ω
(2) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 22 V; RL = 2 × 4 Ω
Fig 15. Gain as a function of frequency
Fig 16. Supply voltage ripple rejection as a function of
frequency
001aad778
001aad779
120
0
α
cs
(2)
(1)
(dB)
S/N
(dB)
−20
80
40
0
−40
−60
(1)
(2)
−80
−100
−2
−1
2
2
3
4
5
10
10
1
10
10
10
10
10
10
10
P
(W)
f (Hz)
i
o
VP = 22 V; Ri = 0 Ω; 20 kHz brick-wall filter AES17
(1) RL = 2 × 4 Ω
Po = 1 W; Chvpref = 47 µF
(1) VP = 22 V; RL = 2 × 4 Ω
(2) VP = 30 V; RL = 2 × 8 Ω
(2) RL = 2 × 8 Ω
Fig 17. Signal-to-noise ratio as a function of output
power
Fig 18. Channel separation as a function of frequency
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
31 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
001aad780
001aad781
100
3.0
(2)
(1)
η
po
(%)
P
(W)
80
2.0
60
40
20
0
(2)
(1)
1.0
0
10
−2
−1
2
0
5
10
15
20
10
1
10
10
P
(W)
P (W)
o
o
(1) VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 30 V; RL = 2 × 8 Ω; fi = 1 kHz
(1) VP = 22 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 30 V; RL = 2 × 8 Ω; fi = 1 kHz
Fig 19. Output power efficiency as a function of output
power
Fig 20. Power dissipation as a function of output power
per channel (two channels driven)
14.10 BTL curves measured in reference design
001aad782
001aad783
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
(1)
−1
−1
10
10
(1)
(2)
(3)
(2)
(3)
−2
−2
10
10
−3
−3
10
10
−2
−1
2
−2
−1
2
10
10
1
10
10
10
10
1
10
10
P
(W)
P (W)
o
o
a. VP = 12 V; RL = 4 Ω
b. VP = 24 V; RL = 8 Ω
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
Fig 21. Total harmonic distortion-plus-noise as a function of output power
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
32 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
001aae114
001aae115
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
−1
−1
10
10
(1)
(2)
−2
−2
(1)
(2)
10
10
−3
−3
10
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
a. VP = 22 V; RL = 4 Ω
b. VP = 22 V; RL = 8 Ω
(1) Po = 10 W
(2) Po = 1 W
Fig 22. Total harmonic distortion-plus-noise as a function of frequency
001aae116
001aae117
40
0
SVRR
(dB)
G
v
(dB)
−20
(2) (1)
30
−40
−60
20
10
(1)
(2)
−80
−100
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
Vi = 100 mV (RMS); Ri = 0 Ω
(1) VP = 12 V; RL = 4 Ω
Vripple = 500 mV (RMS) referenced to ground;
Ri = 0 Ω (shorted input)
(1) RL = 4 Ω
(2) RL = 8 Ω
(2) VP = 24 V; RL = 8 Ω
Fig 23. Gain as a function of frequency
Fig 24. Supply voltage ripple rejection as a function of
frequency
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
33 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
001aae118
120
S/N
(dB)
(2)
(1)
80
40
0
10
−2
−1
2
10
1
10
10
P
(W)
o
Ri = 0 Ω; 20 kHz brick-wall filter AES17
(1) RL = 4 Ω; VP = 15 V
(2) RL = 8 Ω; VP = 29 V
Fig 25. Signal-to-noise ratio as a function of output power
001aae119
001aae120
100
3.0
η
(%)
po
(1)
(2)
P
(W)
80
2.0
60
40
20
0
(2)
(1)
1.0
0
10
−2
−1
2
0
10
20
30
10
1
10
10
P
(W)
P (W)
o
o
(1) VP = 12 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 22 V; RL = 2 × 8 Ω; fi = 1 kHz
(1) VP = 12 V; RL = 2 × 4 Ω; fi = 1 kHz
(2) VP = 22 V; RL = 2 × 8 Ω; fi = 1 kHz
Fig 26. Output power efficiency as a function of output
power
Fig 27. Power dissipation as a function of output power
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
34 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
14.11 Typical application schematics (simplified)
VP
Rvdda
VP
VPA
10 Ω
Cvdda
100 nF
Cvddp
220 µF
(35 V)
GND
V
V
SSD(HW)
SSD(HW)
IN1P
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Cin
OSCIO
HVP1
2
Cin
470 nF
470 nF
IN1N
3
VP
V
DDP1
DIAG
4
Cvddp
Chvp
100 nF
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
Cbo
15
nF
MUTE control
SLEEP control
5
1 MΩ
Cen
470 nF
Llc
6
V
SSP1
7
Rsn
10 Ω
V
DDA
STAB1
STAB2
Cosc
VPA
8
U1
TDA8932
Csn
470 pF
Clc
Cse
V
SSA
100 nF
Rosc
9
Cstab
100 nF
V
SSP2
OSCREF
HVPREF
INREF
TEST
10
11
12
13
14
15
16
39 kΩ
Llc
OUT2
Cbo
15
nF
Chvpref
47 µF (25 V)
Chvp
100 nF
BOOT2
1 MΩ
Rsn
10 Ω
Cinref
100 nF
V
DDP2
VP
Cvddp
100 nF
Csn
470 pF
Clc
Cse
Cin
470 nF
IN2N
HVP2
DREF
Cin
470 nF
IN2P
Cdref
Chvp
V
V
SSD(HW)
SSD(HW)
100 nF
100 nF
001aad764
Fig 28. Typical simplified application diagram for 2 × SE (asymmetrical supply)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
35 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
VP
Rvdda
10 Ω
VP
VPA
Cvdda
100 nF
Cvddp
220 µF
(35 V)
GND
V
V
SSD(HW)
SSD(HW)
IN1P
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Rhvp
470 Ω
Rhvp
470 Ω
Cin
OSCIO
HVP1
2
Cin
1 µF
IN1N
3
VP
1 µF
V
DDP1
DIAG
4
Cvddp
100 nF
Chvp
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
Cbo
15 nF
MUTE
control
5
1 MΩ
Cen
470 nF
Llc
6
V
SSP1
SLEEP
control
7
Rsn
10 Ω
Clc
Clc
V
DDA
STAB1
STAB2
Cosc
VPA
8
U1
TDA8932
Csn
470 pF
V
SSA
100 nF
Rosc
9
Cstab
100 nF
V
SSP2
OSCREF
HVPREF
INREF
TEST
10
11
12
13
14
15
16
39 kΩ
Llc
OUT2
Cbo
15 nF
BOOT2
1 MΩ
Rsn
10 Ω
Chvp
100 nF
Cinref
V
DDP2
100 nF
VP
Cvddp
100 nF
Csn
470 pF
IN2N
HVP2
DREF
IN2P
Cdref
Chvp
V
V
SSD(HW)
SSD(HW)
100 nF
100 nF
001aaf594
Fig 29. Typical simplified application diagram for 1 × BTL (asymmetrical supply)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
36 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
VDD
Rvdda
VDD
GND
VSS
VDDA
VSSA
10 Ω
Cvddp
220 µF
(25 V)
Cvdda
100 nF
Cvssp
220 µF
(25 V)
Cvssa
100 nF
Rvssa
10 Ω
VSS
V
V
SSD(HW)
SSD(HW)
IN1P
VSSA
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSSA
Cin
OSCIO
HVP1
2
Cin
470 nF
470 nF
IN1N
3
VDD
V
DDP1
DIAG
4
Cvddp
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
Cbo
15
nF
MUTE control
SLEEP control
5
1 MΩ
Cen
470 nF
Llc
6
V
SSP1
Rsn
10 Ω
7
VSS
Cvssp
100 nF
V
DDA
STAB1
STAB2
Cosc
Csn
470 pF
VDDA
VSSA
8
U1
TDA8932
Clc
V
SSA
VSS
100 nF
Rosc
9
Cstab
100 nF
Cvssp
V
SSP2
OSCREF
HVPREF
INREF
VSSA
10
11
12
13
14
15
16
39 kΩ
100 nF
Llc
OUT2
Cbo
15
nF
BOOT2
1 MΩ
Rsn
10 Ω
Cinref
100 nF
V
DDP2
TEST
VDD
Cin
Cvddp
100 nF
Csn
470 pF
IN2N
HVP2
DREF
Clc
Cin
470 nF
470 nF
IN2P
Cdref
100 nF
V
V
SSD(HW)
SSD(HW)
VSSA
VSSA
001aaf595
Fig 30. Typical simplified application diagram for 2 × SE (symmetrical supply)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
37 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
VDD
Rvdda
VDD
GND
VSS
VDDA
VSSA
10 Ω
Cvddp
220 µF
(25 V)
Cvdda
100 nF
Cvssp
220 µF
(25 V)
Cvssa
100 nF
Rvssa
10 Ω
VSS
V
V
SSD(HW)
SSD(HW)
IN1P
VSSA
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSSA
Cin
OSCIO
HVP1
2
Cin
1 µF
IN1N
3
VDD
1 µF
V
DDP1
DIAG
4
Cvddp
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
Cbo
15
nF
MUTE
control
5
1 MΩ
Cen
470 nF
Llc
6
V
SSP1
Rsn
10 Ω
SLEEP
control
7
VSS
Cvssp
100 nF
Clc
V
DDA
STAB1
STAB2
Cosc
VDDA
VSSA
8
Csn
470 pF
U1
TDA8932
V
SSA
VSS
100 nF
Rosc
9
Cstab
100 nF
Cvssp
100 nF
V
SSP2
OSCREF
HVPREF
INREF
TEST
Clc
VSSA
10
11
12
13
14
15
16
39 kΩ
Llc
OUT2
Cbo
15
nF
BOOT2
1 MΩ
Rsn
10 Ω
Cinref
V
DDP2
100 nF
VDD
IN2N
HVP2
DREF
Cvddp
100 nF
Csn
470 pF
IN2P
Cdref
100 nF
V
V
SSD(HW)
SSD(HW)
VSSA
VSSA
001aaf596
Fig 31. Typical simplified application diagram for 1 × BTL (symmetrical supply)
15. Test information
15.1 Quality information
The General Quality Specification for Integrated Circuits, SNW-FQ-611 is applicable.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
38 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
16. Package outline
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w
M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches
0.1
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-08-17
03-02-19
SOT287-1
MO-119
Fig 32. Package outline SOT287-1 (SO32)
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
39 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
40 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 33) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17
Table 16. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 17. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 33.
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
41 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 33. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 18. Abbreviations
Acronym
BTL
Description
Bridge Tied Load
DMOS
ESD
PWM
OCP
OTP
OVP
SE
Double diffused Metal Oxide Semiconductor
ElectroStatic Discharge
Pulse Width Modulation
OverCurrent Protection
OverTemperature Protection
OverVoltage Protection
Single Ended
UBP
UVP
TF
UnBalance Protection
UnderVoltage Protection
Thermal Foldback
WP
Window Protection
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
42 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
19. Revision history
Table 19. Revision history
Document ID
TDA8932_2
Release date
20061212
Data sheet status
Change notice
Supersedes
Preliminary data sheet
-
TDA8932_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number TDA8932TW has been deleted
• Two new symbols and parameters in Table 9 “Thermal characteristics”
• Minor adaptions in application diagrams Figure 29, Figure 30 and Figure 31
TDA8932_1
20060511
Preliminary data sheet
-
-
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
43 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
20.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
21. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8932_2
© NXP B.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 02 — 12 December 2006
44 of 45
TDA8932
NXP Semiconductors
Class-D audio amplifier
22. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
17.2
17.3
17.4
Wave and reflow soldering . . . . . . . . . . . . . . . 40
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 40
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 41
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 44
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44
20.1
20.2
20.3
20.4
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
8.3
Functional description . . . . . . . . . . . . . . . . . . . 6
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode selection and interfacing. . . . . . . . . . . . . 6
Pulse width modulation frequency . . . . . . . . . . 7
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . . 9
OverTemperature Protection (OTP) . . . . . . . . . 9
OverCurrent Protection (OCP) . . . . . . . . . . . . . 9
Window Protection (WP). . . . . . . . . . . . . . . . . 10
Supply voltage protection . . . . . . . . . . . . . . . . 10
Diagnostic input and output . . . . . . . . . . . . . . 11
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage buffers. . . . . . . . . . . . . . . . . . . 12
21
22
Contact information . . . . . . . . . . . . . . . . . . . . 44
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
8.7
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics. . . . . . . . . . . . . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 18
Dynamic characteristics . . . . . . . . . . . . . . . . . 20
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 23
Output power estimation. . . . . . . . . . . . . . . . . 23
Output current limiting. . . . . . . . . . . . . . . . . . . 25
Speaker configuration and impedance . . . . . . 25
Single-ended capacitor. . . . . . . . . . . . . . . . . . 25
Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 26
Device synchronization. . . . . . . . . . . . . . . . . . 27
Thermal behavior (printed-circuit board
14.1
14.2
14.3
14.4
14.5
14.6
14.7
considerations) . . . . . . . . . . . . . . . . . . . . . . . . 27
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 29
SE curves measured in reference design. . . . 30
BTL curves measured in reference design. . . 32
Typical application schematics (simplified) . . . 35
14.8
14.9
14.10
14.11
15
15.1
16
Test information. . . . . . . . . . . . . . . . . . . . . . . . 38
Quality information . . . . . . . . . . . . . . . . . . . . . 38
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introduction to soldering . . . . . . . . . . . . . . . . . 40
17
17.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2006
Document identifier: TDA8932_2
相关型号:
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TDA8932T/N1,112
IC 25 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO32, 7.50 MM , PLASTIC, MO-119, SOT287-1, SOP-32, Audio/Video Amplifier
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TDA8932T/N1,118
IC 25 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO32, 7.50 MM , PLASTIC, MO-119, SOT287-1, SOP-32, Audio/Video Amplifier
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