TDA8933BTW/N2,518 [NXP]
TDA8933B - Class D Audio Amplifier TSSOP 32-Pin;
| 型号： | TDA8933BTW/N2,518 |
| 厂家： | 
NXP |
| 描述： | TDA8933B - Class D Audio Amplifier TSSOP 32-Pin 放大器 光电二极管 商用集成电路 |
| 文件： | 总42页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8933B
Class D audio amplifier
Rev. 01 — 23 October 2008
Preliminary data sheet
1. General description
The TDA8933B is a high-efficiency class D amplifier with low power dissipation.
The continuous time output power is 2 × 10 W in a stereo half-bridge application
(RL = 8 Ω) or 1 × 20 W in a mono full-bridge application (RL =16 Ω). Due to the low power
dissipation the device can be used without any external heat sink when playing music.
Due to the implementation of Thermal Foldback (TF) the device remains operating with
considerable music output power without the need for an external heat sink, even for high
supply voltages and/or lower load impedances.
The device has two full differential inputs driving two independent outputs. It can be used
in a mono full-bridge configuration (Bridge-Tied Load (BTL)) or as stereo half-bridge
configuration (Single-Ended (SE)).
2. Features
I Operating voltage from 10 V to 36 V asymmetrical or ±5 V to ±18 V symmetrical
I Mono bridge-tied load (full-bridge) or stereo single-ended (half-bridge) application
I Application without heat sink using thermally enhanced small outline package
I High efficiency and low-power dissipation
I Thermal foldback to avoid audio holes
I Current limiting to avoid audio holes
I Full short circuit proof across load and to supply lines (using advanced current
protection)
I Internal or external oscillator (master-slave setting) that can be switched
I No pop noise
I Full differential inputs
3. Applications
I Flat-panel television sets
I Flat-panel monitor sets
I Multimedia systems
I Wireless speakers
I Mini/micro systems
I Home sound sets
TDA8933B
NXP Semiconductors
Class D audio amplifier
4. Quick reference data
Table 1.
Quick reference data
General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 °C unless specified otherwise
Symbol Parameter
Conditions
Min
Typ
25
Max
36
Unit
V
VP
supply voltage
supply current
asymmetrical supply
Sleep mode
10
-
IP
0.6
40
1.0
50
mA
mA
Iq(tot)
total quiescent
current
Operating mode; no load; no
snubbers or filter connected
-
Stereo SE channel; Rs < 0.1 Ω[1]
Po(RMS) RMS output power continuous time output power per channel[2]
RL = 4 Ω; VP = 17 V
THD+N = 10 %, fi = 1 kHz
RL = 8 Ω; VP = 25 V
7.5
9.3
8.5
-
-
W
W
THD+N = 10 %, fi = 1 kHz
10.3
Mono BTL channel; Rs < 0.1 Ω[1]
Po(RMS) RMS output power continuous time output power[2]
RL = 8 Ω; VP = 17 V
THD+N = 10 %, fi = 1 kHz
15.4
18.9
17.1
20.6
-
-
W
W
RL = 16 Ω; VP = 25 V
THD+N = 10 %, fi = 1 kHz
[1] Rs is the total series resistance of an inductor and an ESR single-ended capacitor in the application.
[2] Output power is measured indirectly, based on RDSon measurement.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8933BTW
HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
2 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
6. Block diagram
OSCREF OSCIO
V
DDA
8
10
31
28
BOOT1
OSCILLATOR
29
2
V
DDP1
IN1P
DRIVER
HIGH
27
26
PWM
MODULATOR
OUT1
V
SSD
CTRL
DRIVER
LOW
V
SSP1
3
IN1N
INREF
IN2P
21
20
22
23
12
15
MANAGER
BOOT2
V
DDP2
DRIVER
HIGH
PWM
MODULATOR
OUT2
CTRL
DRIVER
LOW
V
SSP2
14
4
IN2N
DIAG
PROTECTIONS:
OVP, OCP, OTP,
UVP, TF, WP
V
DDA
25
24
18
STABILIZER 11 V
STAB1
STAB2
DREF
V
SSP1
V
DDA
STABILIZER 11 V
V
7
6
CGND
SSP2
POWERUP
REGULATOR 5 V
V
SSD
MODE
5
ENGAGE
11
30
19
V
V
DDA
HVPREF
HVP1
SSA
TDA8933BTW
13
TEST
HVP2
HALF SUPPLY VOLTAGE
9
1, 16, 17, 32
010aaa455
V
V
SSD(HW)
SSA
Fig 1. Block diagram
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
3 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
7. Pinning information
7.1 Pinning
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
SSD(HW)
SSD(HW)
IN1P
OSCIO
HVP1
3
IN1N
DIAG
4
V
DDP1
5
ENGAGE
POWERUP
CGND
BOOT1
OUT1
6
7
V
SSP1
8
V
STAB1
STAB2
DDA
TDA8933BTW
9
V
SSA
10
11
12
13
14
15
16
OSCREF
HVPREF
INREF
TEST
V
SSP2
OUT2
BOOT2
V
DDP2
IN2N
HVP2
DREF
IN2P
V
V
SSD(HW)
SSD(HW)
010aaa456
Fig 2. Pin configuration diagram (HTSSOP32 package)
7.2 Pin description
Table 3.
Symbol
Pinning description
Pin Description
VSSD(HW)
IN1P
1
negative digital supply voltage and handle wafer connection
positive audio input for channel 1
2
IN1N
3
negative audio input for channel 1
DIAG
4
diagnostic output; open-drain
ENGAGE
POWERUP
CGND
VDDA
5
engage input to switch between Mute mode and Operating mode
power-up input to switch between Sleep mode and Mute mode
control ground; reference for POWERUP, ENGAGE and DIAG
positive analog supply voltage
6
7
8
VSSA
9
negative analog supply voltage
OSCREF
HVPREF
INREF
TEST
10
11
12
13
14
15
16
17
18
input internal oscillator setting (only master setting)
decoupling of internal half supply voltage reference
decoupling for input reference voltage
test signal input; for testing purpose only
IN2N
negative audio input for channel 2
IN2P
positive audio input for channel 2
VSSD(HW)
VSSD(HW)
DREF
negative digital supply voltage and handle wafer connection
negative digital supply voltage and handle wafer connection
decoupling of internal (reference) 5 V regulator for logic supply
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
4 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 3.
Pinning description …continued
Symbol
Pin
Description
HVP2
19
half supply output voltage 2 for charging single-ended capacitor for
channel 2
VDDP2
BOOT2
OUT2
VSSP2
STAB2
STAB1
VSSP1
OUT1
BOOT1
VDDP1
HVP1
20
21
22
23
24
25
26
27
28
29
30
positive power supply voltage for channel 2
bootstrap high-side driver channel 2
Pulse Width Modulated (PWM) output channel 2
negative power supply voltage for channel 2
decoupling of internal 11 V regulator for channel 2 drivers
decoupling of internal 11 V regulator for channel 1 drivers
negative power supply voltage for channel 1
PWM output channel 1
bootstrap high-side driver for channel 1
positive power supply voltage for channel 1
half supply output voltage 1 for charging single-ended capacitor for
channel 1
OSCIO
31
oscillator input in slave configuration or oscillator output in master
configuration
VSSD(HW)
32
-
negative digital supply voltage and handle wafer connection
Exposed die
pad[1]
[1] The exposed die pad has to be connected to VSSD(HW)
.
8. Functional description
8.1 General
The TDA8933B is a mono full-bridge or stereo half-bridge audio power amplifier using
class D technology. The audio input signal is converted into a PWM signal via an analog
input stage and a PWM modulator. To enable the output power Diffusion Metal Oxide
Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to a
control and handshake block and driver circuits for both the high side and low side. A
2nd-order low-pass filter in the application converts the PWM signal to an analog audio
signal across the loudspeakers.
The TDA8933B contains two independent half bridges with full differential input stages.
The loudspeakers can be connected in the following configurations:
• Mono full-bridge: Bridge-Tied Load (BTL)
• Stereo half-bridge: Single-Ended (SE)
The TDA8933B contains circuits common to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. The following
protections are built-in: thermal foldback and overtemperature, current and voltage
protections.
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
5 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
8.2 Mode selection and interfacing
The TDA8933B can be switched to one of four operating modes using pins POWERUP
and ENGAGE:
• Sleep mode: with low supply current.
• Mute mode: the amplifiers are switching to idle (50 % duty cycle), but the audio signal
at the output is suppressed by disabling the Vl-converter input stages. The capacitors
on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical
supply only)
• Operating mode: the amplifiers are fully operational with an output signal
• Fault mode
Both pins POWERUP and ENGAGE refer to pin CGND.
Table 4 shows the different modes as a function of the voltages on the POWERUP and
ENGAGE pins.
Table 4.
Mode
Mode selection for the TDA8933B
Pin
POWERUP[1]
ENGAGE[1]
< 0.8 V
DIAG
Sleep
< 0.8 V
undefined
> 2 V
Mute
2 V to 6 V
2 V to 6 V
2 V to 6 V
< 0.8 V
Operating
Fault
2.4 V to 6 V
undefined
> 2 V
< 0.8 V
[1] When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must
never exceed the supply voltage (VDDA, VDDP1 or VDDP2).
If the transition between Mute mode and Operating mode is controlled via a time constant,
the start-up will be pop-free since the DC output offset voltage is applied gradually to the
output. The bias current setting of the V/I-converters is related to the voltage on pin
ENGAGE.
• Mute mode: the bias current setting of the V/I-converters is zero (V/I-converters
disabled).
• Operating mode: the bias current is at maximum.
The time constant required to apply the DC output offset voltage gradually between Mute
mode and Operating mode can be generated by applying a capacitor on pin ENGAGE.
The value of the capacitor on pin ENGAGE should be 470 nF.
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
6 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
V
P
POWERUP
DREF
OSCIO
HVPREF
HVP1, HVP2
2.0 V (typical)
1.2 V (typical)
≤ 0.8 V
ENGAGE
OUT1, OUT2
AUDIO
AUDIO
AUDIO
PWM
PWM
PWM
DIAG
operating
mute
operating
fault
operating
sleep
010aaa457
Fig 3. Start-up sequence
8.3 Pulse Width Modulation (PWM) frequency
The output signal of the amplifier is a PWM signal with a carrier frequency of
approximately 320 kHz. Using a 2nd-order low-pass filter in the application results in an
analog audio signal across the loudspeaker. The PWM switching frequency can be set by
an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier
frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ,
the carrier frequency is set to a typical value of 320 kHz (see Figure 4).
If two or more TDA8933B devices are used in the same audio application, it is
recommended to synchronize the switching frequency of all devices. See Section 14.6 for
more information.
The value of the resistor also sets the frequency of the carrier and can be calculated with
Equation 1:
12.45x109
f osc
=
(1)
------------------------
Rosc
Where:
fosc = oscillator frequency (Hz)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
7 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Rosc = oscillator resistor (Ω) (on pin OSCREF)
010aaa531
550
f
osc
(kHz)
450
350
250
25
30
35
40
45
R
osc
(kΩ)
Fig 4. Oscillation frequency as a function of Rosc
Table 5 summarizes how to configure the TDA8933B in master or slave configuration.
For device synchronization see Section 14.6.
Table 5.
Master or slave configuration
Configuration
Pin
OSCREF
OSCIO
output
input
Master
Slave
Rosc > 25 kΩ to VSSD(HW)
Rosc = 0 Ω; shorted to VSSD(HW)
8.4 Protections
The following protections are implemented in the TDA8933B:
• Thermal Foldback (TF)
• OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• Window Protection (WP)
• Supply voltage protections
– UnderVoltage Protection (UVP)
– OverVoltage Protection (OVP)
– UnBalance Protection (UBP)
• Electro Static Discharge (ESD)
The behavior of the device under the different fault conditions differs according to the
protection activated and is described in the following sections.
8.4.1 Thermal Foldback (FT)
If the junction temperature of the TDA8933B exceeds the threshold level (Tj > 140 °C), the
gain of the amplifier is decreased gradually to a level where the combination of
dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a
junction temperature of around the threshold level.
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
8 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
This means that the device will not switch off completely, but remains operational at lower
output power levels. With music output signals, this feature enables high peak output
powers while still operating without any external heat sink other than the copper area on
the Printed-Circuit Board (PCB).
If the junction temperature still increases due to external causes the OTP shuts down the
amplifier completely.
8.4.2 OverTemperature Protection (OTP)
If the junction temperature Tj > 155 °C the power stage will shut down immediately.
8.4.3 OverCurrent Protection (OCP)
The OCP can distinguish between an impedance drop of the loudspeaker and a
low-ohmic short circuit.
If an impedance drop causes the output current to exceed 2 A, e.g. due to dynamic
behavior of the loudspeaker, the amplifier will start limiting the current above 2 A.
Therefore the current limiting feature will avoid audio interruption (audio holes) due to a
loudspeaker impedance drop.
If a fault condition causes the output current to exceed 2 A, like a short circuit between the
loudspeaker terminals or from the loudspeaker terminal to the supply lines or ground, the
amplifier is switched off and a timer of 100 ms is started. The DIAG is set low for the first
50 ms of the timer. The timer will keep the power stage disabled for at least 100 ms.
Every 100 ms the amplifier will try to restart as long as the short circuit between the
loudspeaker terminals remains. The average power dissipation in the TDA8933B will be
low because the short circuit current will flow only during a very short time every 100 ms.
If a short circuit occurs between a loudspeaker terminal and the supply lines or ground,
the activated WP will keep the power stage disabled (no restart every 100 ms). Restart
will take place after removing this short.
8.4.4 Window Protection (WP)
The window protection protects the amplifier against the following fault conditions:
• During the start-up sequence, when pin POWERUP is switched from Sleep mode to
Mute mode. In the event of a short circuit at one of the output terminals to VDDP1
,
VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8933B waits
for open circuit outputs. Because the check is done before enabling the power stages
no large currents will flow in the event of a short circuit.
• When the amplifier is shut down completely due to activation of the OCP or because
of a short circuit to one of the supply lines, then during restart (i.e. after 100 ms) the
window protection will be activated. As a result the amplifier will not start up until the
short circuit to the supply lines has been removed.
8.4.5 Supply voltage protection
If the supply voltage drops below 10 V the UnderVoltage Protection (UVP) circuit is
activated and the system will shut down directly. This switch-off will be silent and without
pop noise. When the supply voltage rises above the threshold level the power stage is
restarted after 100 ms.
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
9 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
If the supply voltage exceeds 36 V the OVP circuit is activated and the power stages will
shut down. It is enabled again as soon as the supply voltage drops below the threshold
level. The power stage is restarted after 100 ms.
Supply voltages > 40 V may damage the TDA8933B. Two conditions should be
distinguished here:
• If the supply voltage is pumped to higher values by the TDA8933B application itself
(see also Section 14.8), the OVP is triggered and the TDA8933B is shut down. The
supply voltage will decrease and the TDA8933B is thus protected against any
overstress.
• If a supply voltage > 40 V is caused by other or by external causes the TDA8933B will
shut down, but the device can still be damaged since the supply voltage in this case
will remain > 40 V. The OVP protection is not a supply clamp.
An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage VDDA with the negative analog supply voltage VSSA and is triggered if the
difference between them exceeds a certain level. This level depends on the sum of both
supply voltages. The UBP threshold levels can be defined as follows:
• LOW-level threshold: VP(th)(ubp)l < 8/5 × VHVPREF
• HIGH-level threshold: VP(th)(ubp)h > 8/3 × VHVPREF
In a symmetrical supply the UBP is released when the unbalance of the supply voltage is
within 6 % of its starting value.
Table 6 shows an overview of all protections and their effect on the output signal.
Table 6.
Overview of protections for the TDA8933B
Protection
Restart
When fault is removed
Every 100 ms
OTP
OCP
WP
no
yes
no
yes
yes
no
no
UVP
OVP
UBP
yes
yes
yes
no
no
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
10 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
8.5 Diagnostic input and output
Except for TF, whenever one of the protections is triggered pin DIAG is activated to LOW
level (see Table 6). An internal current source will pull up the open-drain DIAG output to
approximately 2.5 V. This current source can deliver approximately 50 µA. The DIAG pin
refers to pin CGND. The diagnostic output signal during different short circuit conditions is
illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the device into
Fault mode.
V
V
o
o
2.4 V
2.4 V
amplifier
restart
no restart
0 V
0 V
≈ 50 ms ≈ 50 ms
short to
shorted load
supply line
001aad759
Fig 5. Diagnostic output for different short circuit conditions
8.6 Differential inputs
For a high common-mode rejection ratio and for maximum flexibility in the application the
audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of
the two channels can be inverted so that the amplifier can then operate as a mono BTL
amplifier. The input configuration for a mono BTL application is illustrated in Figure 6.
In the SE configuration it is also recommended to connect the two differential inputs in
anti-phase. This has advantages for the current handling of the power supply at low signal
frequencies and minimizes supply pumping (see also Section 14.8).
IN1P
OUT1
IN1N
audio
input
IN2P
OUT2
IN2N
001aad760
Fig 6. Input configuration for a mono BTL application
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
11 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
8.7 Output voltage buffers
When pin POWERUP is set HIGH the half-supply output voltage buffers are switched on
in asymmetrical configuration. The start-up will then be pop-free because the device
starts switching when the capacitor on pin HVPREF and the SE capacitors are completely
charged.
Output voltage buffer pins:
• Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its
value. The half-supply voltage output is disabled when the TDA8933B is used in a
symmetrical supply application.
• Pin HVPREF: This output voltage reference buffer charges the capacitor on pin
HVPREF.
• Pin INREF: This output voltage reference buffer charges the input reference capacitor
on pin INREF, which applies the bias voltage for the inputs.
9. Internal circuitry
Table 7.
Internal circuitry
Symbol
Pin
1
Equivalent circuit
VSSD(HW)
1, 16,
17, 32
V
V
DDA
16
17
32
SSA
001aad784
2
IN1P
IN1N
INREF
IN2N
IN2P
V
DDA
3
2 kΩ
± 20 %
12
14
15
2, 15
V/I
48 kΩ
± 20 %
12
HVPREF
48 kΩ
± 20 %
2 kΩ
± 20 %
3, 14
V/I
V
SSA
001aad785
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
12 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 7.
Internal circuitry
Symbol
Pin
Equivalent circuit
4
DIAG
V
2.5 V
DDA
50 µA
500 Ω
± 20 %
4
100 kΩ
± 20 %
V
V
CGND
SSA
001aaf607
5
ENGAGE
2.8 V
DDA
I
= 50 µA
ref
2 kΩ
± 20 %
5
100 kΩ
± 20 %
V
CGND
SSA
001aaf608
6
POWERUP
V
DDA
6
V
CGND
001aad788
SSA
7
CGND
V
DDA
7
V
SSA
001aad789
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
13 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 7.
Internal circuitry
Symbol
Pin
Equivalent circuit
8
VDDA
8
V
V
SSA
SSD
001aad790
9
VSSA
V
DDA
9
V
SSD
001aad791
10
OSCREF
V
DDA
I
ref
10
V
001aad792
SSA
11
HVPREF
V
DDA
11
V
SSA
001aaf604
13
TEST
V
V
DDA
13
SSA
001aad795
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
14 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 7.
Internal circuitry
Symbol
Pin
Equivalent circuit
18
DREF
V
DD
18
V
SSD
001aag025
19
30
HVP2
HVP1
V
DDA
19, 30
V
001aag026
SSA
20
23
26
29
VDDP2
VSSP2
VSSP1
VDDP1
20, 29
23, 26
001aad798
21
28
BOOT2
BOOT1
21, 28
OUT1, OUT2
001aad799
22
27
OUT2
OUT1
V
V
DDP1,
DDP2
22, 27
V
SSP1,
V
SSP2
001aag027
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
15 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 7.
Internal circuitry
Symbol
Pin
24
Equivalent circuit
STAB2
V
DDA
25
STAB1
24, 25
V
SSP1,
V
SSP2
001aag028
31
OSCIO
DREF
31
V
SSD
001aag029
10. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VP
supply voltage
asymmetrical
supply[1]
−0.3
+40.1
V
Vx
voltage on pin x
[2]
[3]
[4]
IN1P, IN1N, IN2P, IN2N
OSCREF, OSCIO, TEST
−5
+5
5
V
V
V
VSSD(HW) − 0.3
POWERUP, ENGAGE,
DIAG
VCGND − 0.3
6
[5]
[6]
all other pins
VSS − 0.3
2
VDD + 0.3
-
V
A
IORM
repetitive peak output
current
maximum output
current limiting
Tj
junction temperature
storage temperature
ambient temperature
power dissipation
-
150
+150
+85
5
°C
°C
°C
W
V
Tstg
Tamb
P
−55
−40
-
[7]
[8]
Vesd
electrostatic discharge
voltage
human body
model
−2000
+2000
machine model
−200
+200
V
[1] VP = VDDP1 − VSSP1 = VDDP2 − VSSP2
[2] Measured with respect to pin INREF; Vx < VDD + 0.3 V.
[3] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V.
[4] Measured with respect to pin CGND; Vx < VDD + 0.3 V.
[5] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2
.
[6] Current limiting concept.
[7] Human Body Model (HBM); Rs = 1500 Ω; C = 100 pF. For pins 2, 3, 11, 14 and 15 Vesd = 1800V.
TDA8933B_1
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Preliminary data sheet
Rev. 01 — 23 October 2008
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TDA8933B
NXP Semiconductors
Class D audio amplifier
[8] Machine Model (MM); Rs = 0 Ω; C = 200 pF; L = 0.75 µH.
11. Thermal characteristics
Table 9.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
junction to ambient
free air natural convection
JEDEC test board
[1]
[2]
[3]
-
-
-
47
48
30
50
-
K/W
K/W
K/W
Two-layer application board
Three-layer application
board
-
Ψj-lead
thermal characterization
parameter from junction to
lead
-
-
-
-
30
2
K/W
K/W
K/W
[4]
Ψj-top
thermal characterization
parameter from junction to
top of package
-
Rth(j-c)
thermal resistance from
junction to case
free-air natural convection
4.0
-
[1] Measured on a JEDEC high K-factor test board (standard EIA/JESO 51-7) in free air with natural convection.
[2] Measured on a two-layer application board (55 mm × 40 mm), 35 µm copper, FR4 base material in free air with natural convection.
[3] Measured on a three-layer application board (70 mm × 50 mm), 35 µm copper, FR4 base material in free air with natural convection.
[4] Strongly dependent on where the measurement is taken on the package.
12. Static characteristics
Table 10. Characteristics
VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise.
Symbol
Supply
VP
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
asymmetrical supply
symmetrical supply
Sleep mode
10
±5
-
25
36
V
±12.5
0.6
40
±18
1.0
50
V
IP
mA
mA
Iq(tot)
total quiescent current Operating mode; no load,
no snubbers or filter
-
connected
Series resistance output switches
RDSon drain-source on-state Tj = 25 °C
-
-
380
545
-
-
mΩ
mΩ
resistance
Tj = 125 °C
Power-up input: pin POWERUP[1]
VI
II
input voltage
input current
0
-
-
6.0
20
V
VI = 3 V
1
-
µA
V
VIL
LOW-level input
voltage
0
0.8
VIH
HIGH-level input
voltage
2
-
6.0
V
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
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TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 10. Characteristics …continued
VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Engage input: pin ENGAGE[1]
VO
VI
output voltage
input voltage
output current
2.4
0
2.8
-
3.1
6.0
60
V
V
IO
VI = 3 V
-
50
-
µA
V
VIL
LOW-level input
voltage
0
0.8
VIH
HIGH-level input
voltage
2.4
-
6.0
V
Diagnostic output: pin DIAG[1]
VO output voltage
protection activated; see
Table 6
-
-
0.8
3.3
V
V
Operating mode
2
2.5
Bias voltage for inputs: pin INREF
VO(bias) bias output voltage
Reference to VSSA
-
2.1
-
V
Half-supply voltage
Pins HVP1 and HVP2
VO
output voltage
half-supply voltage to
charge SE capacitor
0.5VP − 0.2 V 0.5VP
50
0.5VP + 0.2 V V
IO
output current
output voltage
VHVP1 = VHVP2 = VO − 1 V
-
-
mA
Pin HVPREF
VO
half-supply reference
voltage in Mute mode
0.5VP − 0.2 V 0.5VP
0.5VP + 0.2 V V
Reference voltage for internal logic: pin DREF
VO output voltage reference to VSSA
Amplifier outputs: pins OUT1 and OUT2
4.5
4.8
5.1
V
VO(offset)
output offset voltage
SE; with respect to HVPREF
Mute mode
-
-
-
-
15
mV
mV
Operating mode
BTL
100
Mute mode
-
-
-
-
20
mV
mV
Operating mode
150
Stabilizer output: pins STAB1, STAB2
VO output voltage
Mute mode and
Operating mode; with
respect to pins VSSP1 and
VSSP2
10
11
12
V
Voltage protections
VP(uvp) undervoltage
8.0
9.5
9.9
40
V
V
protection supply
voltage
VP(ovp)
overvoltage protection
supply voltage
36.1
38.5
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
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TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 10. Characteristics …continued
VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VP(th)(ubp)l
low unbalance
VP = 22 V;
-
-
18
V
protection threshold
supply voltage
VHVPREF = 11 V
VP(th)(ubp)h
high unbalance
protection threshold
supply voltage
VP = 22 V;
HVPREF = 11 V
29
-
-
-
V
A
V
Current protections
IO(ocp)
overcurrent protection current limiting
output current
2.0
2.5
Temperature protection
Tact(th_prot) thermal protection
155
140
-
-
160
150
°C
°C
activation temperature
Tact(th_fold)
thermal foldback
activation temperature
Oscillator reference: pin OSCIO[2]
VIH
HIGH-level input
voltage
4.0
0
-
-
-
-
-
5.0
0.8
5.0
0.8
-
V
V
V
V
-
VIL
LOW-level input
voltage
VOH
HIGH-level output
voltage
4.0
0
VOL
LOW-level output
voltage
Nslave(max)
maximum number of
slaves
driven by one master
12
[1] Measured with respect to pin CGND.
[2] Measured with respect to pin VSSD(HW)
.
13. Dynamic characteristics
Table 11. Switching characteristics
VP = 25 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Internal oscillator
fosc oscillator frequency
Parameter
Conditions
Min
Typ
Max
Unit
Rosc = 39 kΩ
-
320
-
-
kHz
kHz
range
300
500
Timing PWM output: pins OUT1 and OUT2
tr
rise time
IO = 0 A
IO = 0 A
IO = 0 A
-
-
-
10
10
80
-
-
-
ns
ns
ns
tf
fall time
tw(min)
minimum pulse width
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
19 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 12. SE characteristics
VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [1] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Po(RMS)
RMS output power
continuous time output power per channel[2]
RL = 4 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 8 Ω; VP = 25 V
5.9
-
6.8
6.8
8.5
8.5
-
-
-
-
W
W
W
W
7.5
-
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
Po = 1 W
7.3
-
8.2
-
-
-
-
W
W
W
W
8.2
9.3
-
10.3
10.3
[3]
THD+N
total harmonic
distortion-plus-noise
fi = 1 kHz
-
0.014
0.05
30
0.1
0.1
31
1
%
fi = 6 kHz
-
%
Gv(cl)
|∆GV|
αcs
closed-loop voltage gain
voltage gain difference
channel separation
Vi =100 mV; no load
29
-
dB
dB
dB
0.5
Po = 1 W; fi = 1 kHz
Operating mode
fi = 100 Hz
70
80
-
[4]
SVRR
supply voltage ripple
rejection
-
60
-
dB
dB
kΩ
µV
µV
µV
dB
fi = 1 kHz
40
70
-
50
-
|Zi|
input impedance
differential
100
100
70
-
[5]
[5]
Vn(o)
output noise voltage
Operating mode; Ri = 0 Ω
Mute mode
150
-
100
VO(mute)
CMRR
mute output voltage
Mute mode; Vi = 1 V (RMS)
Vi(cm) = 1 V (RMS)
-
100
75
-
-
common mode rejection
ratio
-
ηpo
output power efficiency
VP = 17 V; RL = 4 Ω;
Po = 8 W/channel
86
89
89
92
-
-
%
%
VP = 25 V; RL = 8 Ω;
Po = 10 W/channel
[1] RS is the total series resistance of an inductor and a ESR single ended capacitor in the application.
[2] Output power is measured indirectly; based on RDSon measurement.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] Vripple = 2 V (p-p); Ri = 0 Ω.
[5] B = 20 Hz to 20 kHz, AES17 brick wall.
TDA8933B_1
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Preliminary data sheet
Rev. 01 — 23 October 2008
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TDA8933B
NXP Semiconductors
Class D audio amplifier
Table 13. BTL characteristics
VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [1] and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Po(RMS)
RMS output power
continuous time output power[2]
RL = 8 Ω; VP = 17 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
RL = 16 Ω; VP = 25 V
THD+N = 0.5 %, fi = 1 kHz
THD+N = 0.5 %, fi = 100 Hz
THD+N = 10 %, fi = 1 kHz
THD+N = 10 %, fi = 100 Hz
Po = 1 W
11.9
13.7
13.7
17.1
17.1
-
-
-
-
W
W
W
W
-
15.4
-
14.9
16.5
16.5
20.6
20.6
-
-
-
-
W
W
W
W
-
18.9
-
[3]
THD+N
total harmonic
distortion-plus-noise
fi = 1 kHz
-
0.01
0.04
36
0.1
0.1
37
-
%
fi = 6 kHz
-
%
Gv(cl)
|Zi|
closed-loop voltage gain
input impedance
35
35
dB
kΩ
differential
50
Vn(o)
output noise voltage
Ri = 0 Ω
[4]
[4]
Operating mode
Mute mode
-
-
-
-
100
70
150
µV
µV
µV
dB
100
VO(mute)
CMRR
mute output voltage
Mute mode; Vi = 1 V (RMS)
Vi(cm) = 1 V (RMS)
100
75
-
-
common mode rejection
ratio
[5]
ηpo
output power efficiency
Po = 17 W; VP = 17 V; RL = 8 Ω
Po = 21 W; VP = 25 V; RL = 16 Ω
89
92
91
94
-
-
%
%
[1] RS is the total series resistance of an inductor and a ESR single ended capacitor in the application.
[2] Output power is measured indirectly; based on RDSon measurement.
[3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall.
[4] B = 22 Hz to 20 kHz, AES17 brick wall.
2 Po
[5] η po
=
-----------------------
2 Po + P
14. Application information
14.1 Output power estimation
The output power Po at THD+N = 0.5 %, just before clipping, for the SE and the BTL
configurations can be estimated using Equation 2 and Equation 3.
TDA8933B_1
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Preliminary data sheet
Rev. 01 — 23 October 2008
21 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
SE configuration:
2
RL
----------------------------------------------------------
RL + RDSon + Rs + RESR
------------------------------------------------------------------------------------------------------------------------------------------
8 × RL
× (1 – tw(min) × f osc) × VP
Po(0.5%)
=
(2)
(3)
BTL configuration:
2
RL
------------------------------------------------------
RL + 2 × (RDSon + Rs )
--------------------------------------------------------------------------------------------------------------------------------------
2 × RL
× (1 – tw(min) × f osc) × VP
Po(0.5%)
=
Where:
• VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V)
• RL = load resistance (Ω)
• RDSon = drain-source on-state resistance (Ω)
• Rs = series resistance output inductor (Ω)
• RESR = Equivalent Series Resistance SE capacitance (Ω)
• tw(min) = minimum pulse width(s); 80 ns typical
• fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ
The output power Po at THD+N = 10 % can be estimated by:
Po(10%) = 1.25 × Po(0.5%)
(4)
Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and
THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at
different load impedances. The output power is calculated with: RDSon = 0.38 Ω (at
Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 2 A (minimum).
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
22 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa499
(3)
010aaa500
(3)
20
20
P
(10 %)
(W/channel)
P
(0.5 %)
(W/channel)
o
o
16
16
(2)
(2)
12
8
12
8
(1)
(1)
4
4
0
0
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
V
V
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) RL = 4 Ω
(2) RL = 6 Ω
(3) RL = 8 Ω
When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP
details.
Fig 7. SE output power as a function of supply voltage
010aaa501
(3)
010aaa502
(3)
40
40
P
(0.5 %)
(W)
P
(10 %)
(W)
o
o
30
20
10
0
30
20
10
0
(2)
(2)
(1)
(1)
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
V
V
P
P
a. THD+N = 0.5 %
b. THD+N = 10 %
(1) RL = 6 Ω
(2) RL = 8 Ω
(3) RL = 16 Ω
When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP
details.
Fig 8. BTL output power as a function of supply voltage
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
23 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
14.2 Output current limitation
The peak output current IO(max) is internally limited to a minimum value of 2 A. During
normal operation the output current should not exceed this threshold level, otherwise the
signal will be distorted. The peak output current in SE or BTL configurations can be
calculated using Equation 5 and Equation 6.
SE configuration:
0.5 × VP
IO(max)
≤
≤ 2A
(5)
(6)
----------------------------------------------------------
RL + RDSon + Rs + RESR
BTL configuration:
VP
IO(max)
≤
≤ 2A
-----------------------------------------------------
RL + 2 × (RDSon + Rs)
Where:
• VP = supply voltage VDDP1 − VSSP1 (V) or VDDP2 − VSSP2 (V)
• RL = load resistance (Ω)
• RDSon = drain-source on-state resistance (Ω)
• Rs = series resistance output inductor (Ω)
• RESR = Equivalent Series Resistance SE capacitance (Ω)
Example:
An 8 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V
without running into current limiting. Current limiting (clipping) will avoid audio holes but
produces a similar distortion to voltage clipping.
14.3 Speaker configuration and impedance
For a flat frequency response (second-order Butterworth filter with an output frequency of
40 kHz) it is necessary to change the low-pass filter components LLC and CLC according
to the speaker configuration and impedance. Table 14 shows the values required in
practice.
Table 14. Filter component values
Configuration
RL (Ω)
LLC (µH)
CLC (nF)
680
SE
4
22
33
47
22
47
6
470
8
330
BTL
8
680
16
330
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
24 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
14.4 Single-ended capacitor
The SE capacitor forms a high-pass filter with the speaker impedance. This means that
the frequency response will roll off with 20 dB per decade below f−3dB and a cut-off
frequency of 3 dB.
The 3 dB cut-off frequency is equal to:
1
f –3dB
=
(7)
-----------------------------------
2π × RL × CSE
Where:
• f−3dB = 3 dB cut-off frequency (Hz)
• RL = load resistance (W)
• CSE = single-ended capacitance (F); see Figure 32
Table 15 shows an overview of the required SE capacitor values in the case of a 60 Hz,
40 Hz or 20 Hz 3 dB cut-off frequency.
Table 15. SE capacitor values
Impedance (Ω)
CSE (µF)
−3dB = 60 Hz
f
f
−3dB = 40 Hz
f−3dB = 20 Hz
4
6
8
680
470
330
1000
680
2200
1500
1000
470
14.5 Gain reduction
The gain of the TDA8933B is internally fixed at 30 dB for SE and 36 dB for BTL. The gain
can be reduced by a resistive voltage divider at the input (see Figure 9).
R1
R2
470 nF
470 nF
100
kΩ
R3
audio in
010aaa137
Fig 9. Input configuration for reducing gain
When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using
Equation 8 and Equation 9:
REQ
Gv(tot) = Gv(cl) + 20log
(8)
-----------------------------------------
REQ + (R1 + R2)
Where:
• Gv(tot) = total voltage gain (dB)
• Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB)
• REQ = equivalent resistance, R3 and Zi (Ω)
TDA8933B_1
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Preliminary data sheet
Rev. 01 — 23 October 2008
25 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
• R1 = series resistors (Ω)
• R2 = series resistors (Ω)
R3 × Zi
REQ
=
(9)
------------------
R3 + Zi
Where:
• REQ = equivalent resistance (Ω)
• R3 = parallel resistor (Ω)
• Zi = internal input impedance (Ω)
Example:
Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9
results in a gain of Gv(tot) = 26.3 dB.
14.6 Device synchronization
If two or more TDA8933B devices are used in one application it is recommended that all
the devices are synchronized at the same switching frequency to avoid beat tones. This
can be done by connecting all OSCIO pins together and configuring one of the devices as
master while the others are configured as slaves (see Figure 10).
A device is configured as master when a resistor Rosc is connected between pin OSCREF
and pin VSSD(HW), thus setting the carrier frequency. Pin OSCIO of the master is then
configured as an oscillator output for synchronization. The OSCREF pins of the slave
devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input.
master
slave
IC1
IC2
TDA8933B
TDA8933B
V
V
SSD(HW) OSCREF
OSCREF SSD(HW) OSCIO
OSCIO
C
R
osc
39 kΩ
osc
100 nF
010aaa138
Fig 10. Master/slave concept in a two-chip application
TDA8933B_1
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Preliminary data sheet
Rev. 01 — 23 October 2008
26 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
14.7 Thermal behavior (PCB considerations)
The TDA8933B is available in a thermally enhanced HTSSOP32 (SOT549-1) package for
reflow soldering.
The HTSSOP32 package has an exposed die pad that reduces significantly the overall
Rth(j-a). Therefore it is required to solder the exposed die pad (at VSSD level) to a copper
plane for cooling. A low thermal-resistance can be achieved when using a multilayer PCB
with sufficient space for two or three thermal planes. Increasing the area of the thermal
plane, the number of planes or the copper thickness can reduce further the thermal
resistance Rth(j-a) of both packages.
Find below the typical thermal resistance (free air and natural convection) of two practical
PCB implementations:
• Rth(j-a) = 48 K/W for a small two-layer application board (55 mm × 40 mm, µm copper,
FR4 base material).
• Rth(j-a) = 30 K/W for a three-layer application board (70 mm × 50 mm, 35 µm copper,
FR4 base material).
Equation 10 shows the relation between the maximum allowable power dissipation P and
the thermal resistance from junction to ambient.
T j(max) – Tamb
Rth( j – a)
=
(10)
-----------------------------------
P
Where:
• Rth(j-a) = thermal resistance from junction to ambient (K/W)
• Tj(max) = maximum junction temperature (°C)
• Tamb = ambient temperature (°C)
• P = power dissipation, which is determined by the efficiency of the TDA8933B
The power dissipation is shown in Figure 19 (SE) and Figure 27 (BTL).
Thermal foldback will limit the maximum junction temperature to 140 °C.
14.8 Pumping effects
When the amplifier is used in an SE configuration a so-called ‘pumping effect’ can occur.
During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of
that energy is delivered back to the other supply line (e.g. VSSP1) and vice versa. When
the power supply cannot sink energy the voltage across output capacitors that power
supply will increase.
The voltage increase caused by the pumping effect depends on:
• Speaker impedance
• Supply voltage
• Audio signal frequency
• Value of decoupling capacitors on supply lines
• Source and sink currents of other channels
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
27 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
The pumping effect should not cause a malfunction of either the audio amplifier or the
power supply, which can also be caused by triggering of the undervoltage or overvoltage
protection of the amplifier.
Pumping effects in an SE configuration can be minimized by connecting audio inputs in
anti-phase and changing the polarity of one speaker as shown in Figure 11.
IN1P
OUT1
audio
in1
IN1N
IN2N
OUT2
audio
in2
IN2P
010aaa140
Fig 11. SE application for reducing pumping effect
14.9 SE curves measured in the reference design
010aaa503
010aaa504
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
(3)
(3)
−1
−1
10
10
(1)
(1)
(2)
(2)
−2
−2
10
10
−3
−3
10
10
−2
−1
2
−2
−1
2
10
10
1
10
o
10
10
10
1
10
P (W/channel)
o
10
P
(W/channel)
a. VP = 25 V; RL = 2 × 8 Ω SE
b. VP = 17 V; RL = 2 × 4 Ω SE
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 100 Hz
Fig 12. Total harmonic distortion-plus-noise as a function of output power
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
28 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa505
010aaa506
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
−1
−1
(1)
(2)
10
10
(1)
−2
−2
(2)
10
10
10
−3
−3
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
a. VP = 25 V; RL = 2 × 8 Ω SE
b. VP = 17 V; RL = 2 × 4 Ω SE
(1) Po = 7 W
(2) Po = 1 W
Fig 13. Total harmonic distortion-plus-noise as a function of frequency
010aaa507
010aaa508
40
0
SVRR
(dB)
G
(dB)
v(cl)
−20
30
(2)
(1)
−40
−60
−80
(2)
(1)
20
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
Ri = 0 Ω; Vi = 100 mV (RMS); Cse = 1000 µF
Vripple = 500 mV (RMS) referenced to ground;
Shorted input; CHVPREF = 47 µF
(1) RL = 2 × 4 Ω SE at VP = 17 V
(2) RL = 2 × 8 Ω SE at VP = 25 V
(1) VP = 17 V; RL = 2 × 4 Ω SE
(2) VP = 25 V; RL = 2 × 8 Ω SE
Fig 14. Gain as a function of frequency
Fig 15. Supply voltage ripple rejection as a function of
frequency
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
29 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa509
010aaa510
100
S/N
0
α
cs
(dB)
(dB)
(2)
80
−20
−40
(1)
60
40
20
0
(1)
(2)
−60
−80
−100
−2
−1
2
2
3
4
5
10
10
1
10
10
10
10
10
10
10
P
(W)
f (Hz)
i
o
Ri = 0 Ω; 20 kHz brick wall filter AES17
(1) RL = 2 × 4 Ω SE at VP = 17 V
(2) RL = 2 × 8 Ω SE at VP = 25 V
Po = 1 W
(1) RL = 2 × 4 Ω SE at VP = 17 V
(2) RL = 2 × 8 Ω SE at VP = 25 V
Fig 16. Signal-to-noise ratio as a function of output
power
Fig 17. Channel separation as a function of frequency
010aaa511
010aaa512
100
3.0
η
po
(%)
P
(1)
(W)
80
(2)
2.0
60
40
20
0
(1)
(2)
1.0
0.0
−2
−1
2
0
3
6
9
12
o
15
10
10
1
10
P (W/channel)
o
10
P
(W/channel)
fi = 1 kHz; Power dissipation in junction only
2 × Po
------------------------
2 × Po + P
fi = 1 kHz; η po
=
(1) RL = 2 × 4 Ω SE at 17 V
(2) RL = 2 × 8 Ω SE at 25 V
(1) RL = 2 × 4 Ω SE at 17 V
(2) RL = 2 × 8 Ω SE at 25 V
Fig 18. Output power efficiency as a function of
output power
Fig 19. Power dissipation as a function of output
power per channel (two channels driven)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
30 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa513
010aaa514
30
4.0
P
(W)
P
o
(W/channel)
(2)
3.0
(1)
(2)
20
(1)
2.0
1.0
0.0
(3)
(4)
10
0
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
V
V
P
P
fi = 1 kHz; Short time Po
fi = 1 kHz; Po at THD+N = 10 %;
Power dissipation in junction only
(1) RL = 2 × 8 Ω SE at THD = 10 %
(2) RL = 2 × 8 Ω SE at THD = 0.5 %
(3) RL = 2 × 4 Ω SE at THD = 10 %
(4) RL = 2 × 4 Ω SE at THD = 0.5 %
(1) RL = 2 × 4 Ω SE
(2) RL = 2 × 8 Ω SE
Fig 20. Maximum output power per channel as a
function of supply voltage
Fig 21. Power dissipation as a function of supply
voltage
010aaa515
010aaa516
4
4
V
V
o
o
(V)
(V)
Operating
Operating
3
2
1
0
3
2
1
0
Sleep
0.5
Mute
0.5
0
1
1.5
2
2.5
3
0
1.0
1.5
2.0
2.5
(V)
ENGAGE
3.0
V
(V)
V
POWERUP
VENGAGE > 2 V; fi = 1 kHz; Vi = 100 mV (RMS)
VPOWERUP = 2 V; fi = 1 kHz; Vi = 100 mV (RMS)
Fig 22. Output voltage as a function of voltage on pin
POWERUP
Fig 23. Output voltage as a function of voltage on pin
ENGAGE
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
31 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
14.10 BTL curves measured in the reference design
010aaa517
010aaa518
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
−1
−1
10
10
(1)
(2)
(1)
(2)
−2
−2
10
10
(3)
(3)
−3
−3
10
10
−2
−1
2
−2
−1
2
10
10
1
10
10
10
10
1
10
10
P
(W)
P (W)
o
o
a. VP = 17 V; RL = 8 Ω BTL
b. VP = 25 V; RL = 16 Ω BTL
(1) fi = 6 kHz
(2) fi = 1 kHz
(3) fi = 1 kHz
Fig 24. Total harmonic distortion-plus-noise as a function of output power
010aaa519
010aaa520
2
2
10
10
THD+N
(%)
THD+N
(%)
10
10
1
1
−1
−1
10
10
(1)
(2)
(1)
(2)
−2
−2
10
10
−3
−3
10
10
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
10
10
f (Hz)
i
f (Hz)
i
a. VP = 17 V; RL = 8 Ω BTL
b. VP = 25 V; RL = 16 Ω BTL
(1) Po = 12 W
(2) Po = 1 W
(1) Po = 10 W
(2) Po = 1 W
Fig 25. Total harmonic distortion-plus-noise as a function of frequency
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
32 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa521
(2)
010aaa522
100
45
η
po
(%)
(1)
Gv(cl)
(dB)
80
(1)
(2)
35
60
40
20
0
25
15
2
3
4
5
0
5
10
15
20
25
10
10
10
10
10
P
(W)
f (Hz)
i
o
fi = 1 kHz
Vi = 100 mV (RMS)
(1) 8 Ω BTL at 17 V
(2) 16 Ω BTL at 25 V
(1) RL = 8 Ω BTL at VP = 17 V
(2) RL = 16 Ω BTL at VP = 25 V
Fig 26. Output power efficiency as a function of
output power
Fig 27. Gain as a function of frequency
010aaa523
010aaa524
3
5
4
3
2
1
0
P
(W)
P
(W)
2
(1)
(1)
(2)
(2)
1
0
10
−2
−1
2
10
1
10
10
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
P
(W)
V
o
P
fi = 1 kHz; Power dissipation in junction only
(1) 8 Ω BTL at 17 V
fi = 1 kHz; Po at THD+N = 10 %;
Power dissipation in junction only
(1) RL = 8 Ω BTL
(2) RL = 16 Ω BTL
(2) 16 Ω BTL at 25 V
Fig 28. Power dissipation as a function of output
power
Fig 29. Power dissipation as a function of supply
voltage
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
33 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
010aaa525
(1)
010aaa526
50
0
P
SVRR
(dB)
o
(W)
40
−20
(2)
30
20
10
0
−40
−60
(3)
(4)
(1)
(2)
−80
−100
2
3
4
5
10 12 14 16 18 20 22 24 26 28 30 32 34 36
(V)
10
10
10
10
10
f (Hz)
i
V
P
fi = 1 kHz
Vripple = 500 mV (RMS) with relation to ground;
Shorted inputs; CHVP = 100 nF
(1) 16 Ω BTL at THD+N = 10 %
(2) 16 Ω BTL at THD+N = 0.5 %
(3) 8 Ω BTL at THD+N = 10 %
(4) 8 Ω BTL at THD+N = 0.5 %
(1) VP = 17 V; RL = 8 Ω BTL
(2) VP = 25 V; RL = 16 Ω BTL
Fig 30. Output power as a function of supply voltage
Fig 31. Supply voltage ripple rejection as a function of
frequency
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
34 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
14.11 Typical application schematics (simplified)
V
P
R
vdda
V
V
PA
P
10 Ω
C
C
vddp
220 µF
vdda
100 nF
(35 V)
GND
V
V
SSD(HW)
SSD(HW)
IN1P
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
C
in
OSCIO
HVP1
2
C
470 nF
in
IN1N
3
V
P
470 nF
V
DDP1
DIAG
4
C
vddp
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
C
15 nF
MUTE control
SLEEP control
5
bo
C
en
470 nF
L
lc
6
V
SSP1
7
R
10 Ω
sn
V
DDA
STAB1
STAB2
C
osc
V
8
PA
U1
TDA8932B
C
C
lc
sn
470 pF
C
se
V
SSA
100 nF
9
C
stab
R
osc
V
100 nF
SSP2
OSCREF
HVPREF
INREF
TEST
Optional
10
11
12
13
14
15
16
39 kΩ
L
lc
OUT2
C
C
15 nF
hvpref
bo
BOOT2
47 µF (25 V)
R
10 Ω
sn
Optional
C
inref
100 nF
V
DDP2
V
P
vddp
100 nF
C
sn
470 pF
C
in
C
C
lc
C
se
IN2N
HVP2
DREF
C
in
470 nF
IN2P
C
dref
100 nF
470 nF
V
V
SSD(HW)
SSD(HW)
010aaa527
Fig 32. Typical simplified application diagram for 2 × SE (asymmetrical supply)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
35 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
V
P
R
vdda
V
V
PA
P
10 Ω
C
C
vddp
220 µF
vdda
100 nF
(35 V)
GND
V
V
SSD(HW)
SSD(HW)
IN1P
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R
hvp
470 Ω
R
hvp
470 Ω
C
in
OSCIO
HVP1
2
C
in
1 µF
IN1N
3
V
P
1 µF
V
DDP1
DIAG
4
C
C
vddp
hvp
100 nF
100 nF
ENGAGE
POWERUP
CGND
BOOT1
OUT1
C
bo
15 nF
MUTE
control
5
C
L
lc
en
470 nF
6
V
SSP1
SLEEP
control
7
R
sn
10 Ω
C
C
lc
V
DDA
STAB1
STAB2
C
osc
V
8
PA
U1
TDA8932B
C
sn
V
470 pF
SSA
100 nF
9
R
osc
C
stab
100 nF
V
SSP2
OSCREF
HVPREF
INREF
TEST
lc
Optional
10
11
12
13
14
15
16
39 kΩ
L
lc
OUT2
C
bo
15 nF
BOOT2
R
sn
10 Ω
C
C
hvp
100 nF
inref
100 nF
V
DDP2
Optional
V
P
C
C
vddp
sn
470 pF
IN2N
HVP2
DREF
100 nF
IN2P
C
C
dref
100 nF
hvp
100 nF
V
V
SSD(HW)
SSD(HW)
010aaa528
Fig 33. Typical simplified application diagram for 1 × BTL (asymmetrical supply)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
36 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
V
DD
R
vdda
V
V
V
DD
DDA
10 Ω
C
vddp
C
vdda
100 nF
220 µF
(25 V)
GND
C
vssp
C
vssa
100 nF
220 µF
(25 V)
R
vssa
V
SS
SSA
10 Ω
V
SS
V
SSA
V
SSD(HW)
SSD(HW)
IN1P
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SSA
C
in
OSCIO
HVP1
2
C
in
470 nF
IN1N
3
V
DD
470 nF
V
DDP1
DIAG
4
C
vddp
ENGAGE
BOOT1
OUT1
100 nF
C
bo
15 nF
MUTE control
SLEEP control
5
C
L
en
470 nF
lc
POWERUP
CGND
6
Optional
V
SS
V
SSP1
R
10 Ω
sn
7
C
V
vssp
DDA
STAB1
STAB2
C
osc
C
100 nF
V
V
8
sn
DDA
U1
TDA8932B
C
lc
470 pF
V
SSA
VSS
100 nF
9
SSA
C
stab
100 nF
C
vssp
R
osc
V
SSP2
OSCREF
HVPREF
INREF
TEST
V
SSA
10
11
12
13
14
15
16
39 kΩ
100 nF
L
lc
OUT2
Optional
C
bo
15 nF
BOOT2
R
10 Ω
sn
C
inref
100 nF
V
DDP2
V
C
DD
C
in
V
C
IN2N
HVP2
DREF
vddp
sn
SSA
C
lc
100 nF
470 pF
C
in
470 nF
IN2P
C
dref
100 nF
470 nF
V
V
SSA
V
SSD(HW)
SSD(HW)
V
SSA
010aaa529
Fig 34. Typical simplified application diagram for 2 × SE (symmetrical supply)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
37 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
V
DD
R
vdda
V
V
V
DD
DDA
10 Ω
C
vddp
C
vdda
100 nF
220 µF
(25 V)
GND
C
vssp
C
vssa
100 nF
220 µF
R
vssa
(25 V)
V
SS
SSA
10 Ω
V
SS
V
V
SSD(HW)
SSD(HW)
IN1P
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SSA
SSA
C
in
OSCIO
HVP1
2
C
in
1 µF
IN1N
3
V
DD
1 µF
V
DDP1
DIAG
4
C
vddp
ENGAGE
BOOT1
OUT1
C
100 nF
bo
15 nF
MUTE
control
5
C
L
lc
en
470 nF
POWERUP
CGND
6
Optional
V
SSP1
R
10 Ω
sn
SLEEP
control
7
V
SS
C
vssp
100 nF
C
C
lc
V
DDA
STAB1
STAB2
C
osc
V
V
8
C
DDA
U1
TDA8932B
sn
470 pF
V
SSA
V
SS
100 nF
9
SSA
C
stab
100 nF
C
vssp
R
osc
V
SSP2
OSCREF
HVPREF
INREF
lc
VSSA
10
11
12
13
14
15
16
39 kΩ
100 nF
L
lc
OUT2
C
bo
15 nF
BOOT2
R
10 Ω
sn
C
inref
V
DDP2
TEST
100 nF
V
DD
Optional
V
SSA
IN2N
HVP2
DREF
C
C
vddp
100 nF
sn
470 pF
IN2P
C
dref
100 nF
V
V
SSD(HW)
SSD(HW)
V
V
SSA
SSA
010aaa530
Fig 35. Typical simplified application diagram for 1 × BTL (symmetrical supply)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
38 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
15. Package outline
HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
SOT549-1
E
A
X
D
c
H
v
M
A
y
exposed die pad side
E
D
h
Z
32
17
A
(A )
3
2
E
A
h
A
1
pin 1 index
θ
L
p
L
detail X
1
16
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
D
E
E
e
H
L
L
p
v
w
y
Z
θ
1
2
3
p
h
h
E
max.
8o
0o
0.15 0.95
0.05 0.85
0.30 0.20 11.1
0.19 0.09 10.9
5.1
4.9
6.2
6.0
3.6
3.4
8.3
7.9
0.75
0.50
0.78
0.48
mm
1.1
0.65
1
0.2
0.25
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-07
05-11-02
SOT549-1
MO-153
Fig 36. Package outline SOT549-1 (HTSSOP32)
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
39 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
16. Revision history
Table 16. Revision history
Document ID
Release date
20081023
Data sheet status
Change notice
Supersedes
TDA8933B_1
Preliminary data sheet
-
-
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
40 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8933B_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 23 October 2008
41 of 42
TDA8933B
NXP Semiconductors
Class D audio amplifier
19. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
17.4
18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Contact information . . . . . . . . . . . . . . . . . . . . 41
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
19
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
8.3
Functional description . . . . . . . . . . . . . . . . . . . 5
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mode selection and interfacing. . . . . . . . . . . . . 6
Pulse Width Modulation (PWM) frequency. . . . 7
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Foldback (FT) . . . . . . . . . . . . . . . . . . . 8
OverTemperature Protection (OTP) . . . . . . . . . 9
OverCurrent Protection (OCP) . . . . . . . . . . . . . 9
Window Protection (WP). . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . 9
Diagnostic input and output . . . . . . . . . . . . . . 11
Differential inputs . . . . . . . . . . . . . . . . . . . . . . 11
Output voltage buffers. . . . . . . . . . . . . . . . . . . 12
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
8.7
9
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal characteristics. . . . . . . . . . . . . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 17
Dynamic characteristics . . . . . . . . . . . . . . . . . 19
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 21
Output power estimation. . . . . . . . . . . . . . . . . 21
Output current limitation . . . . . . . . . . . . . . . . . 24
Speaker configuration and impedance . . . . . . 24
Single-ended capacitor. . . . . . . . . . . . . . . . . . 25
Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 25
Device synchronization. . . . . . . . . . . . . . . . . . 26
Thermal behavior (PCB considerations). . . . . 27
Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 27
SE curves measured in the reference design. 28
BTL curves measured in the reference design 32
Typical application schematics (simplified) . . . 35
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 40
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 41
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
17.1
17.2
17.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 October 2008
Document identifier: TDA8933B_1
相关型号：
TDA8942P/N1,112
IC 1.5 W, 2 CHANNEL, AUDIO AMPLIFIER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-1, MO-001, DIP-16, Audio/Video Amplifier
NXP
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