TDA9847T [NXP]
TV and VTR stereo/dual sound processor with digital identification; 电视和录像机立体声/数字标识的双音频处理器
| 型号： | TDA9847T |
| 厂家： | 
NXP |
| 描述： | TV and VTR stereo/dual sound processor with digital identification |
| 文件： | 总28页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9847
TV and VTR stereo/dual sound
processor with digital identification
1995 May 23
Preliminary specification
Supersedes data of September 1993
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
FEATURES
GENERAL DESCRIPTION
• Supply voltage 5 to 8 V
• Source selector
• Stereo matrix
The TDA9847 is a stereo/dual sound processor for TV and
VTR sets. Its identification ensures safe operation by using
internal digital PLL technique with extremely small
bandwidth, synchronous detection and digital integration
(switching time maximum 2.0 s; identification concerning
the main functions).
• AF inputs for external stereo AF signals
(SCART or NICAM)
• AF outputs for main and SCART
• LED operation mode indication (stereo and dual)
• High identification reliability.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage (pin 22)
supply current (pin 22)
CONDITIONS
MIN.
4.5
TYP.
MAX.
8.8
UNIT
VP
5
V
IP
without LED current
54% modulation
B/G
14
15
20
mA
Vi(rms)
nominal input signal voltage
Vi1 to Vi4 (RMS value)
−
−
−
250
500
500
−
−
−
mV
mV
mV
L
Vo(rms)
Vo(rms)
nominal output signal voltage
(RMS value)
54% modulation
clipping level of the output signal
voltages (RMS value)
THD ≤ 1.5%; B/G or L
VP = 5 V
1.4
2.4
−
1.60
2.65
−
−
V
VP = 8 V
−
V
ILon
input current
LED on
12
100
mA
mV
Vi pil
input voltage sensitivity of pilot
frequency
unmodulated
5
−
S/N(W)
THD
weighted signal-to-noise ratio
total harmonic distortion
“CCIR468-3”
66
−
75
0.2
−
−
dB
%
0.3
+70
2.2
2.3
2.0
−
Tamb
operating ambient temperature
identification window width
0
°C
fident
stereo
dual
2.2
2.3
0.35
−
−
Hz
Hz
s
−
tident on
Vi tuner
∆fpil
total identification time on
−
identification voltage sensitivity
pull-in frequency range of pilot PLL
28
dBµV
fosc = 10.008 MHz
lower side
−296
−
−
−296
Hz
Hz
upper side
302
302
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA9847
SDIP24 plastic shrink dual in-line package; 24 leads (400 mil)
SO24 plastic small outline package; 24 leads; body width 7.5 mm
SOT234-1
SOT137-1
TDA9847T
1995 May 23
2
SCART
V
V
i4
i3
250 mV
RMS
C
C
D2
D1
250 mV RMS
10 nF
±5%
10 nF
±5%
21
2.2 µF
2.2 µF
17
12 11
6 dB (AM)
0 dB
V
V
ref
ref
V
V
V
V
50 kΩ
50 kΩ
o1
o2
o3
o4
500 mV RMS 14
500 mV RMS 13
2.2 µF
2.2 kΩ
2.2 kΩ
6 dB
6 dB
6 dB
6 dB
3 dB
9
V
3 dB
5 kΩ
i1
main
15 kΩ
AM
250 mV
L + R
2
RMS
, A
3 dB
V
A/mono
250 mV RMS
35 kΩ
L/A/mono
250 mV RMS
(AM: 500 mV RMS)
L
ref
16
500 mV RMS
10 kΩ
10 kΩ
V
50 kΩ
ref
SCART
10
R/B
250 mV RMS
V
0 dB
i2
R, B
5 kΩ
2.2 µF
500 mV RMS 15
250 mV RMS
TDA9847
mute
R
stereo transmission
30 kΩ
FP
DIGITAL PLL
AND
DEMODULATOR
dual bit
19
18
DIGITAL
INTEGRATOR
C
47 pF
FP
(274 Hz)
7
6
1 kΩ
V
Q = 70
o
P
stereo
bit
3.3 nF
DIGITAL PLL
AND
DEMODULATOR
DIGITAL
INTEGRATOR
DIGITAL
PLL
2.5 mH
100 nF
tan δ ≤ 0.002
(117 Hz)
V
ref
dual transmission
C
25 kΩ
DCL
V
ref
1
2
C1
C2
C3
C4
OSCILLATOR
CONTROL
LOGIC
25 kΩ
24
3
4
5
C
V
POWER-ON
RESET
AGC
ref
SUPPLY
10 µF
C
LP
23
8
22 20
10 nF
1/2 V
C
MED803
P
ref
10 MHz
100 µF/
16 V
V
P
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: ∆f = ±27 kHz).
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
SCART
V
V
i4
i3
250 mV
RMS
C
C
D2
D1
250 mV RMS
10 nF
5%
10 nF
5%
2.2 µF
2.2 µF
17
21
12 11
6 dB (AM)
0 dB
V
ref
V
V
V
V
50 kΩ
50 kΩ
o1
o2
o3
o4
500 mV RMS 14
500 mV RMS 13
2.2 µF
2.2 kΩ
2.2 kΩ
V
6 dB
6 dB
6 dB
6 dB
ref
3 dB
9
V
3 dB
5 kΩ
i1
main
15 kΩ
AM
250 mV
L + R
2
RMS
, A
3 dB
V
A/mono
250 mV RMS
35 kΩ
L/A/mono
250 mV RMS
(AM: 500 mV RMS)
L
ref
16
500 mV RMS
10 kΩ
10 kΩ
V
ref
50 kΩ
SCART
10
R/B
250 mV RMS
V
0 dB
i2
R, B
5 kΩ
2.2 µF
500 mV RMS 15
250 mV RMS
TDA9847
mute
R
stereo transmission
27 kΩ
FP
DIGITAL PLL
AND
DEMODULATOR
dual bit
19
18
DIGITAL
INTEGRATOR
C
180 pF
FP
(274 Hz)
7
6
1 kΩ
V
P
4.7 mH
±5%
stereo
bit
1.8 nF
±2%
DIGITAL PLL
AND
DEMODULATOR
DIGITAL
INTEGRATOR
DIGITAL
PLL
Q = 25
o
tan δ ≤ 0.01
(117 Hz)
V
ref
dual transmission
C
25 kΩ
DCL
V
ref
100 nF
1
2
C1
C2
C3
C4
OSCILLATOR
CONTROL
LOGIC
25 kΩ
24
3
4
5
C
V
POWER-ON
RESET
AGC
ref
SUPPLY
10 µF
C
LP
23
8
22 20
10 nF
1/2 V
C
MED804
P
ref
10 MHz
100 µF/
16 V
V
P
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: ∆f = ±27 kHz).
The components of the external LC band-pass filter have the following order-No.: Philips Germany only No: 4312 020 17525 or Fastron Sdn. Bha., Malaysia type SMCC 472 J
for L = 4.7 MHz (±5%) Philips Components No: 2222 429 71802, C = 1.8 nF (±2%).
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
PINNING
SYMBOL
PIN
DESCRIPTION
control input Port C1
C1
1
2
3
4
5
6
7
8
9
C2
control input Port C2
C4
control input Port C4
CAGC
CLP
CDCL
Vi pil
Cref
Vi1
AGC capacitor of pilot frequency amplifier
identification low-pass capacitor
DC loop capacitor
C1
C2
C4
1
2
24
23
22
21
20
19
18
17
16
15
14
13
C3
XTAL
pilot frequency input voltage
capacitor of reference voltage (1⁄2VP)
3
V
P
4
C
C
AGC
D2
AF input signal voltage 1 [from sound carrier 1 or
AM sound (standard L)]
5
C
GND
LP
6
Vi2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AF input signal voltage 2 (from sound carrier 2)
AF input signal voltage 3 (SCART)
AF input signal voltage 4 (SCART)
AF output signal voltage 2 (main)
AF output signal voltage 1 (main)
AF output signal voltage 4 (SCART)
AF output signal voltage 3 (SCART)
50 µs de-emphasis capacitor of AF Channel 1
LED (dual)
C
LEDST
LEDDU
DCL
TDA9847
Vi3
7
V
i pil
Vi4
8
C
C
ref
D1
Vo2
V
9
V
i1
i2
i3
i4
o3
Vo1
V
V
V
10
11
12
V
o4
Vo4
V
o1
Vo3
V
CD1
LEDDU
LEDST
GND
CD2
VP
o2
MED805
LED (stereo)
ground (0 V)
50 µs de-emphasis capacitor of AF Channel 2
supply voltage (5 to 8 V)
XTAL
C3
10 MHz crystal input
Fig.3 Pin configuration.
control input Port C3
1995 May 23
5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
to obtain the AGC voltage for controlling the gain of the
pilot signal amplifier.
FUNCTIONAL DESCRIPTION
AF signal handling
The identification stages consist of two digital PLL circuits
with digital synchronous demodulation and digital
integrators to generate the stereo or dual sound
identification bits which can be indicated via LEDs.
The input AF signals, derived from the two sound carriers,
are processed in analog form using operational amplifiers.
De-matrixing uses the technique of two amplifiers
processing the AF signals. Finally, a source selector
provides the facility to route the mono signal through to the
outputs (‘forced mono’).
A 10 MHz crystal oscillator provides the reference clock
frequency. The corresponding detection bandwidth is
larger than ±50 Hz for the pilot carrier signal, so that
fp-variations from the transmitter can be tracked in the
event of missing synchronization with the horizontal
frequency fH. However the detection bandwidth for the
identification signal is made small (±1 Hz) to reduce
mis-identification.
De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
This provides a frequency response with the tolerances
given in Fig.4.
A source selector, controlled via the control input ports
allows selection of the different modes of operation in
accordance with the transmitted signal. The device was
designed for a nominal input signal (FM: 54% modulation
is equivalent to ∆f = ±27 kHz) of 250 mV RMS value (Vi1
and Vi2) and for a nominal input signal (AM: m = 0.54) of
500 mV RMS value (Vi1), respectively 250 mV RMS (Vi3
and Vi4). A nominal gain of 6 dB for Vi1 and Vi2 signals
(0 dB for Vi1 signal (AM sound)) and 6 dB for Vi3 and Vi4
signals is built-in. By using rail-to-rail operational
amplifiers, the clipping level (THD ≤ 1.5%) is 1.60 V RMS
for VP = 5 V and 2.65 V RMS for VP = 8 V at outputs
Vo1 to Vo3 and Vo4. Care has been taken to minimize
switching plops. Also total harmonic distortion and random
noise are considerably reduced.
Figure 2 shows an example of the alignment-free fp
band-pass filter. To achieve the required QL of around 12,
the Q0 at fp of the coil was chosen to be around 25
(effective Q0 including PCB influence). Using coils with
other Q0, the RC-network (RFP and CFP) has to be adapted
accordingly. It is assumed that the loss factor tan δ of the
resonance capacitor is ≤0.01 at fp.
Copper areas under the coil might influence the loaded Q
and have to be taken into account. Care has also to be
taken in environments with strong magnetic fields when
using coils without magnetic shielding.
Control input ports
The complete IC is controlled by the four control input ports
C1, C2, C3 and C4. Which AF output channel pair can be
selected is determined by the control input Port C4 [LOW:
main; HIGH: SCART; 3-state: preset position
(see Section “General information”)]. With the other
control input ports C1, C2 and C3 the user can select
between different AF sources in accordance with the
transmitter status (see Tables 1 and 2). Finally,
Identification
The pilot signal is fed via an external RC high-pass filter
and single tuned LC band-pass filter to the input of a gain
controlled amplifier. The external LC band-pass filter in
combination with the external RC high-pass filter should
have a loaded Q-factor of approximately 40 to 50 to
ensure the highest identification sensitivity. By using a
fixed coil (±5%) to save the alignment (see Fig.2), a
Q-factor of approximately 12 is proposed. This may cause
a loss in sensitivity of approximately 2 to 3 dB. A digital
PLL circuit generates a reference carrier, which is
synchronized with the pilot carrier. This reference carrier
and the gain controlled pilot signal are fed to the
AM-synchronous demodulator. The demodulator detects
the identification signal, which is fed through a low-pass
filter with external capacitor CLP (pin 5) to a
Schmitt triggers are added in the input Port interfaces to
suppress spikes on the control lines C1, C2, C3 and C4.
After a Power-On Reset (POR) both registers are reset
(mute mode for both AF channel pairs). After some time
(≤1 ms), when the POR is automatically deactivated, the
switch positions of the main channel (C4 = LOW) are
changed in accordance with the other control input Port
levels. If C4 is HIGH after a POR, the switch positions of
the SCART channel cannot change. The reason is, that
the main register is reset (mute mode; see Table 1). Thus,
at first the main register byte has to be changed out of the
mute function, e.g. sound mute.
Schmitt trigger for pulse shaping and suppression of LOW
level spurious signal components. This is a measure
against mis-identification.
The identification signal is amplified and fed through an
AGC low-pass filter with external capacitor CAGC (pin 4)
1995 May 23
6
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
After that, when C4 is HIGH (see Table 2), the switch
positions of the SCART channel are changed in
accordance with the other control line levels.
EXTERNAL MODE
External sound sources, e.g. from SCART input, are fed to
both AF channel pair outputs. When the user chooses the
external mode of the main channel (see Table 1), the
identification circuit is still running, but the LEDs are
switched-off.
When the supply voltage of the TDA9847 is not connected
(standby function), the control lines remain undisturbed.
The logic level combination 1000 of the control input ports
(C4, C3, C2 and C1) is not allowed (see Tables 1 and 2).
Programming of the main and SCART register
Operating mode selection
GENERAL INFORMATION
Tables 1 and 2 show the different operating modes of this
stereo decoder.
The switch positions of both AF channels are directly
controlled by the data of the main and SCART register.
These registers are programmable by a microcontroller.
MUTE MODE
In the 3-state mode the logic content of the C1, C2 and C3
control lines remains stored in the registers for main and
SCART, so the switch positions in the source selector do
not change. The logic content of these control lines can be
changed without changing the switch positions of the
source selector (preset position) to prepare the new
operating mode selection for the main or SCART channel.
The execution of this new mode is achieved by leaving the
preset position (3-state): When the C4 level goes LOW,
the logic content of the control lines C1, C2 and C3 are
valid for the main channel (see Table 1) and in the event
of HIGH the C1, C2 and C3 are valid for the SCART
channel (see Table 2).
This IC has two different mute modes:
1. Mute mode.
2. Sound mute mode.
In the mute mode, when all control input lines are set LOW,
all AF channels are muted (‘fast mute’). Finally, the
integrators are reset provided the user does not leave this
mode (identification is disabled). When the user changes
this mode, the identification circuit starts with the
detection.
In the sound mute mode each AF channel can be
separately muted (0100 = main and 1100 = SCART). The
identification circuit is activated and the LEDs are on or off
in accordance with the detection status of this circuit.
The identification bits and the control lines influence the
operating mode selection for the AF switches in the source
selector and de-matrix, e.g. both AF channels are
programmed in the mono mode (X001,
MONO MODE
see Tables 1 and 2). The LEDs are switched-off. When
the identification circuit detects the stereo identification
frequency (fs = 117 Hz) the de-matrix is immediately
switched in the stereo mode without changing the control
line levels. The stereo signals are routed to all AF outputs.
In the event of dual frequency detection (fD = 274 Hz) both
dual sounds are fed to the AF output pairs.
For the transmitter status mono the user must set the
TDA9847 in the mono mode with X001 or X010
(see Tables 1 and 2). The level combination X011 is
reserved for the AM sound (standard L), because in this
mode the de-emphasis is deactivated and the gain of the
AF signal from input to output is reduced from
6 dB to 0 dB. At the AF outputs the signal has the same
level for standards with FM or AM modulated sound
assuming the same modulation degree.
MICROCONTROLLER WITH 3-STATE OUTPUT PORTS
Figure 10 shows an example of an application circuit for
TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a
microcontroller, which has a LOW/high-ohmic/HIGH
output port to control the main and SCART channel (C4
control line). For the C1, C2 and C3 line the microcontroller
requires only LOW/HIGH output ports. Two resistors RC4A
and RC4B are necessary for the C4 line to generate the
3-state voltage. The values and tolerances of these
components are given in Fig.10.
STEREO MODE
In this mode the choice between stereo and mono (‘forced
mono’) signals is common for both AF channel pairs. The
mode for main and SCART is achieved by control of the
main channel (see Tables 1 and 2).
DUAL MODE
In this mode there is no restriction to select AF inputs and
outputs independently in both channels.
1995 May 23
7
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
When the microcontroller has only open drain ports
available for the C1, C2 and C3 control line, external
Figure 5 shows the hold and set-up time of the C1,
C2 and C3 control line in the 3-state mode,
pull-up resistors must be connected to these control lines. see Chapter “Characteristics”.
Figure 7 shows an example of a timing diagram to program
MICROCONTROLLER WITH LOW/HIGH OUTPUT PORTS
the main and SCART register of the TDA9847 with a
microcontroller via the control lines C1, C2, C3 and C4.
Both registers are programmed with the same control line
levels: C1 = LOW, C2 = HIGH and C3 = LOW. The dual
identification frequency is detected and the dual LED is
switched-on. The A-signal (dual mode) is fed to all
AF outputs (see Tables 1 and 2). This is shown in the
beginning of this timing diagram.
Figure 11 shows an example of an application circuit for
TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a
microcontroller, which has open drain output ports to
control the main and SCART channel. Four resistors and
two output ports of the microcontroller are necessary to
generate the 3-state voltage. The other control lines have
a pull-up resistor (10 kΩ) in the event of open drain output
stages. These resistors are not necessary for LOW/HIGH
output ports of the microcontroller having internal pull-up
or push-pull stages. The values and tolerances of these
components are given in this figure. Table 4 shows the
conversion logic truth table.
The second period of time shows the programming of the
external mode (C3 goes to HIGH: CC-signal) for the main
channel. The switch positions are immediately changed to
the external AF source, because the C4 level is LOW. The
dual LED is switched-off by the logic (see Section
“External mode”).
For information about programming the different operation
mode selections see Section “Operating mode selection”.
The next periods of time show the way to change the
switch positions for the SCART channel to route B-signals
to the AF outputs (dual mode: BB). At first the control
output Port of the microcontroller for the C4 line goes into
the high ohmic state. The changing of the C1, C2 or C3
level has no influence on the register data. In the timing
diagram the C1 level changes from LOW-to-HIGH and the
C3 level goes from HIGH-to-LOW. In the next steps the C4
line goes from 3-state-to-HIGH, and the level of the other
control lines are valid for the SCART channel, and the
B-signals are fed (dual mode: BB) to the AF outputs of the
main channel.
Power supply
The different supply voltages and currents required for the
analog and digital circuits are derived from an internal
band-gap reference circuit. The AF reference voltage is
1⁄2VP. For a fast setting to 1⁄2VP an internal start-up circuit
is added. A good ripple rejection is achieved with the
external capacitor Cref = 100 µF/16 V in conjunction with
the high ohmic input of the 1⁄2VP pin (pin 8). No additional
DC load on this pin is allowed.
Power-On Reset (POR)
After some time in this example the C1 and C2 levels
change from HIGH-to-LOW and the C3 level goes from
LOW-to-HIGH (sound mute). The SCART channel is
immediately muted, because the level of the C4 line is
HIGH.
When a POR is activated by switching on the supply
voltage or because of a supply voltage breakdown, the
117/274 Hz DPLL, the 117/274 Hz integrator and the logic
will be reset. Both AF channels (main and SCART) are
muted (≤1 ms).
The last period of time shows the programming of the dual
mode (AA) for the main channel. At first the control output
Port of the microcontroller for the C4 line goes into the high
ohmic state. The changing of the C1, C2 or C3 level has
no influence on the register data. The switch positions of
the SCART channel stay in the sound mute.
ESD protection
All pins are ESD protected. The protection circuits
represent the latest state of the art.
Internal circuit
In the 3-state mode the C2 level changes from
LOW-to-HIGH, and the C3 level goes from HIGH-to-LOW.
When the C4 level is LOW, the level of the other control
lines are valid for the main channel. The A-signal (dual
mode) is fed to the main outputs.
The internal pin configuration is given in Fig.7.
The operation mode mute (see Table 1) can be achieved
from any position of the C4 control line without going via
3-state.
1995 May 23
8
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage (pin 22)
CONDITIONS
MIN.
−0.3
MAX.
+10
UNIT
VP
Vi
V
input voltage at pins 1 to 3 and 24
input voltage at pins 4 to 17, 21 and 23
input voltage at pins 18 and 19
storage temperature
−0.3
−0.3
−0.3
−25
0
+9.0
VP
V
Vi
V
Vi
+10
+150
+70
±300
V
Tstg
Tamb
Ves
°C
°C
V
operating ambient temperature
electrostatic handling for all pins
note 1
−
Note
1. Charge device model class B: discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
SDIP24
SO24
69
95
K/W
K/W
CHARACTERISTICS
VP = 5 V; Tamb = 25 °C; nominal input signal Vi1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to
∆f = ±27 kHz); nominal input signal Vi1 = 0.5 V RMS value (AM: m = 0.54); nominal input signal
Vi3, 4 = 0.25 V RMS value (AM: m = 0.54); nominal output signal Vo1, 2, 3, 4 = 0.5 V RMS value; fAF = 1 kHz;
Vi pil = 16 mV RMS value; fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 µs
pre-emphasis; noise measurement in accordance with “CCIR468-3”, operating oscillator frequency fosc = 10.008 MHz;
currents into the IC positive; measured in test circuit Fig.8; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pin 22)
supply current (pin 22)
total power dissipation
4.5
14
63
5
8.8
20
V
IP
without LED current
15
75
mA
mW
V
Ptot
Vn(DC)
176
1⁄2VP + 0.1
DC voltage
1⁄2VP − 0.1 1⁄2VP
(pins 9 to 17 and 21)
Vref(DC)
lL(DC)
DC reference voltage (pin 8)
DC leakage current (pin 8)
1⁄2VP − 0.1 1⁄2VP
1⁄2VP + 0.1
±1
V
−
−
µA
1995 May 23
9
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AF Inputs (Vi1 and Vi2 [pins 9 and 10)]
Vi(rms)
nominal input signal voltage
(RMS value)
54% modulation
B/G
−
−
0.25
−
−
V
L (only Vi1)
THD ≤1.5%
VP = 5 V; B/G
VP = 8 V; B/G
0.5
V
Vi(rms)
clipping voltage level
(RMS value)
0.625
1.050
0.715
1.200
1.400
2.350
−
−
−
−
V
V
V
V
VP = 5 V; L (only Vi1) 1.200
VP = 8 V; L (only Vi1) 2.100
G = Vo/Vi; note 1
Gv
AF signal voltage gain
input resistance
B/G
5
6
7
dB
dB
kΩ
kΩ
L (only Vi1)
−1
40
4.25
0
+1
60
Ri
50
5.0
Rdeem
internal de-emphasis resistor
(pins 17 and 21)
see Fig.4
5.75
Additional AF inputs (pins 11 and 12)
Vi(rms)
nominal input signal voltage
(RMS value)
54% modulation
−
0.25
−
−
V
Vi(rms)
clipping voltage level
(RMS value)
THD ≤ 1.5%
VP = 5 V
0.625
1.050
5
0.715
1.200
6
V
VP = 8 V
V
Gv
Ri
AF signal voltage gain
input resistance
G = Vo/Vi; note 1
7
dB
kΩ
40
50
60
AF outputs (pins 13 to 16)
Vo(rms) nominal output signal voltage THD ≤ 0.3%;
−
0.5
−
V
(RMS value)
54% modulation
THD ≤ 1.5%
VP = 5 V
Vo(rms)
clipping voltage level
(RMS value)
1.4
2.4
250
−
1.6
2.65
350
−
−
V
VP = 8 V
−
V
Ro
CL
RL
output resistance
450
1.5
-
Ω
load capacitor on output
nF
kΩ
load resistor on output
(AC-coupled)
10
−
B
frequency response
(bandwidth)
fi = 40 to 20000 Hz;
note 2
−0.5
−
+0.5
dB
B−3 dB
THD
frequency response
−3 dB; note 2
300
−
350
0.2
75
400
0.3
−
kHz
%
total harmonic distortion
note 1
S/N(W)
weighted signal-to-noise ratio “CCIR468-3”
(quasi-peak)
66
dB
1995 May 23
10
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SYMBOL
PARAMETER
CONDITIONS
notes 1 and 3
MIN.
TYP.
MAX.
UNIT
αcr
crosstalk attenuation for
dual
Zs ≤ 1 kΩ
Zs ≤ 1 kΩ
70
40
76
−
75
45
80
−
−
−
−
dB
stereo
dB
dB
mV
αmute
mute attenuation
Zs ≤ 1 kΩ; note 1
after switching
∆VDC
change of DC level output
voltage between any two
modes of operation
±10
PSRR
IO(DC)
power supply ripple rejection
DC output current
fr = 70 Hz; see Fig.9
50
65
−
dB
−
−
±20
µA
10 MHz crystal oscillator (pin 23)
fr
series resonant frequency of
crystal (fundamental mode)
CL = 20 pF
9.995
9.988
10.008
10.008
10.021
10.028
MHz
MHz
fosc
operating oscillator frequency over operating
(running in parallel resonance temperature range
mode)
including ageing and
influence of drive
circuit
Rxtal
equivalent crystal series
resistance
even at extremely low
drive level (<1 pW)
over operating
temperature range
with C0 = 6 pF
−
60
200
Ω
Ω
Rn
crystal series resistance of
unwanted mode
2 × Rr
−
−
C0
crystal parallel capacitance
crystal motional capacitance
level of drive in operation
with Rr ≤ 100 Ω
−
6
10
50
5
pF
fF
C1
−
25
−
Pxtal
Vosc(p-p)
−
µW
mV
oscillator operating voltage
(peak-to-peak value)
500
550
600
Pilot processing
Vi pil(rms)
pilot input voltage level at pin 7 unmodulated
5
−
100
mV
(RMS value)
Ri pil
Ci pil
m
pilot input resistance
pilot input capacitance
modulation depth
500
−
1000
−
−
kΩ
pF
%
3
AM
25
50
75
1995 May 23
11
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
∆fpil
pilot PLL pull-in frequency
range (referenced to
fosc = 9.988 MHz
lower side
−405
−
−
−405
Hz
fpil = 54.6875 kHz)
upper side
192
192
Hz
fosc = 10.008 MHz
lower side
−296
−
−
−296
Hz
Hz
upper side
302
302
fosc = 10.028 MHz
lower side
−188
411
0
−
−
−
−188
411
1.7
Hz
Hz
ms
Hz
kΩ
mV
upper side
tpil
pilot PLL pull-in time
fLP
low-pass frequency response −3 dB
450
18.75
−
600
25
−
750
31.25
70
R5
low-pass output resistance
V5(rms)
identification threshold voltage
(RMS value)
QL
loaded quality factor of
resonance circuit
high sensitivity;
see Fig.1
40
−
50
loaded quality factor of
resonance circuit with fixed
coil
sensitivity loss
2 to 3 dB; see Fig.2
−
12
−
tacqui AGC AGC acquisition time
Vi pil(rms) switched from
0 to 100 mV (RMS
value)
−
−
0.1
s
Identification (internal functions)
Vi tuner
C/N
identification voltage sensitivity note 4
−
−
28
33
−
dBµV
pilot carrier-to-noise ratio for
start of identification
note 5
-
dB/Hz
H
hysteresis
note 4
lower side
stereo
dual
−
−
2
dB
fdet
pull-in frequency range of
identification PLL (referred to
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
−0.63
−0.69
−
−
−0.63
−0.69
Hz
Hz
upper side
stereo
dual
0.63
0.69
0
−
−
−
−
0.63
0.69
0.8
Hz
Hz
s
tdet
pull-in time of identification
PLL (referenced to
stereo
dual
0
0.8
s
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
fident
identification window
stereo; note 6
dual; note 6
2.2
2.3
−
−
2.2
2.3
Hz
Hz
frequency width (referred to
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
tintegr
integrator time constant
0.94
−
0.94
s
1995 May 23
12
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SYMBOL
PARAMETER
CONDITIONS
stereo; note 7
MIN.
0.35
TYP.
MAX.
UNIT
tident(on)
total identification time on
−
−
−
−
2.0
2.0
1.5
1.5
s
s
s
s
dual; note 7
stereo; note 8
dual; note 8
0.35
0.60
0.60
tident(off)
total identification time off
LED (pins 18 and 19)
VL(off)
VL(on)
IL(off)
IL(on)
output voltage
output voltage
input current
input current
LED off
LED on
LED off
LED on
−
−
−
−
−
−
−
−
8.8
0.7
1
V
V
µA
mA
12
Control input ports C1 to C3 (pins 1, 2 and 24)
VIL
VIH
IIL
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
−
0.8
8.8
-1
V
2.0
−
5.0
−
V
µA
µA
IIH
−
−
1
Control input Port C4 (pin 3)
VIL
VCT
VIH
IIL
LOW level input voltage
3-state level input voltage
HIGH level input voltage
LOW level input current
3-state level input current
HIGH level input current
HIGH level hold time
0
−
0.8
2.1
8.8
−1
−1
1
V
1.5
2.8
−
1.8
5.0
−
V
V
µA
µA
µA
µs
µs
µs
µs
ICT
IIH
−
−
−
−
th1
see Fig.5
see Fig.5
see Fig.5
see Fig.5
5
−
−
th2
LOW level hold time
5
−
−
tsu1
tsu2
HIGH level set-up time
LOW level set-up time
0.25
0.25
−
−
−
−
Notes to the characteristics
1. Vo = 0.5 V (RMS value); f = 1 kHz.
2. Without de-emphasis capacitors with respect to nominal gain.
3. In dual mode: A (B)-signal into B (A) channel; in stereo mode: R-signal into left channel; L-signal = 0.
4. Tuner input signal, measured with PCALH reference front end (1⁄2EMF, 75 Ω, 2T/20T/white bar, 100% video) and
PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned.
5. Bandwidth of the pilot BP-filter B−3 dB = 1.2 kHz. Vi2 input driven with identification-modulated pilot carrier and white
noise.
6. Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL
(steady detection) plus window increase due to integrator (fluctuating detection).
7. The maximal total system identification time on is equal to tident(on) plus tacqui AGC
.
8. The maximal total system identification time off is equal to tident(off)
.
1995 May 23
13
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
Table 1 Control input Port matrix to select AF inputs and AF outputs (main channel)
INPUT SIGNAL
ST/DS/M SCART
OUTPUT SIGNAL
MAIN SCART
Vo1 Vo2 Vo3 Vo4 C4 C3 C2 C1 DUAL STEREO
CONTROL INPUT
PORT(1)
LED
MODE
Vi1
9
Vi2
10
Vi3
11
Vi4
12
14
13
16
15
3
24
2
1
18
off
note 4 note 4
19
Mute(2)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
C
C
C
−
−
−
−
−
−
−
−
−
−
−
D
D
D
no signal
no signal
no signal
note 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
off
Sound mute
Mono
−
M
M
M
AM
S
−
M
M
AM
L
M
M
AM
R
note 3
off
off
off
off
off
off
on
on
on
off
off
off
off
off
off
on
on
on
off
off
off
off
off
off
−
−
Stereo
Dual
ST
DS
−
R
R
R
B
B
B
−
L
S
S
R
S
S
S
S
S
S
S
S
A
A
B
note 3
A
A
A
A
B
B
External
−
C
D
note 3
−
−
C
C
−
−
D
D
Notes
1. The combination 1000 is not allowed.
2. In mute mode the content of the 117 Hz/274 Hz integrator will be reset. The LEDs are switched-off.
3. The previous state is unchanged.
4. The LED shows the identification status.
1995 May 23
14
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
Table 2 Control input Port matrix to select AF inputs and AF outputs (SCART channel)
INPUT SIGNAL
ST/DS/M SCART
OUTPUT SIGNAL
MAIN SCART
Vo1
CONTROL INPUT
PORT(1)
MODE
Vi1
Vi2
10
Vi3
Vi4
12
Vo2
13
Vo3
Vo4
15
C4
3
C3
24
C2
2
C1
1
9
11
14
16
Sound mute
Mono
−
−
M
M
AM
S
−
−
−
−
−
−
−
−
−
−
−
−
C
C
C
−
−
−
−
−
−
−
−
−
−
D
D
D
note 2
no signal
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
M
note 2
note 2
note 2
note 2
M
M
AM
−
M
M
AM
−
−
−
Stereo
Dual
ST
DS
−
R
R
R
B
B
B
−
S
−
−
S
−
−
A
A
B
A
A
A
A
B
B
External
−
C
C
D
D
C
D
−
−
−
−
Notes
1. The combination 1000 is not allowed.
2. The previous state is unchanged.
Table 3 Explanation of Tables 1 and 2
Table 4 Conversion logic truth table for the C4 control
line (see Fig.11)
SIGNAL
DESCRIPTION
MICROPROCESSOR
OUTPUT
CONTROL PORTS
R
L
right
left
TDA9847
C4-level
S
(L + R)
--------------------
2
C41
C42
0
C4
0
1
1
0
1
≥3.2 V
A and B
C and D
AM
dual sound A/B
0
3-state
0
1.8 ±0.25 V
≤0.45 V
external sound source (SCART)
AM sound (standard L)
mono sound
1
1
not allowed
undefined
M
DS
dual sound
ST
stereo sound
1995 May 23
15
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
MED647
+2
V
R: −15%;
C: −5%
oAF
(dB)
+1
0
−1
−2
R: +15%;
C: +5%
2
3
4
5
10
10
10
10
10
f
(Hz)
oAF
Fig.4 Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (±5%);
Rinternal = 5 kΩ (±15%).
V
C4
(V)
5
HIGH
2.8
2.1
1.5
3-state
LOW
0.8
0
t (s)
t
t
t
t
h1
h2
su1
t
h1
h2
su1
t
t
t
V
su2
su2
C1/C2/C3
(V)
5
HIGH
2
0
0.8
LOW
t (s)
MED811
Fig.5 Waveforms showing the hold and set-up times of the C1 to C3 control line in the 3-state mode.
1995 May 23
16
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
V
C1
(V)
5
HIGH
2
0.8
LOW
0
t (s)
t (s)
t (s)
V
C2
(V)
5
HIGH
2
0
0.8
LOW
V
C3
(V)
5
HIGH
2
0
0.8
LOW
V
C4
(V)
5
HIGH
2.8
2.1
1.5
3-state
LOW
0.8
t (s)
0
valid main
dual: AA
valid main
storage main
valid SCART
storage SCART
AF outputs
main
dual: AA
dual: AA
external: CC
dual: BB
sound mute
SCART
MED810
Fig.6 Programming the main and SCART register of the TDA9847 with a microcontroller via the control lines
C1 to C4; the dual identification frequency is detected.
1995 May 23
17
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
INTERNAL CIRCUITRY
V
V
P
P
3 µA
3 µA
2 kΩ
2 kΩ
1
24
23
5 kΩ
C3
C1
V
P
XTAL
–
+
3 µA
+5 V
22
21
V
P
2 kΩ
2
C2
13 kΩ
3 pF
V
+
–
TDA9847
P
5 kΩ
C
D2
V
P
3 µA
–
+
3 µA
2 kΩ
3
4
C4
GND
20
19
60 µA
25 kΩ
V
C
P
AGC
LEDST
V
V
P
P
5
C
LP
V
V
40 µA
P
25 kΩ
P
18
17
60 µA
LEDDU
Z\xV
P
6
C
DCL
V
P
25 kΩ
40 µA
5 kΩ
+
5 kΩ
5 kΩ
C
D1
7
8
–
V
i pil
–
+
C
ref
V
P
22.5 kΩ
I
B
5 kΩ
5 kΩ
V
P
16
15
9
V
V
o3
i1
I
15 kΩ
35 kΩ
V
P
B
200 µA
I
V
B
o4
Z\xV
10
11
12
P
V
P
V
i2
AF outputs
200 µA
14
50 kΩ
50 kΩ
I
B
AF inputs
V
o1
Z\xV
P
V
i3
V
P
200 µA
I
B
Z\xV
13
P
P
V
o2
V
i4
50 kΩ
Z\xV
I
B
200 µA
MED807
V
P
ESD protection diode
for pins 4 to 17, 21 and 23
zener diode protection
for pins 1, 2, 3, 18, 19, 20 and 24
Fig.7 Internal circuits.
18
1995 May 23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
TEST AND APPLICATION INFORMATION
C1
C2
1
24
23
22
21
20
19
18
17
16
15
14
C3 control input port
X
TAL
10 MHz
control input
ports
2
C
VP
V
P
C4
3
10 µF
10 µF
C
AGC
50 µs
5%
D2
4
100 µF/16V
de-emphasis
C
10 nF
C
C
LP
10 nF
ref
5
C
stereo transmission
100 nF
DCL
1/2 V
P
6
1 kΩ
TDA9847
V
P
3.3 nF 2.5 mH
7
dual transmission
47 pF
5%
D1
50 µs
8
de-emphasis
C
10 nF
30 kΩ
2.2 kΩ
AF from 5.5 MHz
or from AM demodulator (L)
V
V
V
V
V
V
V
V
9
i1
o3
o4
o1
o2
SCART
main
2.2 kΩ
10
11
12
AF from 5.742 MHz
i2
i3
i4
external sound
source C
SCART
external sound
source D
13
4 x 2.2 µF
MED806
Fig.8 Test circuit of the stereo decoder TDA9847.
1995 May 23
19
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
20
16
15
14
13
V
P
22
HP3585
TDA9847
10 kΩ
5 V modulated
with 200 mV (p-p)
100 µF
8
9
10 11 12
100 µF/16V
100 µF
70 Hz
MED808
Fig.9 Test circuit for measurement of ripple rejection.
V
= 5 V ±10%
P
V
= 4.5 to 8.8 V
P
R
C4A
11 kΩ
C4
22
3
R
C4B
6.2 kΩ
STEREO
DECODER
MICROCONTROLLER
C1
C2
C3
TDA9847
1
2
24
20
MED809
All resistors: ±2%.
Fig.10 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller
[LOW/HIGH output ports with internal pull-ups or push-pull stages (C1 to C3) and
LOW/high-ohmic/HIGH output Port (C4)].
1995 May 23
20
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
V
= 5 V ±10%
V
= 4.5 to 8.8 V
P
P
R
R
C42A
10 kΩ
C41A
10 kΩ
R
22
C4A
11 kΩ
R
C41B
C41
C42
100 kΩ
C4
3
R
C42B
R
STEREO
DECODER
C4B
6.2 kΩ
100 kΩ
MICROCONTROLLER
TDA9847
R
R
R
C1
10 kΩ
C2
10 kΩ
C3
10 kΩ
C1
C2
C3
1
2
24
20
MED812
Resistors RC4A and RC4B ±2%; all other resistors ±10%; transistors BC types or equivalent.
Fig.11 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller
(LOW/HIGH with open-drain output ports).
1995 May 23
21
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
PACKAGE OUTLINES
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
1
(1)
(1)
Z
w
UNIT
b
b
c
D
E
e
e
L
M
M
1
1
E
H
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT234-1
1995 May 23
22
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1995 May 23
23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SOLDERING
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Plastic small outline packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
1995 May 23
24
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 May 23
25
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
NOTES
1995 May 23
26
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
NOTES
1995 May 23
27
Philips Semiconductors – a worldwide company
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Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557
For all other countries apply to: Philips Semiconductors,
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P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
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Tel. (03)3740 5130, Fax. (03)3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
SCD40
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
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533061/1500/02/pp28
Date of release: 1995 May 23
9397 750 00154
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Tel. (022)74 8000, Fax. (022)74 8341
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