TDA9850P [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PDIP32, Consumer IC:Other;
| 型号： | TDA9850P |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PDIP32, Consumer IC:Other 解码器 |
| 文件： | 总32页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9850
I2C-bus controlled BTSC
stereo/SAP decoder
1995 Jun 19
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
FEATURES
• Quasi alignment-free application due to automatic
adjustment of channel separation via I2C-bus
• Dbx noise reduction circuit
• Dbx decoded stereo, Second Audio Program (SAP) or
mono selectable at the AF outputs
GENERAL DESCRIPTION
• Additional SAP output without dbx, including
de-emphasis
The TDA9850 is a bipolar-integrated BTSC stereo/SAP
decoder (I2C-bus controlled) for application in TV sets,
VCRs and multimedia.
• High integration level with automatically tuned
integrated filters
• Input level adjustment I2C-bus controlled
• Alignment-free SAP processing
• Stereo pilot PLL circuit with ceramic resonator,
automatic adjustment procedure for stereo channel
separation, two pilot thresholds selectable via I2C-bus
• Automatic pilot cancellation
• Composite input noise detector with I2C-bus selectable
thresholds for stereo and SAP off
• I2C-bus transceiver.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage
supply current
CONDITIONS
MIN.
8.5
TYP. MAX. UNIT
VCC
ICC
9
9.5
75
−
V
−
58
mA
mV
mV
Vcomp(rms) input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −
VoR(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −
VoL(rms)
250
500
;
−
GLA
input level adjustment control
stereo channel separation
total harmonic distortion L + R
signal-to-noise ratio
−3.5
−
+4.0
−
dB
dB
%
αcs
fL = 300 Hz; fR = 3 kHz
fi = 1 kHz
25
35
0.2
THDL,R
S/N
−
−
500 mV (RMS) mono output signal
CCIR noise weighting filter
(peak value)
−
−
60
73
−
−
dB
DIN noise weighting filter
(RMS value)
dBA
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA9850
SDIP32
SO32
plastic shrink dual in-line package; 32 leads (400 mil)
plastic small outline package; 32 leads; body width 7.5 mm
SOT232-1
SOT287-1
TDA9850T
1995 Jun 19
2
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
License information
A license is required for the use of this product. For further information, please contact:
COMPANY
THAT Corporation
BRANCH
ADDRESS
Licensing Operations
734 Forest St.
Marlborough, MA 01752
USA
Tel.: (508) 229-2500
Fax: (508) 229-2590
Tokyo Office
405 Palm House, 1-20-2 Honmachi
Shibuya-ku, Tokyo 151
Japan
Tel.: (03) 3378-0915
Fax: (03) 3374-5191
1995 Jun 19
3
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e
C3
R1
+
ceramic
resonator
C4
C5
Q1
C6
C7
+
+
+
C2
13
15
18
19
14
16
17
L + R
stereo
mono
SAP
27
21
OUTL
OUTR
DEMATRIX
+
MODE
SELECT
STEREO DECODER
to
L − R/SAP
audio
processing
TDA9850
C8
22
23
INPUT
LEVEL
ADJUST
composite
baseband
input
NOISE
DETECTOR
STEREO/SAP
SWITCH
DE-EMPHASIS
11
SAP without DBX
C1
7
STEREO
ADJUST
LOGIC, I2C-
TRANSCEIVER
SAP
DEMODULATOR
SUPPLY
12
DBX
28
MAD
4
10
5
6
32
25 20
26
3
1
2
31 30 29
24
8
9
MHA010
R2
+
+
+
+
+
+
+
+
+
+
C15
C17
C16
C19
C18
C14
CL CR
C9
C12 C11 C10
SDA
SCL
R3
C13
VCC
VCAP
Vref
only during
adjustment
Fig.1 Block, application and test diagram.
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
COMPONENT LIST
Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENT VALUE TYPE REMARK
electrolytic
C1
C2
C3
C4
C5
C6
C7
C8
C9
10 µF
63 V
63 V
470 nF
4.7 µF
220 nF
10 µF
4.7 µF
4.7 µF
15 nF
10 µF
10 µF
1 µF
foil
electrolytic
foil
electrolytic
electrolytic
electrolytic
foil
63 V; Ileak < 1.5 µA
63 V
63 V
electrolytic
electrolytic
electrolytic
electrolytic
foil
63 V ±10%
63 V ±10%
63 V
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
CR
1 µF
63 V
47 nF
10 µF
100 nF
4.7 µF
100 nF
100 µF
100 µF
2.2 µF
2.2 µF
2.2 kΩ
8.2 kΩ
160 Ω
±5%
electrolytic
foil
63 V
electrolytic
foil
63 V
electrolytic
electrolytic
electrolytic
electrolytic
16 V
16 V
63 V
63 V
CL
R1
R2
±2%
R3
±2%
Q1
CSB503F58
radial leads
alternative as SMD
CSB503JF958
1995 Jun 19
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
PINNING
SYMBOL
VEO
PIN
DESCRIPTION
1
variable emphasis output for dbx
variable emphasis input for dbx
capacitor noise reduction for dbx
capacitor mute for SAP
VEI
2
CNR
CM
3
4
CDEC
AGND
DGND
SDA
SCL
VCC
5
capacitor DC-decoupling for SAP
analog ground
page
C
C
1
2
32
31
30
29
VEO
VEI
6
S
7
digital ground
W
8
serial data input/output
C
C
3
NR
TS
9
serial clock input
C
C
4
TW
M
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
supply voltage (+9 V)
C
5
28 MAD
DEC
COMP
VCAP
CP1
composite input signal
AGND
6
27 OUTL
capacitor for electronic filtering of supply
capacitor for pilot detector
capacitor for pilot detector
capacitor for phase detector
capacitor for filter adjustment
ceramic resonator
C
C
V
7
26
25
24
23
22
21
20
19
18
17
DGND
SDA
ND
8
CP2
L
TDA9850
CPH
9
SCL
ref
SAP
C
CADJ
CER
CMO
CSS
V
10
11
12
13
14
15
16
CC
COMP
SDE
capacitor DC-decoupling mono
capacitor DC-decoupling stereo/SAP
adjustment capacitor, right channel
output, right channel
V
OUTR
CAP
C
C
R
P1
CR
C
C
P2
SS
OUTR
CSDE
SAP
Vref
C
C
capacitor SAP de-emphasis
SAP output
PH
MO
C
CER
ADJ
reference voltage 0.5 × (VCC − 1.5 V)
adjustment capacitor, left channel
noise detector capacitor
MHA012
CL
CND
OUTL
MAD
CTW
CTS
output, left channel
programmable address bit
capacitor timing wideband for dbx
capacitor timing spectral for dbx
capacitor wideband for dbx
capacitor spectral for dbx
CW
Fig.2 Pin configuration.
CS
1995 Jun 19
6
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
FUNCTIONAL DESCRIPTION
Input level adjustment
Noise detector
The composite input noise increases with decreasing
antenna signal. This makes it necessary to switch stereo
or SAP off at certain thresholds. These thresholds can be
set via the I2C-bus. With ST0 to ST3 (see Table 6) the
stereo threshold can be selected and with SP0 to SP3 the
SAP threshold. A hysteresis can be achieved via software
by making the threshold dependent of the identification
bits STP and SAPP (see Table 2).
The composite input signal is fed to the input level
adjustment stage. The control range is from
−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress
control 4 of Tables 5 and 6 and the level adjust setting of
Table 10 allows an optimum signal adjustment during the
set alignment. The maximum input signal voltage is
2 V (RMS).
Mode selection
Stereo decoder
The stereo/SAP switch feeds either the L − R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/switching circuit. Table 8
shows the different switch modes provided at the output
pins OUTR and OUTL.
The output signal of the level adjustment stage is coupled
to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit. The
decoded sub-signal L − R is sent to the stereo/SAP switch.
To generate the pilot signal the stereo demodulator uses a
PLL circuit including a ceramic resonator. The stereo
channel separation is adjusted by an automatic procedure
to be performed during set production. For a detailed
description see Section “Adjustment procedure”. The
stereo identification can be read by the I2C-bus
dbx decoder
The dbx circuit includes all blocks required for the noise
reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.
SAP output
(see Table 2). Two different pilot thresholds (data
STS = 1; STS = 0) can be selected via the I2C-bus
(see Table 14).
Independent of the stereo/SAP switch, the SAP signal is
also available at pin SAP. At SAP, the SAP signal is not
dbx decoded. The capacitor at SDE provides a
recommended de-emphasis (150 µs) at SAP.
SAP demodulator
The composite signal is fed from the output of the input
level adjustment stage to the SAP demodulator circuit
through a 5fH band-pass filter. The demodulator level is
automatically controlled. The SAP demodulator includes
an internal field strength detector that mutes the SAP
output in the event of insufficient signal conditions. The
SAP identification signal can be read by the I2C-bus
(see Table 2).
Integrated filters
The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.
1995 Jun 19
7
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
Adjustment procedure
MANUAL ADJUSTMENT
Manual adjustment is necessary when no dual tone
COMPOSITE INPUT LEVEL ADJUSTMENT
generator is available (e.g. for service).
Feed in from FM demodulator the composite signal with
100% modulation (25 kHz deviation) L + R; fi = 300 Hz.
Set input level control via I2C-bus monitoring OUTL or
OUTR (500 mV ±20 mV). Store the setting in a
non-volatile memory.
• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
• Composite input L = 300 Hz; 14% modulation
• Adjust channel separation by varying wideband data
• Composite input L = 3 kHz; 14% modulation
• Adjust channel separation by varying spectral data
AUTOMATIC ADJUSTMENT PROCEDURE
• Connect 2.2 µF capacitors from ACR and ACL to
ground.
• Iterative spectral/wideband operation for optimum
adjustment
• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel.
• Store data in non-volatile memory.
After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.
• Mode selection setting bits: STEREO = 1, SAP = 0
(see Table 8).
• Start adjustment by transmission ADJ = 1 in register
ALI3. The decoder will align itself.
TIMING CURRENT FOR RELEASE RATE
• After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an
I2C-bus read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory. The alignment procedure
overwrites the previous data stored in ALI1 and ALI2.
Due to possible internal and external spreading, the timing
current can be adjusted via I2C-bus, see Table 9, as
recommended by dbx.
• The capacitors from ACR and ACL may be
disconnected after alignment.
1995 Jun 19
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
10
UNIT
0
0
0
0
0
0
0
V
V
V
V
V
V
V
VVCAP
VVEO
VSDA
VSCL
Vn
voltage of VCAP to GND
voltage of VEO to GND
voltage of SDA to GND
voltage of SCL to GND
voltage of all other pins to GND
VCC
1⁄2VCC
8.5
8.5
V
CC ≥ 8.5 V
CC < 8.5 V
8.5
V
VCC
+70
+150
Tamb
Tstg
Ves
operating ambient temperature
storage temperature
Tj < 125 °C
−20
−65
°C
°C
electrostatic handling
HBM; note 1
Note
1. Human Body Model (HBM): C = 100 pF; R = 1.5 kΩ; V = 2 kV; charge device model: C = 200 pF; R = 0 Ω;
V = 300 V.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
SOT232-1
SOT287-1
55
68
K/W
K/W
1995 Jun 19
9
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
REQUIREMENTS FOR THE COMPOSITE INPUT SIGNAL TO ENSURE CORRECT SYSTEM PERFORMANCE
SYMBOL
PARAMETER
CONDITIONS
MIN.
162
TYP.
250
MAX. UNIT
COMPL+R(rms) composite input level for 100% measured at COMP
363
mV
modulation L + R (25 kHz
deviation); RMS value;
fi = 300 Hz
∆COMP
composite input level
spreading under operating
conditions
T
amb = −20 to +70 °C; aging;
−0.5
−
+0.5
dB
power supply influence
Zsource
flf
source impedance
note 1
−
−
low-ohmic 5
kΩ
Hz
kHz
%
low frequency roll-off
high frequency roll-off
25 kHz deviation L + R; −2 dB
−
−
−
−
5
fhf
25 kHz deviation L + R; −2 dB 100
−
THDL,R
total harmonic distortion L + R fi = 1 kHz; 25 kHz deviation
−
−
0.5
1.5
fi = 1 kHz; 125 kHz deviation;
note 2
%
S/N
signal-to-noise ratio
L + R/noise
CCIR 468-2 weighted quasi
peak; L + R; 25 kHz deviation;
fi = 1 kHz; 75 µs de-emphasis
critical picture modulation;
note 3
44
54
−
−
dB
with sync only
−
−
−
−
dB
dB
αSB
side band suppression mono
mono signal: 25 kHz deviation, 40
into unmodulated SAP carrier; fi = 1 kHz; side band: SAP
SAP carrier/side band
carrier frequency ±1 kHz
αSP
spectral spurious attenuation
L + R/spurious
50 Hz to 100 kHz;
mainly n × fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference
n = 1, 4, 5, 6
n = 2, 3
35
26
−
−
−
−
dB
dB
Notes
1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by ZO and the composite input
impedance (see Chapter “Characteristics”; row head “Input level adjustment control”) must be taken into account.
2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is
73 kHz).
3. For example colour bar or flat field white; 100% video modulation.
1995 Jun 19
10
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
CHARACTERISTICS
All voltages are measured relative to GND; VCC = 9 V; Rs = 600 Ω; RL = 10 kΩ; AC-coupled; CL = 2.5 nF; fi = 1 kHz;
Tamb = +25 °C; see Fig.1; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCC
supply voltage
8.5
9
9.5
V
Vripple(p-p)
allowed supply voltage
ripple (peak-to-peak
value)
fi = 50 Hz to 100 kHz
−
−
100
mV
ICC
supply current
−
−
58
75
mA
V
Vref
internal reference voltage
at pin Vref
3.7
−
αct
notes 1 and 2
−
110
−
dB
crosstalk between bus
inputs and signal outputs
Input level adjustment control
GLA
input level adjustment
control
−3.5
−
+4.0
dB
Gstep
step resolution
−
0.5
−
−
dB
V
Vi(rms)
maximum input voltage
level (RMS value)
2
−
Zi
input impedance
29.5
35
40.5
kΩ
Stereo decoder
MPXL+R
input voltage level for
input level adjusted via
I2C-bus (L + R;
fi = 300 Hz); monitoring
OUTL or OUTR
−
250
707
−
mV
100% modulation L + R;
25 kHz deviation
(RMS value)
MPXL−R
input voltage level for
100% modulation L − R;
50 kHz deviation
−
−
mV
(peak value)
MPX(max)
MPXpilot
STon(rms)
maximum headroom for
L + R, L, R
fmod < 15 kHz;
THD < 15%
9
−
−
−
dB
nominal stereo pilot
voltage level (RMS value)
−
50
mV
pilot threshold voltage
stereo on (RMS value)
data STS = 1
data STS = 0
data STS = 1
data STS = 0
−
−
35
30
−
mV
mV
mV
mV
dB
−
−
SToff(rms)
pilot threshold voltage
stereo off (RMS value)
15
10
−
−
−
−
Hys
hysteresis
2.5
500
−
OUTL+R
output voltage level for
100% modulation L + R at I2C-bus (L + R;
input level adjusted via
480
520
mV
OUTL, OUTR
fi = 300 Hz); monitoring
OUTL or OUTR
1995 Jun 19
11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
SYMBOL
αcs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
stereo channel separation aligned with dual tone
L/R
14% modulation for each
channel; see Section
“Adjustment procedure”
fL = 300 Hz; fR = 3 kHz 25
fL = 300 Hz; fR = 8 kHz 20
35
30
25
−
−
−
dB
dB
dB
fL = 300 Hz;
fR = 10 kHz
15
fL, R
L, R frequency response 14% modulation;
fref = 300 Hz L or R
fi = 50 Hz to 10 kHz
fi = 12 kHz
−3
−
−
−
dB
dB
%
−3
0.2
−
THDL,R
S/N
total harmonic distortion
L, R
modulation L or R
−
1.0
1% to 100%; fi = 1 kHz
signal-to-noise ratio
mono mode;
50
60
−
−
dB
CCIR 468-2 weighted;
quasi peak; 500 mV
output signal
Stereo decoder, oscillator (VCXO); note 3
fo
nominal VCXO output
frequency (32fH)
with nominal ceramic
resonator
−
503.5
−
kHz
kHz
Hz
fof
spread of free-running
frequency
with nominal ceramic
resonator
500.0
507.0
∆fH
capture range frequency
(nominal pilot)
±190
±265
−
SAP demodulator; note 4
SAPi(rms)
nominal SAP carrier
15 kHz frequency
input voltage level (RMS deviation of intercarrier
value)
−
150
−
mV
SAPon(rms) threshold voltage SAP on
(RMS value)
−
−
−
68
mV
mV
SAPoff(rms)
threshold voltage SAP off
(RMS value)
28
−
SAPhys
SAPLEV
hysteresis
−
−
2
−
−
dB
SAP output voltage level mode selector in position
500
mV
at OUTL, OUTR
SAP/SAP;
fmod = 300 Hz;
100% modulation
fres
frequency response
total harmonic distortion
14% modulation;
50 Hz to 8 kHz;
fref = 300 Hz
−3
−
−
dB
%
THD
fi = 1 kHz
−
0.5
2.0
1995 Jun 19
12
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SAP output
Zo
output impedance
DC output voltage
−
−
5
80
120
−
Ω
VO
RL
0.5VCC−1.5
V
output load resistance
(AC-coupled)
−
−
kΩ
CL
output load capacitance
−
−
2.5
nF
Vo(rms)
nominal output voltage
(RMS value)
150 µs de-emphasis
see Fig.3
Outputs OUTL and OUTR
Vo(rms)
nominal output voltage
100% modulation
−
500
−
mV
(RMS value)
HEADo
Zo
output headroom
output impedance
DC output voltage
9
−
−
dB
−
80
120
Ω
VO
0.45VCC−1.5 0.5VCC−1.5 0.55VCC−1.5 V
RL
output load resistance
(AC-coupled)
5
−
−
kΩ
CL
output load capacitance
crosstalk L, R into SAP
−
−
2.5
nF
dB
αct
100% modulation;
fi = 1 kHz; L or R;
mode selector switched
to SAP/SAP
50
75
−
crosstalk SAP into L, R
100% modulation;
fi = 1 kHz; SAP;
mode selector switched
to stereo
50
70
−
dB
dB
∆VST-SAP
output voltage difference 250 Hz to 6.3 kHz
−
−
3
if switched from L, R to
SAP
Dbx noise reduction circuit
tadj stereo adjustment time
see Section “Adjustment
procedure”
−
−
−
1
s
Is
nominal timing current for Is can be measured at pin
24
−
µA
nominal release rate of
spectral RMS detector
CTS via current meter
connected to
1⁄2VCC + 0.25 V
∆Is
spread of timing current
timing current range
−15
−
−
+15
−
%
Is range
It
7 steps via I2C-bus
±30
1⁄3Is
%
timing current for release
rate of wideband RMS
detector
−
−
µA
Relrate
nominal RMS detector
release rate
nominal timing current
and external capacitor
values
wideband
spectral
−
−
125
381
−
−
dB/s
dB/s
1995 Jun 19
13
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Noise detector
f0
noise band-pass centre
frequency
composite input level
100 mV (RMS)
−
185
−
kHz
Q
quality factor
−
6
−
−
Ster1,
SAP1
lowest noise threshold
for stereo off respectively
SAP off (RMS value;
see Tables 11 and 12)
fi = 185 kHz
17
24
34
mV
Ster16,
SAP16
highest noise threshold
for stereo off respectively
SAP off (RMS value)
fi = 185 kHz
210
0
290
1.5
400
3
mV
dB
∆Ster,
∆SAP
noise threshold step width fi = 185 kHz
Power-on reset; note 5
VRESET(STA) start of reset voltage
increasing supply voltage −
−
2.5
5.8
V
V
decreasing supply
voltage
4.2
5
VRESET(END) end of reset voltage
increasing supply voltage 5.2
6
6.8
V
Digital part (I2C-bus pins); note 6
VIH
VIL
IIH
HIGH level input voltage
LOW level input voltage
3
−
−
−
−
−
8.5
V
−0.3
+1.5
+10
+10
0.4
V
HIGH level input current
−10
−10
−
µA
µA
V
IIL
LOW level input current
VOL
LOW level output voltage IIL = 3 mA
Notes to the characteristics
Vbus(p-p)
1. Crosstalk: 20 log
--------------------
Vo(rms)
2. The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).
3. The oscillator is designed to operate together with MURATA resonator CSB503F58 or CSB503JF958 as SMD.
Change of the resonator supplier is possible, but the resonator specification must be close to the specified ones.
4. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.
5. When reset is active the SMU-bit (SAP mute) and the LMU-bit (OUTL, OUTR mute) is set and the I2C-bus receiver
is in the reset position.
6. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification.
Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011).
1995 Jun 19
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
I2C-BUS PROTOCOL
I2C-bus format to read (slave transmits data)
S
SLAVE ADDRESS
R/W
A
DATA
MA
DATA
P
Table 1 Explanation of I2C-bus format to read (slave transmits data)
NAME
DESCRIPTION
S
START condition; generated by the master
1011011 pin MAD not connected
Standard SLAVE ADDRESS (MAD)
Pin programmable SLAVE ADDRESS
1011010 pin MAD connected to ground
1 (read); generated by the master
R/W
A
acknowledge; generated by the slave
slave transmits an 8-bit data word
DATA
MA
P
acknowledge; generated by the master
STOP condition; generated by the master
Table 2 Definition of the transmitted bytes after read condition
MSB
LSB
D0
FUNCTION
BYTE
D7
D6
D5
D4
D3
D2
D1
Alignment read 1
Alignment read 2
ALR1
ALR2
Y
Y
SAPP
SAPP
STP
STP
A14
A24
A13
A23
A12
A22
A11
A21
A10
A20
Table 3 Function of the bits in Table 2
BITS
FUNCTION
STP
stereo pilot identification (stereo received = 1)
SAP pilot identification (SAP received = 1)
stereo alignment read data
for wideband expander
SAPP
A1X to A2X
A1X
A2X
for spectral expander
Y
indefinite
The master generates an acknowledge when it has received the first data word, ALR1, then the slave transmits the next
data word ALR2. The master next generates an acknowledge, then slave begins transmitting the first data word ALR1,
and so on until the master generates no acknowledge and transmits a STOP condition.
1995 Jun 19
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
I2C-bus format to write (slave receives data)
S
SLAVE ADDRESS
R/W
A
SUBADDRESS
A
DATA
A
P
Table 4 Explanation of I2C-bus format to write (slave receives data)
NAME
DESCRIPTION
S
START condition
Standard SLAVE ADDRESS (MAD)
101 101 1 pin MAD not connected
101 101 0 pin MAD connected to ground
0 (write)
Pin programmable SLAVE ADDRESS
R/W
A
acknowledge; generated by the slave
see Table 5
SUBADDRESS (SAD)
DATA
P
see Table 6
STOP condition
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5 Subaddress second byte after MAD
MSB
LSB
FUNCTION
Control 1
REGISTER
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
CON1
CON2
CON3
CON4
ALI1
Control 2
0
0
0
0
0
1
0
1
Control 3
0
0
0
0
0
1
1
0
Control 4
0
0
0
0
0
1
1
1
Alignment 1
Alignment 2
Alignment 3
0
0
0
0
1
0
0
0
ALI2
0
0
0
0
1
0
0
1
ALI3
0
0
0
0
1
0
1
0
Table 6 Definition of third byte, third byte after MAD and SAD
MSB
LSB
D0
FUNCTION
Control 1
REGISTER
D7
D6
D5
D4
D3
D2
D1
CON1
CON2
CON3
CON4
ALI1
0
0
0
0
0
0
0
0
0
0
0
0
0
ST3
SP3
LMU
L3
ST2
SP2
0
ST1
SP1
0
ST0
SP0
0
Control 2
Control 3
SAP STEREO
SMU
0
Control 4
0
0
0
0
0
L2
L1
L0
Alignment 1
Alignment 2
Alignment 3
0
A14
A24
0
A13
A23
0
A12
A22
TC2
A11
A21
TC1
A10
A20
TC0
ALI2
STS
ADJ
ALI3
1995 Jun 19
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
Table 7 Function of the bits in Table 6
BITS
FUNCTION
ST0 to ST3
SP0 to SP3
STEREO, SAP
LMU
noise threshold for stereo
noise threshold for SAP
mode selection
mute control OUTL and OUTR
mute control SAP
SMU
L0 to L3
ADJ
input level adjustment
stereo adjustment on/off
stereo alignment data
for wideband expander
for spectral expander
timing current alignment data
stereo level switch
A1X to A2X
A1X
A2X
TC0 to TC2
STS
Table 8 Mode selection
FUNCTION MODE AT
DATA
SETTING BITS
TRANSMISSION STATUS
INTERNAL SWITCH, READABLE BITS: STP, SAPP
OUTL
SAP
OUTR
SAP
STEREO
SAP
SAP received
1
1
1
1
0
0
0
1
1
0
0
1
1
0
Mute
Left
mute
right
no SAP received
STEREO received
no STEREO received
SAP received
Mono
Mono
Mono
Mono
mono
SAP
mute
mono
no SAP received
independent
Table 9 Timing current setting
DATA
FUNCTION
IS RANGE
TC2
TC1
TC0
+30%
+20%
+10%
Nominal
−10%
−20%
−30%
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1995 Jun 19
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
Table 10 Level adjust setting
Table 12 SAP noise threshold (SAP)
DATA
DATA
GL
(dB)
THRESHOLD
L3
L2
L1
L0
SP3
SP2
SP1
SP0
+4.0
+3.5
+3.0
+2.5
+2.0
+1.5
+1.0
+0.5
0.0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
SAP1
SAP2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SAP3
SAP4
SAP5
SAP6
SAP7
SAP8
SAP9
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
−3.5
SAP10
SAP11
SAP12
SAP13
SAP14
SAP15
SAP16
Table 11 Stereo noise threshold (Ster)
Table 13 ADJ bit setting
DATA
FUNCTION
DATA
THRESHOLD
Stereo decoder operation mode
0
1
ST3
ST2
ST1
ST0
Auto adjustment of channel separation
Ster1
Ster2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 14 STS bit setting (pilot threshold stereo on)
FUNCTION DATA
Ster3
Ster4
STon ≤ 35 mV
STon ≤ 30 mV
1
0
Ster5
Ster6
Ster7
Table 15 Mute setting
Ster8
DATA
LMU
DATA
SMU
Ster9
FUNCTION
FUNCTION
Ster10
Ster11
Ster12
Ster13
Ster14
Ster15
Ster16
Forced mute at
OUTR, OUTL
1
forced mute at
SAP
1
No forced
mute at OUTR,
OUTL
0
no forced mute at
SAP
0
1995 Jun 19
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
Table 16 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2
DATA
FUNCTION
D4
D3
D2
D1
D0
AX4
AX3
AX2
AX1
AX0
Gain increase
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Nominal gain
Gain decrease
1995 Jun 19
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
MHA011
3
10
V
SAP
(1)
(mV RMS)
(2)
2
10
(3)
10
1
10
−1
f (kHz)
1
10
i
150 µs de-emphasis.
(1) 100% modulation.
(2) 14% modulation.
(3) 1% modulation.
Fig.3 Voltage at SAP output.
1995 Jun 19
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
INTERNAL PIN CONFIGURATIONS
2
1
V
b
V
b
600 Ω
MHA013
MHA014
Fig.4 Pin 1; VEO.
Fig.5 Pin 2; VEI.
4
3
V
V
b
b
10 kΩ
10 kΩ
MHA015
MHA016
Fig.6 Pin 3; CNR
.
Fig.7 Pin 4; CM.
5
8
V
b
1.8 kΩ
20 kΩ
20 kΩ
MHA018
MHA017
Fig.8 Pin 5; CDEC
.
Fig.9 Pin 8; SDA.
1995 Jun 19
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
12
10
9
4.7 kΩ
300 Ω
1.8 kΩ
200 Ω
MHA019
V
b
MHA020
Fig.10 Pin 9; SCL.
Fig.11 Pin 10; VCC and pin 12; VCAP.
11
V
b
13
V
b
30 kΩ
3.5 kΩ
MHA022
MHA021
Fig.12 Pin 11; COMP.
Fig.13 Pin 13; CP1.
V
b
14
15
V
b
8.5 kΩ
12 kΩ
10 kΩ
10 kΩ
MHA024
MHA023
Fig.14 Pin 14; CP2.
Fig.15 Pin 15; CPH.
1995 Jun 19
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
17
16
V
b
V
b
3 kΩ
MHA025
MHA026
Fig.16 Pin 16; CADJ
.
Fig.17 Pin 17; CER.
20
18
V
b
V
b
20 kΩ
20 kΩ
10 kΩ
10 kΩ
MHA027
MHA028
Fig.18 Pin 18; CMO and pin 19; CSS
.
Fig.19 Pin 20; CR and pin 25; CL.
V
b
21
22
V
b
5 kΩ
10 kΩ
MHA030
MHA029
Fig.20 Pin 21; OUTR and pin 27 OUTL.
Fig.21 Pin 22; CSDE.
1995 Jun 19
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
24
V
b
23
V
b
3.4 kΩ
3.4 kΩ
MHA031
MHA032
Fig.22 Pin 23; SAP.
Fig.23 Pin 24; Vref.
26
28
V
V
b
b
1.8 kΩ
30 kΩ
MHA033
MHA034
Fig.24 Pin 26; CND
.
Fig.25 Pin 28; MAD.
31
29
V
b
V
b
4.6 kΩ
MHA035
MHA036
Fig.26 Pin 29; CTW and pin 30; CTS
.
Fig.27 Pin 31; CW and pin 32; CS.
1995 Jun 19
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
PACKAGE OUTLINES
SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
SOT232-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
32
17
pin 1 index
E
1
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
29.4
28.5
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT232-1
1995 Jun 19
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
SO32: plastic small outline package; 32 leads; body width 7.5 mm
SOT287-1
D
E
A
X
c
y
H
v
M
A
E
Z
17
32
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
16
1
w M
detail X
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.
0.3
0.1
2.45
2.25
0.49
0.36
0.27 20.7
0.18 20.3
7.6
7.4
10.65
10.00
1.1
0.4
1.2
1.0
0.95
0.55
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25
0.01
0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.086
0.02 0.011 0.81
0.01 0.007 0.80
0.30
0.29
0.419
0.394
0.043 0.047
0.016 0.039
0.037
0.022
inches 0.10
0.004
0.055
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-25
97-05-22
SOT287-1
1995 Jun 19
26
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
SOLDERING DIP, SDIP, HDIP, DBS and SIL
Introduction
Reflow soldering
Reflow soldering techniques are suitable for all
SO packages.
There is no soldering method that is ideal for all
IC packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Soldering by dip or wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
Wave soldering
Wave soldering techniques can be used for all
SO packages if the following conditions are observed:
The device may be mounted to the seating plane, but the
temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
Repairing soldered joints
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
SOLDERING SO
Introduction
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
There is no soldering method that is ideal for all
IC packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
cases reflow soldering is often used.
Repairing soldered joints
Fix the component by first soldering two
diagonally-opposite end leads. Use only a low voltage
soldering iron (less than 24 V) applied to the flat part of the
lead. Contact time must be limited to 10 seconds at up to
300 °C. When using a dedicated tool, all other leads can
be soldered in one operation within 2 to 5 seconds at
between 270 and 320 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
1995 Jun 19
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Jun 19
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
NOTES
1995 Jun 19
29
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
NOTES
1995 Jun 19
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP decoder
TDA9850
NOTES
1995 Jun 19
31
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
Japan: Philips Bldg 13-37, Kohnan2-chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5130, Fax. (03)3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
SCD40
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
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Tel. 9-5(800)234-7381, Fax. (708)296-8556
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
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533061/1500/01/pp32
Date of release: 1995 Jun 19
9397 750 00176
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022)74 8000, Fax. (022)74 8341
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