TDA9851T-T [NXP]
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NXP 
INTEGRATED CIRCUITS
DATA SHEET
TDA9851
I2C-bus controlled economic BTSC
stereo decoder
1997 Nov 12
Product specification
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
FEATURES
• Voltage Controlled Amplifier (VCA) noise reduction
circuit
• Stereo or mono selectable at the AF outputs
• Stereo pilot PLL circuit with ceramic resonator
• Automatic pilot cancellation
• Automatic Volume Level (AVL) control (+6 to −15 dB)
• I2C-bus transceiver.
GENERAL DESCRIPTION
The TDA9851 is a bipolar-integrated BTSC stereo
decoder for application in TV sets, VCRs and multimedia
PCs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
TYP. MAX. UNIT
VCC
8
9
9.5
40
−
V
ICC
supply current
−
−
30
500
mA
mV
Vo(rms)
output voltage (RMS value)
composite input voltage
250 mV (RMS) for
100% modulation L + R
(25 kHz deviation); fmod = 300 Hz
αcsL,R
THDL,R
S/N
stereo channel separation
L and R
14% modulation; fL = 300 Hz;
fR = 3 kHz
−
−
20
−
dB
%
total harmonic distortion L and R 100% modulation L or R;
mod = 1 kHz
0.2
1.0
f
signal-to-noise ratio
mono mode; referenced to 500 mV
output signal
CCIR 468-2 weighted;
quasi peak
50
60
73
−
−
dB
DIN noise weighting filter
(RMS value)
−
dBA
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA9851
SDIP24
SO24
plastic shrink dual in-line package; 24 leads (400 mil)
plastic small outline package; 24 leads; body width 7.5 mm
SOT234-1
SOT137-1
TDA9851T
1997 Nov 12
2
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
BLOCK DIAGRAM
HM6A9
b
1997 Nov 12
3
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
Component list
Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENT VALUE TYPE REMARK
2.2 µF electrolytic
C1
C2
C3
C4
C5
C6
C7
C9
63 V
63 V
220 nF
2.2 µF
220 nF
2.2 µF
2.2 µF
4.7 µF
22 nF
foil
electrolytic
foil
electrolytic
electrolytic
electrolytic
foil
63 V
63 V
63 V ±10%
C10
C11
C13
C14
C15
R1
4.7 nF
1 µF
foil
electrolytic
electrolytic
electrolytic
electrolytic
63 V
63 V
16 V
16 V
10 µF
100 µF
100 µF
3.3 kΩ
15 kΩ
1.3 kΩ
100 kΩ
R2
R3
R4
Q1
CSB503F58
radial leads
CSB503JF958
alternative as SMD
1997 Nov 12
4
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
PINNING
SYMBOL PIN
DESCRIPTION
SCL
VCC
1
2
3
4
5
6
7
8
9
serial clock input (I2C-bus)
supply voltage
CPH
capacitor for phase detector
ceramic resonator
CER
CP1
handbook, halfpage
SCL
SDA
1
2
24
capacitor for pilot detector
capacitor for pilot detector
composite input signal
V
CP2
DGND
AGND
FDI
23
22
21
20
19
18
CC
COMP
CMO
CSS
C
3
PH
capacitor DC-decoupling mono
capacitor DC-decoupling stereo
CER
4
C
FDO
5
P1
RFR
10 resistor for filter reference
11 not connected
C
6
BPU
P2
n.c.
TDA9851
C
COMP
7
W
OUTL
OUTR
Vref
12 output, left channel
13 output, right channel
14 reference voltage 0.5VCC
C
8
17 TW
C
MO
C
9
16
15
14
13
SS
AV
VCAP
capacitor for electronic filtering of
supply
R
V
V
10
11
12
FR
CAP
ref
15
n.c.
CAV
TW
CW
16 automatic volume control capacitor
17 capacitor timing
OUTL
OUTR
MHA968
capacitor for VCA and band-pass filter
lower corner frequency
18
BPU
band-pass filter upper corner
frequency
19
FDO
20 fixed de-emphasis output
21 fixed de-emphasis input
22 analog ground
FDI
AGND
DGND
SDA
23 digital ground
24 serial data input/output (I2C-bus)
Fig.2 Pin configuration.
1997 Nov 12
5
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
an input voltage range between 0.1 to 1.1 V (RMS).
The circuit adjusts variations in modulation during
FUNCTIONAL DESCRIPTION
Stereo decoder
broadcasting and because of changes in the programme
material. The function can be switched off. To avoid
audible plops during the permanent operation of the AVL
circuit a soft blending scheme has been applied between
the different gain stages. A capacitor (4.7 µF) at pin CAV
determines the attack and decay time constants.
In addition the ratio of attack and decay times can be
changed via the I2C-bus.
The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator.
The main L + R signal passes a 75 µs fixed de-emphasis
filter and is fed into the dematrix circuit. The decoded
sub-signal L − R is sent to the VCA circuit. To generate the
pilot signal the stereo demodulator uses a PLL circuit
including a ceramic resonator.
Integrated filters
Mode selection
The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled by the filter reference circuit via
the external resistor R4.
The L − R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via
the I2C-bus.
Automatic volume level control
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
SDA, VSCL
PARAMETER
CONDITIONS
MIN.
MAX.
9.9
UNIT
supply voltage
0
0
0
0
V
V
voltage of SDA and SCL to GND
VCC < 9 V
VCC
9
V
V
CC ≥ 9 V
V
Vn
voltage of all other pins to GND
operating ambient temperature
storage temperature
VCC
+70
+150
−
V
Tamb
Tstg
Ves
Tj < 125 °C
−20
−65
−
°C
°C
V
electrostatic handling
note 1
Note
1. Machine model class B.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
TDA9851 (SOT234-1; SDIP24)
55
90
K/W
K/W
TDA9851T (SOT137-1; SO24)
1997 Nov 12
6
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
CHARACTERISTICS
All voltages are measured relative to GND; VCC = 9 V; Rs = 600 Ω; AC-coupled; RL = 10 kΩ; CL = 2.5 nF; fmod = 1 kHz
mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); Tamb = 25 °C;
see Fig.1; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VCC
ICC
supply voltage
8
9
9.5
V
supply current
−
30
40
mA
Input stage
Vi(max)(rms)
maximum input voltage
(RMS value)
2
−
−
V
Zi
input impedance
20
25
30
kΩ
Stereo decoder
HR
headroom for L + R, L and R
fmod = 300 Hz; THD < 15%
9
−
−
−
dB
Vpil(rms)
nominal stereo pilot voltage
(RMS value)
−
50
mV
Vth(on)(rms)
Vth(off)(rms)
pilot threshold voltage
stereo on (RMS value)
−
−
35
mV
mV
pilot threshold voltage
stereo off (RMS value)
15
−
−
hys
hysteresis
−
−
2.5
−
−
dB
Vo(rms)
output voltage (RMS value)
100% modulation L + R;
fmod = 300 Hz
500
mV
αcsL,R
THDL,R
S/N
stereo channel separation
L and R
14% modulation; fL = 300 Hz;
fR = 3 kHz
−
−
20
−
dB
%
total harmonic distortion
L and R
100% modulation L or R;
fmod = 1 kHz
0.2
1.0
signal-to-noise ratio
mono mode; referenced to
500 mV output signal
CCIR 468-2 weighted;
quasi peak
50
60
73
−
−
dB
DIN noise weighting filter
(RMS value)
−
dBA
Stereo decoder, oscillator (VCXO); note 1
fo
nominal VCXO output
frequency (32fH)
with nominal ceramic
resonator
−
503.5
−
−
kHz
kHz
Hz
∆ffr
∆fcr
spread of free-running
frequency
with nominal ceramic
resonator
500.0
±190
507.0
capture range frequency
nominal pilot
±265
−
1997 Nov 12
7
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Outputs OUTL and OUTR
Zo
output impedance
−
80
120
Ω
VO
RL
DC output voltage
0.45VCC 0.5VCC
0.55VCC
V
output load resistance
(AC-coupled)
5
−
−
kΩ
CL
output load capacitance
−
−
2.5
nF
dB
αct
crosstalk SAP into L and R
100% modulation;
mod = 1 kHz; SAP;
50
70
−
f
mode selector switched to
stereo
VCA
Is
nominal timing current for
nominal release rate of VCA
detector
Is can be measured at pin TW 6.5
via current meter connected to
0.5VCC + 1 V
8
9.5
µA
Relrate
nominal detector release rate nominal timing current and
external capacitor values
−
125
−
dB/s
Automatic volume level control
Gv
voltage gain
maximum boost; note 2
5
6
7
dB
dB
dB
maximum attenuation; note 2
14
−
15
1.5
16
−
Gstep
equivalent step width between
the input stages (soft switching
system)
Viop(rms)
input voltage (RMS value)
maximum boost; note 2
−
0.1
−
V
maximum attenuation; note 2
−
1.125
200
−
V
Vo(rms)
output voltage in AVL
operation (RMS value)
160
250
mV
Voffset(DC)
DC offset voltage between
different gain steps
voltage at pin CAV
7.0 to 6.83 V or
−
−
20
mV
6.83 to 6.61 V or
6.61 to 5.83 V or
5.83 to 3.1 V; note 3
Ratt
discharge resistors for attack
time constant
AT1 = 0; AT2 = 0; note 4
AT1 = 1; AT2 = 0; note 4
AT1 = 0; AT2 = 1; note 4
AT1 = 1; AT2 = 1; note 4
340
590
0.96
1.7
420
730
1.2
2.1
2.0
30
520
910
1.5
2.6
2.4
−
Ω
Ω
kΩ
kΩ
µA
µA
Idec
charge current for decay time normal mode; CCD = 0; note 5 1.6
power-on speed-up; CCD = 1;
−
note 5
Muting at power supply voltage drop for OUTR and OUTL
∆VCC
supply voltage drop for mute
active
−
V
CAP − 0.7 −
V
1997 Nov 12
8
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
SYMBOL
Power-on reset; note 6
VPOR(start) start of reset voltage
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
increasing supply voltage
decreasing supply voltage
increasing supply voltage
−
−
5
6
2.5
5.8
6.8
V
V
V
4.2
5.2
VPOR(end)
end of reset voltage
Digital part (I2C-bus pins); note 7
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
LOW-level input current
LOW-level output voltage
3
−
−
−
−
−
V
CC ≤ 9
V
−0.3
−10
−10
−
+1.5
+10
+10
0.4
V
µA
µA
V
IIL
VOL
IIL = 3 mA
Notes to the characteristics
1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change
of the resonator supplier is possible, but the resonator specification must be close to the specified ones.
2. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off.
3. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.
4. Attack time constant = CCAV × Ratt.
–G1
–G2
----------
----------
C
CAV × 0.76 V 10 20 – 10 20
5. Decay time =
----------------------------------------------------------------------------------
Idec
Example: CCAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s.
6. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position.
7. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification.
Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011).
1997 Nov 12
9
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
I2C-BUS PROTOCOL
I2C-bus format to read (slave transmits data)
S
SLAVE ADDRESS
R/W
A
DATA
P
Table 1 Explanation of I2C-bus format to read (slave transmits data)
NAME
DESCRIPTION
S
START condition; generated by the master
101 101 1
Standard SLAVE ADDRESS (MAD)
R/W
A
logic 1 (read); generated by the master
acknowledge; generated by the slave
slave transmits an 8-bit data word
STOP condition; generated by the master
DATA
P
Table 2 Definition of the transmitted bytes after read condition
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Y
Y
Y
Y
Y
Y
Y
STP
Table 3 Function of the bits in Table 2
BITS
FUNCTION
STP
Y
stereo pilot identification (stereo received = 1)
indefinite
I2C-bus format to write (slave receives data)
S
SLAVE ADDRESS
R/W
A
DATA
A
P
Table 4 Explanation of I2C-bus format to write (slave receives data)
NAME
DESCRIPTION
S
START condition
101 101 1
Standard SLAVE ADDRESS (MAD)
R/W
A
logic 0 (write)
acknowledge; generated by the slave
see Table 5
DATA
P
STOP condition
Table 5 Definition of the DATA (second byte after MAD)
MSB
LSB
D0
D7
D6
D5
D4
D3
D2
D1
0
0
AT2
AT1
CCD
AVLON
GMU
STEREO
1997 Nov 12
10
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
Table 6 Function of the bits in Table 5
Table 9 AVLON bit setting
BITS
FUNCTION
FUNCTION
DATA
STEREO
GMU
mode selection stereo or mono
mute control OUTL and OUTR
AVL on/off
Automatic volume control on
Automatic volume control off
1
0
AVLON
CCD
Table 10 CCD bit setting
increased AVL decay current on/off
AT1 and AT2 attack time at AVL
FUNCTION
DATA
Load current for normal AVL decay time
Increased load current
0
1
Table 7 Mode setting
FUNCTION MODE
READABLE BIT SETTING BIT
Table 11 AVL attack time
STP
STEREO
OUTL
Left
OUTR
right
DATA
1 (stereo
1
Ratt
received)
(Ω)
AT1
AT2
Mono
Mono
Mono
mono
mono
mono
1 (stereo
received)
0
1
0
420
730
0
1
0
1
0
0
1
1
0 (no stereo
received)
1200
2100
0 (no stereo
received)
Table 8 Mute setting
FUNCTION
DATA
GMU
Forced mute at OUTR and OUTL
No forced mute at OUTR and OUTL
1
0
1997 Nov 12
11
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
INTERNAL PIN CONFIGURATIONS
1
2
1.8 kΩ
+
MHA972
MHA971
Fig.3 Pin 1; SCL.
Fig.4 Pin 2; VCC.
3
4
+
+
3 kΩ
MHA974
10 kΩ
10 kΩ
MHA973
Fig.5 Pin 3; CPH
.
Fig.6 Pin 4; CER.
6
+
5
+
3.5 kΩ
8.5
12
kΩ
kΩ
MHA975
MHA976
Fig.7 Pin 5; CP1.
Fig.8 Pin 6; CP2.
1997 Nov 12
12
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
7
+
8, 9
+
25 kΩ
25 kΩ
25 kΩ
50 pF
100 pF
10 kΩ
10 kΩ
MHA978
MHA977
Fig.9 Pin 7; COMP.
Fig.10 Pin 8; CMO and pin 9; CSS
.
+
12, 13
80 Ω
1 kΩ
+
10
MHA979
MHA980
Fig.11 Pin 10; RFR
.
Fig.12 Pin 12; OUTL and pin 13; OUTR.
14
+
15
3.4
kΩ
4.7 kΩ
300 Ω
3.4
kΩ
5 kΩ
MHA982
MHA981
Fig.13 Pin 14; Vref.
Fig.14 Pin 15; VCAP.
1997 Nov 12
13
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
17
16
+
+
MHA983
MHA984
Fig.15 Pin 16; CAV
.
Fig.16 Pin 17; TW.
+
21
18
+
+
6 kΩ
16 kΩ
19
MHA985
MHA986
Fig.17 Pin 18; CW.
Fig.18 Pin 19; BPU and pin 21; FDI.
24
20
1.8 kΩ
+
MHA987
MHA988
Fig.19 Pin 20; FDO.
Fig.20 Pin 24; SDA.
1997 Nov 12
14
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
APPLICATION INFORMATION
HM9A70
bnok,lfuapgedwith
1997 Nov 12
15
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
PACKAGE OUTLINES
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
1
(1)
(1)
Z
w
UNIT
b
b
c
D
E
e
e
L
M
M
1
1
E
H
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT234-1
1997 Nov 12
16
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT137-1
075E05
MS-013AD
1997 Nov 12
17
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SDIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1997 Nov 12
18
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder
TDA9851
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Nov 12
19
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp20
Date of release: 1997 Nov 12
Document order number: 9397 750 02702
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