TDA9870A_技术文档

INTEGRATED CIRCUITS

DATA SHEET

TDA9870A

Digital TV Sound Processor

(DTVSP)

1998 Aug 10

Product speciﬁcation

File under Integrated Circuits, IC02

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

CONTENTS

1

FEATURES

1.1

1.2

1.3

Demodulator and decoder section

DSP section

Analog audio section

2

GENERAL DESCRIPTION

Supported standards

ORDERING INFORMATION

BLOCK DIAGRAM

2.1

3

4

5

PINNING

6

FUNCTIONAL DESCRIPTION

6.1

Description of the demodulator and decoder

section

6.2

6.3

Description of the DSP

Description of the analog audio section

7

LIMITING VALUES

8

THERMAL CHARACTERISTICS

CHARACTERISTICS

I²C-BUS CONTROL

9

10

10.1

10.2

10.3

10.4

10.5

Introduction

Power-up state

Slave receiver mode

Slave transmitter mode

Expert mode

11

12

13

14

15

I²S-BUS DESCRIPTION

EXTERNAL COMPONENTS

APPLICATION CIRCUITRY

PACKAGE OUTLINE

SOLDERING

15.1

15.2

15.3

Introduction

Soldering by dipping or by wave

Repairing soldered joints

16

17

18

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

1998 Aug 10

2

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

1

FEATURES

1.1

Demodulator and decoder section

• Sound IF (SIF) input switch e.g. to select between

terrestrial TV SIF and SAT SIF sources

• SIF AGC with 24 dB control range

2

GENERAL DESCRIPTION

• SIF 8-bit Analog-to-Digital Converter (ADC)

• Two-carrier multistandard FM demodulation (B/G, D/K

and M standard)

The TDA9870A is a single-chip Digital TV Sound

Processor (DTVSP) for analog multi-channel sound

systems in TV sets and satellite receivers.

• Decoding for three analog multi-channel systems (A2,

A2+ and A2*) and satellite sound

2.1

Supported standards

• Programmable identification (B/G, D/K and M standard)

and different identification times.

The multistandard/multi-stereo capability of the

TDA9870A is mainly of interest in Europe, but also in Hong

Kong/Peoples Republic of China and South East Asia.

This includes B/G, D/K, I, M and L standard. In other

application areas there exists only subsets of those

standard combinations otherwise only single standards

are transmitted.

1.2

DSP section

• Digital crossbar switch for all digital signal sources and

destinations

• Control of volume, balance, contour, bass, treble,

pseudo stereo, spatial, bass boost and soft-mute

M standard is transmitted in Europe by the American

Forces Network (AFN) with European channel spacing

(7 MHz VHF, 8 MHz UHF) and monaural sound.

• Plop-free volume control

• Automatic Volume Level (AVL) control

• Adaptive de-emphasis for satellite

• Programmable beeper

Korea has a stereo sound system similar to Europe and is

supported by the TDA9870A. Differences include

deviation, modulation contents and identification. It is

based on M standard.

• Monitor selection for FM/AM DC values and signals,

with peak detection option

• I²S-bus interface for a feature extension (e.g. Dolby

surround) with matrix, level adjust and mute.

An overview of the supported standards and sound

systems and their key parameters is given in Table 1.

The analog multi-channel sound systems (A2, A2+ and

A2*) are sometimes also named 2CS (2-Carrier Systems).

1.3

Analog audio section

• Analog crossbar switch with inputs for mono and stereo

(also applicable as SCART 3 input), SCART 1

input/output, SCART 2 input/output and line output

• User defined full-level/−3 dB scaling for SCART outputs

• Output selection of mono, stereo, dual A/B, dual A or

dual B

• 20 kHz bandwidth for SCART-to-SCART copies

• Standby mode with functionality for SCART copies

• Dual audio Digital-to-Analog Converter (DAC) from DSP

to analog crossbar switch, bandwidth of 15 kHz

• Dual audio ADC from analog inputs to DSP

• Two dual audio DACs for loudspeaker (Main) and

headphone (Auxiliary) outputs; also applicable for

L, R, C and S in the Dolby Pro Logic mode with feature

extension.

1998 Aug 10

3

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

2.1.1

ANALOG 2-CARRIER SYSTEMS

Table 1 Frequency modulation

CARRIER

FREQUENCY

(MHz)

FM DEVIATION (kHz)

MODULATION

BANDWIDTH/

DE-EMPHASIS

(kHz/µs)

SOUND

SYSTEM

STANDARD

NOM.

MAX.

OVER

SC1

SC2

M

mono

A2+

A2

4.5

15

27

25

50

80

mono

¹⁄₂(L + R) ¹⁄₂(L − R)

¹⁄₂(L + R)

−

15/75

15/75 (Korea)

15/50

4.5/4.724

5.5/5.742

6.0

B/G

I

R

−

mono

A2

mono

15/50

D/K

6.5/6.742

6.5/6.258

¹⁄₂(L + R)

R

15/50

A2*

15/50

Table 2 Identiﬁcation for A2 systems

PARAMETER

A2/A2*

A2+ (KOREA)

Pilot frequency

54.6875 kHz = 3.5 × line frequency

55.0699 kHz = 3.5 × line frequency

Stereo identiﬁcation

frequency

line frequency

117.5 Hz =

149.9 Hz =

--------------------------------------

133

--------------------------------------

105

Dual identiﬁcation frequency

line frequency

--------------------------------------

57

line frequency

--------------------------------------

57

274.1 Hz =

276.0 Hz =

AM modulation depth

50%

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

2.1.2

SATELLITE SYSTEMS

An important specification for satellite TV reception is the “Astra specification”. The TDA9870A is suited for the reception

of Astra and other satellite signals.

Table 3 FM satellite sound

BANDWIDTH/

MODULATION DE-EMPHASIS

CARRIER

TYPE

CARRIER

FREQUENCY (MHz)

MODULATION

INDEX

MAXIMUM

FM DEVIATION (kHz)

(kHz/µs)

Main

Sub

6.50⁽¹⁾

0.26

0.15

85

50

mono

15/50⁽¹⁾

7.02/7.20

7.38/7.56

7.74/7.92

8.10/8.28

m/st/d⁽²⁾

15/adaptive⁽³⁾

Notes

1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis

of 60 µs, or in accordance with J17, is available.

2. m/st/d = mono or stereo or dual language sound.

3. Adaptive de-emphasis is compatible to transmitter specification.

3

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

TDA9870A

SDIP64

plastic shrink dual in-line package; 64 leads (750 mil)

SOT274-1

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

4

BLOCK DIAGRAM

SIF2

10

SIF1

12

handbook, full pagewidth

9

P1

P2

7

6

20

3

V

I

DEC1

SSA1

ref1

SUPPLY

SOUND IF

(SIF)

ADDR1

ADDR2

SCL

2

I C-BUS

INPUT SWITCH

AGC, ADC

11

8

13

4

INTERFACE

ref

5

SDA

FM (AM)

DEMODULATION

IDENTIFICATION

33

34

SCIR1

SCIL1

SCIR2

SCIL2

EXTIR

EXTIL

18

19

21

XTALI

XTALO

36

37

A2/SATELLITE

DECODER

CLOCK

SYSCLK

31

32

29

ANALOG

CROSSBAR

SWITCH

MONOIN

47

SCOR1

SCOL1

SCOR2

SCOL2

LOR

48

51

52

63

62

PEAK

DETECTION

LEVEL

ADJUST

LOL

27

26

25

24

22

23

SDI1

SDI2

SDO1

SDO2

SCK

1

2

i.c.

ADC (2)

2

41

42

44

45

I S-BUS

INTERFACE

DIGITAL

SELECT

WS

15

64

14

49

35

17

16

V

DDD1

DAC (2)

54

55

V

DDD2

PCAPR

PCAPL

V

SSD1

DIGITAL

SUPPLY

V

SSD2

V

SSD3

59

38

V

SSD4

DDA2

AUDIO PROCESSING

V

CRESET

DEC2

39

40

V

ref(p)

V

ref(n)

TDA9870A

SUPPLY

SCART,

DAC,

46

53

V

ref2

DAC (2)

ADC

V

ref3

28

30

TEST1

TEST2

43

56

50

V

TEST

SSA2

V

SSA3

V

SSA4

61

60

58

57

MHB110

MOL MOR

AUXOL AUXOR

Fig.1 Block diagram.

6

1998 Aug 10

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

5

PINNING

SYMBOL

I/O

DESCRIPTION

i.c.

1

−

internally connected; note 1

i.c.

2

ADDR1

SCL

3

I

ﬁrst I²C-bus slave address modiﬁer

I²C-bus clock input

4

I

SDA

5

I/O

I²C-bus data input/output

V_SSA1

V_DEC1

I_ref

6

supply supply ground 1; analog front-end circuitry

7

−

I/O

I

positive power supply voltage 1 decoupling; analog front-end circuitry

8

resistor for reference current generator; analog front-end circuitry

ﬁrst general purpose I/O pin

P1

9

SIF2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

sound IF input 2

V_ref1

−

I

reference voltage; analog front-end circuitry

sound IF input 1

second I²C-bus slave address modiﬁer

SIF1

ADDR2

V_SSD1

V_DDD1

CRESET

V_SSD4

XTALI

XTALO

P2

I

supply supply ground 1; digital circuitry

supply digital supply voltage 1; digital circuitry

−

capacitor for power-on reset

supply supply ground 4; digital circuitry

I

crystal oscillator input

O

crystal oscillator output

I/O

second general purpose I/O pin

system clock output

I²S-bus clock input/output

I²S-bus word select input/output

I²S-bus data output 2

I²S-bus data output 1

SYSCLK

SCK

O

I/O

WS

I/O

SDO2

SDO1

SDI2

O

I

I²S-bus data input 2

I²S-bus data input 1

SDI1

I

TEST1

MONOIN

TEST2

EXTIR

EXTIL

SCIR1

SCIL1

V_SSD3

SCIR2

SCIL2

V_DEC2

I

ﬁrst test pin; connected to V_SSD1for normal operation

audio mono input

I

second test pin; connected to V_SSD1for normal operation

external audio input right channel

external audio input left channel

SCART 1 input right channel

SCART 1 input left channel

I

supply supply ground 3; digital circuitry

I

SCART 2 input right channel

SCART 2 input left channel

−

positive power supply voltage 2 decoupling; audio analog-to-digital converter

circuitry

38

39

V_ref(p)

−

positive reference voltage; audio analog-to-digital converter circuitry

1998 Aug 10

7

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

V_ref(n)

I/O

DESCRIPTION

40

41

42

43

44

45

46

47

48

49

50

51

52

−

reference voltage ground; audio analog-to-digital converter circuitry

internally connected; note 2

i.c.

internally connected; note 3

V_SSA2

i.c.

supply supply ground 2; audio analog-to-digital converter circuitry

−

internally connected; note 3

i.c.

internally connected; note 2

V_ref2

−

reference voltage; audio analog-to-digital converter circuitry

SCART 1 right channel output

SCOR1

SCOL1

V_SSD2

V_SSA4

SCOR2

SCOL2

V_ref3

O

SCART 1 left channel output

supply supply ground 2; digital circuitry

supply supply ground 4; audio operational ampliﬁer circuitry

O

−

SCART 2 right channel output

SCART 2 left channel output

reference voltage; audio digital-to-analog converter and operational ampliﬁer

circuitry

53

PCAPR

PCAPL

V_SSA3

AUXOR

AUXOL

V_DDA

54

55

56

57

58

59

60

61

62

63

64

−

post-ﬁlter capacitor pin right channel, audio digital-to-analog converter

post-ﬁlter capacitor pin left channel, audio digital-to-analog converter

supply supply ground 3; audio digital-to-analog converter circuitry

O

headphone (Auxiliary) right channel output

headphone (Auxiliary) left channel output

supply positive analog power supply voltage; analog circuitry

MOR

O

loudspeaker (Main) right channel output

loudspeaker (Main) left channel output

line output left channel

MOL

LOL

LOR

line output right channel

V_DDD2

supply digital supply voltage 2; digital circuitry

Notes

1. Test pin, CMOS 3-state stage, pull-up resistor, can be connected to V_SS

2. Test pin, CMOS level input, pull-up resistor, can be connected to V_SS

3. Test pin, CMOS 3-state stage, can be connected to V_SS

.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

handbook, halfpage

i.c.

1

2

3

4

5

6

7

8

9

64 V

DDD2

63 LOR

62 LOL

61 MOL

60 MOR

ADDR1

SCL

SDA

V

59 V

DDA

SSA1

V

58 AUXOL

57 AUXOR

DEC1

I

ref

P1

56 V

SSA3

SIF2 10

11

55 PCAPL

54 PCAPR

V

ref1

SIF1 12

53 V

ref3

ADDR2 13

52 SCOL2

51 SCOR2

V

14

15

SSD1

50

49

V

DDD1

SSA4

SSD2

CRESET 16

TDA9870A

V

17

48 SCOL1

47 SCOR1

SSD4

XTALI 18

XTALO 19

P2 20

46

V

ref2

45 i.c.

44 i.c.

SYSCLK 21

SCK 22

43

V

SSA2

WS 23

42 i.c.

41 i.c.

SDO2 24

SDO1 25

SDI2 26

40

39

38

V

ref(n)

ref(p)

DEC2

SDI1 27

TEST1 28

MONOIN 29

TEST2 30

EXTIR 31

EXTIL 32

37 SCIL2

36 SCIR2

35

V

SSD3

34 SCIL1

33 SCIR1

MHB111

Fig.2 Pin configuration.

9

1998 Aug 10

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

6

FUNCTIONAL DESCRIPTION

6.1.5

FM IDENTIFICATION

The identification of the FM sound mode is performed by

AM synchronous demodulation of the pilot signal and

narrow-band detection of the identification frequencies.

The result is available via the I²C-bus interface. A selection

can be made via the I²C-bus for B/G, D/K and M standard

and for three different modes that represent different

trade-offs between speed and reliability of identification.

6.1

Description of the demodulator and decoder

section

6.1.1

SIF INPUT

Two input pins are provided, SIF1 e.g. for terrestrial TV

and SIF2 e.g. for a satellite tuner. For higher SIF signal

levels the SIF input can be attenuated with an internally

switchable −10 dB resistor divider. As no specific filters are

integrated, both inputs have the same specification giving

flexibility in application. The selected signal is passed

through an AGC circuit and then digitized by an 8-bit ADC

operating at 24.576 MHz.

6.1.6

CRYSTAL OSCILLATOR

The crystal oscillator (XO) is illustrated in Fig.8

(see Chapter 12). The circuitry of the XO is fully

integrated, only the external 24.576 MHz crystal is

needed.

6.1.2

AGC

6.1.7

TEST PINS

The gain of the AGC amplifier is controlled from the ADC

output by means of a digital control loop employing

hysteresis. The AGC has a fast attack behaviour to

prevent ADC overloads and a slow decay behaviour to

prevent AGC oscillations. For AM demodulation the AGC

must be switched off. When switched off, the control loop

is reset and fixed gain settings can be chosen

Both test pins are active HIGH, in normal operation of the

device they are connected to V_SSD1. Test functions are for

manufacturing tests only and are not available to

customers. Without external circuitry these pads are pulled

down to LOW level with internal resistors.

(see Table 14; subaddress 0).

6.1.8

POWER FAIL DETECTOR

The AGC can be controlled via the I²C-bus. Details can be

found in the I²C-bus register definitions (see Chapter 10).

The power fail detector monitors the internal power supply

for the digital part of the device. If the supply has

temporarily been lower than the specified lower limit, the

power-on reset bit POR, transmitter register subaddress 0

(see Section 10.4.1), will be set to HIGH. The CLRPOR bit,

slave register subaddress 1 (see Section 10.3.2), resets

the power-on reset flip-flop to LOW. If this is detected, an

initialization of the TDA9870A has to be performed to

ensure reliable operation.

6.1.3

MIXER

The digitized input signal is fed to the mixers, which mix

one or both input sound carriers down to zero IF. A 24-bit

control word for each carrier sets the required frequency.

Access to the mixer control word registers is via the

I²C-bus.

6.1.4

FM AND AM DEMODULATION

An FM or AM input signal is fed via a band-limiting filter to

a demodulator that can be used for either FM or AM

demodulation. Apart from the standard (fixed)

de-emphasis characteristic, an adaptive de-emphasis is

available for encoded satellite programs. A stereo decoder

recovers the left and right signal channels from the

demodulated sound carriers. Both the European and

Korean stereo systems are supported.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Pseudo stereo is based on a phase shift in one channel via

a 2nd-order all-pass filter. There are fixed coefficient sets

to provide 90 degrees phase shift at frequencies of

150, 200 and 300 Hz.

6.2.1

LEVEL SCALING

All input channels to the digital crossbar switch (except for

the loudspeaker feedback path) are equipped with a level

adjust facility to change the signal level in a range of

±15 dB. It is recommended to scale all input channels to be

15 dB below full scale (−15 dB full scale) under nominal

conditions.

Volume is controlled individually for each channel ranging

from +24 to −83 dB with 1 dB resolution. There is also a

mute position. For the purpose of a simple control software

in the microcontroller, the decimal number that is sent as

an I²C-bus data byte for volume control is identical to the

volume setting in dBs (e.g. the I²C-bus data byte +10 sets

the new volume value to +10 dB).

6.2.2

FM (AM) PATH

A high-pass filter suppresses DC offsets from the FM

demodulator, due to carrier frequency offsets, and

supplies the monitor/peak function with DC values and an

unfiltered signal, e.g. for the purpose of carrier detection.

Balance can be realized by independent control of the left

and right channel volume settings.

Contour is adjustable between 0 and +18 dB with 1 dB

resolution. This function is linked to the volume setting by

means of microcontroller software.

The de-emphasis function offers fixed settings for the

supported standards (50 µs, 60 µs and 75 µs).

An adaptive de-emphasis is available for

Wegener-Panda 1 encoded programs.

Bass is adjustable between +15 and −12 dB with 1 dB

resolution and treble is adjustable between ±12 dB with

1 dB resolution.

A matrix performs the dematrixing of the A2 stereo, dual

and mono signals.

For the purpose of a simple control software in the

microcontroller, the decimal number that is sent as an

I²C-bus data byte for contour, bass or treble is identical to

the new contour, bass or treble setting in dBs (e.g. the

I²C-bus data byte +8 sets the new value to +8 dB).

6.2.3

MONITOR

This function provides data words from a number of

locations of the signal processing paths to the I²C-bus

interface (2 data bytes). Signal sources include the FM

demodulator outputs, most inputs to the digital crossbar

switch and the outputs of the ADC. Source selection and

data read-out is performed via the I²C-bus.

Extra bass boost is provided up to 20 dB with 2 dB

resolution. The implemented coefficient set serves merely

as an example on how to use this filter.

The beeper provides tones in a range from approximately

400 Hz to 30 kHz. The frequency can be selected via the

I²C-bus. The beeper output signal is added to the

loudspeaker and headphone channel signals. The beeper

volume is adjustable with respect to full scale between

0 and −93 dB with 3 dB resolution. The beeper is not

effected by mute.

Optionally, the peak value can be measured instead of

simply taking samples. The internally stored peak value is

reset to zero when the data is read via the I²C-bus.

The monitor function may be used, for example, for signal

level measurements or carrier detection.

6.2.4

LOUDSPEAKER (MAIN) CHANNEL

Soft mute provides a mute ability in addition to volume

control with a well defined time (32 ms) after which the soft

mute is completed. A smooth fading is achieved by a

cosine masking.

The matrix provides the following functions; forced mono,

stereo, channel swap, channel 1, channel 2 and spatial

effects.

There are fixed coefficient sets for spatial settings of 30%,

40% and 52%.

6.2.5

HEADPHONE (AUXILIARY) CHANNEL

The Automatic Volume Level (AVL) function provides a

constant output level of −23 dB full scale for input levels

between 0 and −29 dB full scale. There are some fixed

decay time constants to choose from, i.e. 2, 4 and 8 s.

The matrix provides the following functions; forced mono,

stereo, channel swap, channel 1 and channel 2

(or C and S in Dolby Surround Pro Logic mode).

Volume is controlled individually for each channel in a

range from +24 to −83 dB with 1 dB resolution. There is

also a mute position.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

For the purpose of a simple control software in the

microcontroller, the decimal number that is sent as an

I²C-bus data byte for volume control is identical to the

volume setting in dB (e.g. the I²C-bus data byte +10 sets

the new volume value to +10 dB).

6.2.7

CHANNEL FROM THE AUDIO ADC

The signal level at the output of the ADC can be adjusted

in a range of ±15 dB with 1 dB resolution. The audio ADC

itself is scaled to a gain of −6 dB.

Balance can be realized by independent control of the left

and right channel volume settings.

6.2.8

CHANNEL TO THE ANALOG CROSSBAR PATH

Level adjust with control positions 0 dB, +3 dB, +6 dB

and +9 dB.

Bass is adjustable between +15 and −12 dB with 1 dB

resolution and treble is adjustable between ±12 dB with

1 dB resolution.

6.2.9

DIGITAL CROSSBAR SWITCH (see Fig.6)

For the purpose of a simple control software in the

microcontroller, the decimal number that is sent as an

I²C-bus data byte for bass or treble is identical to the new

bass or treble setting in dB (e.g. the I²C-bus data byte +8

sets the new value to +8 dB).

Input channels to the crossbar switch are from the audio

ADC, I²S1, I²S2, FM path and from the loudspeaker

channel path after matrix and AVL.

Output channels comprise loudspeaker, headphone, I²S1,

I²S2 and the audio DACs for line output and SCART.

The beeper provides tones in a range from approximately

400 Hz to 30 kHz. The frequency can be selected via the

I²C-bus. The beeper output signal is added to the

loudspeaker and headphone channel signals. The beeper

volume is adjustable with respect to full scale between

0 and −93 dB with 3 dB resolution. The beeper is not

effected by mute.

The I²S1 and I²S2 outputs also provide digital outputs from

the loudspeaker and headphone channels, but without the

beeper signals.

6.2.10 GENERAL

There are a number of functions that can provide signal

gain, e.g. volume, bass and treble control. Great care has

to be taken when using gain with large input signals in

order not to exceed the maximum possible signal swing,

which would cause severe signal distortion. The nominal

signal level of the various signal sources to the digital

crossbar switch should be 15 dB below digital full scale

(−15 dB full scale). This means that a volume setting of,

say, +15 dB would just produce a full scale output signal

and not cause clipping, if the signal level is nominal.

Soft mute provides a mute ability in addition to volume

control with a well defined time (32 ms) after which the soft

mute is completed. A smooth fading is achieved by a

cosine masking.

6.2.6

FEATURE INTERFACE

The feature interface comprises two I²S-bus input/output

ports and a system clock output. Each I²S-bus port is

equipped with level adjust facilities that can change the

signal level in a range of ±15 dB with 1 dB resolution.

Outputs can be disabled to improve EMC performance.

Sending illegal data patterns via the I²C-bus will not cause

any changes of the current setting for the volume, bass,

treble, bass boost and level adjust functions.

The I²S-bus output matrix provides the following functions;

forced mono, stereo, channel swap, channel 1 and

channel 2.

6.2.11 EXPERT MODE

The TDA9870A provides a special expert mode that gives

direct write access to the internal Coefficient RAM (CRAM)

of the DSP. It can be used to create user-defined

characteristics, such as a tone control with different corner

frequencies or special boost/cut characteristics to correct

the low-frequency loudspeaker and/or cabinet frequency

responses by means of the bass boost filter. However, this

mode must be used with great care.

One example of how the feature interface can be used in

a TV set is to connect an external Dolby Surround

Pro Logic DSP, such as the SAA7710, to the I²S-bus

ports. Outputs must be enabled and a suitable master

clock signal for the DSP can be taken from pin SYSCLK.

A stereo signal from any source will be output on one of

the I²S-bus serial data outputs and the four processed

signal channels will be entered at both I²S-bus serial data

inputs. Left and right could then be output to the power

amplifiers via the Main channel, centre and surround via

the Auxiliary channel.

More information on the functions of this device, such as

the number of coefficients per function, their default

values, memory addresses, etc., can be made available

on request.

1998 Aug 10

13

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

6.2.12 OVERVIEW OF DSP FUNCTIONS

Table 4 Overview of DSP functions

EXPERT

FUNCTION

MODE

PARAMETER

control range

VALUE

UNIT

dB

Bass control for loudspeaker and

headphone output

−12 to +15

yes

resolution

1

dB

Hz

dB

kHz

dB

Hz

dB

Hz

dB

resolution at frequency

control range

40

Treble control for loudspeaker

and headphone output

−12 to +12

resolution

1

resolution at frequency

control range

14

Contour for loudspeaker output

0 to +18

resolution

1

resolution at frequency

control range

40

Bass boost for loudspeaker

output

0 to +20

resolution

2

yes

resolution at frequency

corner frequency

control range

20

350

Volume control for each separate

channel in loudspeaker and

headphone output

−83 to +24

no

resolution

1

mute position at step

processing time

10101100

32

Soft-mute for loudspeaker and

headphone output

ms

Spatial effects

Pseudo stereo

yes

anti-phase crosstalk positions

90 degree phase shift at frequency

beep frequencies

30, 40 and 52

150, 200 and 300

see Section 10.3.38

0 to −93

%

Hz

Beeper additional to the signal in

the loudspeaker and headphone

channel

control range

dB

yes

resolution

3

mute position at step

step width

00100000

Automatic Volume Level (AVL)

quasi continuously

−23

AVL output level for an input level

dBFS

between 0 and −29 dB full scale

yes

attack time

10

ms

s

decay time constant

2, 4 and 8

General

−3 dB lower corner frequency of DSP 10

Hz

kHz

dB

no

−1 dB bandwidth of DSP

control range

14.5

Level adjust I²S1 and I²S2 inputs

−15 to +15

1

yes

resolution

Level adjust I²S1 and I²S2

outputs

control range

−15 to +15

1

yes

no

resolution

mute position at step

control positions

00010000

0, 3, 6 and 9

Level adjust analog crossbar path

1998 Aug 10

dB

14

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

EXPERT

FUNCTION

MODE

PARAMETER

control range

VALUE

UNIT

dB

Level adjust audio ADC outputs

+15 to −15

yes

resolution

1

dB

Level adjust FM path

control range

resolution

+15 to −15

1

6.3

Description of the analog audio section

handbook, full pagewidth

SCART 1

3 dB

0 dB

2

ANALOG

MATRIX

SCART 1

SCART 2

Line output

−3 dB

3 dB

0 dB

ANALOG

MATRIX

2

ANALOG

CROSSBAR

SWITCH

SCART 2

3 dB

0 dB

ANALOG

MATRIX

external

mono

2

D

A

D

A

2

FM

DSP

AND

DIGITAL

CROSSBAR

SWITCH

2

D

A

2

I S1

Main

2

I S2

2

I S1

D

A

Auxiliary

2

I S2

MHB113

Fig.4 Block diagram for the audio section.

1998 Aug 10

15

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

6.3.1

ANALOG CROSSBAR SWITCH AND ANALOG MATRIX

6.3.2

SCART INPUTS

(see also Fig.6)

The SCART specification allows for a signal level of up to

2 V (RMS). Because of signal handling limitations, due to

the 5 V supply voltage of the TDA9870A, it is necessary to

have fixed 3 dB attenuators at the SCART inputs to obtain

a 2 V input. This results in a −3 dB SCART-to-SCART

copy gain. If 0 dB copy gain is preferred (with maximum

1.4 V input), there are 3 dB and 0 dB amplifiers at the

outputs of SCART 1 and SCART 2 and at the line output.

There are a number of analog input and output ports with

the TDA9870A. Analog source selector switches are

employed to provide the desired analog signal routing

capability. The analog signal routing is performed by the

analog crossbar switch section. A dual audio ADC

provides the connection to the DSP section and a dual

audio DAC provides the connection from the DSP section

to the analog crossbar switch. The digital signal routing is

performed by a digital crossbar switch.

The input attenuator is realized by an external series

resistor in combination with the input impedance, both of

which form a voltage divider. With this voltage divider the

maximum SCART signal level of 2 V (RMS) is scaled

down to 1.4 V (RMS) at the input pin.

The basic signal routing philosophy of the TDA9870A is

that each switch handles two signal channels at the same

time, e.g. left and right, language A and B, directly at the

source.

6.3.3

EXTERNAL AND MONO INPUTS

Each source selector switch is followed by an analog

matrix to perform further selection tasks, such as putting a

signal from one input channel, say language A, to both

output channels or for swapping left and right channels.

The analog matrix provides the functions given in Table 5

(see also Fig.5).

The 3 dB input attenuators are not required for the external

and mono inputs, because those signal levels are under

control of the TV designer. The maximum allowed input

level is 1.4 V (RMS). By adding external series resistors,

the external inputs can be used as an additional SCART

input.

Table 5 Analog matrix functions

6.3.4

SCART OUTPUTS

MATRIX OUTPUT

MODE

The SCART outputs employ amplifiers with two gain

settings. The gain can be set to 3 dB or to 0 dB via the

I²C-bus. The 3 dB position is needed to compensate for

the 3 dB attenuation at the SCART inputs should

SCART-to-SCART copies with 0 dB gain be preferred

[under the condition of 1.4 V (RMS) maximum input level].

The 0 dB position is needed, for example, for an

external-to-SCART copy with 0 dB gain.

LEFT OUTPUT RIGHT OUTPUT

1

2

3

4

left input

right input

left input

right input

left input

right input

handbook, halfpage

left input

left output

ANALOG

MATRIX

right input

right output

MGK110

Fig.5 Analog matrix.

All switches and matrices are controlled via the I²C-bus.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

6.3.5

LINE OUTPUT

6.3.8

DUAL AUDIO ADC

The line output can provide an unprocessed copy of the

audio signal in the loudspeaker channels. This can be

either an external signal that comes from the dual audio

ADC, or a signal from an internal digital audio source that

comes from the dual audio DAC. The line output employs

amplifiers with two gain settings. The 3 dB position is

needed to compensate for the attenuation at the SCART

inputs, while the 0 dB position is needed, for example, for

non-attenuated external or internal digital signals

(see Section 6.3.4).

There is one dual audio ADC in the TDA9870A for the

connection of the analog crossbar switch section to the

DSP. The dual audio ADC consists of two bitstream

3rd-order sigma-delta audio ADCs and a high-order

decimation filter.

6.3.9

STANDBY MODE

The standby mode (subaddress 1, bit 5) disables most

functions and reduces power dissipation. The analog

crossbar switch and the SCART section remains

operational and can be controlled by the I²C-bus to

support copying of analog signals from

6.3.6

LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY)

OUTPUTS

SCART-to-SCART.

Signals from any audio source can be applied to the

loudspeaker and to the headphone output channels via the

digital crossbar switch and the DSP.

Unused internal registers may lose their information in

standby mode. Therefore, the device needs to be

initialized on returning to normal operation. This can be

accomplished in the same way as after a power-on reset.

6.3.7

DUAL AUDIO DAC

6.3.10 SUPPLY GROUND

The TDA9870A contains three dual audio DACs, one for

the connection from the DSP to the analog crossbar switch

section and two for the loudspeaker and headphone

outputs. Each of the three dual low-noise high-dynamic

range DACs consists of two 15-bit DACs with current

outputs, followed by a buffer operational amplifier.

The audio DACs operate with four-fold oversampling and

noise shaping.

The different supply grounds V_SSXare internally

connected via substrate. It is therefore recommended to

connect all ground pins externally close to the pins by a

copper plane.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

7

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS

V_DDDC supply voltage

MIN.

−0.5

MAX.

+6.0

550

V_DD+ 0.5 V

UNIT

V

∆V_DD

voltage differences between two V_DDpins

maximum input/output voltage

DC V_DDor V_SScurrent per digital supply pin

latch-up protection current

−

mV

I_I/O(max)

−0.5

−

I

_DDD, I_SSD

I_lu(prot)

P_tot

±180

−

mA

100

−

mA

W

°C

V

total power dissipation

1.2

+125

+70

−

T_stg

storage temperature

−55

−20

2000

200

T_amb

V_es

operating ambient temperature

electrostatic handling

note 1

note 2

−

V

Notes

1. Human body model: C = 100 pF; R = 1.5 kΩ.

2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω.

8

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

40

UNIT

R_th(j-a)

thermal resistance from junction to ambient in free air

K/W

1998 Aug 10

19

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

9

CHARACTERISTICS

V_SIF(p-p)= 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note 3;

V_DD= 5 V; T_amb= 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; f_mod= 1 kHz; FM sound

parameters in accordance with system A2; 1 kΩ measurement source resistance for AF inputs; unless otherwise

speciﬁed; with external components of Fig.8.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDD1

V_SSD1

I_DDD1

digital supply voltage 1

digital supply ground 1

digital supply current 1

digital supply voltage 2

digital supply ground 2

digital supply current 2

4.75

5.0

5.5

V

note 1

−

0.0

68

−

V

V_DDD1= 5.0 V

53

4.75

−

83

5.5

−

mA

V

V_DDD2

V_SSD2

I_DDD2

5.0

0.0

0.4

note 1

V

V_DDD2= 5.0 V;

SYSCLOCK off

0.1

2

mA

V_SSD3

V_SSD4

V_DDA

I_DDA

digital supply ground 3

digital supply ground 4

analog supply voltage

note 1

−

0.0

5.0

56

−

V

−

V

4.75

5.5

68

V

analog supply current for

DAC part

V_DDA= 5.0 V; digital silence 44

mA

V_SSA1

V_SSA2

V_SSA3

V_SSA4

analog ground for analog

front-end

note 1

−

0.0

−

V

analog ground for audio ADC

part

analog ground for audio DAC

part

analog ground for SCART

Demodulator supply decoupling and references

V_DEC1

analog supply decoupling

voltage for demodulator part

3.0

−

3.3

2

3.6

−

V

V_ref1

analog reference voltage for

demodulator part

V

I_ref1(sink)

V_ref1sink current

−

200

−

µA

Audio supply decoupling and references

V_DEC2

analog supply decoupling

voltage for audio ADC part

3.0

3.3

50

3.6

V

V_ref2

reference voltage for audio

ADCs

referenced to V_DEC2/V_SSA2

−

%

Z_Vref2-VDEC2impedance V_ref2to V_DEC2

−

20

50

−

kΩ

%

Z_Vref2-VSSA2

V_ref3

impedance V_ref2to V_SSA2

reference voltage for audio

referenced to V_DDA/V_SSA3

DAC and operational ampliﬁer

Z_Vref3-VDDA

Z_Vref3-VSSA3

impedance V_ref3to V_DDA

impedance V_ref3to V_SSA3

−

20

−

kΩ

1998 Aug 10

20

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power fail detector

V_th(pf)

power fail threshold level

−

3.9

−

V

Digital inputs and outputs

INPUTS

CMOS level input, pull-down (pins TEST1 and TEST2)

V_IL

V_IH

C_i

LOW-level input voltage

HIGH-level input voltage

input capacitance

−

0.3V_DDD

V

0.7V_DDD

−

V

−

10

−

pF

kΩ

Z_i

input impedance

50

CMOS level input, hysteresis, pull-up (pin CRESET)

V_IL

V_IH

V_hys

C_i

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−

0.3V_DDD

V

0.7V_DDD

−

V

−

1.3

−

V

input capacitance

10

−

pF

kΩ

Z_i

input impedance

50

INPUTS/OUTPUTS

I²C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I²C operation and level (pins SCL and SDA)

V_IL

V_IH

V_hys

I_LI

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

−

0.3V_DDD

−

V

0.7V_DDD

−

V

−

0.05V_DDD

−

V

input leakage current

input capacitance

−

±10

10

µA

pF

V

C_i

V_OL

C_L

LOW-level output voltage

load capacitance

0.6

400

pF

TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1

and SDI2)

V_IL

V_IH

C_i

LOW-level input voltage

HIGH-level input voltage

input capacitance

−

0.8

−

V

2.0

−

V

−

10

0.4

−

pF

V

V_OL

V_OH

C_L

LOW-level output voltage

HIGH-level output voltage

load capacitance

−

2.4

−

V

−

100

−

pF

kΩ

Z_i

input impedance

−

50

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

OUTPUTS

CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK)

V_OL

V_OH

C_L

LOW-level output voltage

HIGH-level output voltage

load capacitance

−

0.3V_DDD

−

V

0.7V_DDD

V

−

100

pF

µA

I_LIZ

3-state leakage current

V_i= 0 to V_DDD

±10

SIF1 and SIF2 analog inputs

V_{SIF(max)(p-p)}maximum composite SIF input SIF input level adjust 0 dB

−

941

−

mV

voltage for clipping

(peak-to-peak value)

SIF input level adjust

2976

−10 dB

V_{SIF(min)(p-p)}minimum composite SIF input SIF input level adjust 0 dB

−

59

−

mV

voltage for lower limit of AGC

(peak-to-peak value)

SIF input level adjust

188

−10 dB

AGC

f_i

AGC range

−

24

−

dB

input frequency

input resistance

input capacitance

FM deviation

4

9.2

−

MHz

kΩ

R_i

AGCLEV = 0

10

−

C_i

7.5

−

11

−

pF

∆f_FM

∆f_FM(FS)

B/G standard; THD < 1%

±100

±150

kHz

FM deviation full-scale level

terrestrial FM; level adjust

0 dB

−

C/N_FM

FM carrier C/N_cratio

N_FMbandwidth = 6 MHz;

white noise for

S/N = 40 dB; “CCIR468”;

quasi peak

−

77

−

dB_FM

-------------

Hz

α_ct

crosstalk attenuation

SIF1 to SIF2

f_i= 4 to 9.2 MHz; note 2

50

−

dB

Demodulator performance; note 3

THD + N

total harmonic distortion plus

noise

from FM source to any

output; V_o= 1 V (rms) with

low-pass ﬁlter

−

0.3

70

66

0.5

−

%

S/N

signal-to-noise ratio

SC1 from FM source to any 64

output; V_o= 1 V (rms);

“CCIR468”; quasi peak

dB

SC2 from FM source to any 60

output; V_o= 1 V (rms);

−

“CCIR468”; quasi peak

B_−3dB

f_res

−3 dB bandwidth

from FM source to any

output

14.5

15

−

kHz

dB

frequency response

20 Hz to 14 kHz

from FM to any output;

f_ref= 1 kHz; inclusive

pre-emphasis and

de-emphasis

−

±2

α_cs(dual)

dual signal channel separation note 4

65

70

−

dB

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

40

TYP.

MAX.

UNIT

dB

α_cs(stereo)

α_AM

stereo channel separation

AM suppression for FM

note 5

45

−

AM: 1 kHz, 30%

50

−

dB

modulation; reference:

1 kHz, 50 kHz deviation

S/N_AM

AM demodulation

SIF level 100 mV (RMS);

54% AM; 1 kHz AF;

36

45

−

dB

“CCIR468”; quasi peak

IDENTIFICATION FOR FM SYSTEMS

mod_p

pilot modulation for

identiﬁcation

25

50

27

75

%

C/N_p

pilot sideband C/N for

identiﬁcation start

−

dB

------

Hz

f_ident

identiﬁcation window

B/G stereo

slow mode

medium mode

fast mode

116.85

116.11

114.65

−

118.12

118.89

Hz

120.46 Hz

B/G dual

slow mode

medium mode

fast mode

273.44

−

274.81 Hz

276.20 Hz

277.60 Hz

272.07

270.73

t_ident(on)

total identiﬁcation time ON

total identiﬁcation time OFF

slow mode

medium mode

fast mode

−

2

s

1

0.5

2

t_ident(off)

slow mode

medium mode

fast mode

1

0.5

Analog audio inputs

MONO INPUT AND EXTERNAL INPUT

V_i(nom)(rms)

nominal level input voltage

(RMS value)

note 3

−

500

1400

35

−

mV

kΩ

V_i(clip)(rms)

clipping level input voltage

(RMS value)

THD < 3%; note 6

note 6

1250

28

−

R_i

input resistance

42

SCART INPUTS

V_i(nom)(rms)

nominal level input voltage at

input pin (RMS value)

−3 dB divider with external

15 kΩ resistor;

notes 3 and 7

−

350

1400

35

−

mV

kΩ

V_i(clip)(rms)

clipping level input voltage at

input pin (RMS value)

−3 dB divider with external 1250

15 kΩ resistor; THD < 3%;

notes 6 and 7

−

R_i

input resistance

note 6

28

42

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Analog audio outputs

LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS

V_o(clip)(rms)

clipping level output voltage

(RMS value)

THD < 3%

1250

1400

−

mV

R_o

output resistance

150

10

−

250

−

375

−

Ω

R_L(AC)

R_L(DC)

C_oL

AC load resistance

DC load resistance

output load capacitance

static DC offset voltage

mute suppression

kΩ

nF

mV

dB

−

10

30

−

12

70

−

V_offset(DC)

α_mute

−

nominal input signal from

any source; f_i= 1 kHz;

note 3

80

G_ro(main,aux)

roll-off gain at 14.5 kHz for

Main and Auxiliary channels

from any source

−3

−2

−

dB

PSRR_main,auxpower supply ripple rejection

for Main and Auxiliary

f_ripple= 70 Hz;

40

45

V_ripple= 100 mV (peak);

C_Vref= 47 µF;

signal from I²S-bus

channels

SCART OUTPUTS AND LINE OUTPUT

V_o(nom)(rms)

nominal level output voltage

(RMS value)

3 dB ampliﬁcation; note 3

THD < 3%

−

500

−

mV

V_o(clip)(rms)

clipping level output voltage

(RMS value)

1250

1400

R_o

output resistance

150

10

−

250

−

375

−

Ω

R_L(AC)

R_L(DC)

C_oL

AC load resistance

DC load resistance

output load capacitance

static DC offset voltage

kΩ

nF

mV

−

2.5

50

V_offset(DC)

output ampliﬁers at 3 dB

position

−

30

α_mute

mute suppression

bandwidth

nominal input signal from

any source; f_i= 1 kHz;

note 3

80

−

dB

B

from SCART, external and 20

mono sources;

kHz

−3 dB bandwidth

from DSP sources;

−3 dB bandwidth

14.5

40

−

kHz

dB

PSRR

power supply ripple rejection

f_ripple= 70 Hz;

45

V_ripple= 100 mV (peak);

C_Vref= 47 µF;

signal from I²S-bus

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Audio performance

THD + N

total harmonic distortion plus

noise

V_i= V_o= 1 V (RMS);

f_i= 1 kHz; bandwidth

20 Hz to 15 kHz; note 8

from any analog audio

input to I²S-bus

from I²S-bus to any

analog audio output

−

0.1

0.3

%

0.1

0.3

%

SCART-to-SCART copy

SCART-to-Main copy

−

0.1

0.2

0.3

0.5

%

S/N

signal-to-noise ratio

reference voltage

V_o= 1.4 V (RMS);

f_i= 1 kHz; “CCIR468”;

quasi peak; note 8

from any analog audio

input to I²S-bus

from I²S-bus to any

analog audio output

73

78

77

85

−

dB

SCART-to-SCART copy 78

85

77

−

dB

SCART-to-Main copy

73

70

α_ct

α_cs

G_A

crosstalk attenuation

channel separation

between any analog input

pairs; f_i= 1 kHz

between any analog output 65

pairs; f_i= 10 kHz

−

0

−

dB

between left and right of

any input pair

65

−

between left and right of

any output pair

60

−

gain from SCART-to-SCART

output ampliﬁer in 3 dB

−1.5

+1.1

with −3 dB input voltage divider position;

R

_ext= 15 kΩ ±10%

output ampliﬁer in 0 dB

position;

−4.5

−3.0

−1.9

dB

R

_ext= 15 kΩ ±10%

1998 Aug 10

25

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Crystal speciﬁcation (fundamental mode)

f_xtal

C_L

crystal frequency

load capacitance

series capacitance

parallel capacitance

pulling sensitivity

−

24.576

20

−

7

−

MHz

pF

fF

C₁

20

C₀

−

pF

Φ_pull

C_Lchanged from

18 to 16 pF

25

10^–6

-----------

pF

R_R

R_N

equivalent series resistance

at nominal frequency

−

30

Ω

equivalent series resistance of

unwanted mode

2R_R

−

∆T

X_J

temperature range

adjustment tolerance

drift

−20

−

+25

−

+70

±30

±5

°C

10⁻⁶

X_D

X_A

across temperature range

−

ageing

−

10^–6

-----------

year

Notes

1. All analog and digital supply ground pins are connected internally.

2. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch

AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference.

Switch to the other SIF input to which no signal is connected and which is terminated with 50 Ω. Measure now the

1 kHz crosstalk signal level. The SIF source resistance should be low (50 Ω).

3. Definitions of levels and level setting:

The full-scale level for analog audio signals is V_FS= 1.4 V (RMS). The nominal level at the digital crossbar switch is

defined at −15 dB (full-scale). Nominal audio input levels:

external, mono: 500 mV (RMS); −9 dB (full-scale).

See also Tables 6 and 7.

4. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output;

V_o= 1 V (RMS) of modulated channel.

5. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output;

V_o= 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of

the transmitter.

6. If the supply voltage for the TDA9870A is switched off, because of the ESD protection circuitry, all audio input pins

are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used.

7. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the

5 V supply voltage for the TDA9870A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve

SCART-to-SCART copies with 0 dB gain, there are 3 dB and 0 dB amplifiers at the outputs of SCART 1 and

SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external

series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is

scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input

signal is larger than 1.4 V (RMS).

8. ADC level adjust = 6 dB, all other level adjusts = 0 dB, if external −3 dB divider is used set output buffer gain to 3 dB,

tone control to 0 dB, AVL off and volume control to 0 dB.

1998 Aug 10

26

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10 I²C-BUS CONTROL

10.1 Introduction

10.2 Power-up state

At power-up the device is in the following state:

• All outputs muted

The TDA9870A is fully controlled via the I²C-bus. Control

is exercised by writing data to one or more internal

registers. Status information can be read from an array of

registers to enable the controlling microcontroller to

determine whether any action is required.

• No sound carrier frequency loaded

• General purpose I/O pins ready for input (HIGH)

• Input SIF1 selected with:

– AGC on

The device has an I²C-bus slave transceiver, in

accordance with the fast-mode specification, with a

maximum speed of 400 kbits/s. Information concerning the

I²C-bus can be found in brochure “I²C-bus and how to use

it” (order number 9398 393 40011). To avoid conflicts in a

real application with other ICs providing similar or

complementary functions, there are four possible slave

addresses available which can be selected by pins

ADDR1 and ADDR2 (see Table 8).

– Small hysteresis

– SIF input level shift 0 dB.

• Demodulators for both sound carriers set to FM with:

– Identification for B/G, D/K, response time 1 s

– Level adjust set to 0 dB

– De-emphasis 50 µs

– Matrix set to mono.

• Main channel set to FM input with:

– Spatial off

Table 8 Possible slave addresses

ADDR2

ADDR1

SLAVE ADDRESS A6 TO A0

– Pseudo off

0

1

0

1

0

1

1 0 1 1 0 0 0

1 0 1 1 0 0 1

1 0 1 1 0 1 0

1 0 1 1 0 1 1

– AVL off

– Volume mute

– Bass flat

– Treble flat

– Contour off

The I²C-bus interface remains operational in the standby

mode of the TDA9870A to allow control of the analog

source selectors with regard to SCART-to-SCART

copying.

– Bass boost flat.

• Auxiliary channel set to FM input with:

– Volume mute

The device will not respond to a ‘general call’ on the

I²C-bus, i.e. when a slave address of 0000000 is sent by a

master.

– Bass flat

– Treble flat.

• Feature interface all outputs off

• Beeper off

The data transmission between the microcontroller and

the other I²C-bus controlled ICs is not disturbed when the

supply voltage of the TDA9870A is not connected.

• Monitoring of carrier 1 FM demodulator DC output.

After power-up a device initialization has to be performed

via the I²C-bus to put the TDA9870A into the proper mode

of operation, in accordance with the desired TV standard,

audio control settings, etc.

1998 Aug 10

28

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3 Slave receiver mode

As a slave receiver, the TDA9870A provides 46 registers for storing commands and data. These registers are accessed

via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location.

Table 9 I²C-bus; slave address, subaddress and data format

S

SLAVE ADDRESS

0

ACK

SUBADDRESS

ACK

DATA

ACK

P

Table 10 Explanation of Table 9

BIT

FUNCTION

S

START condition

SLAVE ADDRESS

7-bit device address

0

data direction bit (write to device)

acknowledge by slave

ACK

SUBADDRESS

address of register to write to

data byte to be written into register

STOP condition

DATA

P

It is allowed to send more than one data byte per transmission to the TDA9870A. In this event, the subaddress is

automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register

locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with

ACK (acknowledge).

There is no ‘wrap-around’ of subaddresses.

Commands and data are processed as soon as they have been completely received. Functions requiring more than one

byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated

(STOP condition) before all bytes have been received, the incomplete data for that function is ignored.

Table 11 Format for a transmission employing auto-increment of subaddresses

S

SLAVE

0

ACK SUBADDRESS ACK

DATA BYTE A⁽¹⁾

DATA

ACK

P

ADDRESS

Note

1. n data bytes with auto-increment of subaddresses.

Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the

functions of volume, bass, treble control, bass boost and level adjust.

Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will

not then be executed.

1998 Aug 10

29

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 12 Overview of the slave receiver registers

DATA

SUBADDRESS

(DECIMAL)

FUNCTION

MSB

LSB

0

c

p

f

0

c

0

f

s

c

g

c

m

f

g

c

m

f

g

c

s

f

g

c

s

f

g

c

s

f

AGC level shift, AGC gain selection

general conﬁguration

1

2

0

f

monitor select, peak detector on/off

carrier 1 frequency; MS part

carrier 1 frequency

3

4

f

5

f

carrier 1 frequency; LS part

carrier 2 frequency; MS part

carrier 2 frequency

6

f

7

f

8

f

carrier 2 frequency; LS part

demodulator conﬁguration

FM de-emphasis

9

c

d

0

m

g

0

s

0

v

0

v

0

c

d

0

m

g

s

m

0

v

0

m

v

0

m

c

d

0

l

c

d

0

l

c

d

m

l

c

d

m

l

c

d

m

l

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

d

0

m

s

FM matrix

channel 1 output level adjust

channel 2 output level adjust

set to logic 0; note 1

l

0

m

l

0

m

g

0

l

0

m

s

0

l

0

m

s

0

l

0

m

s

l

set to logic 0; note 1

audio mute control

DAC output select

SCART 1 output select

SCART 2 output select

line output select

ADC output select

m

s

m

s

v

c

b

t

0

p

v

c

b

t

s

p

v

c

b

t

s

a

v

c

b

t

s

a

v

c

b

t

Main channel select

audio effects (AVL, pseudo, spatial)

volume control, Main left

volume control, Main right

contour control, Main

v

0

m

v

bass control, Main

treble control, Main

m

v

b

t

0

v

b

t

s

v

b

t

s

v

b

t

s

v

b

t

Auxiliary channel select

volume control, Auxiliary left

volume control, Auxiliary right

bass control, Auxiliary

treble control, Auxiliary

feature interface conﬁguration

I²S1 output select

v

0

m

c

m

c

0

c

s

c

s

c

s

1998 Aug 10

30

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

DATA

SUBADDRESS

(DECIMAL)

FUNCTION

I²S1 input level adjust

I²S1 output level adjust

I²S2 output select

I²S2 input level adjust

I²S2 output level adjust

beeper frequency

MSB

LSB

38

39

40

41

42

43

44

45

0

b

0

m

0

b

0

m

0

v

i

o

m

i

o

0

i

o

s

i

o

s

i

o

s

i

o

0

v

b

o

0

v

b

o

f

o

f

o

f

v

b

v

b

v

b

beeper volume, Main and Auxiliary

bass boost, Main left and right

b

Note

1. These bits have not been assigned to a function.

The following sub-sections provide a detailed description of the slave receiver registers:

10.3.1 AGC GAIN REGISTER

10.3.1.1 Description

If the automatic gain control function is switched off in the general configuration register, the contents of this register will

define a fixed gain of the AGC stage. The input voltages given are meant to generate a full scale output from the SIF

ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control

function, the latest gain control setting is copied to the AGC gain register. If the AGC input level shift bit AGCLEV is set

to HIGH the input signal is scaled with −10 dB. The AGCLEV bit is also active if the automatic gain function is enabled.

It should be noted that the input voltages should be considered as approximate target values.

Table 13 Description of the AGC gain register

BIT

NAME

DESCRIPTION

7 (MSB)

−

set to logic 0

6

5

AGCLEV If the AGC input level shift bit AGCLEV is set to HIGH the input signal is scaled with −10 dB.

The AGCLEV bit is also active if the automatic gain function is enabled.

4

AGCGAIN If the automatic gain control function is switched off in the general conﬁguration register, the

contents of this register will deﬁne a ﬁxed gain of the AGC stage.

3

2

1

0 (LSB)

1998 Aug 10

31

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.1.2 Deﬁnition

Table 14 Subaddress 0

MSB

LSB

B0

AGC GAIN SIF INPUT VOLTAGE

(dB)

(mV (p-p))

B7

B6

B5

B4

B3

B2

B1

0

0/1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.0

941/2976

861/2723

788/2490

720/2278

659/2084

603/1906

551/1744

504/1595

461/1459

422/1334

386/1221

353/1117

323/1021

295/934

270/855

247/782

226/715

207/654

189/598

173/547

158/501

145/458

132/419

121/383

111/350

0.8

1.5

2.3

3.1

3.9

4.6

5.4

6.2

7.0

7.7

8.5

9.3

10.1

10.8

11.6

12.4

13.2

13.9

14.7

15.5

16.3

17.0

17.8

18.6

19.4

20.1

20.9

21.7

22.5

23.2

24.0

101/321

93/293

85/268

78/245

71/224

65/205

59/188 (note 1)

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

32

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.2 GENERAL CONFIGURATION REGISTER

10.3.2.1 Description

Table 15 Description of Table 16

NAME

HIGH/LOW

HIGH

FUNCTION

Selects pin SIF2 for input (recommended for satellite tuner).

Pin SIF1 (terrestrial TV) is selected.

SIFSEL

LOW

AGCOFF

AGCSLOW

CLRPOR

INIT

HIGH

Forces the AGC block to a ﬁxed gain as deﬁned in the AGC gain register.

LOW

The automatic gain control function is enabled and the contents of the AGC gain register is

ignored.

HIGH

A longer decay time is selected for input signals with strong video modulation (intercarrier).

This bit only has an effect when bit AGCOFF = 0.

LOW

HIGH

LOW

Selects normal attack and decay times for the AGC.

Resets the power fail detector to LOW.

This bit is automatically reset to LOW after bit POR in the device status register has been

reset.

HIGH

Causes initialization of TDA9870A to its default settings. This has the same effect as a

power-on reset. If there is a conﬂict between the default settings and any bit set HIGH in

this register, the bits of this register have priority over the corresponding default setting.

LOW

HIGH

This bit is automatically reset to LOW after initialization. When set LOW, the TDA9870A is

in its normal mode of operation.

STDBY

Puts the TDA9870A into the standby mode. Most functions are disabled and power

dissipation is somewhat reduced, but the analog selectors/matrices remain operational to

support analog copying from SCART-to-SCART and vice versa.

LOW

The TDA9870A is in its normal mode of operation. On return from standby mode, the

device is in its power-on reset mode and needs to be re-initialized.

P1OUT,

P2OUT

−

These bits control the general purpose input/output pins. The contents of these bits is

written directly to the corresponding pins. If input is desired, the bits must be set HIGH to

allow the pins to be pulled LOW externally. Input from the pins is reﬂected in the device

status register (see Section 10.4, subaddress 0). P1OUT is recommended to be used for

switching an SIF trap for the adjacent picture carrier in designs that employ such a trap.

10.3.2.2 Deﬁnition

Table 16 Subaddress 1 (note 1)

BIT

NAME

DESCRIPTION

general purpose I/O pin 2

7 (MSB)

P2OUT

P1OUT

6

general purpose I/O pin 1

standby mode on/off

initialize to defaults (as reset)

clear power-on reset ﬂip-ﬂop

AGC decay time

5

STDBY

4

INIT

3

CLRPOR

AGCSLOW

AGCOFF

SIFSEL

2

1

AGC on/off

0 (LSB)

SIF input select

Note

1. The default setting at power-up is 11000000.

1998 Aug 10

33

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.3 MONITOR SELECT REGISTER

10.3.3.1 Description

This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be

monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Data can be read-out in the I²C-bus

slave transmitter mode (see Section 10.4, subaddresses 5 and 6).

Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in

FM mode, while magnitude is supplied in AM mode.

Table 17 Description of bit PEAKMON

NAME

HIGH/LOW

FUNCTION

PEAKMON

HIGH

LOW

selects the peak level of a source to be monitored

the last sample will be supplied

10.3.3.2 Deﬁnition

Table 18 Subaddress 2 (note 1)

MSB

LSB

B7

B6

0

B5

0

B4

B3

B2

B1

B0

PEAKMON

see Table 20

see Table 19

Note

1. The default setting at power-up is 00000000.

Table 19 Signal source (note 1)

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DC output of FM demodulator

audio magnitude/phase, FM demodulator output

crossbar input from FM/AM channel

don’t care

crossbar input from I²S1 channel

crossbar input from I²S2 channel

crossbar input from audio ADC channel

input to Main channel DAC (without beeper)

Note

1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available.

1998 Aug 10

34

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 20 Monitor output

10.3.4.2 Deﬁnition

Most significant part at subaddress 3.

B4

B3

MONITOR OUTPUT

L input + R input

Table 21 Subaddresses 3 to 5

0

------------------------------------------

2

BIT

SUBADDRESSES

0

1

0

L input (channel 1, respectively)

R input (channel 2, respectively)

7 (MSB)

6

10.3.3.3 Note

5

4

By reading out level read-out registers

(subaddresses 5 and 6, see Section 10.4), the current

peak level will be reset.

3

2

1

10.3.4 CARRIER 1 FREQUENCY REGISTER

10.3.4.1 Description

0

7

The three bytes together constitute a 24-bit frequency

control word to represent the sound carrier (i.e. mixer)

frequency in accordance with the following formula:

6

5

4

f

4

data = ^mix× 2 ²⁴

--------

3

f_clk

2

Where:

1

data = 24-bit frequency control word.

f_mix= desired sound carrier frequency.

f_clk= 12.288 MHz (clock frequency of mixer).

2²⁴= 16777216 (number of steps in a 24-bit word size).

0

7

6

5

4

Example: A 5.5 MHz sound carrier frequency will be

generated by sending the following sequence of data

bytes to the TDA9870A (data = 7509333 in decimal

notation or 729555 in HEX): 01110010 10010101

01010101.

5

3

2

1

0 (LSB)

As three bytes are required to define a carrier frequency,

execution of this command starts only after all bytes have

been received. If an error occurs, e.g. a premature STOP

condition, partial data for this function is ignored.

10.3.5 CARRIER 2 FREQUENCY REGISTER

10.3.5.1 Description

Same as for sound carrier 1.

The default setting at power-up is 00000000 for all three

bytes.

If the carrier 2 frequency register is used, it will be for the

second FM sound carrier of a terrestrial or satellite FM

program.

1998 Aug 10

35

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.5.2 Deﬁnition

Subaddresses 6 to 8.

Same as for sound carrier 1, except for subaddresses used.

10.3.6 DEMODULATOR CONFIGURATION REGISTER

10.3.6.1 Description

Table 22 Description of subaddress 9 (notes 1 and 2)

NAME

HIGH/LOW

FUNCTION

CH1MODE

HIGH

LOW

−

selects the hardware for the ﬁrst sound carrier to operate in AM mode

FM mode is assumed. This applies to both terrestrial and satellite FM reception.

selects the ﬁlter bandwidth for channel 1 and channel 2 in accordance with Table 25

FILTBW0,

FILTBW1

CH2MOD0,

CH2MOD1

−

These bits control the hardware for the second sound carrier in accordance with the

truth Table 24.

IDAREA

HIGH

LOW

−

selects FM identiﬁcation frequencies in accordance with the speciﬁcation for Korea

frequencies for Europe are selected (B/G and D/K standard)

IDMOD0,

IDMOD1

These bits deﬁne the response time after which a sound mode identiﬁcation result may be

expected. The longer the time, the more reliable the identiﬁcation.

Notes

1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial

2-carrier sound.

2. Switching the identification off will reset the associated hardware to a defined state.

10.3.6.2 Deﬁnition

Table 23 Subaddress 9 (note 1; see Table 22)

BIT

NAME

DESCRIPTION

7 (MSB)

IDMOD1

IDMOD0

response time for FM sound mode identiﬁcation

6

5

IDAREA

application area for FM identiﬁcation

selects ﬁlter bandwidth in accordance with Table 25

channel 2 receive mode

4

FILTBW1

CH2MOD1

CH2MOD0

FILTBW0

CH1MODE

3

2

1

selects ﬁlter bandwidth in accordance with Table 25

channel 1 receive mode

0 (LSB)

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

36

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 24 Channel 2 receive mode (see Table 23)

B3

B2

CHANNEL 2

0

1

0

1

0

FM

AM

don’t care

Table 25 Filter bandwidth Channel 1 and Channel 2 (see Table 23)

FILTER BANDWIDTH

B4

B1

FILTER MODES

CH1

CH2

narrow

recommended for nominal terrestrial broadcast conditions and SAT with

2 carriers

0

1

extra wide

narrow

recommended only for high-deviation SAT mono carriers (e.g. obsolete

main channel on Astra)

1

0

1

medium

wide

medium

wide

recommended for moderately overmodulated broadcast conditions

recommended for strongly overmodulated broadcast conditions

Table 26 Identiﬁcation mode (see Table 23)

B7

B6

IDENT MODE

0

1

0

1

0

1

slow

medium

fast

off/reset

10.3.7 FM DE-EMPHASIS REGISTER

10.3.7.1 Description

This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received

carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of A2 reception, both

groups must be set to the same characteristics.

10.3.7.2 Deﬁnition

Table 27 Subaddress 10 (note 1)

BIT

NAME

DESCRIPTION

7 (MSB)

ADEEM2 adaptive de-emphasis on/off

6

time constant selection for FM de-emphasis

5

4

3

ADEEM1 adaptive de-emphasis on/off

time constant selection for FM de-emphasis

2

1

0 (LSB)

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

37

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 28 De-emphasis

B6, B2

B5, B1

B4, B0

DE-EMPHASIS

0

1

0

1

0

1

0

1

0

50 µs (Europe)

60 µs

75 µs (M standard)

J17

off

Table 29 Description of bits ADEEM1 and ADEEM2 (note 1)

NAME

HIGH/LOW

FUNCTION

HIGH

Activates the adaptive de-emphasis function, which is required for certain satellite

FM channels. The standard FM de-emphasis must then be set to 75 µs.

ADEEM1,

ADEEM2

LOW

the adaptive de-emphasis is off

Note

1. The FM de-emphasis gain is 0 dB at 40 Hz.

10.3.8 FM MATRIX REGISTER

10.3.8.1 Description

This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received

carrier and the related sound mode identification.

10.3.8.2 Deﬁnition

Table 30 Subaddress 11 (notes 1)

MSB

LSB

B7

0

B6

0

B5

0

B4

0

B3

0

B2

B1

B0

see Table 31

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

38

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 31 Description of Subaddress 11 (bits B2 to B0)

B2

B1

B0

L OUTPUT

R OUTPUT

MODE

0

1

0

1

0

1

0

1

0

CH1 input; note 1

CH2 input; note 2

CH1 input; note 1

CH2 input; note 2

2CH1 input − CH2 input

CH1 input; note 1

CH2 input; note 2

CH1 input; note 1

CH2 input; note 2

mono 1

mono 2

dual

dual swapped

stereo Europe

stereo Korea; note 3

CH1 input + CH2 input CH1 input – CH2 input

----------------------------------------------------------- ----------------------------------------------------------

1

0

1

2

Notes

1. CH1: audio signal from FM channel 1.

2. CH2: audio signal from FM channel 2.

3. See Table 6. For stereo Korea the dematrix applies 6 dB attenuation.

10.3.9 FM CHANNEL 1 LEVEL ADJUST REGISTER

10.3.9.1 Description

This register is used to correct for standard and station-dependent differences of signal levels. Table 32 applies to sound

carrier 1.

1998 Aug 10

39

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.9.2 Deﬁnition

Table 32 Subaddress 12

MSB

LSB

B0

GAIN SETTING

(dB)

B7

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER

10.3.10.1 Description

This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to sound

carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.10.2 Deﬁnition

Table 33 Subaddress 13

MSB

LSB

B0

GAIN SETTING

(dB)

B7

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

41

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.11 REGISTER 14

10.3.11.1 Description

10.3.14 REGISTER 17

10.3.14.1 Description

Set to logic 0. This bits have not been assigned to a

function.

Set to logic 0. This bits have not been assigned to a

function.

10.3.12 REGISTER 15

10.3.12.1 Description

10.3.15 AUDIO MUTE CONTROL REGISTER

10.3.15.1 Description

Set to logic 0. This bits have not been assigned to a

function.

When any of these bits are set HIGH, the corresponding

pair of output channels will be muted. A LOW bit allows

normal signal output.

10.3.13 REGISTER 16

10.3.13.1 Description

There is a soft-mute facility for the Main and Auxiliary

output channels to provide click-free muting independent

of the volume control. This is switched on/off by bits

MUTMAIN and MUTAUX.

Set to logic 0. This bits have not been assigned to a

function.

10.3.15.2 Deﬁnition

Table 34 Subaddress 18 (note 1)

BIT

NAME

MUTI²S2

DESCRIPTION

7 (MSB)

mute I²S2 outputs

mute I²S1 outputs

6

MUTI²S1

MUTDAC

MUTLINE

MUTSC2

MUTSC1

MUTAUX

MUTMAIN

5

mute internal DAC

4

mute line outputs

3

mute SCART 2 outputs

mute SCART 1 outputs

mute Auxiliary outputs

mute Main channels

2

1

0 (LSB)

Note

1. The default setting at power-up is 11111111.

10.3.16 DAC OUTPUT SELECT REGISTER

10.3.16.1 Description

This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for

signal selection. The DAC is used for signal output from digital sources at analog outputs.

The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and

DACGAIN2 adds 6 dB of gain, respectively.

1998 Aug 10

42

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.16.2 Deﬁnition

Table 35 Subaddress 19 (note 1)

MSB

LSB

B7

B6

B5

B4

B3

B2

B1

B0

DACGAIN2⁽²⁾

see Table 37

DACGAIN1⁽²⁾

see Table 36

Notes

1. The default setting at power-up is 00000000.

2. See Table 38.

Table 36 Signal source left and right

SIGNAL SOURCE

B2

B1

B0

LEFT

RIGHT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FM left

FM right

don’t care

I²S1 left

I²S2 left

ADC left

AVL left

I²S1 right

I²S2 right

ADC right

AVL right

don’t care

Table 37 Bits B6 to B4

B6

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

L + R

-------------

2

L + R

-------------

2

1

0

Table 38 Description of bits DACGAIN1 and DACGAIN2

GAIN

(dB)

B7

B3

0

1

0

1

0

1

0

3

6

9

1998 Aug 10

43

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.17 SCART 1 OUTPUT SELECT REGISTER

10.3.17.1 Description

This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.

10.3.17.2 Deﬁnition

Table 39 Subaddress 20 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

SC1GAIN⁽²⁾

see Table 41

see Table 40

Notes

1. The default setting at power-up is 00000001.

2. See Table 42.

Table 40 Signal source

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

SCART 1 input

SCART 2 input

external input

mono input

DAC input

Table 41 Bits B5 and B4

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

Table 42 Description of bit SC1GAIN

NAME

HIGH/LOW

FUNCTION

SC1GAIN

HIGH

Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input

passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation,

resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output.

However, that gain must be used with great care, as it will cause signal clipping at high

input levels.

LOW

The audio signal will be output unchanged (0 dB gain).

1998 Aug 10

44

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.18 SCART 2 OUTPUT SELECT REGISTER

10.3.18.1 Description

This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.

10.3.18.2 Deﬁnition

Table 43 Subaddress 21 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

SC2GAIN⁽²⁾

see Table 45

see Table 44

Notes

1. The default setting at power-up is 00000000.

2. See Table 46.

Table 44 Signal source

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

SCART 1 input

SCART 2 input

external input

mono input

DAC input

Table 45 Bits B5 and B4

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

Table 46 Description of bit SC2GAIN

NAME

HIGH/LOW

FUNCTION

SC2GAIN

HIGH

Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input

passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation,

resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output.

However, that gain must be used with great care, as it will cause signal clipping at high

input levels.

LOW

The audio signal will be output unchanged (0 dB gain).

1998 Aug 10

45

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.19 LINE OUTPUT SELECT REGISTER

10.3.19.1 Description

By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form.

This register is used to characterize the signal to be output at the line output and define the output channel selector mode.

10.3.19.2 Deﬁnition

Table 47 Subaddress 22 (note 1)

BIT

NAME

DESCRIPTION

7 (MSB)

−

set to logic 0

line output gain on/off; see Table 49

see Table 48

6

LINGAIN

5

4

3

−

set to logic 0

2

1

−

0 (LSB)

LINSEL

select source for line output;

see Table 49

Note

1. The default setting at power-up is 00000000.

Table 48 Bits B5 and B4

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

Table 49 Description of bits LINSEL and LINGAIN

NAME

HIGH/LOW

FUNCTION

LINSEL

HIGH

Speciﬁes that a signal from an analog source is being processed in the Main channel.

Analog signal sources comprise SCART 1 input, SCART 2 input, external input and

mono input, i.e. any input to the ADC.

LOW

Speciﬁes that a signal from a digital source is being processed in the Main channel.

Digital signal sources comprise FM, I²S1 input and I²S2 input.

LINGAIN

HIGH

LOW

Activates the 3 dB gain stage at the line output buffers.

The audio signal will be output unchanged (0 dB gain).

1998 Aug 10

46

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.20 ADC OUTPUT SELECT REGISTER

10.3.20.1 Description

This register is used to define the signal source for the ADC. There is no output channel selector, because all digital

signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided.

10.3.20.2 Deﬁnition

Table 50 Subaddress 23 (note 1)

MSB

LSB

B7

B6

B5

B4

B3

B2

B1

B0

see Table 51

see Table 52

Note

1. The default setting at power-up is 00000000.

Table 51 Signal source

B7

B6

B5

SIGNAL SOURCE

0

1

0

1

0

1

SCART 1 input

SCART 2 input

external input

mono input

1998 Aug 10

47

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 52 ADC level adjust (note 1)

GAIN SETTING

B4

B3

B2

B1

B0

(dB)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a level of −6 dB full-scale at the

digital x-bar.

1998 Aug 10

48

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.21 MAIN CHANNEL SELECT REGISTER

10.3.21.1 Description

This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode

of the digital matrix for signal selection.

10.3.21.2 Deﬁnition

Table 53 Subaddress 24 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

see Table 55

see Table 54

Note

1. The default setting at power-up is 00000000.

Table 54 Signal source

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

FM input

don’t care

I²S1 input

I²S2 input

ADC input

Table 55 Bits B6 to B4

B6

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

L + R

-------------

2

L + R

-------------

2

1

0

1998 Aug 10

49

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.22 AUDIO EFFECTS REGISTER

10.3.22.1 Deﬁnition

Table 56 Subaddress 25 (note 1; see Table 60)

MSB

LSB

B7

0

B6

0

B5

B4

B3

B2

B1

AVL1⁽⁴⁾

B0

AVL0⁽⁴⁾

SPATIAL1⁽²⁾SPATIAL0⁽²⁾PSEUDO1⁽³⁾PSEUDO0⁽³⁾

Notes

1. The default setting at power-up is 00000000.

2. See Table 59.

3. See Table 58.

4. See Table 57.

Table 57 AVL control mode

B1

B0

AVL MODE

0

1

0

1

0

1

off/reset

short decay

medium decay

long decay

Table 58 Pseudo control setting

B3

B2

PSEUDO SETTING (Hz)

0

1

0

1

0

1

off

300

200

150

Table 59 Spatial control setting

B5

0

B4

0

SPATIAL SETTING (%)

off

30

40

52

0

1

0

1

1998 Aug 10

50

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 60 Description of Table 56 (notes 1, 2 and 3)

NAME

FUNCTION

AVL0, AVL1 these bits set the mode of operation of the automatic volume level control function at the entrance to the

Main (loudspeaker) channel

PSEUDO0, These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel.

PSEUDO1 This function should be activated only in accordance with the result of the sound mode identiﬁcation.

SPATIAL0, These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the

SPATIAL1

Main channel. This function should be activated only in accordance with the result of the sound mode

identiﬁcation.

Notes

1. Switching the AVL off will reset the associated hardware to a defined state.

2. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to

avoid excessive settling times. This can be achieved by switching the AVL off and on again.

3. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated

in Table 58. There is a gain of 3 dB in the left audio channel.

10.3.23 VOLUME CONTROL REGISTERS (MAIN)

10.3.23.1 Description

These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies

to the left channel signal, while the register at subaddress 27 applies to the right channel signal.

Balance control is exercised by offsetting the left and right channel volume settings.

10.3.23.2 Deﬁnition

Table 61 Subaddresses 26 and 27

MSB

B7

LSB

B0

VOLUME SETTING (dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+24

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

+9

1998 Aug 10

51

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

B0

VOLUME SETTING (dB)

B7

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+8

+7

+6

+5

+4

+3

+2

+1

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

−16

−17

−18

−19

−20

−21

−22

−23

−24

−25

−26

−27

−28

−29

−30

1998 Aug 10

52

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

B0

VOLUME SETTING (dB)

B7

B6

B5

B4

B3

B2

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

−31

−32

−33

−34

−35

−36

−37

−38

−39

−40

−41

−42

−43

−44

−45

−46

−47

−48

−49

−50

−51

−52

−53

−54

−55

−56

−57

−58

−59

−60

−61

−62

−63

−64

−65

−66

−67

−68

−69

1998 Aug 10

53

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Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

B0

VOLUME SETTING (dB)

B7

B6

B5

B4

B3

B2

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

−70

−71

−72

−73

−74

−75

−76

−77

−78

−79

−80

−81

−82

−83

mute (note 1)

Note

1. The default setting at power-up is 10101100.

1998 Aug 10

54

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.24 CONTOUR CONTROL REGISTER

10.3.24.1 Description

This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal

channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the

volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so,

of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to

contour off.

10.3.24.2 Deﬁnition

Table 62 Subaddress 28

MSB

B7

LSB

B0

CONTOUR GAIN (dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0 (note 1)

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

55

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.25 BASS CONTROL REGISTER (MAIN)

10.3.25.1 Description

This register is used to apply bass control to the left and right signal channels of the Main channel.

10.3.25.2 Deﬁnition

Table 63 Subaddress 29

MSB

B7

LSB

B0

BASS SETTING (dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

56

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.26 TREBLE CONTROL REGISTER (MAIN)

10.3.26.1 Description

This register is used to apply treble control to the left and right signal channels of the Main channel.

10.3.26.2 Deﬁnition

Table 64 Subaddress 30

MSB

B7

LSB

B0

TREBLE SETTING (dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

57

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.27 AUXILIARY CHANNEL SELECT REGISTER

10.3.27.1 Description

This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode

of the digital matrix for signal selection.

10.3.27.2 Deﬁnition

Table 65 Subaddress 31 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

see Table 67

see Table 66

Note

1. The default setting at power-up is 00000000.

Table 66 Signal source

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

1

FM input

don’t care

I²S1 input

I²S2 input

ADC input

AVL input

Table 67 Bits B6 to B4

B6

B5

B4

L OUTPUT

R OUTPUT

0

1

0

1

0

1

L input

R input

L input

R input

L input

L + R

-------------

2

L + R

-------------

2

1

0

1998 Aug 10

58

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)

10.3.28.1 Description

These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32

applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal.

Balance control is exercised by offsetting the left and right channel volume settings.

10.3.28.2 Deﬁnition

Table 68 Subaddresses 32 and 33

MSB

B7

LSB

B0

VOLUME SETTING

(dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+24

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0

−1

−2

−3

−4

−5

−6

−7

1998 Aug 10

59

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

B0

VOLUME SETTING

(dB)

B7

B6

B5

B4

B3

B2

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

−8

−9

−10

−11

−12

−13

−14

−15

−16

−17

−18

−19

−20

−21

−22

−23

−24

−25

−26

−27

−28

−29

−30

−31

−32

−33

−34

−35

−36

−37

−38

−39

−40

−41

−42

−43

−44

−45

−46

−47

−48

1998 Aug 10

60

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

B0

VOLUME SETTING

(dB)

B7

B6

B5

B4

B3

B2

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

−49

−50

−51

−52

−53

−54

−55

−56

−57

−58

−59

−60

−61

−62

−63

−64

−65

−66

−67

−68

−69

−70

−71

−72

−73

−74

−75

−76

−77

−78

−79

−80

−81

−82

−83

mute (note 1)

Note

1. The default setting at power-up is 10101100.

1998 Aug 10

61

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.29 BASS CONTROL REGISTER (AUXILIARY)

10.3.29.1 Description

This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.

10.3.29.2 Deﬁnition

Table 69 Subaddress 34

MSB

B7

LSB

B0

BASS SETTING

(dB)

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

62

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)

10.3.30.1 Description

This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.

10.3.30.2 Deﬁnition

Table 70 Subaddress 35

MSB

B7

LSB

B0

TREBLE SETTING

(dB)

B6

B5

B4

B3

B2

B1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

63

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER

10.3.31.1 Deﬁnition

Table 71 Subaddress 36 (note 1)

MSB

LSB

B7

0

B6

0

B5

0

B4

SYSCL1⁽²⁾

B3

SYSCL0⁽²⁾

B2

B1

B0

I²SOUT⁽⁵⁾

SYSOUT⁽³⁾I²SFORM⁽⁴⁾

Notes

1. The default setting at power-up is 00000000.

2. System clock frequency select; see Table 72.

3. System clock output on/off; see Table 73.

4. Serial output format; see Table 73.

5. I²S-bus outputs on/off; see Table 73.

Table 72 System clock frequency select

B4

B3

SYSCLK OUTPUT

FREQUENCY (MHz)

8.192

0

1

0

1

0

1

256f_s

384f_s

512f_s

768f_s

12.288

16.384; note 1

24.576

Note

1. With 16.384 MHz, the duty cycle is 33% : 67%.

Table 73 Description of Table 71

NAME

HIGH/LOW

FUNCTION

I²SOUT

HIGH

Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a

format determined by the I²SFORM bit. The TDA9870A is then an I²S-bus master.

LOW

HIGH

the outputs mentioned will be 3-stated, thereby improving the EMC performance

I²SFORM

SYSOUT

an MSB-aligned, MSB-ﬁrst output format is selected, i.e. a level change at the word

select pin indicates the beginning of a new audio sample

the standard I²S-bus output format is selected

LOW

HIGH

LOW

enables the output of a system (or master) clock signal at pin SYSCLK

the output will be off, thereby improving the EMC performance

1998 Aug 10

64

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.32 I²S1 OUTPUT SELECT REGISTER

10.3.32.1 Description

This register is used to define both the signal source to be output at I²S1 and the mode of the digital matrix for signal

selection.

10.3.32.2 Deﬁnition

Table 74 Subaddress 37 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

see Table 76

see Table 75

Note

1. The default setting at power-up is 00000000.

Table 75 Signal source (note 1)

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FM output

don’t care

I²S1 input

I²S2 input

ADC output

AVL output

Auxiliary output

Main output

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

Table 76 Bits B6 to B4

B6

0

B5

0

B4

0

L OUTPUT

L input

R OUTPUT

R input

0

1

L input

0

1

0

R input

0

1

L input

L + R

-------------

2

L + R

-------------

2

1

0

1998 Aug 10

65

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.33 I²S1 INPUT LEVEL ADJUST REGISTER

10.3.33.1 Description

This register is used to adjust the input level at the I²S1 interface. Left and right signal channel are treated identically.

10.3.33.2 Deﬁnition

Table 77 Subaddress 38

MSB

LSB

GAIN SETTING

(dB)

B7

0

B6

0

B5

0

B4

0

1

B3

1

0

1

0

B2

1

0

1

0

1

0

1

0

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

66

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.34 I²S1 OUTPUT LEVEL ADJUST REGISTER

10.3.34.1 Description

This register is used to adjust the output level at the I²S1 interface. Left and right signal channel are treated identically.

10.3.34.2 Deﬁnition

Table 78 Subaddress 39

MSB

LSB

GAIN SETTING

(dB)

B7

0

B6

0

B5

0

B4

0

1

B3

1

0

1

0

B2

1

0

1

0

1

0

1

0

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

67

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.35 I²S2 OUTPUT SELECT REGISTER

10.3.35.1 Description

This register is used to define both the signal source to be output at I²S2 and the mode of the digital matrix for signal

selection.

10.3.35.2 Deﬁnition

Table 79 Subaddress 40 (note 1)

MSB

LSB

B7

0

B6

B5

B4

B3

0

B2

B1

B0

see Table 81

see Table 80

Note

1. The default setting at power-up is 00000000.

Table 80 Signal source (note 1)

B2

B1

B0

SIGNAL SOURCE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FM output

don’t care

I²S1 input

I²S2 input

ADC output

AVL output

Auxiliary output

Main output

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

Table 81 Bits B6 to B4

B6

0

B5

0

B4

0

L OUTPUT

L input

R OUTPUT

R input

0

1

L input

0

1

0

R input

0

1

L input

L + R

-------------

2

L + R

-------------

2

1

0

1998 Aug 10

68

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.36 I²S2 INPUT LEVEL ADJUST REGISTER

10.3.36.1 Description

This register is used to adjust the input level at the I²S2 interface. Left and right signal channel are treated identically.

10.3.36.2 Deﬁnition

Table 82 Subaddress 41

MSB

LSB

GAIN SETTING

(dB)

B7

0

B6

0

B5

0

B4

0

1

B3

1

0

1

0

B2

1

0

1

0

1

0

1

0

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

69

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.37 I²S2 OUTPUT LEVEL ADJUST REGISTER

10.3.37.1 Description

This register is used to adjust the output level at the I²S2 interface. Left and right signal channel are treated identically.

10.3.37.2 Deﬁnition

Table 83 Subaddress 42

MSB

LSB

GAIN SETTING

(dB)

B7

0

B6

0

B5

0

B4

0

1

B3

1

0

1

0

B2

1

0

1

0

1

0

1

0

B1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+15

+14

+13

+12

+11

+10

+9

+8

+7

+6

+5

+4

+3

+2

+1

0 (note 1)

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

mute

Note

1. The default setting at power-up is 00000000.

1998 Aug 10

70

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.38 BEEPER FREQUENCY CONTROL REGISTER

10.3.38.1 Description

This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main

and Auxiliary channel output DAC.

Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than

the 390 Hz beep.

10.3.38.2 Deﬁnition

Table 84 Subaddress 43 (note 1)

MSB

LSB

GENERATED FREQUENCY (Hz)

B7

0

B6

0

B5

0

B4

0

B3

0

B2

1

B1

1

B0

1

25000

7040

3580

1770

1270

900

0

1

0

1

0

1

0

1

0

1

0

1

0

1

640

0

390

Note

1. The default setting at power-up is 00000000.

10.3.39 BEEPER VOLUME CONTROL REGISTER

10.3.39.1 Description

This register is used to set the beeper volume. The gain setting is relative to digital full scale at the input to the Main and

Auxiliary channel output DACs. The beeper volume is independent of any other volume setting.

The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × f_sdomain. The beeper volume

should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to

avoid output signal distortion due to overload.

1998 Aug 10

71

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.39.2 Deﬁnition

Table 85 Subaddress 44

MSB

LSB

B0

GAIN SETTING

(dB)

B7

B6

B5

B4

B3

B2

B1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

−3

−6

−9

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−48

−51

−54

−57

−60

−63

−66

−69

−72

−75

−78

−81

−84

−87

−90

−93

mute (note 1)

Note

1. The default setting at power-up is 00100000.

1998 Aug 10

72

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.40 BASS BOOST CONTROL REGISTER

10.3.40.1 Description

This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main

channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function

must be used with care in order to avoid clipping distortion at high volume settings.

More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then

has full control over this 2nd-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies,

Q factors and boost/cut settings.

10.3.40.2 Deﬁnition

Table 86 Subaddress 45 (note 1; see Table 87)

MSB

LSB

B7

B6

B5

B4

B3

B2

B1

B0

Note

1. The default setting at power-up is 00000000.

Table 87 Gain setting

B7 AND B3 B6 AND B2 B5 AND B1 B4 AND B0

GAIN SETTING (dB)

CORNER FREQUENCY (Hz)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

20

18

16

14

12

10

8

350

6

4

2

0

1998 Aug 10

73

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4 Slave transmitter mode

As a slave transmitter, the TDA9870A provides 13 registers with status information and data, a part of which is for Philips

internal purposes only. These registers can be accessed by means of subaddresses.

Table 88 General format for reading data from the TDA9870A

S

SLAVE ADDRESS

0

ACK SUBADDRESS ACK Sr SLAVE ADDRESS

1

ACK DATA NAm

P

Table 89 Explanation of Tables 88 and 90

BIT

FUNCTION

S

START condition

SLAVE ADDRESS

7-bit device address

0

data direction bit (write to device)

acknowledge (by the slave)

address of register to read from

repeated START condition

ACK

SUBADDRESS

Sr

1

data direction bit (read from device)

data byte read from register

not acknowledge (by the master)

acknowledge (by the master)

STOP condition

DATA

NAm

Am

P

Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the

TDA9870A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading

the sequence of data bytes from successive register locations, starting at SUBADDRESS.

Table 90 Format of a transmission using automatic incrementing of subaddresses

S

SLAVE

ADDRESS

0

ACK SUBADDRESS ACK

Sr

SLAVE

ADDRESS

1

ACK DATA BYTE DATA NAm P

Am⁽¹⁾

Note

1. n data bytes with auto-increment of subaddresses.

Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).

The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress,

the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.

1998 Aug 10

74

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 91 Overview of the slave transmitter registers (note 1)

DATA

SUBADDRESS

(DECIMAL)

FUNCTION

MSB

LSB

0

1

s

X

l

s

X

l

X

l

X

l

X

l

s

X

l

s

X

l

s

X

l

device status (power-on, identiﬁcation, etc.)

don’t care; note 1

2

don’t care; note 1

3

don’t care; note 1

4

don’t care; note 1

5

level read-out (MSB)

level read-out (LSB)

SIF level

6

l

7

X

a

d

s

X

a

d

s

X

a

d

s

c

a

d

s

c

a

d

s

c

a

d

s

c

a

d

s

c

a

d

s

251

252

253

254

255

test register 3; note 2

test register 2; note 2

test register 1; note 2

device identiﬁcation code

software identiﬁcation code

Notes

1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions.

2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of

registers for the identification of individual members and some key parameters in a family of devices.

A detailed description of the slave transmitter registers is given in below.

10.4.1 DEVICE STATUS REGISTER

10.4.1.1 Description

Table 92 Description of Table 93

NAME

HIGH/LOW

FUNCTION

POR

−

The power supply for the digital part of the device, V_DDD2, has temporarily been

lower than the speciﬁed lower limit. If this is detected an initialization of the

TDA9870A has to be carried out to ensure reliable operation.

IDSTE

IDDUA

−

this bit is HIGH if an FM stereo signal has been identiﬁed

This bit is HIGH if an FM dual-language signal has been identiﬁed. When neither

IDSTE nor IDDUA are set, the received signal has to be assumed to be FM mono.

P1IN, P2IN

−

these bits reﬂect the status of the corresponding general purpose port pins,

see Section 10.3.2

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4.1.2 Deﬁnition

Table 93 Subaddress 0

BIT

NAME

DESCRIPTION

7 (MSB)

P2IN

P1IN

−

input from port 2

input from port 1

don’t care

6

5

4

−

don’t care

3

−

don’t care

2

1

IDDUA

IDSTE

POR

identiﬁcation of FM dual sound

identiﬁcation of FM stereo

power fail bit

0 (LSB)

10.4.2 REGISTER 1

10.4.6.2 Deﬁnition

Table 94 Subaddress 5

10.4.2.1 Description

Subaddress 1: These bits have not been assigned to a

function. These bits are reserved for future extensions.

BIT

7 (most signiﬁcant bit or sign bit)

6

5

4

3

2

1

0

10.4.3 REGISTER 2

10.4.3.1 Description

Subaddress 2: These bits have not been assigned to a

function. These bits are reserved for future extensions.

10.4.4 REGISTER 3

10.4.4.1 Description

Subaddress 3: These bits have not been assigned to a

function. These bits are reserved for future extensions.

Table 95 Subaddress 6

BIT

10.4.5 REGISTER 4

10.4.5.1 Description

7

6

5

Subaddress 4: These bits have not been assigned to a

function. These bits are reserved for future extensions.

4

3

10.4.6 LEVEL READ-OUT REGISTERS

10.4.6.1 Description

2

1

0 (least signiﬁcant bit)

These two bytes constitute a word that provides data from

a location that has been specified with the monitor select

register. The most significant byte of the data is stored at

subaddress 5.

10.4.7 SIF LEVEL REGISTER

10.4.7.1 Description

If peak-level monitoring has been selected, the peak-level

monitoring register is cleared and monitoring resumes

after its contents has been transferred to these two bytes.

When the SIF AGC is on, bits B4 to B0 of this register

contain a number that gives an indication of the SIF input

level. That number corresponds to the AGC gain register

setting (see Section 10.3, subaddress 0).

1998 Aug 10

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Philips Semiconductors

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Digital TV Sound Processor (DTVSP)

TDA9870A

When the SIF AGC is off, this register returns the contents

of the AGC gain register.

10.4.11 DEVICE IDENTIFICATION CODE

10.4.11.1 Description

10.4.7.2 Deﬁnition

There will be several devices in the digital TV sound

processor family. This byte is used to identify the individual

family members.

Table 96 Subaddress 7

MSB

LSB

10.4.11.2 Deﬁnition

B7

B6

B5

B4

B3

B2

B1

B0

Table 100 Subaddress 254

10.4.8 TEST REGISTER 3

10.4.8.1 Description

MSB

LSB

B7

0

B6

0

B5

1

B4

0

B3

0

B2

0

B1

1

B0

0

This register contains, as a binary number, the highest

memory address used for the Coefficient RAM (CRAM,

expert mode).

10.4.12 SOFTWARE IDENTIFICATION CODE

10.4.12.1 Description

10.4.8.2 Deﬁnition

It is likely that during the life time of this family of devices

several versions of the DSP software will be made, e.g., to

accommodate new application concepts, respond to

customer wishes, etc. This byte is used to identify the

different releases.

Table 97 Subaddress 251

MSB

LSB

B7

0

B6

1

B5

1

B4

1

B3

1

B2

1

B1

1

B0

1

10.4.12.2 Deﬁnition

10.4.9 TEST REGISTER 2

10.4.9.1 Description

Table 101 Subaddress 255

MSB

LSB

This register contains, as a binary number, the highest

subaddress used for slave receiver registers.

B7

0

B6

0

B5

0

B4

0

B3

0

B2

0

B1

1

B0

0

10.4.9.2 Deﬁnition

10.5 Expert mode

Table 98 Subaddress 252

In addition to the slave receiver and slave transmitter

modes previously described, there is a special ‘expert’

mode that gives direct write access to the internal CRAM

of the DSP.

MSB

LSB

B7

0

B6

0

B5

1

B4

0

B3

1

B2

1

B1

0

B0

1

In this mode, transferred data contain 12-bit-wide

coefficients. As those coefficients bypass on-chip

coefficient look-up tables for many functions, they directly

influence the processing of signals within the DSP.

10.4.10 TEST REGISTER 1

10.4.10.1 Description

This register contains, as a binary number, the highest

subaddress used for slave transmitter (status) registers.

This mode must be used with great care. It can be used to

create user-defined characteristics, such as a tone control

with different corner frequencies or special boost/cut

characteristics to correct the low-frequency loudspeaker

and/or cabinet frequency responses.

10.4.10.2 Deﬁnition

Table 99 Subaddress 253

MSB

B7

0

LSB

B0

1

B6

0

B5

0

B4

0

B3

0

B2

1

B1

1

1998 Aug 10

77

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 102 General format for entering the expert mode and writing coefﬁcients into the TDA9870A

S

SLAVE

0

ACK 10000000

ACK

CRAM

ACK DATA ACK DATA

ACK

P

ADDRESS

Table 103 Explanation of Table 102

BIT

FUNCTION

S

START condition

SLAVE ADDRESS

7-bit device address

0

data direction bit (write to device)

acknowledge

ACK

10000000

pattern to enter the expert mode

CRAM ADDRESS

start address of coefficient RAM to write to

data byte containing part of a coefﬁcient

STOP condition

DATA

P

As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 104). The most significant

bit is transferred first.

Table 104 General format (notes 1, 2 and 3)

BYTE

DATA

DESCRIPTION

2 MST of 1st coefﬁcient

1 LST of 1st coefﬁcient

1. data byte

2. data byte

a

X

Notes

1. X = don’t care.

2. MST = most significant third.

3. LST = least significant third.

The general format described in Table 104 shows the minimum number of data bytes required, i.e. two bytes for the

transfer of a single coefficient.

Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each

coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at

CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they

are arranged as shown in Table 105.

Table 105 Transfer of two coefﬁcients

BYTE

DATA

DESCRIPTION

2 MST of 1st coefﬁcient

1 data byte

2 data byte

3 data byte

a

b

a

b

a

b

a

b

a

b

a

b

a

b

a

b

1 LST of 1st coefﬁcient + 1 MST of 2nd coefﬁcient

2 LST of 2nd coefﬁcient

With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing

don’t care data.

1998 Aug 10

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Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

As the transfer of coefficients cannot be accomplished

within one audio sample period, it is necessary that

received coefficients be buffered and made active all at the

same time to avoid audio signal transients. The receive

buffer is designed to store up to 8 coefficients in addition

to the CRAM address. Each byte that fits into the buffer is

acknowledged with ACK (acknowledge). If an attempt is

made to write more coefficients than the buffer can store,

the device acknowledges with NACK (not acknowledge)

and any further coefficients are ignored. Coefficients that

are already in the receive buffer remain intact.

is LOW. Data is written at the trailing edge of SCK and

read at the leading edge of SCK. The most significant bit

is sent first.

At power-up, the outputs of the feature interface are

3-stated to reduce EMC and allow for combinations with

other ICs. If output is desired, it has to be activated by

means of an I²C-bus command.

When the output is enabled, the serial audio data can be

taken from pins SDO1 and SDO2. Depending on the signal

source, switch and matrix positions, the output can be

either mono, stereo or dual language sound on either

output.

An expert mode transfer ends when the I²C-bus STOP

condition or a repeated START condition has been

detected. Only those coefficients that have been received

during the last transmission will then be copied from the

buffer to the CRAM.

The word select output is clocked with the audio sample

frequency at 32 kHz. The serial clock output (SCK) is

clocked at a frequency of 2.048 MHz. This means, that

there are 64 clock pulses per pair of stereo output

samples, or 32 clock pulses per sample. Depending again

on the signal source, the number of significant bits on the

serial data outputs, SDO1 and SDO2, is between

14 and 18.

To make efficient and correct use of the expert mode, it is

recommended to transfer all coefficients for any one

function in a single transmission.

There is no checking of memory addresses and the

automatic incrementing of addresses does not stop at the

highest used CRAM address. The user of this expert mode

must be fully acquainted with the relevant procedures.

Apart from just feeding a digital audio device, such as a

DAC or an AES/EBU transmitter, the serial data outputs

can be connected directly to the serial inputs (loop-back

connection) or first to an external device, e.g. a feature

DSP such as the SAA7710 and then back to the serial

inputs. In all of these configurations, the SCK and WS

clocks will be generated by the TDA9870A, which then is

the I²S-bus master.

More information concerning the functions of this device,

such as the number of coefficients per function, their

default values, memory addresses, etc., can be supplied

on request at a later date.

11 I²S-BUS DESCRIPTION

The serial data inputs, SDI1 and SDI2, are active at all

times, independent of the serial data outputs being on or

off. When the serial data outputs are off (either after

power-up or via the appropriate I²C-bus command) serial

data and clocks WS and SCK from a separate digital audio

source can be fed into the TDA9870A, be processed and

output in accordance with internal selector positions,

provided that the following criteria are met:

The feature interface of the TDA9870A contains two serial

audio inputs and outputs and associated clock signals.

It can be used to supply, for example, audio signals from

received TV programs to a digital audio output device

(AES/EBU format), or import serial audio signals from

other sources for reproduction through the TV set’s

loudspeaker and/or headphone channels. Apart from such

simple data input or output, it is also possible to run audio

signals through an external DSP, which performs some

additional functions, such as room simulation, Dolby

Surround Pro Logic etc. and feed those signals back into

the loudspeaker and/or headphone channels of the

TDA9870A.

• 32 kHz audio sample frequency

• 32 clock bits per sample

• External timing and data synchronized to TDA9870A.

In such cases, the external source is the I²S-bus master

and the TDA9870A is the I²S-bus slave.

To support synchronization of external devices or as a

master clock for them, a system clock output, SYSCLK, is

available from the TDA9870A. At power-up it is off. It can

be enabled and the output frequency set via an I²C-bus

command. Available output frequencies are

Two serial audio formats are supported at the feature

interface, i.e. the I²S-bus format and a very similar

MSB-aligned format. The difference is illustrated in Fig.7.

In both formats the left audio channel of a stereo sample

pair is output first and is placed on the serial data line (SDI

for input, SDO for output) when the word select line (WS)

8.192, 12.288, 16.384 and 24.576 MHz.

1998 Aug 10

79

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

handbook, full pagewidth

SCK

WS

SD

LSB MSB

MGK112

one sample

a. I²S-bus format.

handbook, full pagewidth

SCK

WS

SD

LSB MSB

MGK113

one sample

b. MSB-aligned format.

Fig.7 Serial audio interface formats.

1998 Aug 10

80

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

12 EXTERNAL COMPONENTS

handbook, full pagewidth

V

R19

i.c.

1

DDD2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

+5 V

C35

47 µF 1.5 Ω

C34

i.c.

2

LOR

LOL

2.2 µF

C33

ADDR1

3

2.2 µF

C32

SCL

4

MOL

MOR

10 nF

C30

C31

C29

2.2 µF

SDA

5

10 nF

2.2 µF

R8

V

SSA1

DDA

6

+5 V

47 µF

C28

C26

C24

2.2 Ω

C27

V

DEC1

AUXOL

AUXOR

7

10 nF

C1

4.7 µF

2.2 µF

C25

R1

I

ref

8

10 nF

10 kΩ

2.2 µF

V

P1

SSA3

9

C23

C2

SIF2

PCAPL

PCAPR

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SIFSAT

SIFTV

47 pF

10 nF

C3

C22

V

ref1

100 nF

10 nF

C21

C4

V

SIF1

ref3

47 pF

47 µF

C20

SCOL2

SCOR2

ADDR2

2.2 µF

C19

V

SSD1

2.2 µF

V

R2

1.5 Ω

V

SSA4

DDD1

+5 V

C5

47 µF

C6

V

SSD2

CRESET

1 µF

TDA9870A

C18

V

SCOL1

SCOR1

SSD4

2.2 µF

C17

XTALI

2.2 µF

C16

24.576 MHz

V

ref2

XTALO

P2

47 µF

i.c.

SYSCLK

SCK

V

SSA2

i.c.

WS

SDO2

SDO1

SDI2

V

ref(n)

C15

47 µF

V

R7

ref(p)

C14

4.7 µF

270 Ω

V

DEC2

SDI1

C13

R6

15 kΩ

SCIL2

TEST1

MONOIN

TEST2

EXTIR

EXTIL

330 nF

C7

C12

R5

SCIR2

15 kΩ

330 nF

470 nF

V

SSD3

C8

C11

330 nF

R4

SCIL1

SCIR1

15 kΩ

470 nF

C9

470 nF

C10

R3

33

15 kΩ

330 nF

MHB115

Fig.8 Schematic for measurements.

81

1998 Aug 10

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

13 APPLICATION CIRCUITRY

L9

C42

handbook, full pagewidth

+5 V

POWER

0 V

V

R13

i.c.

DDD2

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

+5 V

C1

47 µF

470

nF

1 Ω

C41

LOR

LOL

2

470 pF

C40

2.2 µF

C39

ADDR1

SCL

3

470 pF

10 nF

470 nF

10 nF

C38

C36

C34

2.2 µF

L1

L2

C37

R1

MOL

MOR

4

100 Ω

2.2 µF

C35

R2

SDA

5

100 Ω

2.2 µF

R12

V

SSA1

DDA

6

+5 V

C32

C31

C30

2.2 Ω

C33

V

DEC1

AUXOL

AUXOR

7

C2

470 nF

2.2 µF

C29

R3

10 kΩ

I

ref

8

R4

2.2 kΩ

2.2 µF

V

P1

SSA3

9

L3

C28

C3

SIF2

PCAPL

PCAPR

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SIFSAT

SIFTV

47 pF

10 nF

C4

C27

V

ref1

100 nF

10 nF

L4

C26

C5

V

SIF1

ref3

47 pF

47 µF

C25

SCOL2

SCOR2

ADDR2

C24

470 pF

2.2 µF

C23

V

SSD1

C22

2.2 µF

L5

V

R5

V

SSA4

DDD1

+5 V

C6

470 nF

1 Ω

C7

V

SSD2

CRESET

1 µF

TDA9870A

C21

V

SCOL1

SCOR1

SSD4

C20

C18

470 pF

2.2 µF

C19

XTALI

2.2 µF

C17

24.576 MHz

V

ref2

XTALO

P2

47 µF

R6

i.c.

2.2 kΩ

SYSCLK

SCK

V

SSA2

i.c.

WS

SDO2

SDO1

SDI2

V

ref(n)

C16

47 µF

V

R11

ref(p)

C15

470 nF

270 Ω

V

DEC2

SDI1

C14

330 nF

R10

SCIL2

TEST1

MONOIN

TEST2

EXTIR

EXTIL

15 kΩ

L6

C8

C13

R9

SCIR2

15 kΩ

330 nF

470 nF

V

SSD3

L7

C9

C12

330 nF

R8

SCIL1

SCIR1

15 kΩ

L8

470 nF

C10

470 nF

C11

R7

33

15 kΩ

330 nF

MHB116

note: L’s are ferrite beads.

Fig.9 Schematic for application.

82

1998 Aug 10

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

14 PACKAGE OUTLINE

SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)

SOT274-1

D

M

E

A

2

A

L

A

1

c

e

(e )

1

w M

Z

b

1

M

H

b

64

33

pin 1 index

E

1

32

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

A

2

max.

(1)

Z

1

w

UNIT

b

c

D

E

e

L

M

H

1

E

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

58.67

57.70

17.2

16.9

3.2

2.8

19.61

19.05

20.96

19.71

mm

0.51

4.57

5.84

1.778

19.05

0.18

1.73

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

92-10-13

95-02-04

SOT274-1

1998 Aug 10

83

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

time of successive solder waves must not exceed

15 SOLDERING

5 seconds.

15.1 Introduction

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_{stg max}). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

15.3 Repairing soldered joints

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “IC Package Databook” (order code 9398 652 90011).

Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not

more than 2 mm above it. If the temperature of the

soldering iron bit is less than 300 °C it may remain in

contact for up to 10 seconds. If the bit temperature is

between 300 and 400 °C, contact may be up to 5 seconds.

15.2 Soldering by dipping or by wave

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact

16 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

18 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1998 Aug 10

84

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

NOTES

1998 Aug 10

85

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

NOTES

1998 Aug 10

86

Philips Semiconductors

Product speciﬁcation

Digital TV Sound Processor (DTVSP)

TDA9870A

NOTES

1998 Aug 10

87

Philips Semiconductors – a worldwide company

Argentina: see South America

Middle East: see Italy

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,

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Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belgium: see The Netherlands

Brazil: see South America

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,

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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

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Romania: see Italy

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Tel. +852 2319 7888, Fax. +852 2319 7700

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Tel. +7 095 755 6918, Fax. +7 095 755 6919

Colombia: see South America

Czech Republic: see Austria

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Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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Slovenia: see Italy

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Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

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Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

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Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

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Tel. +66 2 745 4090, Fax. +66 2 398 0793

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

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Tel. +82 2 709 1412, Fax. +82 2 709 1415

Tel. +1 800 234 7381

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545104/1200/01/pp88

Date of release: 1998 Aug 10

Document order number: 9397 750 03839


型号：	TDA9870A
厂家：	NXP
描述：	Digital TV Sound Processor DTVSP 数字电视音频处理器DTVSP 电视
文件：	总88页 (文件大小：364K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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