TDA9898HL/V3 [NXP]
Multistandard hybrid IF processing; 多标准混合型中频处理
| 型号： | TDA9898HL/V3 |
| 厂家： | 
NXP |
| 描述： | Multistandard hybrid IF processing |
| 文件： | 总103页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA9897; TDA9898
Multistandard hybrid IF processing
Rev. 04 — 25 May 2009
Product data sheet
1. General description
The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including
global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio
using only 1 IC and 1 to 3 fixed Surface Acoustic Waves (SAWs) (application dependent).
TDA9898 includes, TDA9897 excludes L and L-accent standard.
2. Features
2.1 General
I 5 V supply voltage
I I2C-bus control over all functions
I Four I2C-bus addresses provided; selection by programmable Module Address (MAD)
I Three I2C-bus voltage level supported; selection via pin BVS
I Separate gain controlled amplifiers with input selector and conversion for incoming IF
[analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of
different filter shapes and bandwidths
I All conventional ATV standards applicable by using DTV bandwidth window (SAW)
filter
I Two 4 MHz reference frequency stages; the first one operates as crystal oscillator, the
second one as external signal input
I Stabilizer circuit for ripple rejection and to achieve constant output signals
I Smallest size, simplest application
I ElectroStatic Discharge (ESD) protection for all pins
2.2 Analog TV processing
I Gain controlled wideband VIF amplifier; AC-coupled
I Multistandard true synchronous demodulation with active carrier regeneration: very
linear demodulation, good intermodulation figures, reduced harmonics and excellent
pulse response
I Integrated Nyquist processing, providing additionally image suppression for high
adjacent channel selectivity
I Optional use of conventional Nyquist filter to support a wide range of applications
I Gated phase detector for L and L-accent standards
I Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies
switchable for all negative and positive modulated standards via I2C-bus
I VIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync
detector for negative modulated signals and as a peak white detector for positive
modulated signals
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
I Optimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and
SIF
I Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit
Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus
I High precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated
standards; TOP adjust via I2C-bus
I TAGC TOP for positive standards and Received Signal Strength Indication (RSSI);
adjustable via I2C-bus or alternatively by potentiometer
I Fully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz,
5.5 MHz, 6.0 MHz and 6.5 MHz)
I SIF AGC for gain controlled SIF amplifier and high-performance single-reference
Quasi Split Sound (QSS) mixer
I Fully integrated sound BP filter supporting any ATV standard
I Optional use of external FM or AM sound BP filter
I AM sound demodulation for L and L-accent standard
I Alignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity
and low noise; external FM input
I Port function
I VIF AGC voltage monitor output or port function
I TAGC voltage monitor output or port function
I VIF AFC current or tuner, VIF, SIF or FM AGC voltage monitor output
I 2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for
Digital Signal Processor (DSP)
I Fully integrated BP filter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz
2.3 Digital TV processing
I Applicable for terrestrial and cable TV reception
I 70 dB variable gain wideband IF amplifier (AC-coupled)
I Gain control via external control voltage (0 V to 3 V)
I 2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct
Analog-to-Digital Converter (ADC) interfacing
I DVB downconversion with integrated selectivity for Low IF (LIF)
I Integrated anti-aliasing tracking low-pass filter
I Fully integrated synthesizer controlled oscillator with excellent phase noise
performance
I Synthesizer frequencies for a wide range of world wide DVB standards (for IF center
frequencies of e.g. 34.5 MHz, 36 MHz, 44 MHz and 57 MHz)
I TAGC detector for independent tuner gain control loop applications
I TAGC operating as peak detector, fast reaction time due to additional speed-up
detector
I Port function
I TAGC voltage monitor output
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
2 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
2.4 FM radio mode
I Gain controlled wideband Radio IF (RIF) amplifier; AC-coupled
I Buffered RIF amplifier wideband output, gain controlled by internal RIF AGC
I Use of external FM sound BP filter
I 2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for
DSP
I Alignment-free selective FM PLL demodulator with high linearity and low noise
I Precise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus
I Port function
I Radio AFC or tuner, RIF or FM AGC voltage monitor output
3. Applications
I Analog and digital TV front-end applications for TV sets, recording applications and
personal computer cards
4. Quick reference data
Table 1.
Quick reference data
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
4.5
-
Typ
5.0
-
Max
5.5
Unit
V
[1]
VP
IP
supply voltage
supply current
ATV QSS; B/G standard;
sound carrier trap on;
sound BP on
175
mA
Analog TV signal processing
Video part
Vi(IF)(RMS)
RMS IF input voltage
lower limit at −1 dB video
-
60
100
µV
output signal
GVIF(cr)
fVIF
control range VIF gain
VIF frequency
60
-
66
-
-
-
dB
see Table 24
MHz
∆fVIF(dah)
digital acquisition help VIF
frequency window
related to fVIF
all standards except M/N
M/N standard
-
±2.3
±1.8
2.0
-
MHz
MHz
V
-
-
Vo(video)(p-p) peak-to-peak video output voltage positive or negative
modulation; normal mode
1.7
2.3
and sound carrier on;
W6[1] = 0; W4[7] = 0;
W7[4] = 0; see Figure 10
[2][3]
[2][3]
Gdif
differential gain
“ITU-T J.63 line 330”
B/G standard
-
-
-
-
5
7
%
%
L standard
ϕdif
differential phase
“ITU-T J.63 line 330”
B/G standard
-
-
2
2
4
4
deg
deg
L standard
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
3 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[4]
[4]
Bvideo(−3dB) −3 dB video bandwidth
trap bypass mode and
sound carrier off; AC load:
CL < 20 pF, RL > 1 kΩ
6
8
-
MHz
αSC1
first sound carrier attenuation
weighted signal-to-noise ratio
M/N standard;
f = fSC1 = 4.5 MHz;
see Figure 21
38
35
53
-
-
-
-
dB
dB
dB
[4]
B/G standard;
f = fSC1 = 5.5 MHz;
see Figure 23
-
[2][5]
(S/N)w
normal mode and sound
carrier on; B/G standard;
50 % grey video signal;
unified weighting filter
(“ITU-T J.61”);
57
see Figure 20
[2]
[6]
PSRRCVBS power supply ripple rejection on
pin CVBS
normal mode and sound
carrier on; fripple = 70 Hz;
video signal; grey level;
positive and negative
14
20
-
dB
modulation; see Figure 11
∆IAFC/∆fVIF change of AFC current with VIF
AFC TV mode
0.85
430
1.05
540
1.25
650
µA/kHz
frequency
Audio part
Vo(AF)(RMS) RMS AF output voltage
FM: QSS mode;
mV
27 kHz FM deviation;
50 µs de-emphasis
AM: 54 % modulation
400
-
500
600
mV
%
THD
total harmonic distortion
FM: 50 µs de-emphasis;
FM deviation: for TV mode
27 kHz and for radio mode
22.5 kHz
0.15
0.50
AM: 54 % modulation;
BP on; see Figure 33
-
0.5
1.0
-
%
f−3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
80
100
kHz
width = 237.5 kHz
(S/N)w(AF)
AF weighted signal-to-noise ratio
“ITU-R BS.468-4”
FM: 27 kHz FM deviation;
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only
48
56
-
dB
AM: BP off
44
14
50
20
-
-
dB
dB
PSRR
power supply ripple rejection
fripple = 70 Hz; see Figure 11
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
4 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vo(RMS)
RMS output voltage
IF intercarrier single-ended
to GND; see Figure 9 and
Table 21
B/G standard;
SC1 on; SC2 off;
internal BP via FM AGC
90
90
140
140
180
180
mV
mV
L standard; without
modulation; W7[5] = 0;
internal BP + 6 dB
FM sound part
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
2
-
300
mV
W1[1:0] = 11 or
W1[1:0] = 01; see Figure 9
[6]
∆IAFC/∆fRIF change of AFC current with RIF
AFC radio mode
0.85
35
1.05
46
1.25
-
µA/kHz
frequency
αAM
AM suppression
referenced to 27 kHz
FM deviation;
dB
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
Digital TV signal processing
Digital direct IF
[7]
[8]
Vo(dif)(p-p)
peak-to-peak differential output
voltage
between pin OUT2A and
pin OUT2B
W4[7] = 0
W4[7] = 1
-
-
-
1.0
0.50
83
1.1
0.55
-
V
V
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
dB
[8]
[8]
GIF(cr)
PSRR
control range IF gain
60
66
-
dB
power supply ripple rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
-
-
60
60
-
-
dB
dB
Digital low IF
Vo(dif)(p-p)
[7]
[8]
[8]
peak-to-peak differential output
voltage
between pin OUT1A and
pin OUT1B; W4[7] = 0
-
-
2
-
-
V
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
89
dB
GIF(cr)
fsynth
control range IF gain
synthesizer frequency
60
-
66
-
-
-
dB
see Table 34 and Table 35
MHz
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
5 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 1.
Quick reference data …continued
VP = 5 V; Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ϕn(synth)
synthesizer phase noise
with 4 MHz crystal oscillator
reference; fsynth = 31 MHz;
fIF = 36 MHz
[8]
[8]
[8]
[8]
at 1 kHz
89
89
98
115
-
99
99
102
119
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
at 10 kHz
at 100 kHz
at 1.4 MHz
-
-
-
αripple(pb)LIF low IF pass-band ripple
6 MHz bandwidth
2.7
2.7
2.7
-
7 MHz bandwidth
-
-
dB
8 MHz bandwidth
-
-
dB
αstpb
αimage
C/N
stop-band attenuation
image rejection
8 MHz band; f = 15.75 MHz
−10 MHz to 0 MHz; BP on
at fo = 4.9 MHz;
30
30
112
40
34
118
dB
-
dB
[8][9][10]
carrier-to-noise ratio
-
dBc/Hz
Vi(IF) = 10 mV (RMS);
see Figure 37
Reference frequency input from external source
[11]
fref
reference frequency
W7[7] = 0
-
4
-
MHz
mV
Vref(RMS)
RMS reference voltage
W7[7] = 0; see Figure 34
and Figure 46
15
150
500
[1] Values of video and sound parameters can be decreased at VP = 4.5 V.
[2] AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[3] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[4] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[5] Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[6] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by resistors R1 and R2.
[7] With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[8] This parameter is not tested during production and is only given as application information.
[9] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[11] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
6 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
Version
TDA9897HL/V3
TDA9897HN/V3
LQFP48
SOT313-2
SOT619-1
HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
TDA9898HL/V3
TDA9898HN/V3
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
SOT619-1
HVQFN48 plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 × 7 × 0.85 mm
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
7 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
6. Block diagram
SDA
SCL
i.c.
ADRSEL BVS
GNDD
22
23
24
14
25
32
2
I C-BUS
TDA9898
FM peak
A
B
36
SIF AGC
AGCDIN
AM average
sideband
SYNTHESIZER
VCO
3
4
IF3A
IF3B
Q
C
SIDEBAND
FILTER
I
D
6
7
Q
I
IF1A
IF1B
NYQUIST
FILTER
E
VIF PLL
sideband (L-accent)
9
IF2A
10
IF2B
CIFAGC
VIF AGC
5
VIF AFC
ACQUISITION
HELP
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
2
I C-BUS
F
45
DECODER
i.c.
TOPNEG
standard
trap reference
TOP2
TOP1
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
standard
SYNTHESIZER
AND VCO
L STANDARD
TUNER
G
H
2
I C-BUS TOPPOS
AND RSSI
47
TAGC
AGC
J
48
2, 18, 37
8
11
TOP2
optional tuner
13
1
38
34
GDS
GND
CTAGC
LFVIF
LFSYN2
LFSYN1
n.c.
AGC TOP for
positive
001aai732
modulation and
radio signal
strength detector
onset
Fig 1. Block diagram of TDA9898 (continued in Figure 2)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
8 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
4 MHz reference
input
(2)
(2)
R
R
EXTERNAL SOUND
(1)
BAND-PASS FILTER
V
GNDA
40, 41
EXTFILO EXTFILI
15 17
FREF
46
OPTXTAL
39
P
43, 44
4 MHz FREQUENCY
REFERENCE
+3 dB
SUPPLY
29
30
OUT2A
OUT2B
A
B
TDA9898
OUTPUT
SWITCH
26
27
OUT1A
OUT1B
FM
AGC
BP on/off
C
D
BAND-PASS
FILTER
21
EXTFMI
FM
SWITCH
20 CDEEM
31
FM
NB PLL
AUD
28 CAF
AM
DEMODULATOR
E
F
AM
SWITCH
33
16
CVBS
MPP
VIF AGC
TAGC
SIF AGC
FM AGC
AFC
VIF
AGC
G
H
12
35
PORT1
PORT2
port
port
TAGC
42
J
PORT3
2
I C-bus
port
19
LFFM
001aai733
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 2. Block diagram of TDA9898 (continued from Figure 1)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
9 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
SDA
SCL
i.c.
ADRSEL BVS
GNDD
22
23
24
14
25
32
2
I C-BUS
TDA9897
FM peak
A
B
36
SIF AGC
AGCDIN
AM average
sideband
SYNTHESIZER
VCO
3
4
IF3A
IF3B
Q
C
SIDEBAND
FILTER
I
D
6
7
Q
I
IF1A
IF1B
NYQUIST
FILTER
E
VIF PLL
sideband
9
IF2A
IF2B
10
VIF AGC
VIF AFC
ACQUISITION
HELP
SOUND
CARRIER
TRAP
GROUP
DELAY
EQUALIZER
2
I C-BUS
F
45
DECODER
i.c.
TOPNEG
standard
trap reference
TOP2
TOP1
PEAK
AGC
TUNER
RSSI
DETECTOR
AND
standard
SYNTHESIZER
AND VCO
L STANDARD
TUNER
G
H
2
I C-BUS TOPPOS
AND RSSI
47
TAGC
AGC
J
48
2, 5, 18, 37
8
11
TOP2
optional tuner
13
1
38
34
GND
CTAGC
LFVIF
LFSYN2
LFSYN1
GDS
n.c.
AGC TOP for
positive
001aai734
modulation and
radio signal
strength detector
onset
Fig 3. Block diagram of TDA9897 (continued in Figure 4)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
10 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
4 MHz reference
input
(2)
(2)
R
R
EXTERNAL SOUND
(1)
BAND-PASS FILTER
V
GNDA
40, 41
EXTFILO EXTFILI
15 17
FREF
46
OPTXTAL
39
P
43, 44
4 MHz FREQUENCY
REFERENCE
+3 dB
SUPPLY
29
30
OUT2A
OUT2B
A
B
TDA9897
OUTPUT
SWITCH
26
27
OUT1A
OUT1B
FM
AGC
C
D
BP on/off
BAND-PASS
FILTER
21
EXTFMI
FM
SWITCH
20 CDEEM
31
FM
NB PLL
AUD
28 CAF
AM
DEMODULATOR
E
F
AM
SWITCH
33
16
CVBS
MPP
VIF AGC
TAGC
SIF AGC
FM AGC
AFC
VIF
AGC
G
H
12
35
PORT1
PORT2
port
port
TAGC
port
42
J
PORT3
2
I C-bus
19
LFFM
001aai735
(1) Optional.
(2) Connect resistor if input or crystal is not used.
Fig 4. Block diagram of TDA9897 (continued from Figure 3)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
11 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
7. Pinning information
7.1 Pinning
1
2
36
35
34
33
32
31
30
29
28
27
26
25
LFSYN2
n.c.
AGCDIN
PORT2
GDS
3
IF3A
4
IF3B
(1)
CVBS
BVS
5
CIFAGC
6
IF1A
IF1B
AUD
TDA9897HL
TDA9898HL
7
OUT2B
OUT2A
CAF
8
CTAGC
IF2A
9
10
11
12
IF2B
OUT1B
OUT1A
ADRSEL
TOP2
PORT1
008aaa150
(1) Not connected for TDA9897HL.
Fig 5. Pin configuration for LQFP48
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
12 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
terminal 1
index area
1
2
36
35
34
33
32
31
30
29
28
27
26
25
LFSYN2
n.c.
AGCDIN
PORT2
GDS
3
IF3A
4
IF3B
CVBS
BVS
(1)
5
CIFAGC
6
IF1A
IF1B
AUD
TDA9897HN
TDA9898HN
7
OUT2B
OUT2A
CAF
8
CTAGC
IF2A
9
10
11
12
IF2B
OUT1B
OUT1A
ADRSEL
TOP2
PORT1
008aaa151
Transparent top view
(1) Not connected for TDA9897HN.
Fig 6. Pin configuration for HVQFN48
7.2 Pin description
Table 3.
Pin description
Pin Description
Symbol
LFSYN2
n.c.
1
2
3
4
5
loop filter synthesizer 2 (conversion synthesizer)
not connected
IF3A
IF symmetrical input 3 for sound
IF3B
CIFAGC
TDA9898: IF AGC capacitor; L standard
TDA9897: not connected
IF1A
6
IF symmetrical input 1 for vision or digital
IF1B
7
CTAGC
IF2A
8
TAGC capacitor
9
IF symmetrical input 2 for vision or digital
IF2B
10
11
12
13
14
15
TOP2
PORT1
LFVIF
i.c.
TOP potentiometer for positive modulated standards and RSSI reference
digital port function 1 or VIF AGC monitor output
loop filter VIF PLL
internally connected; connect to ground
output to external filter
EXTFILO
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Multistandard hybrid IF processing
Table 3.
Pin description …continued
Symbol
Pin Description
MPP
16
multipurpose pin: VIF AGC or SIF AGC or FM AGC or TAGC or VIF AFC or
FM AFC monitor output
EXTFILI
n.c.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
input from external filter
not connected
LFFM
CDEEM
EXTFMI
GNDD
SDA
loop filter FM PLL
de-emphasis capacitor
external FM input
digital ground
I2C-bus data input and output
I2C-bus clock input
SCL
ADRSEL
OUT1A
OUT1B
CAF
address select
low IF or 2nd sound intercarrier symmetrical output
Direct Current (DC) decoupling capacitor
1st Digital IF (DIF) symmetrical output
OUT2A
OUT2B
AUD
audio signal output
I2C-bus voltage select
BVS
CVBS
GDS
composite video signal output
additional video group delay select; leave open for default operation[1]
digital port function 2
PORT2
AGCDIN
n.c.
AGC input for DIF amplifier for e.g. input from channel decoder AGC
not connected
LFSYN1
loop filter synthesizer 1 (filter control synthesizer)
optional quartz input
OPTXTAL 39
GNDA
GNDA
PORT3
VP
40
41
42
43
44
45
46
47
48
analog ground
analog ground
digital port function 3 or TAGC monitor output
supply voltage
VP
supply voltage
i.c.
internally connected; connect to ground
4 MHz reference input
FREF
TAGC
GND
TAGC output
ground; plateau connection
[1] Recommendation: Leave this pin open or use a capacitor to GND, as shown in the application diagrams in
Figure 47, Figure 48 and Figure 49.
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Multistandard hybrid IF processing
8. Functional description
8.1 IF input switch
Different signal bandwidth can be handled by using two signal processing chains with
individual gain control.
Switch configuration allows independent selection of filter for analog VIF and for analog
SIF (used at same time) or DIF.
The switch takes into account correct signal selection for TAGC in the event of VIF and
DIF signal processing.
8.2 VIF demodulator
ATV demodulation using 6 MHz DVB window (band-pass) filter (for 6 MHz, 7 MHz or
8 MHz channel width).
IF frequencies adapted to enable the use of different filter configurations. The Nyquist
processing is integrated. The integrated Nyquist processing provides also adjacent
channel suppression. Sideband switch supplies selection of lower or upper sideband (e.g.
for L-accent).
For optional use of standard Nyquist filter the integrated Nyquist processing can be
switched off.
Equalizer provides optimum pulse response at different standards [e.g. to cope with
higher demands for Liquid Crystal Display (LCD) TV].
Integrated sound traps.
Sound trap reference independent from received 2nd sound IF (reference taken from
integrated reference synthesizer).
IF level selection provides an optimum adaptation of the demodulator to high linearity or
low noise.
8.3 VIF AGC and tuner AGC
8.3.1 Mode selection of VIF AGC
Peak white AGC for positive modulation mode with adaptation for speed up and black level
AGC (using proven system from TDA9886).
For negative modulation mode equal response times for increasing or decreasing input
level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.
8.3.2 VIF AGC monitor
VIF AGC DC voltage monitor output (with expanded internal characteristic).
VIF AGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting
(TOP setting either via I2C-bus or via TOP potentiometer).
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Multistandard hybrid IF processing
8.3.3 Tuner AGC
Independent integral tuner gain control loop (not nested with VIF AGC). Integral
characteristic provides high control accuracy.
Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via
I2C-bus.
For L standard, TAGC remains VIF AGC nested, as from field experience in the past this
narrowband TAGC gives best performance.
Thus two switchable TAGC systems for negative/DIF and positive modulation
implemented.
L standard tuner time constant switching integrated (= speed up function in the event of
step into high input levels), to speed up settling time.
For TOP setting at L standard, additional adjustment via optional potentiometer or I2C-bus
is provided.
Tuner AGC status bit provided.
8.4 DIF/SIF FM and AM sound AGC
External AGC control input for DIF. DIF includes direct IF and low IF.
Integrated gain control loop for SIF.
AGC control for FM SIF related to used SAW bandwidth.
Peak AGC control in the event of FM SIF.
Ultra fast SIF AGC time constant when VIF AGC set to ultra fast mode.
Slow average AGC control in the event of AM sound.
AM sound AGC related to AM sound carrier level.
Fast AM sound AGC in the event of fast VIF AGC (speed up).
SIF/FM AGC DC voltage monitor output with expanded internal characteristic.
8.5 Frequency phase-locked loop for VIF
Basic function as previous TDA9887 design.
PLL gating mode for positive and negative modulation, optional.
PLL optimized for either overmodulation or strong multipath.
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Multistandard hybrid IF processing
8.6 DIF/SIF converter stage
Frequency conversion with sideband suppression.
Selection mode of upper or lower sideband for pass or suppression.
Suppression around zero for frequency conversion.
Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency
Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM).
External BP filter (e.g. for 4.5 MHz) for additional filtering, optional.
Bypass mode selection for use of external filter.
Integrated SIF BP tracking filter for chroma suppression.
Integrated tracking filters for LIF.
Symmetrical output stages for direct IF, LIF and 2nd SIF (intercarrier signal).
Second narrowband gain control loop for 2nd SIF via FM PLL.
8.7 Mono sound demodulator
8.7.1 FM PLL narrowband demodulation
Additional external input for either TV or radio intercarrier signal.
FM carrier selection independent from VIF trap, because VIF trap uses reference via
synthesizer.
FM wide and ultra wide mode with adapted loop bandwidth and different selectable
FM acquisition window widths to cope with FM overmodulation conditions.
8.7.2 AM sound demodulation
AM sound envelope detector.
L and L-accent standard without SAW switching (done by sideband selection of SIF
converter).
8.8 Audio amplifier
Different gain settings for FM sound to adapt to different FM deviation.
Switchable de-emphasis for FM sound.
Automatic mute function when FM PLL is unlocked.
Forced mute function.
Output amplifier for AM sound.
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Multistandard hybrid IF processing
8.9 Synthesizer
The synthesizer supports SIF/DIF frequency conversion. A large set of synthesizer
frequencies in steps of 0.5 MHz enables flexible combination of SAW filter and required
conversion frequency.
Synthesizer loop internally adapted to divider ratio range for optimum phase noise
requirement (loop bandwidth).
Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins
for crystal and external reference allows optimum interface definition and supports use of
custom reference frequency offset.
8.10 I2C-bus transceiver and slave address
Four different I2C-bus device addresses to enable application with multi-IC use.
I2C-bus transceiver input ports can handle three different I2C-bus voltages.
Read-out functions as TDA9887 plus additional read out of VIF AGC and VIFLOCK,
BLCKLEV and TAGC status.
Table 4.
Slave address detection
Slave address
Selectable address bit
Pin ADRSEL
A3
0
A0
1
MAD1
MAD2
MAD3
MAD4
GND
0
0
VP
1
1
resistor to GND
resistor to VP
1
0
9. I2C-bus control
Table 5.
Slave addresses
For MAD activation via pin ADRSEL: see Table 4.
Slave address
Bit
A6
1
Name
MAD1
MAD2
MAD3
MAD4
Value
A5
0
A4
0
A3
0
A2
0
A1
1
A0
1
43h
42h
4Bh
4Ah
1
0
0
0
0
1
0
1
0
0
1
0
1
1
1
0
0
1
0
1
0
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Multistandard hybrid IF processing
9.1 Read format
S
BYTE 1
A6 to A0
slave address
A
BYTE 2
D7 to D0
data (R1)
A
BYTE 3
D7 to D0
data (R2)
NA
P
R/W
1
from master to slave
from slave to master
S = START condition
A = acknowledge
NA = not acknowledge
P = STOP condition
001aad167
Fig 7. I2C-bus read format (slave transmits data)
Table 6.
7
R1 - data read register 1 bit allocation
6
5
4
3
2
1
0
AFCWIN BLCKLEV CARRDET
AFC4
AFC3
AFC2
AFC1
PONR
Table 7.
R1 - data read register 1 bit description
Bit
Symbol
Description
7
AFCWIN
AFC window[1]
1 = VCO in ±1.6 MHz AFC window[2]
1 = VCO in ±0.8 MHz AFC window[3]
0 = VCO out of ±1.6 MHz AFC window[2]
0 = VCO out of ±0.8 MHz AFC window[3]
6
5
BLCKLEV black level detection
1 = black level detected
0 = no black level detected
CARRDET FM carrier detection[4]
1 = detection (FM PLL is locked and level is less than 6 dB below gain
controlled range of FM AGC)
0 = no detection
4 to 1
0
AFC[4:1]
PONR
automatic frequency control; see Table 8
power-on reset
1 = after power-on reset or after supply breakdown
0 = after a successful reading of the status register
[1] If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC
window border for fast lock-in behavior.
[2] All standards except M/N standard.
[3] M/N standard.
[4] Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is
80 ms.
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Multistandard hybrid IF processing
Table 8.
Automatic frequency control bits
fnom is the nominal frequency.
Bit
f[1]
AFC4
AFC3
AFC2
AFC1
R1[1]
R1[4]
R1[3]
R1[2]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
≤ (fnom − 187.5 kHz)
fnom − 162.5 kHz
fnom − 137.5 kHz
fnom − 112.5 kHz
fnom − 87.5 kHz
fnom − 62.5 kHz
fnom − 37.5 kHz
fnom − 12.5 kHz
fnom + 12.5 kHz
fnom + 37.5 kHz
fnom + 62.5 kHz
fnom + 87.5 kHz
fnom + 112.5 kHz
fnom + 137.5 kHz
fnom + 162.5 kHz
≥ (fnom + 187.5 kHz)
[1] In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.
Table 9.
7
R2 - data read register 2 bit allocation
6
5
4
3
2
1
0
VIFLOCK
TAGC
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
Table 10. R2 - data read register 2 bit description
Bit
Symbol
Description
7
VIFLOCK VIF PLL lock-in detection
1 = VIF PLL is locked
0 = VIF PLL is not locked
6
TAGC
tuner AGC
1 = active
0 = inactive
5 to 0
VAGC[5:0] AGC level detector; VIF AGC in ATV mode, SIF AGC in radio mode and
DIF AGC in DTV mode; see Table 11
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Multistandard hybrid IF processing
Table 11. AGC bits
Bit
Typical
∆VAGC(VIF)
(V)
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
R2[4]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
R2[3]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
R2[2]
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
R2[1]
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
R2[0]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (TOP)[1]
−0.04
−0.08
−0.12
−0.16
−0.20
−0.24
−0.28
−0.32
−0.36
−0.40
−0.44
−0.48
−0.52
−0.56
−0.60
−0.64
−0.68
−0.72
−0.76
−0.80
−0.84
−0.88
−0.92
−0.96
−1.00
−1.04
−1.08
−1.12
−1.16
−1.20
−1.24
−1.28
−1.32
−1.36
−1.40
−1.44
−1.48
−1.52
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Multistandard hybrid IF processing
Table 11. AGC bits …continued
Bit
Typical
∆VAGC(VIF)
(V)
VAGC5
VAGC4
VAGC3
VAGC2
VAGC1
VAGC0
R2[5]
0
R2[4]
1
R2[3]
1
R2[2]
0
R2[1]
0
R2[0]
0
−1.56
−1.60
−1.64
−1.68
−1.72
−1.76
−1.80
−1.84
−1.88
−1.92
−1.96
−2.00
−2.04
−2.08
−2.12
−2.16
−2.20
−2.24
−2.28
−2.32
−2.36
−2.40
−2.44
−2.48
−2.52
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
[1] The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 47 and Table 45) or
via potentiometer at pin TOP2.
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Multistandard hybrid IF processing
9.2 Write format
S
BYTE 1
A6 to A0
slave address
A
BYTE 2
A7 to A0
A
BYTE 3
bits 7 to 0
data 1
A
BYTE n
bits 7 to 0
data n
A
P
R/W
0
subaddress
from master to slave
from slave to master
S = START condition
A = acknowledge
P = STOP condition
001aad166
Fig 8. I2C-bus write format (slave receives data)
9.2.1 Subaddress
Table 12. W0 - subaddress register bit allocation
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Table 13. W0 - subaddress register bit description
Bit
Symbol
A[7:4]
Description
7 to 4
3 to 0
has to be set to logic 0
subaddress; see Table 14
A[3:0]
Table 14. Subaddress control bits
Bit
Mode
A3
0
A2
0
A1
0
A0
0
subaddress for register W1
subaddress for register W2
subaddress for register W3
subaddress for register W4
subaddress for register W5
subaddress for register W6
subaddress for register W7
subaddress for register W8
subaddress for register W9
subaddress for register W10
subaddress for register W11
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
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Multistandard hybrid IF processing
Table 15. I2C-bus write register overview
The register setting after power-on is not specified.
Register 7
6
5
4
3
2
1
0
W1[1]
W2[2]
W3[3]
W4[4]
W5[5]
W6[6]
W7[7]
W8[8]
W9[9]
W10[10]
W11[11]
RADIO
STD1
STD4
AMUTE
BP
STD0
STD3
FMUTE
MPPS1
TV
0
0
FM
EXTFIL
TRAP
AGAIN0
VIFIN
SFREQ0
MOD
STD2
FMWIDE0
MPPS0
SFREQ4
AGC1
SB
PLL
GATE
AGAIN1
IFIN0
SFREQ1
RESCAR
VIFLEVEL
FSFREQ1
TAGC1
DEEMT
AMMODE
SFREQ3
FMWIDE1
DEEM
IFIN1
SFREQ2
TWOFLO
MODEP1
FSFREQ0 SFREQ5
TAGC0
VAGC
AGC2
VIDEO1V7 DIRECT
FILOUTBP NYQOFF
EXTFILO
FEATURE
SIFLEVEL VIDLEVEL PORT1
AVIDRED
MODEP3
TAGCTC
TAGCIN3
FORCESP PORT3
PORT2
0
DAGCSLOPE TAGCIS
TOPNEG4 TOPNEG3 TOPNEG2 TOPNEG1 TOPNEG0
0
0
READTAGC XPOTPOS TOPPOS4
OFFSETN OFFSETP
TOPPOS3
TOPPOS2
TOPPOS1
VIFIN3
TOPPOS0
VIF31875
0
BLACKAGC GDEQ
[1] See Table 17 for detailed description of W1.
[2] See Table 23 for detailed description of W2.
[3] See Table 27 for detailed description of W3.
[4] See Table 29 for detailed description of W4.
[5] See Table 33 for detailed description of W5.
[6] See Table 37 for detailed description of W6.
[7] See Table 40 for detailed description of W7.
[8] See Table 42 for detailed description of W8.
[9] See Table 44 for detailed description of W9.
[10] See Table 47 for detailed description of W10.
[11] See Table 50 for detailed description of W11.
9.2.2 Description of data bytes
Table 16. W1 - data write register bit allocation
7
6
5
4
3
2
1
0
RADIO
STD1
STD0
TV
0
0
FM
EXTFIL
Table 17. W1 - data write register bit description
Bit
Symbol
Description
FM mode
7
RADIO
1 = radio
0 = ATV/DTV
6 and 5
4
STD[1:0]
TV
2nd sound IF; see Table 18 and Table 19
TV mode
1 = ATV QSS
0 = DTV; direct IF or LIF; depends on setting of TV mode (W6[0])
0 = fixed value
3 and 2
1 and 0
-
FM and EXTFIL FM and output switching; see Table 21
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NXP Semiconductors
Multistandard hybrid IF processing
Table 18. Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode
For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.
Bit
fFMPLL Sound BP
(MHz)
RADIO
MOD
STD1
STD0
FSFREQ1
FSFREQ0
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
4.5
5.5
6.0
6.5
off
M/N standard
B/G standard
I standard
D/K standard
L/L-accent standard
Table 19. Intercarrier sound BP and FM PLL frequency select for radio
For description of bit MOD refer to Table 23 and bits FSFREQ[1:0] are described in Table 33.
Bit
fFMPLL Sound BP
(MHz)
RADIO
MOD
STD1
STD0
FSFREQ1
FSFREQ0
W1[7]
W2[7]
W1[6]
W1[5]
W5[7]
W5[6]
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
4.5
5.5
6.0
6.5
M/N standard
B/G standard
I standard
D/K standard
Table 20. Intercarrier sound FM PLL frequency select for radio 10.7 MHz
For description of bit MOD refer to Table 23 and for BP refer to Table 29.
Bit
fFMPLL (MHz)
BP
MOD
W2[7]
0
RADIO
W1[7]
1
W4[6]
0
10.7
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Multistandard hybrid IF processing
Table 21. 2nd intercarrier and sound I/O switching
Switch input numbering in accordance with Figure 9.
AMMODE MOD FM
EXTFIL Audio
mode
Input signal selection Signal at OUT1A and OUT1B Mono sound
Input switch
FM AM
input input path
Output switch
W4[3]
W2[7] W1[1] W1[0]
Signal
Input Signal path
Demodulation
via
X
X
X
X
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FM
sound
1
2
3
2
1
X
X
2
2
X
X
2
X
X
X
X
5
5
5
5
4
5
5
4
internal
EXTFILI
EXTFMI
EXTFILI
internal
internal
internal
EXTFILI
EXTFILI
internal
internal
EXTFILI
6
7
7
6
6
7
7
6
7
7
7
6
internal BP via FM AGC internal BP
internal BP
internal BP
external BP
external input
external BP via FM AGC external BP
AM
sound 1
internal BP + 6 dB
internal BP
internal BP
external BP
internal BP
internal BP
internal BP
external BP
internal BP
internal BP
internal BP
internal BP
external BP
internal BP
internal BP
external BP
AM
sound 2
BYPASS
output
switch
internal
7
6
OUT1A
OUT1B
BAND-PASS
W7.1 = 0
W7.1 = 1
3 dB
FM:
AGC
amplifier
input
switch
1
2
3
external filter output
external filter input
FM PLL
input
switch
AM:
fixed-gain
amplifier
external FM input
4
5
AM
DEMODULATOR
EXTFILI
EXTFILO EXTFMI
008aaa145
Fig 9. Signal path for intercarrier (2nd SIF) processing
TDA9897_TDA9898_4
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Multistandard hybrid IF processing
Table 22. W2 - data write register bit allocation
7
6
5
4
3
2
1
0
MOD
STD4
STD3
STD2
SB
PLL
GATE
TRAP
Table 23. W2 - data write register bit description
Bit
Symbol
Description
7
MOD
modulation
1 = negative; FM mono sound at ATV
0 = positive; AM mono sound at ATV
vision IF; see Table 24
sideband for sound IF and digital low IF
1 = upper
6 to 4
3
STD[4:2]
SB
0 = lower
2
1
PLL
operating modes; see Table 25
PLL gating
GATE
1 = on; fPC = fVIF ± 175 kHz
0 = off
0
TRAP
sound trap
1 = on
0 = bypass
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Multistandard hybrid IF processing
Table 24. Vision IF
Bit
fVIF (MHz) Sideband
in case of
VIF31875 NYQOFF MOD
W11[0][1] W7[0]
STD4
STD3
STD2
TV = 1
(QSS)
W7[0] = 0
W2[7]
W2[6]
W2[5]
W2[4]
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
38.0
low
low
low
low
low
low
low
low
high
high
high
high
high
-
38.375
38.875
39.875
45.75
58.75
46.25
59.25
32.25
32.625
33.125
33.625
31.875
33.9
0
0
0
0
0
0
1
X
1
X
1
0
33.9
high
high
high
1
X
X
35.0
1
36.0
[1] Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass
of any W11 bit.
Table 25. VIF PLL gating and detector mode
Bit
Gating and detector mode
MOD
PLL
W2[7]
W2[2]
0
0
1
0
1
0
0 % gating in positive modulation mode (W2[1] = 1)
36 % gating in positive modulation mode (W2[1] = 1)
π mode on; optimized for overmodulation in negative modulation mode;
fPC = fVIF ± 175 kHz
1
1
π mode off; optimized for multipath in negative modulation mode;
fPC = fVIF ± 175 kHz
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Multistandard hybrid IF processing
Table 26. W3 - data write register bit allocation
7
6
5
4
3
2
1
0
RESCAR
AMUTE
FMUTE FMWIDE0 DEEMT
DEEM
AGAIN1
AGAIN0
Table 27. W3 - data write register bit description
Bit
Symbol
Description
7
RESCAR
video gain correction for residual carrier
1 = 20 % residual carrier
0 = 10 % residual carrier
auto mute
6
AMUTE
FMUTE
1 = on
0 = off
5
forced mute
1 = on
0 = off
4
FMWIDE0 FM window (W6[3] = 0)
1 = 475 kHz; normal FM phase detector steepness
0 = 237.5 kHz; high FM phase detector steepness
3
DEEMT
DEEM
de-emphasis time
1 = 50 µs
0 = 75 µs
2
de-emphasis
1 = on
0 = off
1 and 0
AGAIN[1:0] audio gain
00 = 0 dB
01 = −6 dB
10 = −12 dB (only for FM mode)
11 = −18 dB (only for FM mode)
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Multistandard hybrid IF processing
Table 28. W4 - data write register bit allocation
7
6
5
4
3
2
1
0
VIFLEVEL
BP
MPPS1
MPPS0 AMMODE
IFIN1
IFIN0
VIFIN
Table 29. W4 - data write register bit description
Bit
Symbol
Description
7
VIFLEVEL control of internal VIF mixer input level (W1[4] = 1) and OUT1/OUT2
output level; see Table 30
1 = reduced[1]
0 = normal
6
BP
SIF/DIF BP
1 = on (bit W6[0] = 0; see Table 37)
0 = bypass
5 and 4
3
MPPS[1:0] AGC or AFC output; see Table 31
AMMODE AM mode extension; see Table 21
1 = second selection set
0 = first selection set
2 and 1
IFIN[1:0]
DIF/SIF input
00 = IF1A/B input
01 = IF3A/B input
10 = not used
11 = IF2A/B input
VIF input (W11[1] = 0)
1 = IF1A/B input
0 = IF2A/B input
0
VIFIN
[1] Not recommended in combination with internal video level set to reduced (W7[4] = 1).
Table 30. List of output signals at OUT1 and OUT2
Bit
Output signal at
TV
DIRECT
FM
EXTFIL
OUT1A,
OUT1B
OUT2A,
OUT2B
W1[4]
W6[0]
W1[1]
W1[0]
0
0
1
1
1
1
0
X
X
0
0
1
1
X
X
0
1
0
1
low IF
off
1
off
direct IF
off
X
X
X
X
intercarrier[1]
intercarrier[2]
intercarrier[2]
intercarrier[1]
off
off
off
[1] Intercarrier output level based on wideband AGC of SIF amplifier.
[2] Intercarrier output level based on narrowband AGC of FM amplifier.
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Multistandard hybrid IF processing
Table 31. Output mode at pin MPP for ATV or radio mode
Bit
Pin MPP output mode
VAGC
RADIO
MPPS1
MPPS0
W7[6]
W1[7]
W4[5]
W4[4]
0
0
0
0
0
1
X
X
X
0
0
0
1
1
1
0
0
1
0
1
1
0
gain control voltage of FM PLL
gain control voltage of SIF amplifier
TAGC monitor voltage
AFC current output, VIF PLL
AFC current output, radio mode
gain control voltage of VIF amplifier
1
X
Table 32. W5 - data write register bit allocation
7
6
5
4
3
2
1
0
FSFREQ1
FSFREQ0
SFREQ5 SFREQ4 SFREQ3 SFREQ2 SFREQ1 SFREQ0
Table 33. W5 - data write register bit description
Bit
Symbol
Description
7 and 6
FSFREQ[1:0] DTV filter or sound trap selection for video
ATV; sound trap; TV = 1; see Table 16 and Table 17
00 = M/N standard (4.5 MHz)
01 = B/G standard (5.5 MHz)
10 = I standard (6.0 MHz)
11 = D/K and L/L-accent standard (6.5 MHz)
DTV (low IF); upper BP cut-off frequency; TV = 0; see Table 16 and
Table 17
00 = 7.0 MHz
01 = 8.0 MHz
10 = 9.0 MHz
11 = recommended mode for direct IF; W6[0] = 1
SFREQ[5:0] synthesizer frequencies; see Table 34 and Table 35
5 to 0
TDA9897_TDA9898_4
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Multistandard hybrid IF processing
Table 34. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0)
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
W5[4]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
W5[3]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
W5[2]
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
W5[1]
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
W5[0]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
35.0
35.5
36.0
36.5
37.0
37.5
38.0
38.5
39.0
39.5
40.0
40.5
41.0
TDA9897_TDA9898_4
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Multistandard hybrid IF processing
Table 34. DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) …continued
Bit
fsynth (MHz)
SFREQ5
SFREQ4
SFREQ3
SFREQ2
SFREQ1
SFREQ0
W5[5]
W5[4]
W5[3]
W5[2]
W5[1]
W5[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
41.5
42.0
42.5
43.0
43.5
44.0
44.5
45.0
45.5
46.0
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
50.5
51.0
51.5
52.0
52.5
53.0
53.5
Table 35. DIF/SIF synthesizer frequency for Japan (using bit TWOFLO = 1)
Bit
fsynth (MHz)
SFREQ5
W5[5]
1
SFREQ4
W5[4]
1
SFREQ3
W5[3]
0
SFREQ2
W5[2]
0
SFREQ1
W5[1]
1
SFREQ0
W5[0]
0
57
TDA9897_TDA9898_4
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NXP Semiconductors
Multistandard hybrid IF processing
Table 36. W6 - data write register bit allocation
7
6
5
4
3
2
1
0
TAGC1
TAGC0
AGC2
AGC1
FMWIDE1 TWOFLO VIDEO1V7 DIRECT
Table 37. W6 - data write register bit description
Bit Symbol Description
7 and 6 TAGC[1:0] tuner AGC mode[1]
00 = TAGC integral loop mode; all currents off
01 = TAGC integral loop mode; source current off
10 = TAGC integral loop mode
11 = TAGC derived from IF AGC; recommended for positive modulated
signals
5 and 4 AGC[2:1]
AGC mode and behavior; see Table 38
3
2
1
FMWIDE1 FM window
1 = 1 MHz
0 = see Table 27 bit FMWIDE0
TWOFLO synthesizer frequency selection
1 = Japan mode (57 MHz)
0 = synthesizer mode
VIDEO1V7 video output level selection; sound carrier trap set to on (W2[0] = 1);
see Table 22 and Table 23
1 = 1.7 V at CVBS
0 = 2.0 V at CVBS
0
DIRECT
direct IF at DTV mode; TV set to DTV (W1[4] = 0); see Table 16 and
Table 17
1 = direct IF output
0 = low IF output
[1] In TAGC integral loop mode the pin TAGC provides sink and source currents for control. TakeOver Point
(TOP) is set via register TOPNEG W9[4:0].
Table 38. AGC mode and behavior
Bit
VIF AGC
mode
SIF AGC
mode
MOD
FORCESP
AGC2
AGC1
W2[7]
W8[3]
W6[5]
W6[4]
0
0
0
0
0
1
1
1
1
0
0
0
0
1
X
X
X
X
0
0
1
1
X
0
0
1
1
0
1
0
1
X
0
1
0
1
normal
normal
minimum gain minimum gain
normal
normal
fast
normal
fast
fast
normal
normal
minimum gain minimum gain
2nd
normal
fast
2nd fast
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NXP Semiconductors
Multistandard hybrid IF processing
Table 39. W7 - data write register bit allocation
7
6
5
4
3
2
1
0
EXTFILO
VAGC
SIFLEVEL VIDLEVEL PORT1
MODEP1 FILOUTBP NYQOFF
Table 40. W7 - data write register bit description
Bit
Symbol
Description
7
EXTFILO mute of output buffer of pin EXTFILO
1 = mute
0 = normal
6
5
VAGC
gain control voltage of VIF amplifier at pin MPP; see Table 31
SIFLEVEL SIF level reduction
1 = internal SIF level is reduced by 6 dB (only for AM sound)
0 = internal SIF level is normal
VIDLEVEL video level reduction
4
3
2
1
0
1 = internal video level is reduced by 6 dB[1]
0 = internal video level is normal
PORT1
output state; port 1 mode selection set to logic output port (W7[2] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
MODEP1 port 1 mode selection; pin PORT1
1 = logic output port; level controlled by bit PORT1 (W7[3])
0 = monitor output of VIF AGC voltage
FILOUTBP external filter output signal source; see Figure 9
1 = signal for external filter is obtained behind internal BP filter
0 = signal for external filter is obtained behind SIF mixer
NYQOFF
internal Nyquist processing; see Table 24
1 = internal Nyquist processing off[2]
0 = internal Nyquist processing on
[1] Not recommended in combination with internal IF level set to reduced (W4[7] = 1).
[2] At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level to normal
(W7[4] = 0).
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 41. W8 - data write register bit allocation
7
6
5
4
3
2
1
0
FEATURE AVIDRED MODEP3 TAGCIN3 FORCESP
PORT3
PORT2
0
Table 42. W8 - data write register bit description
Bit
Symbol
Description
7
FEATURE feature enable
1 = feature PORT2; PORT3 monitor output of TAGC voltage and data
write register W11[7:0] enabled
0 = feature disabled; pin PORT2 and pin PORT3 set to high-ohmic;
data write register W11[7:0] = 0000 0000
6
5
4
AVIDRED automatic reduction of internal video level for PC / SC < 11.0 dB
1 = enabled
0 = disabled
MODEP3 port 3 mode selection; pin PORT3
1 = logic output port; level controlled by bit PORT3 (W8[2])
0 = monitor output of TAGC voltage
TAGCIN3 TAGC IF input selection; feature enable set to enable (W8[7] = 1)
1 = IF3A and IF3B input
0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input
selection (W4[0])
3
2
FORCESP VIF AGC and SIF AGC fast mode activation; modulation setting
(W2[7] = 0)
1 = forced
0 = automatic; dependent on video level
PORT3
output state; feature enable set to enable (W8[7] = 1); port 3 mode
selection set to logic output port (W8[5] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
1
0
PORT2
-
output state; feature enable set to enable (W8[7] = 1)
1 = output port is HIGH (external pull-up resistor needed)
0 = output port is LOW
0 = fixed value
TDA9897_TDA9898_4
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 43. W9 - data write register bit allocation
7
6
5
4
3
2
1
0
DAGCSLOPE
TAGCIS
TAGCTC
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
Table 44. W9 - data write register bit description
Bit
Symbol
Description
7
DAGCSLOPE AGCDIN input characteristic; see Figure 44
1 = high voltage for high gain
0 = low voltage for high gain
6
TAGCIS
tuner AGC IF input (TOP1)
1 = inverse to VIF input
0 = aligned to VIF input
tuner AGC charge current (TOP1)
1 = high
5
TAGCTC
0 = normal
4 to 0
TOPNEG[4:0] TOP adjustment for integral loop mode (TOP1); recommended for negative modulation;
see Table 45
Table 45. Tuner takeover point adjustment bits W9[4:0]
Bit
TOP adjustment
(dBµV)[1]
TOPNEG4
TOPNEG3
TOPNEG2
TOPNEG1
TOPNEG0
W9[4]
W9[3]
W9[2]
W9[1]
W9[0]
1
:
1
:
1
:
1
:
1
:
98.5 typical
see Figure 13
79.3[2]
1
:
0
:
0
:
0
:
0
:
see Figure 13
59.6 typical
0
0
0
0
0
[1] Average step size is 1.255 dB typical.
[2] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP).
Table 46. W10 - data write register bit allocation
7
6
5
4
3
2
1
0
0
READTAGC XPOTPOS
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
Table 47. W10 - data write register bit description
Bit
7
Symbol
Description
-
0 = fixed value
6
READTAGC
signal source for TAGC read-out on R2[6]
1 = inverse to used TAGC detector (integral or IF based)
0 = aligned to used TAGC detector (integral or IF based)
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 — 25 May 2009
37 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 47. W10 - data write register bit description …continued
Bit
Symbol
Description
5
XPOTPOS
TOP derived from IF AGC via I2C-bus or potentiometer (TOP2)
1 = TOP adjustment by external potentiometer at pin TOP2
0 = see Table 48
4 to 0
TOPPOS[4:0] TOP adjustment for TAGC derived from IF AGC (TOP2); recommended for positive
modulation; see Table 48
Table 48. Tuner takeover point adjustment bits W10[4:0]
Bit
TOP adjustment
(dBµV)
TOPPOS4
TOPPOS3
TOPPOS2
TOPPOS1
TOPPOS0
W10[4]
W10[3]
W10[2]
W10[1]
W10[0]
1
:
1
:
1
:
1
:
1
:
99.0 typical
see Figure 13
78.5[1]
1
:
0
:
0
:
0
:
0
:
see Figure 13
56.9 typical
0
0
0
0
0
[1] See Table 53 for parameter tuner takeover point accuracy (αacc(set)TOP2).
Table 49. W11 - data write register bit allocation
7
6
5
4
3
2
1
0
0
0
OFFSETN
OFFSETP
BLACKAGC
GDEQ
VIFIN3
VIF31875
Table 50. W11 - data write register bit description[1]
Bit
Symbol
-
Description
7 and 6
5
0 = fixed value
OFFSETN
VIF PLL offset sink current (approximately 0.6 µA)
1 = enabled (requires W11[4] = 0)
0 = disabled
4
3
2
OFFSETP
BLACKAGC
GDEQ
VIF PLL offset source current (approximately 0.6 µA)
1 = enabled (requires W11[5] = 0)
0 = disabled
black level AGC
1 = disabled
0 = enabled
activate group delay equalizer
1 = on (if pin 34 is open-circuit)
1 = off (if pin 34 is connected to ground)
0 = off (if pin 34 is open-circuit)
0 = on (if pin 34 is connected to ground)
VIF input selection
1
VIFIN3
1 = IF3A and IF3B input
0 = IF1A and IF1B input or IF2A and IF2B input depends on VIF input selection (W4[0])
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
38 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 50. W11 - data write register bit description[1] …continued
Bit
Symbol
Description
0
VIF31875
VIF frequency selection for global ATV application inclusive DVB-T; see Table 24
1 = 31.875 MHz
0 = 32.250 MHz
[1] Register W11 is logical AND protected by bit W8[7]. Therefore it is required to set W8[7] = 1 to enable pass of any W11 bit.
10. Limiting values
Table 51. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VP
Parameter
Conditions
Min Max
Unit
V
supply voltage
-
5.5
VP
10
Vn
voltage on any other pin
short-circuit time
storage temperature
ambient temperature
case temperature
all pins except ground
to ground or VP
0
-
V
tsc
s
Tstg
−40 +150
−20 +70
°C
°C
°C
°C
°C
°C
V
Tamb
Tcase
TDA9898HL (LQFP48)
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
human body model
-
-
-
-
-
-
105
115
105
115
[1]
[2]
Vesd
electrostatic discharge voltage
±3000
±300
machine model
V
[1] Class 2 according to JESD22-A114.
[2] Class B according to EIA/JESD22-A115.
11. Thermal characteristics
Table 52. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
TDA9898HL (LQFP48)
in free air; 2 layer board
67
48
67
48
K/W
K/W
K/W
K/W
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
thermal resistance from junction to case
TDA9898HL (LQFP48)
Rth(j-c)
19
10
19
10
K/W
K/W
K/W
K/W
TDA9898HN (HVQFN48)
TDA9897HL (LQFP48)
TDA9897HN (HVQFN48)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
39 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
12. Characteristics
12.1 Analog TV signal processing
Table 53. Characteristics
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin VP
[1]
VP
IP
supply voltage
supply current
4.5
-
5.0
-
5.5
V
ATV QSS; B/G standard;
sound carrier trap on;
sound BP on
175
mA
Power-on reset
VP(POR)
[2]
[2]
power-on reset supply
voltage
for start of reset at
decreasing supply voltage
2.5
-
3.0
3.3
3.5
4.4
V
V
for end of reset at
increasing supply voltage;
I2C-bus transmission
enable
VIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B
VI
input voltage
-
-
-
1.95
2
-
-
-
V
[3]
[3]
Ri(dif)
Ci(dif)
differential input resistance
kΩ
pF
differential input
capacitance
3
Vi(IF)(RMS)
RMS IF input voltage
lower limit at −1 dB video
output signal
-
60
100
-
µV
upper limit at +1 dB video
output signal
150
190
mV
[4]
permissible overload
-
-
-
320
-
mV
dB
∆GIF
IF gain variation
difference between picture
and sound carrier; within
AGC range; ∆f = 5.5 MHz
0.7
GVIF(cr)
control range VIF gain
60
-
66
15
80
-
-
-
dB
f−3dB(VIF)l
f−3dB(VIF)u
lower VIF cut-off frequency
MHz
MHz
upper VIF cut-off frequency
-
VIF PLL and true synchronous video demodulator[5]
VLFVIF
fVCO(max)
fVIF
voltage on pin LFVIF (DC)
0.9
120
-
-
3.6
V
maximum VCO frequency fVCO = 2fPC
140
-
-
-
MHz
MHz
VIF frequency
see Table 24
∆fVIF(dah)
digital acquisition help VIF related to fVIF
frequency window
all standards except
-
-
±2.3
±1.8
-
-
MHz
MHz
M/N
M/N standard
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
40 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
tacq
Parameter
Conditions
Min
Typ
-
Max
30
Unit
ms
[6]
acquisition time
-
-
Vlock(min)(RMS)
RMS minimum lock-in
voltage
measured on active IF
input pins;
30
70
µV
maximum IF gain;
negative modulation mode
W2[7] = 1 and PLL set to
overmodulation mode
W2[2] = 0 and W2[1] = 0
Tcy(dah)
tw(dah)
digital acquisition help
cycle time
-
64
-
-
µs
µs
µA
digital acquisition help
pulse width
64
21
-
Ipul(acq)VIF
VIF acquisition pulse
current
sink or source
-
33
KO(VIF)
KD(VIF)
VIF VCO steepness
∆fVIF / ∆VLFVIF
-
-
26
33
-
-
MHz/V
VIF phase detector
steepness
∆IVPLL / ∆ϕVCO(VIF)
µA/rad
Ioffset(VIF)
VIF offset current
−1
0
+1
µA
Video output 2 V; pin CVBS[7]
Normal mode (sound carrier trap active) and sound carrier on
Vo(video)(p-p)
peak-to-peak video output positive or negative
voltage
modulation; W6[1] = 0;
see Figure 10
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
1.7
1.7
1.7
2.0
2.0
2.0
2.3
2.3
2.3
V
V
V
∆Vo(CVBS)
CVBS output voltage
difference
difference between
L and B/G standard;
W3[7] = 0
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
−240
−240
−240
-
-
-
+240
+240
+240
mV
mV
mV
difference between
I and B/G standard;
20 % residual carrier at
I standard; W3[7] = 1
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
−100
−100
−100
2.0
-
+100
+100
+100
2.75
mV
mV
mV
-
-
Vvideo/Vsync
video voltage to sync
voltage ratio
2.33
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
41 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
1.0
0.9
0.9
Typ
1.2
1.2
1.2
Max
1.4
1.5
1.5
-
Unit
V
Vsyncl
sync level voltage
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
V
V
Vclip(video)u
upper video clipping
voltage
VP − 1.2 VP − 1
V
Vclip(video)l
RO
Ibias(int)
Isink(o)(max)
lower video clipping voltage
output resistance
-
0.4
-
0.9
30
-
V
[3]
-
Ω
internal bias current (DC)
for emitter-follower
AC and DC
1.5
1
2.0
-
mA
mA
maximum output sink
current
-
Isource(o)(max)
maximum output source
current
AC and DC
3.9
-
-
mA
∆Vo(CVBS)
CVBS output voltage
difference
50 dB gain control
30 dB gain control
negative modulation
-
-
-
-
-
-
0.5
0.1
1
dB
dB
%
∆Vblt/VCVBS
black level tilt to CVBS
voltage ratio
∆Vblt(v)/VCVBS
vertical black level tilt to
CVBS voltage ratio
worst case in L standard;
vision carrier modulated
by test line [Vertical
Interval Test Signal
(VITS)] only
-
-
3
%
[8]
[8]
[9]
Gdif
differential gain
“ITU-T J.63 line 330”
B/G standard
-
-
-
-
5
7
%
%
L standard
ϕdif
differential phase
“ITU-T J.63 line 330”
B/G standard
-
2
4
4
-
deg
deg
dB
L standard
-
2
(S/N)w
weighted signal-to-noise
ratio
B/G standard; 50 % grey
video signal; unified
weighting filter
53
57
(“ITU-T J.61”);
see Figure 20
(S/N)unw
unweighted signal-to-noise M/N standard; 50 IRE grey
47
51
-
dB
ratio
video signal;
see Figure 20
VPC(rsd)(RMS)
RMS residual picture
carrier voltage
fundamental wave and
harmonics
-
-
2
-
5
mV
[3]
∆fPC(p-p)
peak-to-peak picture carrier 3 % residual carrier;
12
kHz
frequency variation
50 % serration pulses;
L standard
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
42 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[3]
∆ϕ
phase difference
0 % residual carrier;
-
-
3
%
50 % serration pulses;
L standard; L-gating = 0 %
[10]
[11]
αH(video)
video harmonics
suppression
AC load: CL < 20 pF,
RL > 1 kΩ
35
40
-
dB
αsp
spurious suppression
40
14
-
-
-
dB
dB
PSRRCVBS
power supply ripple
fripple = 70 Hz;
20
rejection on pin CVBS
video signal; grey level;
positive and negative
modulation; see Figure 11
M/N standard inclusive Korea; see Figure 21[12]
αripple(resp)f
frequency response ripple 0.5 MHz to 2.5 MHz
2.5 MHz to 3.6 MHz
−1.5
−2
-
+1
+1
+1
+1
-
dB
dB
dB
dB
dB
dB
dB
dB
ns
-
3.6 MHz to 3.8 MHz
−3
-
3.8 MHz to 4.2 MHz
−16
38
-
αSC1
first sound carrier
attenuation
f = fSC1 = 4.5 MHz
f = fSC1 ± 60 kHz
f = fSC2 = 4.724 MHz
f = fSC2 ± 60 kHz
-
29
-
-
αSC2
second sound carrier
attenuation
25
-
-
16
-
-
[13]
td(grp)CC
color carrier group delay
time
f = 3.58 MHz; including
transmitter pre-correction;
see Figure 22
−75
−50
+75
B/G standard; see Figure 23[12]
αripple(resp)f
frequency response ripple 0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
−1.5
−3
-
-
-
-
-
-
-
-
-
+1
+1
+1
+1
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 4.8 MHz
−5
4.8 MHz to 5 MHz
−12
35
αSC1
first sound carrier
attenuation
f = fSC1 = 5.5 MHz
f = fSC1 ± 60 kHz
f = fSC2 = 5.742 MHz
f = fSC2 ± 60 kHz
26
-
αSC2
second sound carrier
attenuation
25
-
16
-
αSC(NICAM)
α
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
12
-
attenuation
f = f(N+1)ch = 7 MHz
21
5
-
-
dB
dB
ns
f = f(N+1)ch ± 750 kHz
-
-
[13]
td(grp)CC
color carrier group delay
time
f = 4.43 MHz; including
transmitter pre-correction;
see Figure 24
−75
−10
+75
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
43 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I standard; see Figure 25[12]
αripple(resp)f
frequency response ripple 0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
−1.5
−2
-
-
-
-
-
-
-
+1
+1
+1
+1
-
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 5 MHz
−4
5 MHz to 5.5 MHz
−12
35
αSC1
first sound carrier
attenuation
f = fSC1 = 6.0 MHz
f = fSC1 ± 60 kHz
26
-
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 6.55 MHz;
f = fcar(NICAM) ± 250 kHz
12
-
[13]
td(grp)CC
color carrier group delay
time
f = 4.43 MHz;
see Figure 26
−75
−15
+75
ns
D/K standard; see Figure 27[12]
αripple(resp)f
frequency response ripple 0.5 MHz to 3.1 MHz
3.1 MHz to 4.5 MHz
−1.5
−2
−4
−6
35
26
25
16
25
16
6
-
-
-
-
-
-
-
-
-
-
-
+1
+1
+1
+1
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
4.5 MHz to 4.8 MHz
4.8 MHz to 5.1 MHz
αSC1
first sound carrier
attenuation
f = fSC1 = 6.5 MHz
f = fSC1 ± 60 kHz
f = fSC2 = 6.742 MHz
f = fSC2 ± 60 kHz
f = fSC2 = 6.258 MHz
f = fSC2 ± 60 kHz
-
αSC2(us)
second sound carrier
attenuation (upper side)
-
-
αSC2(ls)
second sound carrier
attenuation (lower side)
-
-
αSC(NICAM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
-
[13]
td(grp)CC
color carrier group delay
time
f = 4.28 MHz; including
transmitter pre-correction;
see Figure 28
−50
0
+100
ns
L standard; see Figure 29[12]
αripple(resp)f
frequency response ripple 0.5 MHz to 3.2 MHz
3.2 MHz to 4.5 MHz
−1.5
−2
-
-
-
-
-
+1
+1
+1
+1
-
dB
dB
dB
dB
dB
4.5 MHz to 4.8 MHz
−4
4.8 MHz to 5.3 MHz
−12
5
αSC(NICAM)
αSC(AM)
NICAM sound carrier
attenuation
fcar(NICAM) = 5.85 MHz;
f = fcar(NICAM) ± 250 kHz
AM sound carrier
attenuation
f = fSC(AM) = 6.5 MHz
38
-
-
dB
dB
ns
f = fSC(AM) ± 30 kHz
29
-
-
td(grp)CC
color carrier group delay
time
f = 4.28 MHz; including
transmitter pre-correction;
see Figure 30
−75
−5
+75
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
44 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Video output 1.7 V; pin CVBS; see Figure 50, optional CVBS buffer at setting W6[1] = 1
Normal mode (sound carrier trap active) and sound carrier on
Vo(video)(p-p)
peak-to-peak video output positive or negative
voltage
modulation; W6[1] = 1;
see Figure 10
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
W4[7] = 0; W7[4] = 0
W4[7] = 1; W7[4] = 0
W4[7] = 0; W7[4] = 1
1.44
1.44
1.44
1.0
1.7
1.7
1.7
1.2
1.2
1.2
1.96
1.96
1.96
1.4
V
V
V
V
V
V
Vsyncl
sync level voltage
0.9
1.5
0.9
1.5
Video output 1.1 V; pin CVBS
Trap bypass mode and sound carrier off[12]
Vo(video)(p-p)
peak-to-peak video output see Figure 10
voltage
-
-
1.1
1.5
-
V
Vsyncl
sync level voltage
-
-
V
V
Vclip(video)u
upper video clipping
voltage
VP − 1.2 VP − 1
Vclip(video)l
lower video clipping voltage
-
0.4
8
0.9
-
V
Bvideo(−3dB)
−3 dB video bandwidth
AC load: CL < 20 pF,
6
MHz
RL > 1 kΩ
[9]
[9]
(S/N)w
weighted signal-to-noise
ratio
B/G standard; 50 % grey
video signal; unified
weighting filter
(“ITU-T J.61”);
see Figure 20
54
-
-
dB
(S/N)unw
unweighted signal-to-noise M/N standard; 50 IRE grey
47
51
-
dB
ratio
video signal;
see Figure 20
VIF AGC
Pin MPP
Vmonitor(VIFAGC)
VAGC
[3]
VIF AGC monitor voltage
AGC voltage
0.5
-
4.5
V
see Figure 12; Vi(IF) set to
1 mV (60 dBµV)
2.0
2.4
3.0
-
-
-
2.5
3.0
VP
V
V
V
10 mV (80 dBµV)
200 mV (106 dBµV)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
45 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[14]
tresp
response time
increasing VIF step;
negative modulation
normal mode
2nd mode
-
-
-
100
9
-
-
-
µs/dB
µs/dB
µs/dB
fast 2nd mode
3
[14]
[14]
[15]
increasing VIF step;
positive modulation
normal mode
fast mode
-
-
100
5
-
-
µs/dB
µs/dB
decreasing VIF step;
negative modulation
normal mode
-
-
-
-
-
70
250
20
80
6
-
-
-
-
-
µs/dB
µs/dB
µs/dB
µs/dB
µs/dB
2nd mode
2nd mode (speed-up)
fast 2nd mode
[15]
[14]
fast 2nd mode
(speed-up)
decreasing VIF step;
positive modulation
20 dB
-
900
180
3
-
ms
normal mode
-
-
ms/dB
ms/dB
ms/dB
dB
fast mode; W8[3] = 1
fast mode (speed-up)
L standard
-
-
[16]
-
24
−6
40
-
αth(fast)VIF
VIF fast mode threshold
−10
−2
-
∆VVAGC(step)
VIF AGC voltage difference see Table 11
(step)
-
mV/bit
Pin CIFAGC
Ich(max)
maximum charge current
L standard; normal mode;
W8[3] = 0
75
-
100
2.0
125
µA
mA
nA
L standard; fast mode;
W8[3] = 1
-
-
Ich(add)
additional charge current
discharge current
L standard: in the event of
missing VITS pulses and
no white video content
-
100
Idch
L standard; normal mode;
W8[3] = 0
-
-
35
-
-
nA
L standard; fast mode;
W8[3] = 1 or speed-up
1.4
µA
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
46 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tuner AGC; pin TAGC
TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF;
see Table 44 and Figure 13
Vi(IF)(RMS)
RMS IF input voltage
for TOP1; at starting point
of tuner AGC takeover;
I
sink(TAGC) = 100 µA
W9[4:0] = 0 0000
W9[4:0] = 1 0000
W9[4:0] = 1 1111
-
59.6
78.3
98.5
-
-
dBµV
dBµV
dBµV
dB
-
-
-
-
αacc(set)TOP1
TOP1 setting accuracy
source current
−2
+2
Isource
TAGC charge current
W9[5] = 0
0.20
1.6
7
0.33
2.5
11
0.45
3.4
15
µA
µA
µA
W9[5] = 1
fast mode activated by
internal level detector;
W9[5] = 0
fast mode activated by
internal level detector;
W9[5] = 1
60
90
120
µA
Isink
sink current
TAGC discharge current;
375
-
500
0.006
-
625
µA
VTAGC = 1 V
∆αacc(set)TOP1/∆T TOP1 setting accuracy
W9[4:0] = 1 0000
0.02
dB/K
variation with temperature
[3]
[3]
RL
load resistance
50
-
-
MΩ
Vsat(u)
upper saturation voltage
pin operating as current
output
VP − 0.3 -
V
Vsat(l)
lower saturation voltage
AGC fast mode threshold
pin operating as current
output
-
-
0.3
10
V
αth(fast)AGC
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
6
8
dB
td
delay time
before activating; Vi(IF)
40
60
80
ms
below αth(fast)AGC
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
47 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and
optional for negative modulation); see Table 47, Figure 13 and Figure 14
Vi(IF)(RMS)
RMS IF input voltage
for TOP2; at starting point
of tuner AGC takeover;
VTAGC = 3.5 V
RTOP2 = 22 kΩ or
W10[5:0] = 00 0000
-
-
56.9
78.5
-
-
dBµV
dBµV
RTOP2 = 10 kΩ or
W10[5:0] = 01 0000
RTOP2 = 0 kΩ
-
98
99
-
-
dBµV
dBµV
dB
W10[5:0] = 01 1111
-
-
αacc(set)TOP2
TOP2 setting accuracy
−8
-
+8
0.07
∆αacc(set)TOP2/∆T TOP2 setting accuracy
VTAGC = 3.5 V
0.03
dB/K
variation with temperature
VO
output voltage
no tuner gain reduction
4.5
0.2
-
-
VP
V
V
maximum tuner gain
reduction
0.6
∆Gslip(TAGC)
TAGC slip gain offset
tuner gain voltage from
0.6 V to 3.5 V
3
5
8
dB
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14
VTOP2
RI
voltage on pin TOP2 (DC) pin open-circuit
input resistance
-
-
3.5
27
-
-
V
kΩ
RTOP2
resistance on pin TOP2
adjustment of VIF AGC
based TAGC loop
W10[5] = 1; external
resistor operation
0
-
-
22
-
kΩ
kΩ
W10[5] = 0; forced
I2C-bus operation
100
Pin CTAGC
[3]
[3]
[3]
VCTAGC
IL
voltage on pin CTAGC
leakage current
0.2
-
0.55VP
V
sink or source
-
-
-
10
-
nA
MΩ
RO
output resistance
equivalent time constant
resistance
10
Pin MPP output characteristic
General
Vsat(u)
Vsat(l)
Io(max)
RO
upper saturation voltage
VP − 0.8 VP − 0.5
-
V
lower saturation voltage
maximum output current
output resistance
-
0.5
-
0.8
-
V
[3]
[3]
sink or source
350
-
µA
kΩ
1.3
3
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
48 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
AGC monitor (voltage output)
Gv voltage gain
Parameter
Conditions
Min
Typ
Max
Unit
[17]
voltage on pin MPP to
internal control voltage;
see Table 31
VIF AGC; see Figure 12
SIF AGC; see Figure 16
FM AGC; see Figure 15
TAGC; see Figure 12
-
-
-
-
6
6
6
0
-
-
-
-
dB
dB
dB
dB
AFC monitor (current output)
[18][19]
Io
output current
sink or source;
see Figure 17 and
Figure 18
100 kHz VIF deviation
200 kHz VIF deviation
1.5 MHz VIF deviation
80
-
160
240
240
µA
µA
µA
160
160
200
-
AFC TV mode
[19]
[20]
[20]
∆IAFC/∆fVIF
change of AFC current with
VIF frequency
0.85
−20
−20
1.05
1.25
+20
+20
µA/kHz
kHz
fVIFacc(dig)
fVIFacc(a)
digital accuracy of VIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
-
-
analog accuracy of VIF
frequency
IAFC = 0 A; fref = 4 MHz
kHz
AFC radio mode
[19]
[20]
[20]
∆IAFC/∆fRIF
change of AFC current with
RIF frequency
0.85
−10
−10
1.05
1.25
+10
+10
µA/kHz
kHz
fRIFacc(dig)
fRIFacc(a)
digital accuracy of RIF
frequency
read-out via I2C-bus;
R1[4:1] = f0; fref = 4 MHz
-
-
analog accuracy of RIF
frequency
IAFC = 0 A; fref = 4 MHz
kHz
Pin PORT1 or pin PORT3 operating as voltage monitor
Vsat(u)
Vsat(l)
Io(max)
RO
upper saturation voltage
lower saturation voltage
maximum output current
output resistance
VP − 0.8 VP − 0.5
-
V
-
0.5
-
0.8
V
[3]
[3]
sink or source
10
-
-
µA
kΩ
dB
1.3
6
3
-
[3][17]
Gv
voltage gain
voltage ratio: pin PORT1
to internal VIF AGC
voltage
-
[3][17]
voltage ratio: pin PORT3
to internal TAGC voltage
-
-
0
-
dB
SIF amplifier; pins IF1A and IF1B or pins IF2A and IF2B or pins IF3A and IF3B
VI
input voltage
1.95
-
V
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
49 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Ri(dif)
Parameter
Conditions
Min
Typ
2
Max
Unit
kΩ
differential input resistance
-
-
-
-
Ci(dif)
differential input
capacitance
3
pF
Vi(SIF)(RMS)
RMS SIF input voltage
FM mode; −3 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
-
60
100
µV
AM mode; −3 dB at
AF output pin AUD
-
40
70
-
µV
FM mode; +1 dB at
intercarrier output
pins OUT1A and OUT1B;
without FM AGC;
see Table 21
150
190
mV
AM mode; +1 dB at
AF output pin AUD
70
140
-
mV
permissible overload
FM and AM mode
-
-
320
mV
GSIF(cr)
control range SIF gain
60
-
66
7
-
-
-
dB
f−3dB(SIF)l
f−3dB(SIF)u
lower SIF cut-off frequency
upper SIF cut-off frequency
MHz
MHz
-
80
SIF AGC detector; pin MPP; see Figure 16
tresp
response time
increasing or decreasing
SIF step of 20 dB;
AM mode; fast AGC
increasing
decreasing
-
-
8
-
-
ms
ms
10
increasing or decreasing
SIF step of 20 dB;
AM mode; slow AGC
increasing
decreasing
-
-
65
-
-
ms
ms
125
increasing or decreasing
SIF step of 20 dB;
FM mode; normal AGC
increasing
decreasing
-
-
0.09
28
-
-
ms
ms
increasing or decreasing
SIF step of 20 dB;
FM mode; fast AGC
increasing
decreasing
-
-
0.03
4
-
-
ms
ms
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
50 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
FM mode
Min
Typ
Max
Unit
VAGC(SIF)
SIF AGC voltage
VSIF = 100 µV
VSIF = 10 mV
VSIF = 140 mV
AM mode
1.2
2.4
3.1
-
-
-
2.1
3.2
VP
V
V
V
VSIF = 100 µV
VSIF = 10 mV
VSIF = 70 mV
1.4
2.6
3.2
-
-
-
2.3
3.4
VP
V
V
V
Conversion synthesizer PLL; pin LFSYN2 (radio mode)
VLFSYN2
KO
voltage on pin LFSYN2
VCO steepness
1
-
-
3
-
V
∆fVCO / ∆VLFSYN2
31
MHz/V
KD
phase detector steepness ∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
32
38
47
61
61
-
-
-
-
-
µA/rad
µA/rad
µA/rad
µA/rad
µA/rad
Io(PD)
phase detector output
current
sink or source;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
200
238
294
384
384
-
-
-
-
-
µA
µA
µA
µA
µA
ϕn(synth)
synthesizer phase noise
with 4 MHz crystal
oscillator reference;
f
f
synth = 31 MHz;
IF = 36 MHz
[3]
[3]
[3]
[3]
[3]
[3]
at 1 kHz
89
89
98
115
50
-
99
99
102
119
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
at 10 kHz
at 100 kHz
at 1.4 MHz
-
-
-
αsp
spurious suppression
leakage current
multiple of ∆f = 500 kHz
-
IL
synthesizer spurious
performance > 50 dBc
-
10
nA
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
51 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
power supply ripple
rejection
residual spurious at
-
50
-
dB
nominal differential output
voltage dependent on
power supply ripple at
70 Hz; see Figure 11
Single reference QSS intercarrier mixer; pins OUT1A and OUT1B
VOUT1A
VOUT1B
Ibias(int)
voltage on pin OUT1A (DC)
voltage on pin OUT1B (DC)
internal bias current (DC)
1.8
1.8
2.0
1.4
2.0
2.0
2.5
1.7
2.2
2.2
-
V
V
for emitter-follower
DC and AC
mA
mA
Isink(o)(max)
maximum output sink
current
-
Isource(o)(max)
RO
maximum output source
current
DC and AC; with external
resistor to GND
3.0
-
-
mA
Ω
output resistance
output active;
single-ended to GND
-
-
-
25
-
output inactive; internal
resistance to GND
800
Ω
Vo(RMS)
RMS output voltage
IF intercarrier
single-ended to GND;
B/G standard;
SC1 on; SC2 off;
see Figure 9 and Table 21
internal BP via FM AGC
internal BP
90
90
140
170
180
230
mV
mV
IF intercarrier
single-ended to GND;
L standard;
without modulation;
see Figure 9 and Table 21
W7[5] = 0;
internal BP + 6 dB
90
45
140
70
180
90
mV
mV
W7[5] = 1;
internal BP + 6 dB
W7[5] = 0; internal BP
W7[5] = 1; internal BP
45
20
11
70
35
15
90
45
-
mV
mV
f−3dB(ic)u
αimage
upper intercarrier cut-off
frequency
internal sound band-pass
off
MHz
image rejection
band-pass off;
−8 MHz to 0 MHz
24
-
28
2
-
dB
Vinterf(RMS)
RMS interference voltage
fundamental wave and
harmonics
5
mV
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
52 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B
G
gain
IF intercarrier; L standard;
without modulation
-
5
-
dB
Band-pass mode
fc
center frequency
QSS mode;
BP selection for standard
M/N
-
-
-
-
-
4.7
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
B/G
5.75
6.25
6.25
6.05
I
D/K
L/L-accent
radio mode;
BP selection for standard
M/N
B/G
I
-
-
-
-
4.7
-
-
-
-
MHz
MHz
MHz
MHz
5.75
6.25
6.25
D/K
f−3dB(BP)u
f−3dB(BP)l
αstpb
upper BP cut-off frequency
lower BP cut-off frequency
stop-band attenuation
fc + 0.5 fc + 0.65 fc + 0.8 MHz
fc − 0.5 fc − 0.65 fc − 0.8 MHz
20
30
-
dB
αCC
color carrier attenuation
QSS mode;
BP selection for standard
M/N; fCC = 3.58 MHz
B/G; fCC = 4.43 MHz
I; fCC = 4.43 MHz
15
22
20
20
20
23
30
28
28
28
-
-
-
-
-
dB
dB
dB
dB
dB
D/K; fCC = 4.28 MHz
L/L-accent;
fCC = 4.28 MHz
External filter output; pin EXTFILO
VEXTFILO
voltage on pin EXTFILO
(DC)
1.8
2.0
2.2
V
VEXTFILO(p-p)
peak-to-peak voltage on
pin EXTFILO
IF intercarrier; SC1 on;
SC2 off
420
620
820
mV
IF intercarrier; L standard;
without modulation
W7[5] = 0
W7[5] = 1
210
105
1
310
155
-
410
205
-
mV
mV
mA
Io(max)
maximum output current
AC and DC
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
53 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FM PLL demodulator
fFMPLL
FM PLL frequency
see Table 18 and Table 20
-
-
-
-
-
4.5
5.5
6.0
6.5
10.7
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
FM PLL filter; pin LFFM
VLFFM
voltage on pin LFFM
fFMPLL = 4.5 MHz
fFMPLL = 5.5 MHz
fFMPLL = 6.0 MHz
fFMPLL = 6.5 MHz
fFMPLL = 10.7 MHz
1.5
1.5
1.5
1.5
1.5
-
1.9
2.2
2.35
2.5
2.3
64
3.3
3.3
3.3
3.3
3.3
-
V
V
V
V
V
Tcy(dah)
tw(dah)
Io(dah)
digital acquisition help
cycle time
µs
digital acquisition help
pulse width
-
16
-
µs
digital acquisition help
output current
sink or source
W3[4] = 0; W6[3] = 0;
FM window
width = 237.5 kHz
14
28
14
28
18
36
18
36
22
44
22
44
µA
µA
µA
µA
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
W3[4] = 1; W6[3] = 1;
FM window
width = 1 MHz
KD(FM)
FM phase detector
steepness
∆IFMPLL / ∆ϕVCO(FM)
W3[4] = 0; W6[3] = 0;
FM window
-
-
-
-
5.5
-
-
-
-
µA/rad
µA/rad
µA/rad
µA/rad
width = 237.5 kHz
W3[4] = 1; W6[3] = 0;
FM window
width = 475 kHz
14.5
5.5
W3[4] = 0; W6[3] = 1;
FM window
width = 1 MHz
W3[4] = 1; W6[3] = 1;
FM window
14.5
width = 1 MHz
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
54 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
KO(FM)
FM VCO steepness
∆fFMPLL / ∆VLFFM
f < 10 MHz
-
3.3
5.9
0
-
MHz/V
MHz/V
µA
f = 10.7 MHz
-
-
Ioffset(FM)
FM offset current
W6[3] = 0; W3[4] = 0
W6[3] = 0; W3[4] = 1
−1.5
−2.5
+1.5
+2.5
0
µA
FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 9
|Zi|
input impedance
AC-coupled via 4 pF
-
20
-
-
kΩ
Vi(FM)(RMS)
RMS FM input voltage
gain controlled operation;
W1[1:0] = 10 or
2
300
mV
W1[1:0] = 11 or
W1[1:0] = 01
Vlock(min)(RMS)
RMS minimum lock-in
voltage
W1[1:0] = 10 or
W1[1:0] = 11 or
W1[1:0] = 01
-
-
-
-
1.5
1.8
mV
mV
Vdet(FM)min(RMS) RMS minimum FM carrier W1[1:0] = 10 or
detection voltage
W1[1:0] = 11 or
W1[1:0] = 01
FM demodulator part; audio output; pin AUD
Vo(AF)(RMS)
RMS AF output voltage
QSS mode;
25 kHz FM deviation;
75 µs de-emphasis
400
430
900
360
500
540
-
600
650
1300
540
mV
mV
mV
mV
QSS mode;
27 kHz FM deviation;
50 µs de-emphasis
QSS mode;
55 kHz FM deviation;
50 µs de-emphasis
radio mode;
450
22.5 kHz FM deviation;
75 µs de-emphasis
∆Vo(AF)/∆T
AF output voltage variation
with temperature
-
-
1.1 × 10−3 7 × 10−3 dB/K
0.15 0.50
THD
total harmonic distortion
50 µs de-emphasis;
FM deviation: for
%
TV mode 27 kHz and for
radio mode 22.5 kHz
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
55 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[21]
∆fAF(max)
maximum AF frequency
deviation
THD < 2 %; pre-emphasis
off; fAF = 400 Hz
W3[1:0] = 00 (audio
gain = 0 dB)
±55
-
-
-
-
-
-
-
-
kHz
kHz
kHz
kHz
W3[1:0] = 01 (audio
gain = −6 dB)
±110
±170
±380
W3[1:0] = 10 (audio
gain = −12 dB)
W3[1:0] = 11 (audio
gain = −18 dB) and
W3[4] = 1 (FM window
width = 475 kHz)
[3]
fAF(max)
maximum AF frequency
THD < 2 %;
pre-emphasis off
FM window
15
15
80
48
-
-
-
-
-
kHz
kHz
kHz
dB
width = 237.5 kHz;
−6 dB audio gain;
FM deviation 100 kHz
FM window
-
width = 475 kHz;
−18 dB audio gain;
FM deviation 300 kHz
f−3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0;
without de-emphasis;
FM window
100
56
width = 237.5 kHz
(S/N)w(AF)
AF weighted
27 kHz FM deviation;
50 µs de-emphasis; vision
carrier unmodulated;
FM PLL only;
signal-to-noise ratio
“ITU-R BS.468-4”
(S/N)unw(AF)
VSC(rsd)(RMS)
αAM
AF unweighted
signal-to-noise ratio
radio mode (10.7 MHz);
22.5 kHz FM deviation;
75 µs de-emphasis
-
58
-
-
dB
mV
dB
RMS residual sound carrier fundamental wave and
voltage
-
2
-
harmonics; without
de-emphasis
AM suppression
referenced to 27 kHz
FM deviation;
35
46
50 µs de-emphasis;
AM: f = 1 kHz; m = 54 %
PSRR
power supply ripple
rejection
f
ripple = 70 Hz;
14
20
-
dB
see Figure 11
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
56 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Audio amplifier
Audio output; pin AUD
[3]
RO
VO
RL
output resistance
-
-
300
Ω
output voltage
load resistance
2.0
10
100
-
2.4
2.7
V
[3]
[3]
[3]
AC-coupled
DC-coupled
-
-
-
-
kΩ
kΩ
nF
-
CL
load capacitance
1
Vo(AF)(RMS)
RMS AF output voltage
25 kHz FM deviation;
75 µs de-emphasis;
see Table 27
0 dB
400
500
250
125
62.5
600
mV
mV
mV
mV
−6 dB
−12 dB
−18 dB
-
-
-
-
-
-
AM; m = 54 %;
see Table 27
0 dB
400
500
250
150
600
mV
mV
kHz
−6 dB
-
-
-
-
[22]
[23]
f−3dB(AF)u
f−3dB(AF)l
upper AF cut-off frequency W3[2] = 0 (without
de-emphasis)
lower AF cut-off frequency W3[2] = 0 (without
de-emphasis)
-
20
-
Hz
αmute
mute attenuation
of AF signal
70
-
-
-
dB
∆Vjmp
jump voltage difference
(DC)
switching AF output to
mute state or vice versa;
activated by digital
±50
±150
mV
acquisition help W3[6] = 1
or via W3[5]
PSRR
power supply ripple
rejection
f
ripple = 70 Hz;
14
20
-
dB
see Figure 11
De-emphasis network; pin CDEEM
VO
RO
output voltage
-
2.4
-
-
V
output resistance
W3[3:2] = 11 (50 µs
8.5
14
kΩ
de-emphasis)
W3[3:2] = 01 (75 µs
de-emphasis)
13
-
-
21
-
kΩ
VAF(RMS)
RMS AF voltage
fAF = 400 Hz;
170
mV
Vo(AF) = 500 mV (RMS);
0 dB attenuation
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
57 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
AF decoupling
Pin CAF
Vdec
Parameter
Conditions
Min
Typ
Max
Unit
decoupling voltage (DC)
fFMPLL = 4.5 MHz
fFMPLL = 5.5 MHz
fFMPLL = 6.0 MHz
fFMPLL = 6.5 MHz
fFMPLL = 10.7 MHz
1.5
1.5
1.5
1.5
1.5
-
1.9
2.2
2.35
2.5
2.3
-
3.3
3.3
3.3
3.3
3.3
±25
V
V
V
V
V
IL
leakage current
∆VAUD < ±50 mV (p-p);
nA
0 dB attenuation
Io(max)
maximum output current
sink or source
1.15
1.5
1.85
µA
FM operation[24][25]
Single reference QSS AF performance; pin AUD[26]
(S/N)w(SC1)
first sound carrier weighted PC / SC1 > 40 dB at
signal-to-noise ratio
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz FM
deviation; BP off;
“ITU-R BS.468-4”
black picture
white picture
45
45
43
50
50
47
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
45
50
-
dB
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
58 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Single reference QSS AF performance with external FM demodulator connected to OUT1A and OUT1B[27]
(S/N)w(SC1) first sound carrier weighted PC / SC1 > 40 dB at
Parameter
Conditions
Min
Typ
Max
Unit
signal-to-noise ratio
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz
FM deviation; BP off;
“ITU-R BS.468-4”
black picture
white picture
53
50
44
58
53
48
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
40
45
46
45
51
52
-
-
-
dB
dB
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
(S/N)w(SC2)
second sound carrier
weighted signal-to-noise
ratio
with external reference
FM demodulator;
PC / SC2 > 40 dB at
pins IF1A and IF1B or
IF2A and IF2B; 27 kHz
(54 % FM deviation);
BP off; “ITU-R BS.468-4”
black picture
white picture
48
46
42
55
51
46
-
-
-
dB
dB
dB
6 kHz sine wave
(black-to-white
modulation)
250 kHz square wave
(black-to-white
modulation)
29
44
45
34
50
51
-
-
-
dB
dB
dB
sound carrier
subharmonics;
f = 2.75 MHz ± 3 kHz
sound carrier
subharmonics;
f = 2.87 MHz ± 3 kHz
AM operation
L standard; pin AUD
Vo(AF)(RMS)
RMS AF output voltage
54 % modulation
400
500
600
mV
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
59 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
54 % modulation; BP on;
see Figure 33
-
0.5
1.0
%
BAF(−3dB)
−3 dB AF bandwidth
12
18
-
kHz
(S/N)w(AF)
AF weighted
signal-to-noise ratio
“ITU-R BS.468-4”
BP on
38
44
-
42
50
40
-
-
-
dB
dB
dB
BP off
composite IF;
PC / SC = 10 dB; VIF
modulation = color bar;
“ITU-R BS.468-4”;
SAW filter application
see Figure 47; BP on
Reference frequency
General
[28]
fref
reference frequency
-
4
-
MHz
V
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
pin open-circuit
2.3
2.6
2.9
[3]
Ri
input resistance
-
-
2
-
-
kΩ
Rrsn(xtal)
crystal resonance
resistance
200
Ω
[29]
Cpull
pull capacitance
-
-
-
-
pF
Rswoff(OPTXTAL)
switch-off resistance on pin to switch off crystal input
0.22
4.7
kΩ
OPTXTAL
by external resistor wired
between pin OPTXTAL
and GND
Iswoff
switch-off current
Rswoff(OPTXTAL) = 0.22 kΩ
Rswoff(OPTXTAL) = 3.3 kΩ
-
-
-
5000
-
µA
µA
500
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin OPTXTAL
(DC)
pin open-circuit
2.3
2.6
2.9
V
[3]
Ri
input resistance
-
2
-
-
kΩ
mV
kΩ
Vref(RMS)
RO
RMS reference voltage
output resistance
80
-
400
4.7
[3]
[3]
of external reference
signal source
2
Cdec
decoupling capacitance
to external reference
signal source
22
100
-
pF
Reference frequency input from external source; pin FREF
VFREF
Ri
voltage on pin FREF (DC) pin open-circuit
input resistance
2.2
50
-
2.5
-
2.8
V
[3]
-
-
kΩ
MHz
[28]
fref
reference frequency
4
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
60 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Vref(RMS)
RO
Parameter
Conditions
Min
15
-
Typ
150
-
Max
500
4.7
Unit
mV
kΩ
RMS reference voltage
output resistance
see Figure 34
of external reference
signal source; AC-coupled
Cdec
decoupling capacitance
to external reference
signal source
22
100
-
-
pF
Rswoff(FREF)
switch-off resistance on
pin FREF
to switch off reference
signal input by external
resistor wired between
pin FREF and GND
3.9
27
kΩ
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
Rswoff(FREF) = 22 kΩ
-
-
-
100
-
µA
µA
25
Group delay select; pin GDS; see Figure 24 and Table 50
VGDS
Isink(I)
Isource(I)
VI
voltage on pin GDS
input sink current
input source current
input voltage
pin open-circuit
-
VP
-
V
pin connected to VP
pin connected to GND
-
-
-
-
1
µA
µA
V
-
72
GDEQ on; W11[2] = 0;
pin connected to GND
0
0.46VP
GDEQ on; W11[2] = 1;
pin open-circuit
0.58VP
0
-
-
-
VP
V
V
V
GDEQ off; W11[2] = 1;
pin connected to GND
0.46VP
VP
GDEQ off; W11[2] = 0;
pin open-circuit
0.58VP
I2C-bus transceiver[30]
Address select; pin ADRSEL
VADRSEL
voltage on pin ADRSEL
pin open-circuit
-
0.5VP
-
V
(DC)
for address select
MAD1; pin connected to
GND
0
-
-
-
-
0.04VP
0.34VP
0.80VP
VP
V
V
V
V
MAD3; pin connected to
GND via RADRSEL
0.20VP
0.66VP
0.96VP
MAD4; pin connected to
VP via RADRSEL
MAD2; pin connected to
VP
[3]
Ri
input resistance
-
31
47
-
kΩ
kΩ
RADRSEL
resistance on pin ADRSEL
42.3
51.7
I2C-bus voltage select; pin BVS
VBVS
voltage on pin BVS (DC)
pin open-circuit
-
-
-
0.52VP
-
V
Isink(I)
input sink current
pin connected to VP
pin connected to GND
-
-
10
60
µA
µA
Isource(I)
input source current
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
61 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 53. Characteristics …continued
VP = 5 V; Tamb = 25 °C; see Table 24 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz;
SC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level
f
for L); IF input from 50 Ω via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of Figure 51; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
VCC(I2C-bus) = 5.0 V;
pin connected to VP
0.88VP
-
VP
V
VCC(I2C-bus) = 3.3 V;
pin open-circuit
0.46VP
0
-
-
0.58VP
0.12VP
V
V
VCC(I2C-bus) = 2.5 V;
pin connected to GND
I2C-bus transceiver; pins SCL and SDA[31]
[32]
[33]
[33]
[32]
[33]
[33]
VIH
HIGH-level input voltage
VCC(I2C-bus) = 5.0 V
VCC(I2C-bus) = 3.3 V
VCC(I2C-bus) = 2.5 V
VCC(I2C-bus) = 5.0 V
VCC(I2C-bus) = 3.3 V
VCC(I2C-bus) = 2.5 V
0.6VP
2.3
-
-
-
-
-
-
-
-
-
VP
V
VP
V
1.75
−0.3
−0.3
−0.3
−10
−10
-
VP
V
VIL
LOW-level input voltage
+0.3VP
+1.0
+0.75
+10
+10
0.4
V
V
V
IIH
HIGH-level input current
LOW-level input current
LOW-level output voltage
µA
µA
V
IIL
VOL
IOL = 3 mA; for data
transmission (SDA)
fSCL
SCL clock frequency
0
-
-
-
400
0.4
kHz
V
Pins PORT1 or PORT2 or PORT3 operating as open-collector output port
VOL
LOW-level output voltage
output sink current
I = 2 mA (sink)
PORT1
Isink(o)
W7[3] = 0
-
-
-
-
3
mA
W7[3] = 1
10
µA
PORT2; W8[7] = 1
W8[1] = 0
-
-
-
-
3
mA
W8[1] = 1
10
µA
PORT3; W8[7] = 1
W8[2] = 0
-
-
-
-
-
-
3
mA
W8[2] = 1
10
µA
VOH
HIGH-level output voltage
VP + 0.5 V
[1] Values of video and sound parameters can be decreased at VP = 4.5 V.
[2] Condition for secure POR is a rise or fall time greater than 2 µs.
[3] This parameter is not tested during the production and is only given as application information for designing the receiver circuit.
[4] Level headroom for input level jumps during gain control setting.
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NXP Semiconductors
Multistandard hybrid IF processing
[5] BLF(−3dB) = 100 kHz (damping factor d = 1.7; calculated with sync level within gain control range). Calculation of the VIF PLL filter by
using the following formulae:
BLF(–3dB) = KOKDR , valid for d ≥ 1.2
1
2
d = R 2πK K C
--
O
D
with the following parameters:
KO = VCO steepness (Hz/V),
KD = phase detector steepness (A/rad),
R = loop filter serial resistor (Ω),
C = loop filter serial capacitor (F),
BLF(−3dB) = −3 dB LF bandwidth (Hz),
d = damping factor.
[6] The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation.
[7] AC load; CL < 20 pF and RL > 1 kΩ. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound
carrier traps.
[8] Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps.
[9] Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter (“ITU-T J.64”).
[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz.
[11] Sound carrier on; fvideo = 10 kHz to 10 MHz.
[12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 23. In this way the full composite video
spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p).
[13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz.
[14] The response time is valid for a VIF input level range from 200 µV to 70 mV.
[15] AGC response time increased if no AGC event occurs during two lines at minimum.
[16] AGC response time increased if video level falls below half of selected level.
RL
[17] Load applied to output pin causes signal loss. The resulting gain can be calculated by using Gv(load) = Gv + 20log
.
-------------------
RO + RL
[18] See Figure 19 to smooth current pulses.
[19] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The
AFC steepness can be changed by different applications of resistors R1 and R2.
[20] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided
with an uncertainty of ±1 bit corresponding to ±25 kHz. This uncertainty of ±25 kHz has to be added to the frequency accuracy
parameter.
[21] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage
provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from
0 dB to −18 dB in steps of −6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output
signal clipping.
[22] Amplitude response depends on dimensioning of FM PLL loop filter.
[23] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF. A value of CAF1 = 470 nF leads to f−3dB(AF)l ≈ 20 Hz
and CAF1 = 220 nF leads to f−3dB(AF)l ≈ 40 Hz.
[24] For all signal-to-noise measurements the used VIF modulator has to meet the following specifications:
a) Incidental phase modulation for black-to-white jump less than 0.5 degrees.
b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than
60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation.
c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter).
[25] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is
necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values.
[26] Measurement condition is SC1 / SC2 ≥ 7 dB.
[27] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of
this device is better than 60 dB. The measurement is related to an FM deviation of ±27 kHz and in accordance with “ITU-R BS.468-4”.
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Multistandard hybrid IF processing
[28] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
[29] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
[30] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz).
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011).
[31] The SDA and SCL lines will not be pulled down if VP is switched off.
[32] The threshold is dependent on VP.
[33] The threshold is independent of VP.
Table 54. Examples to the FM PLL filter
BLF(−3dB) (kHz)
Cs (nF)
2.2
Cpar (pF)
100
Rs (kΩ)
8.2
Comment
200
410
110
210
recommended for single-carrier-sound, FM narrow
recommended for single-carrier-sound, FM wide
recommended for two-carrier-sound, FM narrow
used for test circuit
2.2
47
5.6
2.2
470
5.6
2.2
47
8.2
Table 55. Input frequencies and carrier ratios (examples)
Symbol Parameter B/G standard M/N standard L standard L-accent standard Unit
fPC
picture carrier frequency
38.375
32.825
32.583
13
38.375
38.375
33.625
MHz
MHz
MHz
dB
fSC1
fSC2
sound carrier frequency 1
sound carrier frequency 2
33.825
31.825
40.125
-
-
-
PC / SC1 picture to first sound carrier ratio
7
-
10
-
10
-
PC / SC2 picture to second sound carrier ratio 20
dB
trap bypass mode
normal mode 1.7 V
normal mode 2.0 V
zero carrier level
2.72 V
2.6 V
3.08 V
2.9 V
3.41 V
3.20 V
white level
black level
sync level
1.83 V
1.5 V
1.71 V
1.2 V
1.80 V
1.20 V
001aaj651
Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)
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Multistandard hybrid IF processing
V = V + V
P
ripple
TDA9897
TDA9898
V
(V)
P
5.050
5.000
4.950
t (s)
001aae391
Fig 11. Ripple rejection condition
001aaj590
5
5
V
V
monitor(VIFAGC)
(V)
TAGC
(V)
4
3
2
1
4
3
2
1
0
(1)
(2)
(3)
(4)
0
30
50
70
90
110
V
130
(dBµV)
i(VIF)
(1) VIF AGC.
(2) TAGC; W10 = 00h.
(3) TAGC; W10 = 10h.
(4) TAGC; W10 = 1Fh.
Fig 12. Typical VIF monitor and TAGC characteristic
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj591
100
V
i(IF)
(dBµV)
90
80
70
60
50
bit pattern W9[4:0] or W10[4:0]
Integral TAGC (W9); step width: 1.255 dB typical.
IF based TAGC (W10).
Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10
001aaj592
100
V
i(IF)
(dBµV)
90
80
70
60
50
(1)
0
5
10
15
20
TOP2
25
(kΩ)
R
(1) IF based TAGC (TOP2).
Fig 14. Typical tuner takeover point as a function of resistor RTOP2
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Multistandard hybrid IF processing
001aaj593
001aaj594
5
5
V
V
AGC(FM)
(V)
AGC(SIF)
(V)
4
3
2
1
0
4
3
2
1
0
(1)
(2)
40
60
80
100
i(EXTFMI)
120
(dBµV)
20
40
60
80
100
i(SIF)
120
(dBµV)
V
V
(1) AM.
(2) FM.
Fig 15. Typical FM AGC characteristic measured at
pin MPP
Fig 16. Typical SIF AGC characteristic measured at
pin MPP
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Multistandard hybrid IF processing
008aaa035
250
250
(6)
(5)
I
∆f
AFC
AFC(VIF)
(kHz)
(1)
(µA)
150
150
50
0
50
(2)
bit AFCWIN (R1[7]) = 1
0
(3)
−50
−50
−150
−250
−150
(4)
−250
40.375
(MHz)
36.375
36.875
37.375
37.875
38.375
38.875
39.375
39.875
f
VIF
(1) VIF AFC via I2C-bus; accuracy is ±1 digit.
(2) Bit AFCWIN via I2C-bus (VCO is in ±1.6 MHz window) for all standards except M/N standard.
(3) Bit AFCWIN via I2C-bus (VCO is in ±0.8 MHz window) for M/N standard.
(4) VIF AFC average current.
(5) Reading via I2C-bus.
(6) Average; RC network at pin MPP.
Fig 17. Typical analog and digital AFC characteristic for VIF
001aad443
250
250
I
(µA)
(4)
(5)
∆f
AFC(RIF)
AFC
(1)
(kHz)
150
150
(2)
50
50
0
0
−50
−50
−150
−150
(3)
AFC undefined
5.2
bit CARRDET (R1[5]) = 1
5.4 5.6
AFC undefined
5.8
−250
5.0
−250
6.0
f
(MHz)
RIF
Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used
(W2[3] = 0).
(1) RIF AFC via I2C-bus.
(2) FM carrier detection via I2C-bus.
(3) RIF AFC average current.
(4) Reading via I2C-bus.
(5) Average; RC network at pin MPP.
Fig 18. Typical analog and digital AFC characteristic for RIF
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NXP Semiconductors
Multistandard hybrid IF processing
V
P
R1
22 kΩ
I
AFC
MPP
TDA9897
TDA9898
R2
100 nF
22 kΩ
008aaa152
Fig 19. RC network for measurement of analog AFC characteristic
001aaj595
60
S/N
(dB)
(1)
(2)
50
40
30
20
50
60
70
80
90
i(VIF)
100
(dBµV)
V
(1) B/G standard; weighted video S/N; using 50 % grey picture.
(2) M/N standard; unweighted video S/N; using 50 IRE grey picture.
Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj556
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including
Korea)
001aaj555
250
200
t
d(grp)
(ns)
150
100
50
(1)
(3)
(2)
0
−50
−100
−150
−200
−250
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 22. Typical group delay response for sound trap at M/N standard
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Multistandard hybrid IF processing
001aaj557
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 23. Typical amplitude frequency response for sound trap at B/G standard
001aaj554
250
200
150
100
50
t
d(grp)
(ns)
(1)
(2)
(3)
(4)
0
−50
(5)
−100
−150
−200
−250
0
1
2
3
4
5
6
f (MHz)
(1) Minimum requirements upper limit (valid for GDEQ off).
(2) Minimum requirements lower limit (valid for GDEQ off).
(3) Typical trap group delay response; GDEQ off.
(4) Typical trap group delay response; GDEQ on.
(5) Typical group delay response of additional group delay equalizer (difference of curves 3 and 4).
Fig 24. Typical group delay response for sound trap at B/G standard
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj553
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 25. Typical amplitude frequency response for sound trap at I standard
001aaj552
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 26. Typical group delay response for sound trap at I standard
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj551
5
0
(1)
(2)
α
resp(f)
(dB)
−5
−10
−15
−20
−25
−30
−35
−40
−45
(3)
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 27. Typical amplitude frequency response for sound trap at D/K standard
001aaj550
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 28. Typical group delay response for sound trap at D/K standard
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj549
5
0
(1)
(2)
α
resp(f)
(dB)
(3)
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap amplitude frequency response.
Fig 29. Typical amplitude frequency response for sound trap at L standard
001aaj548
250
200
150
100
50
t
d(grp)
(ns)
(1)
(3)
0
−50
(2)
−100
−150
−200
−250
0
1
2
3
4
5
6
7
8
f (MHz)
(1) Minimum requirements upper limit.
(2) Minimum requirements lower limit.
(3) Typical trap group delay response.
Fig 30. Typical group delay response for sound trap at L standard
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NXP Semiconductors
Multistandard hybrid IF processing
001aaf579
10
α
resp(f)
(dB)
(1)
0
−10
−20
−30
−40
−50
(5)
(4)
(3)
(2)
(7)
(6)
−3.0
−2.0
−1.0
0
1.0
2.0
3.0
f − f (MHz)
c
(1) Center frequency.
(2) Minimum upper cut-off frequency.
(3) Minimum lower cut-off frequency.
(4) Maximum upper cut-off frequency.
(5) Maximum lower cut-off frequency.
(6) Minimum upper stop-band attenuation.
(7) Minimum lower stop-band attenuation.
Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP
center frequency
001aaj633
10
V
o(AF)
(dB)
(1)
(2)
(1)
0
(2) (3)
−10
−20
−30
(3)
2
3
4
5
10
10
10
10
10
f
(kHz)
AF
(1) FM; transmitter pre-correction off and receiver de-emphasis off; FM PLL filter: Rs = 5.6 kΩ and
Cpar = 47 pF.
(2) AM and AGC normal.
(3) AM and AGC fast.
Fig 32. Typical AM and FM audio frequency response
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj596
2.0
THD
(%)
1.5
1.0
0.5
0
2
3
4
5
10
10
10
10
10
f
(kHz)
AF
Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard
001aaj597
60
(S/N)
unw
(dB)
50
40
30
0
50
100
150
i(FREF)(RMS)
200
(mV)
V
Reference frequency input signal taken from external quartz circuit.
Fig 34. Unweighted FM audio S/N versus reference frequency input level using radio
mode
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NXP Semiconductors
Multistandard hybrid IF processing
001aaf639
1
120
antenna
input
level
IF signal
RMS
values
(V)
(5)
(2)
(dBµV)
(4)
−1
100
80
60
40
20
0
10
(6)
(3)
RF
gain
control
range
−2
10
IF gain
control
range
IF gain
control
range limited
by TOP
−3
10
adjustment
−4
10
(1)
−5
10
(7)
−6
10
tuner
band-pass
X3450L
VIF
amplifier
demodulator
video
amplifier
TD1716
IF demodulator, TDA989x
Video signal related peak-to-peak levels are divided by factor 2√2 in order to conform with the RMS
value scale of the secondary y-axis, but disregarding the none sine wave signal content.
(1) Signal levels for −1 dB video output level using maximum RF gain and maximum IF gain.
(2) Signal levels for +1 dB video output level using minimum IF gain.
(3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and adjustment-related
minimum IF gain.
(4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and adjustment-related
minimum IF gain.
(5) TOP-adjusted tuner output level.
(6) TOP-adjusted VIF amplifier input level.
(7) Minimum antenna input level at −1 dB video level.
Fig 35. Front-end level diagram
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 — 25 May 2009
77 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
12.2 Digital TV signal processing
Table 56. Characteristics
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
i(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
V
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IF amplifier; IF1A and IF1B or IF2A and IF2B or pins IF3A and IF3B
VI
input voltage
1.8
-
1.93
2
2.2
-
V
[2]
[2]
[2]
Ri(dif)
differential input
resistance
kΩ
Ci(dif)
differential input
capacitance
-
3
-
-
pF
dB
GIF(cr)
control range IF gain
60
66
DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B
VO
output voltage
pin open-circuit
1.8
2.0
2.0
2.5
2.2
-
V
Ibias(int)
internal bias current
(DC)
for emitter-follower
mA
[3]
[3]
Isink(o)(max)
Isource(o)(max)
RO
maximum output sink DC and AC; see Figure 36
current
1.4
6.0
1.7
-
-
-
mA
mA
maximum output
source current
DC and AC; see Figure 36
[2]
[2]
output resistance
differential; output active
-
-
-
50
-
Ω
Ω
output inactive; internal
resistance to GND
800
Vi(IF)(RMS)
RMS IF input voltage minimum input sine wave
level for nominal output level
-
70
170
-
100
-
µV
maximum input sine wave
level for nominal output level
130
-
mV
mV
[2]
permissible overload
320
Direct IF; pins OUT2A and OUT2B
[2]
[4]
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
-
83
-
dB
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
between pin OUT2A and
pin OUT2B
W4[7] = 0
W4[7] = 1
-
-
1.0
1.1
V
V
0.50
0.55
[2][5][6]
C/N
carrier-to-noise ratio
at fo = 33.4 MHz;
see Figure 37
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
115
90
124
104
-
-
dBc/Hz
dBc/Hz
[2]
αIM
intermodulation
suppression
input signals: fi = 47.0 MHz
and 57.5 MHz; output
signals: fo = 36.5 MHz or
68.0 MHz; see Figure 38
W4[7] = 0
W4[7] = 1
40
40
-
-
-
-
dB
dB
TDA9897_TDA9898_4
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
fIF(−1dB)l
lower −1 dB IF cut-off
-
7
-
MHz
frequency
[4]
[7]
[2]
f−3dB(IF)u
PSRR
upper IF cut-off
frequency
W4[7] = 0
W4[7] = 1
60
60
-
-
-
-
MHz
MHz
power supply ripple
rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
-
-
60
60
-
-
dB
dB
Low IF output signal; pins OUT1A and OUT1B; differential
[2]
GIF(max)
maximum IF gain
output peak-to-peak level to
input RMS level ratio
-
89
-
dB
fsynth
synthesizer frequency see Table 34 and Table 35
-
-
-
-
-
-
-
MHz
V
[4]
[4]
Vo(dif)(p-p)
peak-to-peak
differential output
voltage
W4[7] = 0
W4[7] = 1
2
1
V
[2]
PSRR
power supply ripple
rejection
residual spurious at nominal
differential output voltage
dependent on power supply
ripple
fripple = 70 Hz
fripple = 20 kHz
6 MHz bandwidth
7 MHz bandwidth
8 MHz bandwidth
BP off
-
50
30
-
-
dB
-
-
dB
αripple(pb)LIF
low IF pass-band
ripple
-
2.7
dB
-
-
2.7
dB
-
-
2.7
dB
[4]
[4]
[4]
[4]
B−3dB
−3 dB bandwidth
11
-
15
7.8
8.8
9.8
40
35
40
35
40
35
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
dB
6 MHz bandwidth
7 MHz bandwidth
8 MHz bandwidth
-
-
αstpb
stop-band attenuation 6 MHz band; f = 11.75 MHz
6 MHz band; f = 20 MHz
30
28
30
28
30
28
dB
7 MHz band; f = 13.75 MHz
7 MHz band; f = 20 MHz
dB
dB
8 MHz band; f = 15.75 MHz
8 MHz band; f = 20 MHz
dB
dB
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
79 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
[2]
∆td(grp)
group delay time
variation
from 1 MHz to 2 MHz
-
90
200
ns
from 2 MHz to end of band
with a bandwidth of
6 MHz
7 MHz
-
-
-
90
90
90
160
160
160
ns
ns
ns
8 MHz
αimage
image rejection
−10 MHz to 0 MHz
BP on
30
24
34
28
-
-
dB
dB
BP off
[2][5][6]
C/N
carrier-to-noise ratio
at fo = 4.9 MHz;
see Figure 37
Vi(IF) = 10 mV (RMS)
Vi(IF) = 0.5 mV (RMS)
112
90
118
104
-
-
dBc/Hz
dBc/Hz
[2]
αH(ib)
in-band harmonics
suppression
low IF = multiple of
1.31 MHz;
fi = fsynth + 1.31 MHz;
see Figure 40
W4[7] = 0
W4[7] = 1
40
40
-
-
-
-
dB
dB
[2]
αIM
intermodulation
suppression
input signals:
fi = fsynth + 4.7 MHz and
fsynth + 5.3 MHz; output
signals: fo = 4.1 MHz or
5.9 MHz; see Figure 39
W4[7] = 0
W4[7] = 1
40
40
50
-
-
-
-
-
-
dB
dB
dB
[2]
[2]
αsp(ib)
in-band spurious
suppression
single-ended AC load;
RL = 1 kΩ; CL = 5 pF;
1 MHz to end of band;
BP on
αsp(ob)
out-band spurious
suppression
single-ended AC load;
50
-
-
dB
RL = 1 kΩ; CL = 5 pF; BP on
IF AGC control; pin AGCDIN
Isink(i)(max) maximum input sink
[2]
[2]
[2]
-
-
2
µA
V
current
Vi(max)
maximum input
voltage
-
-
VP
3
VAGCDIN
voltage on pin
AGCDIN
0
-
-
V
∆GIF/∆VAGCDIN change of IF gain with VAGCDIN = 0.8 V to 2.2 V
−45
-
dB/V
voltage on
pin AGCDIN
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
80 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Tuner AGC; pin TAGC
TAGC integral loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF; see Table 44 and Figure 13
Parameter
Conditions
Min
Typ
Max
Unit
Vi(IF)(RMS)
RMS IF input voltage at starting point of tuner
AGC takeover;
I
sink(TAGC) = 100 µA
W9[4:0] = 0 0000
W9[4:0] = 1 0000
W9[4:0] = 1 1111
-
59.6
78.3
98.5
-
-
dBµV
dBµV
dBµV
dB
-
-
-
-
αacc(set)TOP
TOP setting accuracy
source current
−2
+2
Isource
TAGC charge current
normal mode; W9[5] = 0
normal mode; W9[5] = 1
0.20
1.6
7
0.33
2.5
11
0.45
3.4
15
µA
µA
µA
fast mode activated by
internal level detector;
W9[5] = 0
fast mode activated by
internal level detector;
W9[5] = 1
60
90
120
µA
Isink
sink current
TAGC discharge current;
375
-
500
625
µA
VTAGC = 1 V
[2]
∆αacc(set)TOP/∆T TOP setting accuracy
variation with
Isink(TAGC) = 100 µA;
0.006
0.02
dB/K
W9[4:0] = 1 0000
temperature
[2]
[2]
RL
load resistance
50
-
-
-
-
MΩ
Vsat(u)
upper saturation
voltage
pin operating as current
output
VP − 0.3
V
[2]
[2]
Vsat(l)
lower saturation
voltage
pin operating as current
output
-
-
0.3
10
V
αth(fast)AGC
AGC fast mode
threshold
activated by internal fast
AGC detector; I2C-bus
setting corresponds to
W9[4:0] = 1 0000
6
8
dB
[2]
td
delay time
before activating; Vi(IF)
below αth(fast)AGC
40
60
-
80
ms
V
Filter synthesizer PLL; pin LFSYN1
VLFSYN1
voltage on pin
LFSYN1
1.0
3.5
KO
KD
VCO steepness
∆fVCO / ∆VLFSYN1
∆ILFSYN1 / ∆ϕVCO
-
-
3.75
9
-
-
MHz/V
phase detector
steepness
µA/rad
Isink(o)PD(max)
maximum phase
detector output sink
current
-
-
65
µA
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
81 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Isource(o)PD(max) maximum phase
detector output
-
-
65
µA
source current
Conversion synthesizer PLL; pin LFSYN2
VLFSYN2
voltage on pin
LFSYN2
1
-
-
3
-
V
KO
KD
VCO steepness
∆fVCO / ∆VLFSYN2
31
MHz/V
phase detector
steepness
∆ILFSYN2 / ∆ϕVCO;
see Table 57;
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
32
38
47
61
61
-
-
-
-
-
µA/rad
µA/rad
µA/rad
µA/rad
µA/rad
Io(PD)
phase detector output sink or source;
current
fVCO selection:
22 MHz to 29.5 MHz
30 MHz to 37.5 MHz
38 MHz to 45.5 MHz
46 MHz to 53.5 MHz
57 MHz
-
-
-
-
-
200
238
294
384
384
-
-
-
-
-
µA
µA
µA
µA
µA
ϕn(synth)
synthesizer phase
noise
fsynth = 31 MHz;
fIF = 36 MHz
[2]
[2]
[2]
[2]
at 1 kHz
89
99
-
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 10 kHz
at 100 kHz
at 1.4 MHz
89
99
98
102
119
115
fsynth = 40 MHz;
IF = 44 MHz; external
f
4 MHz reference signal of
265 mV (RMS) and phase
noise better than
120 dBc/Hz; see Figure 46
[2]
[2]
[2]
[2]
[2]
[2]
at 1 kHz
89
89
96
115
50
-
96
100
100
118
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
at 10 kHz
at 100 kHz
at 1.4 MHz
-
-
-
αsp
spurious suppression multiple of ∆f = 500 kHz
-
IL
leakage current
synthesizer spurious
performance > 50 dBc
-
10
nA
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
82 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reference frequency
General
[8]
fref
reference frequency
-
4
-
MHz
V
Reference frequency generation with crystal; pin OPTXTAL
VOPTXTAL
voltage on pin
pin open-circuit
2.3
2.6
2.9
OPTXTAL (DC)
[2]
[9]
Ri
input resistance
-
-
2
-
-
kΩ
Rrsn(xtal)
crystal resonance
resistance
200
Ω
Cpull
pull capacitance
-
-
-
-
pF
Rswoff(OPTXTAL) switch-off resistance
on pin OPTXTAL
to switch off crystal input by
external resistor wired
between pin OPTXTAL and
GND
0.22
4.7
kΩ
Iswoff
switch-off current
Rswoff(OPTXTAL) = 0.22 kΩ
Rswoff(OPTXTAL) = 3.3 kΩ
-
-
-
5000
-
µA
µA
500
Reference frequency input from external source; pin OPTXTAL
VOPTXTAL
voltage on pin
pin open-circuit
2.3
2.6
2.9
V
OPTXTAL (DC)
[2]
Ri
input resistance
-
2
-
-
kΩ
Vref(RMS)
RMS reference
voltage
80
400
mV
[2]
[2]
RO
output resistance
of external reference signal
source
-
2
4.7
-
kΩ
Cdec
decoupling
capacitance
to external reference signal
source
22
100
pF
Reference frequency input from external source; pin FREF
VFREF
voltage on pin FREF pin open-circuit
(DC)
2.2
2.5
2.8
V
[2]
[8]
Ri
input resistance
50
-
-
-
kΩ
fref
reference frequency
4
-
MHz
mV
Vref(RMS)
RMS reference
voltage
see Figure 46
15
150
500
RO
output resistance
of external reference signal
source; AC-coupled
-
-
4.7
-
kΩ
Cdec
decoupling
capacitance
to external reference signal
source
22
100
pF
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
83 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 56. Characteristics …continued
VP = 5 V[1]; Tamb = 25 °C; 8 MHz system; see Table 33 and Table 34; CW test input signal is used for specification;
Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 Ω via broadband transformer 1 : 1;
gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 51 with 4 MHz
crystal oscillator reference; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rswoff(FREF)
switch-off resistance
on pin FREF
to switch off reference signal
input by external resistor
wired between pin FREF
and GND
3.9
-
27
kΩ
Iswoff
switch-off current
Rswoff(FREF) = 3.9 kΩ
Rswoff(FREF) = 22 kΩ
-
-
-
100
-
µA
µA
25
[1] Some parameters can be decreased at VP = 4.5 V.
[2] This parameter is not tested during production and is only given as application information.
[3] Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is
minimum 1 kΩ.
[4] With single-ended load for fIF < 45 MHz RL ≥ 1 kΩ and CL ≤ 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 kΩ and CL ≤ 3 pF to
ground.
[5] Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[6] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off.
[7] With single-ended load RL ≥ 1 kΩ and CL ≤ 5 pF to ground.
[8] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum
FM deviation, sound trap frequency, LIF band-pass cut-off frequency, as well as the accuracy of the synthesizer.
[9] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
Table 57. Conversion synthesizer PLL; loop filter dimensions[1]
fVCO (MHz)
22 to 29.5
30 to 37.5
38 to 45.5
46 to 53.5
57
RLFSYN2 (kΩ)[2]
CLFSYN2 (nF)
1.5
1.8
2.2
2.7
3.3
4.7
4.7
4.7
4.7
4.7
[1] Calculation of the PLL loop filter by using the following formulae:
K
BLF(–3dB)
=
OK R
, valid for d ≥ 1.2
LFSYN2
-------
D
N
K
1
2
d =
R
2π OK C
--
-------
LFSYN2
D
LFSYN2
N
with the following parameters:
KO = VCO steepness (Hz/V),
fVCO
N = divider ratio: N =
,
--------------------
0.5 MHz
KD = phase detector steepness (A/rad),
RLFSYN2 = synthesizer loop filter serial resistor (Ω),
CLFSYN2 = synthesizer loop filter serial capacitor (F),
BLF(−3dB) = −3 dB LF bandwidth (Hz),
d = damping factor.
[2] If more than one frequency range is used in the application, then the smallest resistor value should be applied.
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
84 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
008aaa153
30
C
L(dif)
(pF)
20
(2)
(1)
10
0
0
1
2
3
R
L(dif)
(kΩ)
W4[7] = 0; nominal output level
(1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 kΩ to GND.
(2) Low IF, fmax = 9 MHz.
Fig 36. Maximum differential load figures at OUT1/OUT2
001aaj598
130
(3)
C/N
(dBc/Hz)
(1)
(2)
120
110
100
90
80
30
50
70
90
i(IF)(RMS)
110
(dBµV)
V
(1) Direct IF.
(2) Low IF.
(3) Noise level of measurement setup.
Fig 37. Typical C/N ratio as a function of IF input voltage
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
85 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
74
0.5
(1)
α
IM
0
0
0
47
57.5
0
36.5
47
57.5
68
f
f
o
i
(MHz)
(MHz)
input signal
output signal
008aaa051
(1) 0.25 V for W4[7] = 1.
Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
74
0.5
(1)
α
IM
0
0
36
40.7 41.3
input signal
0
4.1
4.7
5.3
5.9
f
f
o
(MHz)
i
f
synth
(MHz)
output signal
008aaa053
(1) 0.25 V for W4[7] = 1.
Fig 39. Low IF signal conditions for measurement of intermodulation at OUT1
V
V
i(IF)(RMS)
(dBµV)
o(dif)(p-p)
(V)
80
2.0
(1)
α
H(ib)
0
0
36
37.31
0
1.31 2.62 3.93 5.24 6.55 7.86
output signal
f
f
o
(MHz)
i
f
synth
(MHz)
input signal
008aaa054
(1) 1.0 V for W4[7] = 1.
Fig 40. Low IF signal conditions for measurement of harmonics at OUT1
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
86 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj605
2
1
0
t
d(grp)LIF
(ns)
α
resp(f)
(dB)
−1
−2
(1) (2) (3)
−3
−4
−5
−6
100
0
(1)
(2)
(3)
−100
−200
−7
−8
−9
−10
0
2
4
6
8
10
12
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 41. Detailed low IF amplitude and group delay pass-band tolerance scheme
001aaj607
10
α
resp(f)
(dB)
0
−10
−20
−30
−40
−50
−60
−70
(1)
(2)
(3)
−30
−25
−20
−15
−10
−5
0
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 42. Low IF amplitude stop-band tolerance scheme
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 — 25 May 2009
87 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
001aaj606
10
α
resp(f)
(dB)
0
−10
−20
−30
(1)
(2)
(3)
−40
−50
−60
−70
0
5
10
15
20
25
30
f (MHz)
tolerance scheme:
(1)
(2)
(3)
(1) Channel bandwidth = 6 MHz.
(2) Channel bandwidth = 7 MHz.
(3) Channel bandwidth = 8 MHz.
Fig 43. Low IF amplitude pass-band tolerance scheme
001aaj599
100
(7)
G
(dB)
80
(1)
(2)
(3)
(4)
(5)
(6)
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
AGCDIN
3.5
(V)
V
(1) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 0).
(2) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0, W4[7] = 0).
(3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1).
(4) 2.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 0).
(5) 1.0 V (p-p) differential output voltage (LIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1, W4[7] = 0).
(6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1).
(7) Ratio of output peak-to-peak level to input RMS level.
Fig 44. Typical gain characteristic for AGCDIN control voltage
TDA9897_TDA9898_4
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Product data sheet
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NXP Semiconductors
Multistandard hybrid IF processing
001aaj601
2.5
V
LFSYN2
(V)
2.0
1.5
1.0
20
30
40
50
synth
60
(MHz)
f
Fig 45. Typical synthesizer loop filter voltage as function of synthesizer frequency
001aaj600
105
(1)
ϕ
n(synth)
(2)
(dBc/Hz)
95
(3)
85
75
0
100
200
300
400
i(FREF)(RMS)
500
(mV)
V
fsynth = 40 MHz; fIF = 44 MHz; sound BP off
(1) ∆f = 100 kHz.
(2) ∆f = 10 kHz.
(3) ∆f = 1 kHz.
Fig 46. Typical synthesizer phase noise at carrier frequency plus ∆f on LIF output versus
input voltage on pin FREF
TDA9897_TDA9898_4
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
13. Application information
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
V
P
= 5 V
100 nF
C
C
TAGC
220 nF
FREF
100 pF
(4)
470 Ω
L
analog
ground
470 nF
3.3 kΩ
100 nF
n.c.
37
synthesizer
downconverter
(2)
loop filter
22 pF
n.c.
48
47
46
45
44
43 42 41
40
39
38
AGC input for DIF
(from channel decoder)
1
2
3
4
5
6
7
8
9
36
R
LFSYN2
C
LFSYN2
35
34
33
32
31
30
29
28
27
26
25
1.5 nF
2 V CVBS
output
(5)
IFAGC
C
BVS
AUD
470 nF
(1)
TDA9897
TDA9898
IF
7 MHz WINDOW
1st DIF
C
CTAGC
SAW
X3450L
100 nF
C
AF
470 nF
6 MHz WINDOW
10
11
12
digital LIF or
analog 2nd
sound IF
13
14
15
16
17
18
19
20
21 22 23
24
digital
ground
C
4.7 nF
de-em
C
s
220 nF
ADRSEL
C
par
R
s
100 Ω
100 Ω
100 Ω
(3)
FM PLL loop filter
VIF PLL
loop filter
external
FM input
SDA
SCL
001aai815
(1) Optional single-ended IF input possible.
(2) Application depends on synthesizer frequency; see Table 57.
(3) Application of FM PLL loop filter; see Table 54.
(4) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(5) Capacitor connected only for TDA9898.
Fig 47. Application diagram of TDA9897 and TDA9898; ATV/DVB-T
TDA9897_TDA9898_4
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Product data sheet
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90 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
V
= 5 V
P
100 nF
C
C
TAGC
220 nF
FREF
100 pF
(3)
470 Ω
L
analog
ground
470 nF
3.3 kΩ
100 nF
n.c.
37
synthesizer
downconverter
(1)
loop filter
22 pF
n.c.
48
47
46
45
44
43 42 41
40
39
38
AGC input for DIF
(from channel decoder)
1
2
3
4
5
6
7
8
9
36
R
LFSYN2
C
LFSYN2
35
34
33
32
31
30
29
28
27
26
25
PORT2
12
SOUND
11
1.5 nF
2 V CVBS
output
(4)
IFAGC
C
SAW
X3751L
BVS
470 nF
8
AUD
6 MHz or 8 MHz
WINDOW
TDA9897
TDA9898
7
2
3
17
1st DIF
C
CTAGC
100 nF
C
AF
470 nF
10
11
12
digital LIF or
analog 2nd
sound IF
PORT2
4.7 kΩ
IF
4.7 kΩ
PORT1
13
14
15
16
17
18
19
20
21 22 23
24
BA277
BA277
4.7 kΩ
4.7 kΩ
4.7 kΩ
digital
ground
C
4.7 nF
de-em
C
s
220 nF
ADRSEL
C
par
V
P
R
s
100 Ω
100 Ω
100 Ω
(2)
FM PLL loop filter
VIF PLL
loop filter
external
FM input
SDA
SCL
001aai816
(1) Application depends on synthesizer frequency; see Table 57.
(2) Application of FM PLL loop filter; see Table 54.
(3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(4) Capacitor connected only for TDA9898.
Fig 48. Application diagram of TDA9897 and TDA9898; ATV/DVB-T/DVB-C
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
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91 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
V
P
= 5 V
100 nF
C
C
TAGC
220 nF
FREF
100 pF
(3)
470 Ω
L
analog
ground
470 nF
3.3 kΩ
100 nF
n.c.
37
synthesizer
downconverter
(1)
loop filter
22 pF
n.c.
48
47
46
45
44
43 42 41
40
39
38
AGC input for DIF
(from channel decoder)
1
2
3
4
5
6
7
8
9
36
R
LFSYN2
C
LFSYN2
PORT2
35
34
33
32
31
30
29
28
27
26
25
IF
SAW
SIF
X7550
1.5 nF
2 V CVBS
output
n.c.
BVS
SAW
VIF
M1980
AUD
TDA9897
NYQUIST SLOPE
1st DIF
C
CTAGC
100 nF
(5)
C
AF
470 nF
(5)
(4)
10
11
12
digital LIF or
analog 2nd
sound IF
PORT1
13
14
15
16
17
18
19
20
21 22 23
24
digital
ground
C
4.7 nF
de-em
C
s
220 nF
ADRSEL
C
par
R
s
100 Ω
100 Ω
100 Ω
(2)
FM PLL loop filter
VIF PLL
loop filter
external
FM input
SDA
SCL
001aai817
(1) Application depends on synthesizer frequency; see Table 57.
(2) Application of FM PLL loop filter; see Table 54.
(3) EMI suppression filter for DC, e.g. BLM21RK121SN1 (Murata).
(4) Optional.
(5) Value depends on application.
Fig 49. Application diagram of TDA9897 using SAW filter with Nyquist slope
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 — 25 May 2009
92 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
buffered TAGC
control voltage
output
4 MHz
22 pF
C
TAGC
220 nF
22 kΩ
46
39
47
42
TDA9897
TDA9898
TDA9897
TDA9898
VAGC voltage
monitor output
TDA9897
TDA9898
12
(1)
(2)
(3)
V
V
V
P
P
P
4.7 kΩ
4.7 kΩ
4.7 kΩ
PORT3
42
TDA9897
TDA9898
TDA9897
TDA9898
TDA9897
TDA9898
PORT1
12
35
PORT2
(4a)
(4b)
(4c)
V
V
V
P
P
P
47 µF
47 µF
22 kΩ
TDA9897
TDA9898
TDA9897
TDA9898
TDA9897
TDA9898
33
33
AFC
voltage
output
68 Ω
43 Ω
1 V CVBS
into 75 Ω
1 V CVBS
into 75 Ω
16
(5a)
(5b)
(6)
220 Ω
220 Ω
100 nF
22 kΩ
R ≥ 1 kΩ
R ≥ 1 kΩ
R ≥ 1 kΩ
R ≥ 1 kΩ
30
29
27
26
digital LIF or
analog 2nd
sound IF
TDA9897
TDA9898
TDA9897
TDA9898
TDA9897
TDA9898
1st DIF
15
17
(7a)
(7b)
(8)
560 Ω
BP
560 Ω
001aai818
(1) Optional 4 MHz quartz crystal oscillator.
(2) Alternative buffered TAGC voltage output.
(3) Alternative VIF AGC voltage monitor output.
(4) Optional use of (a) PORT1, (b) PORT2 or (c) PORT3.
(5) Optional CVBS buffer at setting (a) W6[1] = 0, 2 V CVBS or (b) W6[1] = 1, 1.7 V CVBS.
(6) Optional analog AFC voltage output.
(7) Optional output current increase at output (a) 1st DIF respectively (b) digital LIF.
(8) Optional radio application with external BP.
Fig 50. Optional applications
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
93 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
14. Test information
tuner
AGC
output
4 MHz
reference
input
synthesizer
trap control
loop filter
+5 V
PORT3
(2)
3.3 kΩ
(7)
2.7 kΩ
C
C
TAGC
100 nF
FREF
100 pF
(1)
(3)
22 kΩ
470 Ω
4 MHz
analog
ground
V
P
= 5 V
22 pF
100 nF
i.c.
45
n.c.
37
synthesizer
downconverter
AGC input for DIF
(from channel decoder)
(4)
loop filter
22 pF
48
47
46
44
43 42 41
40
39
38
1
2
3
4
5
6
7
8
9
36
(7)
2.7 kΩ
R
LFSYN2
C
LFSYN2
+5 V
n.c.
35
34
33
32
31
30
29
28
27
26
25
PORT2
1 : 1
SIF/DIF
1
2
5
4
1.5 nF
51 Ω
2 V CVBS
output
3
(6)
C
IFAGC
BVS
AUD
(b)
470 nF
1 : 1
VIF/SIF/DIF
1
2
5
4
TDA9897
TDA9898
51 Ω
3
1st DIF
C
CTAGC
(a)
C
100 nF
1 : 1
VIF/SIF/DIF
AF
1
2
5
4
470 nF
(b)
51 Ω
10
11
12
3
digital LIF or
analog 2nd
sound IF
22 kΩ
TOP potentiometer for
RSSI and positive modulation
(a)
PORT1
+5 V
ADRSEL
(7)
2.7 kΩ
13
14
15
16
MPP
17
18
19
20
21 22 23
24
digital
ground
C
4.7 nF
de-em
C
par
C
s
220 nF
FM PLL
(5)
R
s
100 Ω
100 Ω
100 Ω
loop filter
output to
sound BPF
FM input
from sound BPF
VIF
loop filter
external
FM input
SDA
SCL
001aai819
(1) Switch-off resistor connected if external reference signal is not used.
(2) Switch-off resistor connected if crystal is not used.
(3) Use of crystal is optional.
(4) Application depends on synthesizer frequency; see Table 57.
(5) Application of FM PLL loop filter; see Table 54.
(6) Capacitor connected only for TDA9898.
(7) Pull-up resistor connected only for port function.
Fig 51. Test circuit of TDA9897 and TDA9898
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
94 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
15. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 52. Package outline SOT313-2 (LQFP48)
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
95 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
1/2 e
e
v
M
M
b
C
C
A
B
C
1
w
13
24
L
25
12
e
e
E
2
h
1/2 e
1
36
terminal 1
index area
48
37
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
7.1
6.9
5.25
4.95
7.1
6.9
5.25
4.95
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
5.5
5.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-18
SOT619-1
- - -
MO-220
- - -
Fig 53. Package outline SOT619-1 (HVQFN48)
TDA9897_TDA9898_4
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Product data sheet
Rev. 04 — 25 May 2009
96 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA9897_TDA9898_4
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Product data sheet
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97 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 54) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 58 and 59
Table 58. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 59. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 54.
TDA9897_TDA9898_4
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Product data sheet
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TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 54. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of through-hole mount packages
17.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
17.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
17.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
99 of 103
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NXP Semiconductors
Multistandard hybrid IF processing
17.4 Package related soldering information
Table 60. Suitability of through-hole mount IC packages for dipping and wave soldering
Package
Soldering method
Dipping
Wave
CPGA, HCPGA
-
suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL
PMFP[2]
suitable
-
suitable[1]
not suitable
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.
18. Abbreviations
Table 61. Abbreviations
Acronym
ADC
AFC
AGC
ATV
Description
Analog-to-Digital Converter
Automatic Frequency Control
Automatic Gain Control
Analog TV
BP
Band-Pass
CW
Continuous Wave
DAC
DC
Digital-to-Analog Converter
Direct Current
DIF
Digital Intermediate Frequency
Digital Signal Processor
Digital TV
DSP
DTV
DVB
DVB-C
DVB-T
EMI
Digital Video Broadcasting
Digital Video Broadcasting-Cable
Digital Video Broadcasting-Terrestrial
Electro-Magnetic Interference
ElectroStatic Discharge
Frequency Phase-Locked Loop
Input/Output
ESD
FPLL
I/O
IC
Integrated Circuit
IF
Intermediate Frequency
Liquid Crystal Display
Low Intermediate Frequency
Module Address
LCD
LIF
MAD
NB
NarrowBand
NICAM
PLL
Near Instantaneous Companded Audio Multiplex
Phase-Locked Loop
POR
QSS
Power-On Reset
Quasi Split Sound
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
100 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
Table 61. Abbreviations …continued
Acronym
Description
RIF
Radio Intermediate Frequency
RSSI
SAW
SC
Received Signal Strength Indication
Surface Acoustic Wave
Sound Carrier
SIF
Sound Intermediate Frequency
Tuner Automatic Gain Control
TakeOver Point
TAGC
TOP
VCO
VIF
Voltage-Controlled Oscillator
Vision Intermediate Frequency
Vertical Interval Test Signal
VITS
19. Revision history
Table 62. Revision history
Document ID
Release date
20090525
Data sheet status
Change notice
Supersedes
TDA9897_TDA9898_4
Modifications:
Product data sheet
-
TDA9897_TDA9898_3
• Specification of features for V3 version
TDA9897_TDA9898_3
TDA9897_TDA9898_2
TDA9897_TDA9898_1
20080111
20070411
20060922
Product data sheet
Product data sheet
Product data sheet
-
-
-
TDA9897_TDA9898_2
TDA9897_TDA9898_1
-
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
101 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
20.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
20.3 Disclaimers
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9897_TDA9898_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 25 May 2009
102 of 103
TDA9897; TDA9898
NXP Semiconductors
Multistandard hybrid IF processing
22. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
16.3
16.4
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 97
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 98
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Analog TV processing. . . . . . . . . . . . . . . . . . . . 1
Digital TV processing . . . . . . . . . . . . . . . . . . . . 2
FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3
17
17.1
Soldering of through-hole mount packages. 99
Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Soldering by dipping or by solder wave . . . . . 99
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99
Package related soldering information. . . . . 100
2.1
2.2
2.3
2.4
17.2
17.3
17.4
3
4
5
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8
18
19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100
Revision history . . . . . . . . . . . . . . . . . . . . . . 101
20
Legal information . . . . . . . . . . . . . . . . . . . . . 102
Data sheet status . . . . . . . . . . . . . . . . . . . . . 102
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . 12
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13
20.1
20.2
20.3
20.4
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
Functional description . . . . . . . . . . . . . . . . . . 15
IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 15
VIF demodulator . . . . . . . . . . . . . . . . . . . . . . . 15
VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15
Mode selection of VIF AGC . . . . . . . . . . . . . . 15
VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15
Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DIF/SIF FM and AM sound AGC . . . . . . . . . . 16
Frequency phase-locked loop for VIF . . . . . . . 16
DIF/SIF converter stage . . . . . . . . . . . . . . . . . 17
Mono sound demodulator. . . . . . . . . . . . . . . . 17
FM PLL narrowband demodulation. . . . . . . . . 17
AM sound demodulation. . . . . . . . . . . . . . . . . 17
Audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . 17
Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2C-bus transceiver and slave address . . . . . . 18
21
22
Contact information . . . . . . . . . . . . . . . . . . . 102
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.7
8.7.1
8.7.2
8.8
8.9
8.10
9
9.1
9.2
9.2.1
9.2.2
I2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Description of data bytes . . . . . . . . . . . . . . . . 24
10
11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal characteristics. . . . . . . . . . . . . . . . . . 39
12
12.1
12.2
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 40
Analog TV signal processing . . . . . . . . . . . . . 40
Digital TV signal processing . . . . . . . . . . . . . . 78
13
14
15
Application information. . . . . . . . . . . . . . . . . . 90
Test information. . . . . . . . . . . . . . . . . . . . . . . . 94
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95
16
16.1
16.2
Soldering of SMD packages . . . . . . . . . . . . . . 97
Introduction to soldering . . . . . . . . . . . . . . . . . 97
Wave and reflow soldering . . . . . . . . . . . . . . . 97
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 May 2009
Document identifier: TDA9897_TDA9898_4
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