TDA9955HL/17/C1:55 [NXP]
SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100;
| 型号： | TDA9955HL/17/C1:55 |
| 厂家： | 
NXP |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100 商用集成电路 |
| 文件： | 总52页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA9955HL
Triple 8-bit analog-to-digital video converter for HDTV
Rev. 01 — 17 March 2008
Product data sheet
1. General description
The TDA9955HL is a triple 8-bit video converter interface.
The TDA9955HL converts an RGB analog signal into a RGB or YUV (YCBCR) digital
signal or converts a YUV (YPBPR) analog signal into a YUV (YCBCR) or RGB digital signal
with a sampling rate up to 170 MHz.
The TDA9955HL supports analog TV resolutions from 480i (720 × 480i at 60 Hz) to
High-Definition TV (HDTV) (up to 1920 × 1080p at 60 Hz) and analog PC resolutions from
VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz).
The YUV digital output signal can be 4 : 4 : 4 or 4 : 2 : 2 ITU-R BT.656 standard or
semi-planar format following the ITU-R BT.601 standard.
All settings are controlled via the I2C-bus.
2. Features
I Triple 8-bit Analog-to-Digital Converter (ADC)
I Three independent analog video sources, up to 170 MHz selectable via the I2C-bus
I Analog composite sync slicer and recognition integrated
I Frame and field detection for interlaced video signal
I Video analog voltage input from 0.45 V to 0.9 V (p-p) to produce a full-scale ADC input
of 1.0 V (p-p)
I Three clamps for programming a 8-bit clamping code from 0 to +191 in steps of 1 LSB
for RGB and YUV signals
I Three video amplifiers controlled via I2C-bus to reach the full-scale resolution
I Amplifier bandwidth of 100 MHz
I Low gain variation with temperature
I I2C-bus controlled Phase-Locked Loop (PLL) to generate the ADCs, formatter and
output clocks which can be locked into a line frequency from 15 kHz to 95 kHz
I Integrated PLL divider
I Programmable clock phase adjustment cells
I Matrix and offsets available for conversion of RGB or YUV signal coming from analog
video sources into YUV or RGB
I Output format RGB 4 : 4 : 4, YUV 4 : 4 : 4, YUV 4 : 2 : 2 ITU-R BT.656 or YUV 4 : 2 : 2
semi-planar standard on output bus
I Integrated downsampling-by-two with selectable filters on CB and CR channels in the
4 : 2 : 2 mode
I IC controlled via the I2C-bus, 5 V tolerant and bit rate up to 400 kbit/s
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
I TTL inputs 5 V tolerant
I LV-TTL outputs
I Power-down mode
I 1.8 V and 3.3 V power supplies
3. Applications
I Set Top Box (STB)
I YUV or RGB high-speed video digitizer
I Projector, plasma and LCD TV
I Rear projection TV
I High-end TV
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
TDA9955HL
LQFP100
plastic low profile quad flat package; 100 leads;
SOT407-1
body 14 × 14 × 1.4 mm
5. Block diagram
REF
VPA[7:0]
VPB[7:0]
RGB (or YP P ) 1
ADC
8 bits
VIDEO OUTPUT
FORMATTER
B
R
VPC[7:0]
VCLK
RGB (or YP P ) 2
B
R
CLAMP GAIN
(×3)
VREF, HREF,
FREF
VHREF TIMING
GENERATOR
SOG/Y 1
SOG/Y 2
CLOCKS
GENERATOR
SLICERS
VS, HS, CS
VSYNC1/HCSYNC1
VSYNC2/HCSYNC2
ACTIVITY DETECTION
AND
SYNC SELECTION
TDA9955HL
SYNC
SEPARATOR
2
POWER
MANAGEMENT
SYNC TIMING
MEASUREMENT
I C SLAVE
INTERFACE
SDA/SCL
001aag612
Fig 1. Block diagram
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
2 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
6. Functional diagram
2
2
2
2
I C
I C
I C
I C
B1 (or P )
B
B/U CHANNEL
G/Y CHANNEL
VPA[7:0]
VPB[7:0]
VPC[7:0]
B2 (or P )
B
G1 (or Y)
G2 (or Y)
R1 (or P )
R
R/P CHANNEL
R
R2 (or P )
R
(GAIN)
2
I C
+
+
+
FREF
VREF
HREF
−
−
−
(CLAMP)
VHREF
TIMING
GENERATOR
2
I C
CLAMP
(CLK PIX)
(CLK FOR)
VCLK
AVI CLOCK
GENERATOR
+
+
+
+
HS
VS
CS
DE
−
−
−
−
SOG/Y 1
SOG/Y 2
SYNC
SLICERS
TDA9955HL
HCSYNC1
HCSYNC2
VSYNC1
VSYNC2
ACTIVITY
DETECTION SELECTION
SYNC
SDRS
&
2
2
2
I C
I C
I C
SYNC TIME
MEASUREMENT
POWER
MANAGEMENT
MCLK
2
2
I C
I C
001aah352
Fig 2. Functional diagram
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
3 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
7. Pinning information
7.1 Pinning
1
75
TDA9955HL
25
51
001aag613
Fig 3. Pin configuration
7.2 Pin description
Table 2.
Symbol
VPC1
Pin description
Pin Type[1] Description
1
O
O
O
P
video port C output bit 1
VPC2
2
video port C output bit 2
VPC3
3
video port C output bit 3
VDDC(1V8)
VSSC
VDDO(3V3)
VSSO
4
supply voltage for the digital core (1.8 V)
ground for the digital core
5
G
P
6
supply voltage for the video port output (3.3 V)
ground for the video port output
video port C output bit 4
7
G
O
O
O
O
P
VPC4
8
VPC5
9
video port C output bit 5
VPC6
10
11
12
13
14
15
16
17
18
19
video port C output bit 6
VPC7
video port C output bit 7
VDDO(3V3)
VSSO
supply voltage for the video port output (3.3 V)
ground for the video port output
pixel clock output
G
O
O
O
O
O
O
P
VCLK
FREF/CS
VREF/VS
HREF/HS
DE
filed reference output or composite synchronization
vertical reference output or vertical synchronization
horizontal reference output or horizontal synchronization
data enable signal output
VAI_N
video activity indication output (active LOW)
analog supply for the free running oscillator (3.3 V)
analog ground for the free running oscillator
bias analog supply voltage (3.3 V)
bias analog ground
VDDA(OSC)(3V3) 20
VSSA(OSC) 21
VDDA(BIAS)(3V3) 22
VSSA(BIAS) 23
G
P
G
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
4 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 2.
Pin description …continued
Pin Type[1] Description
Symbol
BIAS
24
25
26
27
I
bias input
VSSA
G
G
P
PCB ground
VSSA(B)
VDDA(B)(3V3)
analog ground for the blue (or blue chrominance) channel
analog supply voltage for blue (or blue chrominance) channel
(3.3 V)
B2
28
29
30
31
I
blue channel input 2
REF_B
B1
I
blue channel reference input
blue channel input 1
I
VDDA(B)(1V8)
P
analog supply voltage for blue (or blue chrominance) channel ADC
(1.8 V)
VSSA(B)
32
33
34
G
G
P
analog ground for blue (or blue chrominance) channel ADC
analog ground for green (or green luminance) channel
VSSA(G)
VDDA(G)(3V3)
analog supply voltage for green (or green luminance) channel
(3.3 V)
G2
35
36
37
38
I
green channel input 2
REF_G
G1
I
green channel reference input
green channel input 1
I
VDDA(G)(1V8)
P
analog supply voltage for green (or green luminance) channel ADC
(1.8 V)
VSSA(G)
VSSA(R)
VDDA(R)(3V3)
R2
39
40
41
42
43
44
45
G
G
P
I
analog ground for green (or green luminance) channel ADC
analog ground for red (or red chrominance) channel
analog supply voltage for red (or red chrominance) channel (3.3 V)
red channel input 2
REF_R
R1
I
red channel reference input
I
red channel input 1
VDDA(R)(1V8)
P
analog supply voltage for red (or red chrominance) channel ADC
(1.8 V)
VSSA(R)
SOG2
SOG1
46
47
48
G
I
analog ground for red (or red chrominance) channel ADC
Sync-On-Green (SOG) input 2
I
sync-on-green input 1
VDDA(SOG)(3V3) 49
VSSA(SOG) 50
VDDA(SOG)(3V3) 51
P
G
P
G
G
G
P
P
I
analog supply voltage for SOG (3.3 V)
analog ground for SOG
analog supply voltage for SOG (3.3 V)
analog ground for SOG
VSSA(SOG)
VSSA(PLL)
VSSA(PLL)
52
53
54
analog ground for PLL
analog ground for PLL
VDDA(PLL)(3V3) 55
VDDA(PLL)(1V8) 56
analog supply voltage for PLL (3.3 V)
analog supply voltage for PLL (1.8 V)
reserved for test (connected to the digital ground of the core)
reserved for test (connected to the digital ground of the core)
horizontal (composite) SYNC input 1
horizontal (composite) SYNC input 2
TEST0
57
58
59
60
TEST1
I
HCSYNC1
HCSYNC2
I
I
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
5 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 2.
Pin description …continued
Pin Type[1] Description
Symbol
VSYNC1
VSYNC2
MCLK
CLAMP
COAST
CKEXT
A0
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I
vertical SYNC input 1
I
vertical SYNC input 2
I
synchronization timing measurement clock
clamp input (external mode)
coast (PLL) input (external mode)
external clock input (external mode)
I2C-bus address select bit 0
digital supply for the input (3.3 V)
I2C-bus clock
I
I
I
I
VDDI(3V3)
SCL
P
I
SDA
I
I2C-bus data
VSSA
G
P
G
P
G
O
O
O
O
P
G
O
O
O
O
P
G
O
O
O
O
P
G
O
O
O
O
P
G
O
analog ground
VDDC(1V8)
VSSC
VDDO(3V3)
VSSO
digital supply for core (1.8 V)
digital ground of the core (1.8 V)
supply voltage for the video port output (3.3 V)
ground for video port output
video port A output bit 0
VPA0
VPA1
video port A output bit 1
VPA2
video port A output bit 2
VPA3
video port A output bit 3
VDDO(3V3)
VSSO
supply voltage for the video port output (3.3 V)
ground for video port output
video port A output bit 4
VPA4
VPA5
video port A output bit 5
VPA6
video port A output bit 6
VPA7
video port A output bit 7
VDDO(3V3)
VSSO
supply voltage for the video port output (3.3 V)
ground for video port output
video port output bit 0
VPB0
VPB1
video port output bit 1
VPB2
video port output bit 2
VPB3
video port output bit 3
VDDO(3V3)
VSSO
supply voltage for the video port output (3.3 V)
ground for video port output
video port output bit 4
VPB4
VPB5
video port output bit 5
VPB6
video port output bit 6
VPB7
video port output bit 7
VDDO(3V3)
VSSO
supply voltage for the video port output (3.3 V)
ground for video port output
video port C output bit 0
VPC0
[1] P = power supply; G = ground; I = input and O = output.
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
6 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
8. Functional description
This high-rate front end is designed to convert analog signals coming from an analog
source (RGB or YUV) into parallel digital data used by media processor ICs such as the
NXP Semiconductors Nexperia devices for HDTV or by other video signal ICs. The
high-rate front end is able to output RGB 4 : 4 : 4, YUV 4 : 4 : 4, YUV 4 : 2 : 2 semi-planar
and YUV 4 : 2 : 2 ITU-R BT.656 formats and accepts progressive and interlaced input
formats. The high-rate front end also contains a RGB-to-YUV and YUV-to-RGB
conversion matrix, downsampling filters and range control function.
8.1 Analog multiplexers
The choice between the two analog video inputs is either automatic (activity detection) or
controlled by the I2C-bus. An analog video input is defined by pins SOGx, Rx, Bx, Gx,
HCSYNCx and VSYNCx (where x equals 1 or 2).
8.2 R/PR, B/PB and G/Y channels
8.2.1 Clamps
Three independent parallel clamping circuits are used to clamp the video input signals on
programmable black/blanking levels. The clamp level of each channel can be changed
from 0 to 191 in steps of 1 LSB. The clamp signal comes from the VHREF timing
generator or from the CLAMP pin.
The clamping circuits can be inhibited during the vertical sync pulse and also during false
black/blanking level in the end of active video signal in a frame/field.
8.2.2 ADCs
Three ADCs convert analog signals into three series of 8-bit codes, with a maximum
sampling frequency of 170 MHz. The ADCs input range is 1 V (p-p).
During the gain calibration pulse period, the ADCs are used to calibrate the video
amplifiers and during the clamp active period the ADCs are used to set the clamp level to
the desired values.
8.2.3 Automatic Gain Control (AGC)
Gain registers, one per channel, control directly the gain of each video amplifier. The
programming of these registers is done by I2C-bus and their content is validated only on
the next horizontal synchronization pulse. These contrast registers are programmable
from 0 dB to 5 dB (gain registers on 11 bits).
The gain calibration control signal comes from the VHREF timing generator.
8.3 Sync slicing
Two sync slicers extract the composite sync from the green, luminance or CVBS signal
through SOGx pins. This synchronization signal can be bi-level or tri-level.
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
7 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
8.4 Activity detection
The device detects the presence of signals on each sync input VSYNCx, HCSYNCx and
SOGx after slicing to indicate which kind of synchronization is present (where x equals 1
or 2):
• Digital separated syncs on VSYNCx and HCSYNCx
• Analog composite sync on SOGx
A change of activity is notified by a HIGH-to-LOW transition on the VAI_N output pin.
8.5 Sync detection and selection
The management of the synchronization is done by using vertical sync, horizontal sync
and analog composite sync on the green/luminance signal.
The device scans if a signal is present on the VSYNCx pin. If a signal is detected on this
pin, it means that there is a digital separated sync signal.
If no signal is detected on the HCSYNCx pin, the device scans if a signal is present on the
SOGx pin. If a signal is detected on this pin (and not on the HCSYNCx pin), it means that
there is an analog composite sync signal and the signal is sent into the sync recognition
function after slicing.
If the analog composite sync signal is on the green or on the luminance of the video
signal, the SOGx pin must be connected to this signal.
8.6 Sync Detection Recognition and Separation
The Sync Detection Recognition and Separation (SDRS) allows to retrieve the horizontal
and the vertical synchronizations from composite sync. This composite sync comes from
the sync slicing function when the sync is on the green, luminance or CVBS signal or from
the digital composite sync on the HCSYNCx pin.
This function is able to eliminate any additional synchronization pulses which may be
added in the vertical blanking.
8.7 Clock generator
An internal PLL locked to the reference HSYNC signal from sync recognition provides
three different clocks, one pixel-clock for R/PR, B/PB and G/Y channels sampling and for
the VHREF timing generator, one formatter-clock at double frequency for the 4 : 2 : 2
formatter and one output-clock for the VCLK output pin.
The COAST signal, coming from SDRS and/or VHREF timing generator or coming from
the COAST input pin, allows to freeze the PLL phase frequency detector during the
vertical blanking.
A phase-locked flag indicates if the PLL is locked.
8.8 Sync multiplexers
The sync multiplexer allow to select via the I2C-bus the origin of the synchronization
pulses signals HS, VS, CS and DE.
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
8 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
The origin of those pulses can be the VHREF timing generator or the SDRS block.
8.9 Color conversion
The color conversion allows an RGB signal coming from the analog video interface to
convert into YUV format or to convert a YUV signal coming from the analog video
interface into an RGB format. The color matrix formula is:
C
C
C
C
C
Oin
Oin
Oin
Oout
Oout
Oout
11 12 13
1
2
3
1
2
3
YG
VR
UB
GY
RV
BU
C
C
=
×
–
+
21 22 23
C
C
31 32 33
Activation of the matrix function and programming of all coefficients is made by I2C-bus.
8.10 4 : 2 : 2 downsample filters
These filters downsample the U and V signals with a factor 2.
A delay is added on the G/Y channel corresponding to the pipeline delay of the filters to
put the Y channel in phase with the UV channel.
Four filters are selectable by I2C-bus, from the simple cut to the ITU-R BT.656 compliant
digital filter.
8.11 Range control
The range control function truncates the range of data at specified ceiling and floor values
to remove super-white and super-black pixels.
8.12 4 : 2 : 2 formatter
The 4 : 2 : 2 formatter contains the YUV 4 : 2 : 2 semi-planar and the YUV 4 : 2 : 2
ITU-R BT.656 formatting functions. The choice between these functions is done using the
I2C-bus. A delay is added on the G/Y channel corresponding to the pipeline delay of the
YUV 4 : 2 : 2 semi-planar formatting function to put the Y channel in phase with the
UV channel.
In the case of the YUV 4 : 2 : 2, the data frequency corresponding to the Y signal is at
pixel clock frequency and the data frequency corresponding to the U and V signals is at
half the pixel clock frequency. For semi-planar, the output clock should be at the same
frequency as the pixel clock and for ITU-R BT.656 at the same frequency as the formatter
clock (double of the pixel-clock).
The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be
included in the data stream according the HREF, VREF and FREF signal positions from
the VHREF timing generator.
Specific codes programmed via the I2C-bus can replace the data stream during the
blanking period to mask gain and clamp calibration.
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
9 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
8.13 Video port selection
Each channel (R or G or B in RGB 4 : 4 : 4 mode, Y or CB or CR in YUV 4 : 4 : 4 mode,
Yor CBCR in 4 : 2 : 2 semi-planar mode, CBYCRY in 4 : 2 : 2 ITU-R BT.656 mode) can be
affected to a specified video port VPA, VPB or VPC via the I2C-bus.
8.14 Output buffers
The levels of the output buffers are LV-TTL compatible. The switch of the outputs between
active and high-impedance is set by the I2C-bus.
8.15 VHREF timing generator
The VHREF timing generator outputs all the timing signals used by the device: gain and
clamp pulses for calibration, coast signal to manage the PLL, VREF, HREF and FREF
signals for SAV/EAV and other, VS and HS signals to change width and position
compared with the synchronization inputs.
8.16 I2C-bus serial interface
The I2C-bus serial interface allows to program the internal registers of the device. The
slave address of the device is selected by pin A0. The programmed values in the registers
remain valid.
8.17 Power management
Only the serial interface (and the I2C-bus registers) and the activity detection are powered
up in all cases even in the case when the device is set to power-down with the
PD-registers.
8.18 Sync timing measurement
To assist the recognition of the input format, the vertical and horizontal periods are
measured based on the externally provided MCLK frequency (13.5 MHz). The width of the
horizontal pulse is also measured.
9. I2C-bus interface
9.1 I2C-bus protocol
The TDA9955HL is a slave I2C-bus device and the SCL pin is only an input pin. The timing
and protocol for I2C-bus are standard.
Bit A0 of the I2C-bus device address is externally selected by the A0 pin. The main device
I2C-bus address is given in Table 3.
Table 3.
Device address
I2C-bus slave address
R/W
-
A6
A5
A4
A3
A2
A1
A0
1
0
0
1
1
1
A0
0/1
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
10 of 52
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9.2 Registers definitions
The configuration of the registers is given in Table 4.
Table 4.
I2C-bus registers; (R): reading register[1]
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
5
4
3
2
1
0 (LSB)
VERSION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
10h
11h
12h
13h
14h
15h
R
0
0
0
1
0
1
0
0
0001 0100
0000 0100
0000 0000
0110 0000
0000 0000
0000 0010
0001 0100
0001 0000
0000 0000
0111 1111
0010 0101
0000 0000
0000 0000
0000 0000
0000 0000
1100 0011
0110 0000
INPUT_SEL
W
W
W
W
W
W
W
W
W
W
R
x
x
x
x
x
x
VINS[1:0]
Reserved for test
Reserved for test
SDRS_CTRL1
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
Reserved for test
SDRS_FLAGS
PLL_CTRL
-
-
x
x
x
-
x
x
x
x
x
x
x
x
x
x
x
-
x
x
x
x
x
x
x
x
x
ASD_DIS
SOGF
DCSF
x
x
x
x
x
x
x
x
x
x
x
-
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
-
x
-
x
x
x
x
R
x
x
-
x
x
-
x
SOGD1
x
x
DSSD1
x
R
ASD
x
SOGD2
-
DSSD2
W
W
W
R
-
-
-
EDG
x
PLL_MNDIV_MSB
PLL_NDIV_LSB
LOCK_FLAG
MDIV[1:0]
-
NDIV[11:8]
NDIV[7:0]
-
-
-
-
-
-
-
-
x
PLL_LOCK 0000 0000
0001 0000
DLL_PHASE
W
W
W
W
W
W
W
W
W
-
PHASE[4:0]
PIXCLKGEN_PRST
CLKOUT_PRST[2:0]
CLKFOR_PRST[1:0]
CLKPIX_PRST[2:0]
1101 0111
PIXCLKGEN_CTRL0 16h
PIXCLKGEN_CTRL1 17h
CLKOUT_DIV[1:0]
CLKOUT_TOG
CLKFOR_DIV[1:0]
CLKPIX_DIV[1:0]
CLKFOR_SEL[1:0]
PR_DEL
x
PH_CORR 0011 1011
CLKOUT_SEL[2:0]
x
0100 0110
0001 0000
1000 0000
1000 0000
0000 0000
0000 0000
BRIGHT_GY
1Ah
1Bh
1Ch
1Dh
1Eh
BRIGHT_GY[7:0]
BRIGHT_BU
BRIGHT_BU[7:0]
BRIGHT_RV[7:0]
BRIGHT_RV
Reserved for test
Reserved for test
x
x
-
x
-
x
-
x
-
x
x
x
x
x
x
-
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4.
I2C-bus registers; (R): reading register[1] …continued
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
5
4
3
2
1
0 (LSB)
COARSE_GAINRV
FINE_GAINRV
AGC_HIGHRV
AGC_LOWRV
COARSE_GAINBU
FINE_GAINBU
AGC_HIGHBU
AGC_LOWBU
AGC_CONTGY
AGC_OFFSETGY
AGC_HIGHGY
AGC_LOWGY
V_PER_MSB
20h
21h
22h
23h
2Ah
2Bh
2Ch
2Dh
34h
35h
36h
37h
40h
41h
42h
43h
44h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
W
W
W
W
W
W
W
W
W
W
W
W
R
-
-
-
-
-
COARSE_RV[3:0]
COARSE_BU[3:0]
COARSE_GY[3:0]
0000 0100
0101 1100
1111 0000
1001 0000
0000 0100
0101 1100
1111 0000
1001 0000
0000 0100
0101 1100
1110 1011
1001 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 0001
0000 0110
0000 0000
0110 0100
FINE_RV[6:0]
HIGH_RV[7:0]
LOW_RV[6:0]
x
-
-
-
-
-
-
-
FINE_BU[6:0]
HIGH_BU[7:0]
LOW_BU[6:0]
x
-
-
-
FINE_GY[6:0]
HIGH_GY[7:0]
LOW_GY[6:0]
x
V_PER[19:12]
V_PER[11:4]
H_PER[9:2]
V_PER_ISB
R
H_PER_MSB
R
HS_WIDTH_MSB
STM_LSB
R
HS_WIDTH[9:2]
R
V_PER[3:0]
H_PER[1:0]
HS_WIDTH[1:0]
MAT_SC[1:0]
MAT_CTRL
W
W
W
W
W
W
W
W
W
W
W
W
W
-
-
-
-
-
-
-
-
-
-
MAT_OI1_MSB
MAT_OI1_LSB
MAT_OI2_MSB
MAT_OI2_LSB
MAT_OI3_MSB
MAT_OI3_LSB
MAT_P11_MSB
MAT_P11_LSB
MAT_P12_MSB
MAT_P12_LSB
MAT_P13_MSB
MAT_P13_LSB
-
-
-
-
-
-
MAT_OI1[8:6]
OFFSET_IN1[5:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAT_OI2[8:6]
OFFSET_IN2[5:0]
-
MAT_OI3[8:6]
-
-
-
OFFSET_IN3[5:0]
-
-
-
-
-
-
P11[10:8]
P11[7:0]
P12[7:0]
P13[7:0]
P12[10:8]
P13[10:8]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4.
I2C-bus registers; (R): reading register[1] …continued
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
5
4
3
2
1
0 (LSB)
MAT_P21_MSB
MAT_P21_LSB
MAT_P22_MSB
MAT_P22_LSB
MAT_P23_MSB
MAT_P23_LSB
MAT_P31_MSB
MAT_P31_LSB
MAT_P32_MSB
MAT_P32_LSB
MAT_P33_MSB
MAT_P33_LSB
MAT_OO1_MSB
MAT_OO1_LSB
MAT_OO2_MSB
MAT_OO2_LSB
MAT_OO3_MSB
MAT_OO3_LSB
MAT_BYPASS
Reserved for test
PXCNT_PR_LSB
PXCNT_MSB
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-
-
-
-
-
-
-
-
-
-
-
-
-
P21[10:8]
0000 0110
1000 1001
0000 0001
1100 0000
0000 0111
1011 0111
0000 0110
1101 0111
0000 0111
0110 1001
0000 0001
1100 0000
0000 0000
0100 0000
0000 0010
0000 0000
0000 0010
0000 0000
P21[7:0]
P22[7:0]
P23[7:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P22[10:8]
P23[10:8]
P31[10:8]
P31[7:0]
P32[7:0]
P33[7:0]
-
-
-
-
P32[10:8]
-
P33[10:8]
-
OFFSET_OUT1[8:6]
OFFSET_OUT1[5:0]
-
-
-
-
-
-
OFFSET_OUT2[8:6]
OFFSET_OUT2[5:0]
-
-
-
OFFSET_OUT3[8:6]
OFFSET_OUT3[5:0]
-
-
-
-
-
-
-
-
MAT_BP 0000 0001
x
x
x
x
x
x
x
x
0001 0000
0000 0011
0000 0011
0110 0000
0000 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PXCNT_PR[7:0]
PXCNT_PR[11:8]
LCNT_PR[11:8]
PXCNT_NPIX[11:8]
LCNT_NLIN[11:8]
HREF_END[11:8]
PXCNT_NPIX_LSB
LCNT_PR_LSB
LCNT_MSB
PXCNT_NPIX[7:0]
LCNT_PR[7:0]
LCNT_NLIN_LSB
HREF_S_LSB
HREF_MSB
PXCNT_NLIN[7:0]
HREF_START[7:0]
HREF_START[11:8]
HREF_E_LSB
HS_S_LSB
HREF_END[7:0]
HS_START[7:0]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4.
I2C-bus registers; (R): reading register[1] …continued
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
5
4
3
2
1
0 (LSB)
HS_MSB
ABh
W
HS_START[11:8]
HS_END[11:8]
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0001
0000 0000
0000 0001
0000 0001
0000 0000
0000 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
HS_E_LSB
ACh W
ADh W
HS_END[7:0]
-
VREF_F1_S_MSB
VREF_F1_S_LSB
VREF_F1_WIDTH
VREF_F2_S_MSB
VREF_F2_S_LSB
VREF_F2_WIDTH
-
-
-
-
-
-
-
-
-
-
-
-
-
VREF_F1_START[10:8]
VREF_F2_START[10:8]
VS_F1_LINE_START[10:8]
VS_F2_LINE_START[10:8]
AEh
AFh
B0h
B1h
B2h
W
W
W
W
W
W
W
W
W
W
W
W
W
W
VREF_F1_START[7:0]
VREF_F1_WIDTH[7:0]
-
-
VREF_F2_START[7:0]
VREF_F2_WIDTH[7:0]
VS_F1_LINE_S_MSB B3h
VS_F1_LINE_S_LSB B4h
VS_F1_LINE_WIDTH B5h
VS_F2_LINE_S_MSB B6h
VS_F2_LINE_S_LSB B7h
VS_F2_LINE_WIDTH B8h
-
-
VS_F1_LINE_START[7:0]
VS_F1_LINE_WIDTH[7:0]
-
-
VS_F2_LINE_START[7:0]
VS_F2_LINE_WIDTH[7:0]
VS_F1_PIX_START[7:0]
VS_F1_PIX_S_LSB
VS_F1_PIX_MSB
VS_F1_PIX_E_LSB
VS_F2_PIX_S_LSB
VS_F2_PIX_MSB
VS_F2_PIX_E_LSB
FREF_F1_S_LSB
FREF_POL_MSB
FREF_F2_S_LSB
B9h
BAh
BBh
VS_F1_PIX_START[11:8]
VS_F2_PIX_START[11:8]
VS_F1_PIX_END[11:8]
VS_F2_PIX_END[11:8]
FREF_F2_START[10:8]
VS_F1_PIX_END[7:0]
BCh W
BDh W
VS_F2_PIX_START[7:0]
BEh
BFh
C0h
C1h
W
W
W
W
W
W
VS_F2_PIX_END[7:0]
FREF_F1_START[7:0]
FPOL
FREF_F1_START[10:8]
-
FREF_F2_START[7:0]
CLAMP_PIX_START[7:0]
CLAMP_PIX_S_LSB C8h
CLAMP_PIX_MSB C9h
CLAMP_PIX_START[11:8]
CLAMP_PIX_END[11:8]
CLAMP_PIX_E_LSB CAh W
CLP_F1_LINE_S_MSB CBh W
CLP_F1_LINE_S_LSB CCh W
CLP_F1_LINE_WIDTH CDh W
CLP_F2_LINE_S_MSB CEh W
CLAMP_PIX_END[7:0]
-
-
-
-
-
-
-
-
CLAMP_F1_LINE_START[10:8]
CLAMP_F1_LINE_START[7:0]
CLAMP_F1_LINE_WIDTH[7:0]
-
-
CLAMP_F2_LINE_START[10:8]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4.
I2C-bus registers; (R): reading register[1] …continued
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
5
4
3
2
1
0 (LSB)
CLP_F2_LINE_S_LSB CFh
CLP_F2_LINE_WIDTH D0h
W
W
W
W
W
W
W
W
R
CLAMP_F2_LINE_START[7:0]
CLAMP_F2_LINE_WIDTH[7:0]
GAIN_START[7:0]
0000 0000
0000 0000
0000 0001
0000 0000
0101 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0100 0000
0000 0000
0000 0000
0001 0010
0010 0010
1100 0000
0100 0000
1010 1100
0100 0000
0100 0010
0000 0001
0000 0000
0000 0000
GAIN_S_LSB
GAIN_MSB
D1h
D2h
D3h
D4h
D5h
D6h
GAIN_START[11:8]
FDW_START[11:8]
GAIN_END[11:8]
FDW_END[11:8]
GAIN_E_LSB
FDW_S_LSB
FDW_MSB
GAIN_END[7:0]
FDW_START[7:0]
FDW_E_LSB
FDW_END[7:0]
ASD_MEASLIN_MSB D7h
x
-
x
-
x
-
x
x
MEAS_LINES[10:8]
MEASLIN_LSB
MEASPIX_MSB
MEASPIX_LSB
Reserved for test
BLK_GY_LSB
BLK_BU_LSB
BLK_RV_LSB
BLK_MSB
D8h
D9h
R
MEAS_LINES[7:0]
R
-
MEAS_PIX[11:8]
DAh R
DBh W
DCh W
DDh W
DEh W
MEAS_PIX[7:0]
x
x
x
x
x
x
x
-
x
-
BLK_GY[5:0]
BLK_BU[5:0]
BLK_RV[5:0]
-
-
-
-
-
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
F1h
W
W
W
W
W
W
W
W
W
W
W
W
W
W
BLK_GY[7:6]
BLK_BU[7:6]
-
-
BLK_RV[7:6]
PRE_FILTERS
OF_CCEIL
-
-
FILTERBU[1:0]
-
FILTERRV[1:0]
-
-
C_CEIL[5:0]
OF_CFLOOR
OF_YCEIL
-
-
C_FLOOR[5:0]
Y_CEIL[5:0]
-
-
OF_YFLOOR
OF_CTRL
-
-
Y_FLOOR[5:0]
OUT
VPL
-
x
-
BLC
TRC
-
FOR_SEL[1:0]
Reserved for test
Reserved for test
CSVSHS_SEL
POL_CTRL
x
-
x
x
-
x
x
x
x
x
x
x
-
x
CS_SEL[2:0]
VS_SEL[1:0]
HS_SEL[2:0]
-
-
CS_POL
HS_POL
VS_POL
FREF_POL HREF_POL VREF_POL 0000 0000
OUTPUT_CTRL
DE_CNTRL
-
-
VPC_SEL[1:0]
VPB_SEL[1:0]
VPA_SEL[1:0]
1010 0100
0000 1000
0000 0101
HR_PXQ
-
HR_SEL
-
DE_PXQ
-
DE_POL
-
-
-
-
-
-
RESET_CNTRL
RST_MAN
RST_AVI
-
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4.
I2C-bus registers; (R): reading register[1] …continued
Register
Sub R/W Bit definition
Default
value
addr
7 (MSB)
6
-
5
-
4
3
2
1
0 (LSB)
PD_AVI_CNTRL0
PD_AVI_CNTRL1
FVH_SEL
F4h
F5h
F6h
F7h
F9h
W
W
W
W
W
-
-
-
PD_SOG2 PD_SOG1
PD_DLL
PD_PLL
PD_AVI 0000 0000
-
-
-
-
-
PD_ADC_B PD_ADC_G PD_ADC_R 0010 0000
-
-
-
-
-
FVH_SEL 0000 0001
0000 0000
LSB_OUT_SEL
OR_SEL
LSB_SEL[7:0]
x
x
x
x
x
x
x
x
0000 0000
[1] The symbol ‘x’ indicates a bit reserved for test and the symbol ‘-’ indicates that the bit is not used.
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
9.2.1 Version register
Table 5.
VERSION register (address 00h) bit description
Legend: * = default value
Bit Symbol Access Value Description
7 to 0 -
R
14h* the version register gives the version of the device, version is
0001 0100
9.2.2 Input selection register
Table 6.
INPUT_SEL register (address 01h) bit description
Legend: * = default value
Bit
Symbol
Access Value
Description
7 to 2 x
W
W
00 0001* for test: must be set to default value for proper operation
1 to 0 VINS[1:0]
video input selection: enables analog video input 1,
analog video input 2
00*
01
video input 1
video input 2
9.2.3 Sync detection recognition and separation registers
Table 7.
SDRS_CTRL1 register (address 04h) bit description
Legend: * = default value
Bit
7
Symbol
x
Access Value Description
R/W
W
0*
for test: must be set to default value for proper operation
6
ASD_DIS
automatic sync detection disable: Digital Separated
Syncs > Digital Composite Sync > Sync On Green
0*
1
enable
disable
5
4
SOGF
DCSF
W
W
sync on green forced: when set, forces the use of SOGx
(where x corresponds to the selected analog video input)
input when the automatic sync detection is disabled
0*
1
enable
disable
digital composite sync forced: when set, forces the use
of HCSYNCx (where x corresponds to the selected analog
video input) input when the automatic sync detection is
disabled
0*
1
enable
disable
3 to 0 x
W
0000* for test: must be set to default value for proper operation
Table 8.
SDRS_FLAGS register (address 0Dh) bit description[1]
Legend: * = default value
Bit Symbol Access Value Description
7
ASD
R
additional sync pulses detected: additional sync pulses on the
selected analog input
0*
1
are not detected
are detected
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
17 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 8.
Legend: * = default value
SDRS_FLAGS register (address 0Dh) bit description[1] …continued
Bit Symbol Access Value Description
6
SOGD2 R
sync on green detected: on pin SOG2
pulses are not detected
pulses are detected
0*
1
5
4
-
DSSD2
not used
R
digital separated syncs detected: on pins VSYNC2 and
HCSYNC2
0*
1
pulses are not detected
pulses are detected
not used
3
2
-
SOGD1 R
sync on green detected: on pin SOG1
pulses are not detected
pulses are detected
not used
0*
1
1
0
-
DSSD1
R
digital separated syncs detected: on pins VSYNC1 and
HCSYNC1
0*
1
pulses are not detected
pulses are detected
[1] When one of these bits changes, the VAI_N pin is pulled down until SDRS_FLAGS0 is read.
9.2.4 PLL registers
Table 9.
PLL_CTRL register (address 10h) bit description
Legend: * = default value
Bit
Symbol Access Value Description
7
R
R
R
reserved for test
6 to 4 -
-
not used
3
EDG
edge: synchronizes the PLL on the internal HSYNC pulses
on the rising edge
0*
1
on the falling edge
2 to 0
R
reserved for test
[1] By default, the SDRS toggles automatically the HSYNC to have an internal positive HSYNC signal
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
18 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 10. PLL_MNDIV registers (address 11h and 12h) bit description
Legend: * = default value
Address Register
11h PLL_MNDIV_MSB
Bit
Symbol
Access Value Description
7 to 6 MDIV[1:0]
W
master divider: selects the master divider to
adjust the sampling frequency range with the PLL
frequency range from 110 MHz to 200 MHz
00
divided by 1; > 110 Msample/s
divided by 2; 50 Msample/s to 110 Msample/s
divided by 4; 25 Msample/s to < 50 Msample/s
divided by 8; 12.5 Msample/s to < 25 Msample/s
not used
01
10
11*
00*
3h*
60h*
5 to 4 -
W
W
W
3 to 0 NDIV[11:8]
7 to 0 NDIV[7:0]
pixel divider: pixel division value
12h
PLL_NDIV_LSB
Table 11. LOCKFLAG register (address 13h) bit description
Legend: * = default value
Bit
7 to 2
1
Symbol
Access Value
Description
-
W
W
00 0000* not used
x
0*
for test; must be set to default value for proper
operation
0
PLL_LOCK
R
PLL_lock: indicates when the PLL is locked
0*
1
not locked
locked
9.2.5 Pixel clocks generation registers
Table 12. DLL_PHASE register (address 14h) bit description
Legend: * = default value
Bit
Symbol
Access Value
Description
7 to 5 -
W
W
000*
not used
4 to 0 PHASE[4:0]
1 0000* phase: these bits set the phase shift for the three clock
signals CLKPIX, CLKFOR and CLKOUT; it is the fine
adjustment of the phase, see Table 15
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
19 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 13. PIXCLKGEN_PRST register (address 15h) bit description
Legend: * = default value
Bit Symbol
Access Value Description
7 to 5 CLKOUT_PRST[2:0]
4 to 3 CLKFOR_PRST[1:0]
2 to 0 CLKPIX_PRST[2:0]
W
W
W
110* output clock preset: these bits set the phase
shift for the output clock CLKOUT; it is the rough
adjustment of the phase and there is the same
number of steps as the division factor selected for
CLKOUT
10*
formatter clock preset used to program the
phase shift for the 4 : 2 : 2 formatter clock
CLKFOR It Is the rough adjustment of the phase
and there is the same number of steps than the
division factor selected for CLKFOR
111* pixel clock preset: these bits set the phase shift
for the ADC and VHREF pixel clock CLKPIX; it is
the rough adjustment of the phase and there is the
same number of steps as the division factor
selected for CLKPIX
Table 14. PIXCLKGEN_CTRL0 register (address 16h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7 to 6 CLKOUT_DIV[1:0]
W
output clock division factor: selects the PLL
frequency division factor for the output clock
CLKOUT. For 4 : 2 : 2 semi-planar or 4 : 4 : 4
output formats, the division factor must be the
same as the master division factor. In case of the
4 : 2 : 2 ITU-R BT.656 formats, it must be half of the
master division factor
00*
01
10
11
divide by 2
divide by 4
divide by 8
not defined
5 to 4 CLKFOR_DIV[1:0]
W
formatter clock division factor: selects the PLL
frequency division factor for the ITU-R BT.656
formatter clock CLKFOR The division factor must
be the half of the master division factor
00
01
10
11*
divide by 2
divide by 4
not defined
not defined
3 to 2 CLKPIX_DIV[1:0]
W
pixel clock division factor: selects the PLL
frequency division factor for the pixel clock CLKPIX.
The division factor must be the same as the master
division factor
00
01
10*
11
divide by 2
divide by 4
divide by 8
not defined
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Product data sheet
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TDA9955HL
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Triple 8-bit analog-to-digital video converter for HDTV
Table 14. PIXCLKGEN_CTRL0 register (address 16h) bit description …continued
Legend: * = default value
Bit
Symbol
Access Value Description
1
PR_DEL
W
phase delay: delays the rough adjustment of the
three clock signals, see Table 15
0
no delay
1*
delay of one PLL period
0
PH_CORR
W
phase correction: selects the falling or rising edge
of the horizontal reference signal from the PLL to
synchronize the three clock divisions, see Table 15
0
falling edge selected
rising edge selected
1*
Table 15. Relationship between bits PR_DEL, PH_CORR and phase value
PHASE[4:0]
0 to 7
PR_DEL
PH_CORR
0
1
1
0
1
0
8 to 15
16 to 31
Table 16. Relation between master division and clock division
MDIV[1:0] Master
division
4 : 4 : 4 or semi-planar 4 : 2 : 2 ITU-R BT.656 formatter clock
pixel clock
CLKOUT
_DIV
CLKOUT
_PRST
CLKOUT CLKOUT CLKFOR CLKFOR CLKPIX
CLKPIX
_PRST
_DIV
_PRST
0, 1, 2, 3
0 or 1
0
_DIV
_PRST
0, 1, 2, 3
0 or 1
0
_DIV
10
11
10
01
00
8
4
2
1
10
01
00
11
0 to 7
0 to 3
0 or 1
0
01
01
0 to 7
0 to 3
0 or 1
0
00
00
01
11
11
00
not available
not available
00
9.2.6 Pixel clocks generation registers
Table 17. PIXCLKGEN_CTRL1 register (address 17h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
W output clock toggle
7
CLKOUT_TOG
0*
1
does not toggle the signal CLKOUT
toggles the signal CLKOUT
6 to 4 CLKOUT_SEL[2:0] W
output clock selection: select the clock available
on pin VCLK
000
001
010
011
100*
101
110
111
reserved for test
reserved for test
not defined
not defined
CLKOUT
CLKFOR
CLKPIX
not defined
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Product data sheet
Rev. 01 — 17 March 2008
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 17. PIXCLKGEN_CTRL1 register (address 17h) bit description …continued
Legend: * = default value
Bit
Symbol
Access Value Description
3 to 2 CLKFOR_SEL[1:0] W
formatter clock selection: select the clock for the
ITU-R656 formatter
00
reserved for test
CLKFOR
not defined
0
01*
10
11
1 to 0 x
W
10*
for test: must be set to default value for proper
operation
9.2.7 Clamp levels registers
Table 18. Bright levels registers (address 1Ah to 1Ch) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
1Ah
BRIGHT_GY 7 to 0 BRIGHT_ GY[7:0] W
10h* G/Y brightness: these bits control the clamp level of the
G/Y channel
1Bh
BRIGHT_BU 7 to 0 BRIGHT_ BU[7:0] W
80h* B/PB brightness: these bits control the clamp level of
the B/PB channel
1Ch BRIGHT_RV 7 to 0 BRIGHT_ RV[7:0]
W
80h* R/PR brightness: these bits control the clamp level of
the R/PR channel
Table 19. Relationship between the brightness code and the clamp level
Programmed code (8-bits)
Clamp code (decimal)
Decimal
Binary MSB/LSB
0000 0000
:
0
0
:
:
247
1111 0111
247
9.2.8 Video gain registers (GAIN_RV, GAIN_BU, GAIN_GY)
Table 20. R/V video gain registers (addresses 20h to 23h) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value
Description
20h
21h
COARSE_GAINRV 7 to 4 -
W
not used
3 to 0 COARSE_RV[3:0] W
04h*
coarse_rv: coarse gain value for channel R/V
not used
FINE_GAINRV
7
-
W
W
W
W
W
6 to 0 FINE_RV[6:0]
7 to 0 HIGH_RV[7:0]
5Ch*
F0h*
fine_rv: fine gain value for channel R/V
high_rv: AGC high value for channel R/V
not used
22h
23h
AGC_HIGHRV
AGC_LOWRV
7
-
6 to 0 LOW_RV[6:0]
90h*
low_rv: AGC low value for channel R/V
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 21. B/U video gain registers (addresses 2Ah to 2Dh) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value
Description
2Ah
2Bh
COARSE_GAINBU 7 to 4 -
W
not used
3 to 0 COARSE_GY[3:0] W
04h*
coarse_bu: coarse gain value for channel B/U
not used
FINE_GAINBU
7
-
W
W
W
W
W
6 to 0 FINE_BU[6:0]
7 to 0 HIGH_BU[7:0]
5Ch*
F0h*
fine_bu: fine gain value for channel B/U
high_bu: AGC high value for channel B/U
not used
2Ch AGC_HIGHBU
2Dh AGC_LOWBU
7
-
6 to 0 LOW_BU[6:0]
90h*
low_bu: AGC low value for channel B/U
Table 22. G/Y video gain registers (addresses 34h to 37h) bit description
Legend: * = default value
Addr Register
Bit
COARSE_GAINGY 7 to 4 -
3 to 0 COARSE_GY[3:0] W
Symbol
Access Value Description
34h
35h
W not used
04h* coarse_gy: coarse gain value for the channel
G/Y
FINE_GAINGY
7
-
W
W
W
W
W
not used
6 to 0 FINE_GY[6:0]
7 to 0 HIGH_GY[7:0]
5Ch* fine_gy: fine gain value for the channel G/Y
F0h* high_gy: AGC high value for the channel G/Y
not used
36h
37h
AGC_HIGHGY
AGC_LOWGY
7
-
6 to 0 LOW_GY[6:0]
90h* low_gy: AGC low value for the channel G/Y
9.2.9 Sync timing measurement registers
Table 23. Sync timing measurement registers (address 40h to 44h) bit description
Addr Register Bit Symbol Access Value Description
40h
41h
44h
42h
44h
43h
44h
V_PER_MSB
7 to 0 V_PER[19:12]
7 to 0 V_PER[11:4]
7 to 4 V_PER[3:0]
7 to 0 H_PER[9:2]
3 to 2 H_PER[1:0]
R
R
R
R
R
00h* vertical period: indicates the period of two fields
(interlaced) or frames (progressive), counted in MCLK
clock periods[1]
V_PER_ISB
STM_LSB
00h*
0000*
H_PER_MSB
STM_LSB
00h* horizontal period: indicates the period of the line,
counted in MCLK clock periods[1]
00*
HS_WIDTH_MSB 7 to 0 HS_WIDTH[9:2] R
STM_LSB 1 to 0 HS_WIDTH[1:0] R
00h* horizontal sync width: indicates the width of the
horizontal sync pulse, counted in MCLK clock
periods[1]
00*
[1] The recommended frequency for MCLK signal is 13.5 MHz.
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
9.2.10 Color space conversion registers
Table 24. MAT_CTRL register (address 80h) bit description
Legend: * = default value
Bit
Symbol
Access Value
Description
7 to 2
-
W
00 0000* not used
1 and 0 MAT_SC[1:0] W
scale factor selection: fix the scale factor to
convert the floating matrix [Cxy] into an integer matrix
C11 C12 C13
P11 P12 P13
C21 C22 C23
C31 C32 C33
[Pxy]:
= INT S ×
.
P21 P22 P23
P31 P32 P33
The choice depends on the biggest coefficient in
absolute value |Cxy|:
00
01
10*
11
when 2 ≤ |Cxy| < 4; S = 256
when 1 ≤ |Cxy| < 2; S = 512
when |Cxy| < 1; S = 1024
undefined
Table 25. Offset input registers (address 81h to 86h) bit description
Legend: * = default value[1]
Addr Register
Bit
MAT_OI1_MSB 7 to 3 -
2 to 0 MAT_OI1[8:6]
Symbol
Access Value
Description
81h
W
W
W
0 0000* not used
000*
00h*
offset in 1 compensate the brightness value for
the channel G/Y, e.g. with YCBCR input, −16 for Y
so OFFSET_IN1 = 1111 0000b = F0h[2]
82h
MAT_OI1_LSB 7 to 2 OFFSET_IN1[5:0]
1 to 0 -
W
W
W
W
00*
not used
83h
84h
MAT_OI2_MSB 7 to 3 -
0 0000* not used
2 to 0 MAT_OI2[8:6]
000*
00h*
offset in 2 compensate the brightness value for
the channel R/V, e.g. with YCBCR input, −128 for
CR so OFFSET_IN2 = 1000 0000b = 80h[2]
MAT_OI2_LSB 7 to 2 OFFSET_IN2[5:0]
1 to 0 -
W
00*
not used
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 25. Offset input registers (address 81h to 86h) bit description …continued
Legend: * = default value[1]
Addr Register
Bit
MAT_OI3_MSB 7 to 3 -
2 to 0 MAT_OI3[8:6]
Symbol
Access Value
Description
85h
W
W
W
0 0000* not used
000*
00h*
offset_in3 compensate the brightness value for
the channel B/U, e.g. with YCBCR input, −128 for
CB so OFFSET_IN3 = 1000 0000b = 80h[2]
86h
MAT_OI3_LSB 7 to 0 OFFSET_IN3[5:0]
-
1 to 0 -
W
00*
not used
[1] The default values correspond with the RGB full-scale to YCBCR ITU-R BT.601 reduced-scale conversion.
[2] The value is signed 11-bit two’s complement integer.
Table 26. Coefficient registers (address 87h to 98h) bit description
Legend: * = default value[1]
Addr Register
Bit
MAT_P11_MSB 7 to 3 -
2 to 0 P11[10:8] W
Symbol Access Value
Description
87h
W
0 0000* not used
010*
02h*
coefficient (1,1): coefficient from the G/Y channel to the
G/Y channel[2]
88h
89h
MAT_P11_LSB 7 to 0 P11[7:0]
MAT_P12_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P12[10:8] W
001*
06h*
coefficient (1,2): coefficient from the R/CR channel to the
G/Y channel[2]
8Ah
8Bh
MAT_P12_LSB 7 to 0 P12[7:0]
MAT_P13_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P13[10:8] W
000*
64h*
coefficient (1,3): coefficient from the B/CB channel to the
G/Y channel[2]
8Ch MAT_P13_LSB 7 to 0 P13[7:0]
8Dh MAT_P21_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P21[10:8] W
110*
89h*
coefficient (2,1): coefficient from the G/Y channel to the
R/CR channel[2]
8Eh
8Fh
MAT_P21_LSB 7 to 0 P21[7:0]
MAT_P22_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P22[10:8] W
001*
C0h*
coefficient (2,2): coefficient from the R/CR channel to the
R/CR channel[2]
90h
91h
MAT_P22_LSB 7 to 0 P22[7:0]
MAT_P23_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P23[10:8] W
111*
B7h*
coefficient (2,3): coefficient from the B/CB channel to the
R/CR channel[2]
92h
93h
MAT_P23_LSB 7 to 0 P23[7:0]
MAT_P31_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P31[10:8] W
110
coefficient (3,1): coefficient from the G/Y channel to the
B/CB channel[2]
94h
95h
MAT_P31_LSB 7 to 0 P31[7:0]
MAT_P32_MSB 7 to 3 -
W
W
D7h*
0 0000* not used
2 to 0 P32[10:8] W
111*
69h*
coefficient (3,2): coefficient from the R/CR channel to the
B/CB channel[2]
96h
97h
MAT_P32_LSB 7 to 0 P32[7:0]
MAT_P33_MSB 7 to 3 -
W
W
0 0000* not used
2 to 0 P33[10:8] W
MAT_P33_LSB 7 to 0 P33[7:0]
001*
C0h*
coefficient (3,3): coefficient from the B/CB channel to the
B/CB channel[2]
98h
W
[1] The default values of the coefficients correspond with the RGB full-scale to YCBCR ITU-R BT601 reduced scale conversion.
[2] The value is signed 11-bit two’s complement integer.
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Product data sheet
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25 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 27. Offset output registers (address 99h to 9Eh) bit description
Legend: * = default value[1]
Addr Register
99h MAT_OO1_MSB 7 to 3 -
2 to 0 OFFSET_OUT1[10:8] W
Bit
Symbol
Access Value
Description
W
0 0000* not used
000*
40h*
offset output 1: the new brightness values for
the channel G/Y, e.g. with YCBCR output, 16 for Y
so OFFSET_OUT1 = 0 0001 0000b = 10h[2]
9Ah MAT_OO1_LSB 7 to 0 OFFSET_OUT1[7:0]
W
9Bh MAT_OO2_MSB 7 to 3 -
W
0 0000* not used
2 to 0 OFFSET_OUT2[10:8] W
010*
00h*
offset output 2: the new brightness values for
the channel R/V e.g. with YCBCR output, 128 for
CR so OFFSET_OUT2 = 0 1000 0000b = 80h[2]
9Ch MAT_OO2_LSB 7 to 0 OFFSET_OUT2[7:0]
W
9Dh MAT_OO3_MSB 7 to 3 -
W
0 0000* not used
2 to 0 OFFSET_OUT3[10:8] W
010*
00h*
offset output 3: the new brightness values for
the channel B/U e.g. with YCBCR output, 128 for
CB so OFFSET_OUT3 = 0 1000 0000b = 80h[2]
9Eh MAT_OO3_LSB 7 to 0 OFFSET_OUT3[7:0]
W
9Fh MAT_BYPASS
7 to 1 -
MAT_BP
W
W
00h*
not used
0
matrix bypassed: bypasses or not the matrix
and offsets conversion
0
not bypassed
bypassed
1*
[1] The default values correspond with the RGB full-scale to YCBCR ITU-R BT.601 reduced-scale conversion.
[2] The value is signed 11-bit two’s complement integer.
9.2.11 Line and pixel counters
Table 28. Pixel counter registers (address A1h to A3h) bit description
Legend: * = default value
Address Register
Bit
Symbol
Access Value Description
A1h
A2h
PXCNT_PR_LSB
PXCNT_MSB
7 to 0 PXCNT_PR[7:0]
7 to 4 PXCNT_PR[11:8]
W
W
03h* pixel counter preset: preset value stored in
the pixel counter on the rising edge of the
internal HSYNC
0h*
3 to 0 PXCNT_NPIX[11:8] W
PXCNT_NPIX_LSB 7 to 0 PXCNT_NPIX[7:0]
3h*
pixel counter number of pixels: modulo of
the pixel counter; this counter counts from 1
to PXCNT_NPIX and rolls-over to 1; the
recommended value is the total number of
pixels per line
A3h
W
60h*
Table 29. Line counter registers (address A4h to A6h) bit description
Legend: * = default value
Address Register
Bit
Symbol
Access Value Description
A4h
A5h
LCNT_PR_LSB
LCNT_MSB
7 to 0 LCNT_PR[7:0]
7 to 4 LCNT_PR[11:8]
W
W
01h* line counter preset: preset value stored in the
line counter on the rising edge of the internal
0h*
VSYNC
3 to 0 LCNT_NLIN[11:8] W
LCNT_NLIN_LSB 7 to 0 LCNT_NLIN[7:0]
0h*
line counter number of lines: modulo of the
line counter; this counter counts from 1 to
LCNT_NLIN and rolls-over to 1; the
A6h
W
00h*
recommended value is the total number of lines
per frame; if value is set to 000h the line counter
uses the value of MEAS_LINES
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
PXCNT_NPIX: [4:4095] pixels
pixel counter counts CLKPIX pulses modulo NPIX
iVS
line 1
pixel 1
in case of interlaced signal,
line counter don’t care the
iVS of second field
line counter counts iHS
pulses modulo NLIN
PXCNT_PR
LCNT_PR
rising edge of iVS
loads the line counter with
the LCNT_PR value
iHS
rising edge of iHS
loads the pixel counter with
the PXCNT_PR value
001aaa290
Fig 4. Line and pixel counters
Table 30. Horizontal reference registers (address A7h to A9h) bit description
Legend: * = default value
Address Register
Bit
HREF_S_LSB 7 to 0 HREF_START[7:0]
HREF_MSB 7 to 4 HREF_START[11:8] W
Symbol
Access Value Description
A7h
A8h
W
00h* horizontal reference start: index of the first
active pixel, and also the position of the rising
0h*
edge of HREF signal and the position of SAV; if
null, HREF stays LOW and no SAV is inserted in
the data stream
3 to 0 HREF_END[11:8]
HREF_E_LSB 7 to 0 HREF_END[7:0]
W
W
0h*
horizontal reference end (LSB): index after the
last active pixel, and also the position of the
falling edge of HREF signal and the position of
EAV; if null, HREF falls at the beginning of a new
line and no EAV is inserted in the data stream
A9h
00h*
Table 31. Horizontal reference registers (address AAh to ACh) bit description
Legend: * = default value
Address Register
Bit
Symbol
Access Value Description
AAh
ABh
HS_S_LSB
HS_MSB
7 to 0 HS_START[7:0]
7 to 4 HS_START[11:8]
W
W
00h* horizontal sync start: define the position of the
rising edge of the HS signal generated by the
timing generator[1]
0h*
3 to 0 HS_END[11:8]
7 to 0 HS_END[7:0]
W
W
0h*
horizontal sync end: define the position of the
falling edge of the HS signal generated by the
timing generator[1]
ACh
HS_E_LSB
00h*
[1] If 0, HS signal corresponds with the horizontal sync internal signal.
TDA9955HL_1
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Product data sheet
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27 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 32. Vertical reference registers (address ADh to B2h) bit description[1]
Legend: * = default value
Addr Register
ADh VREF_F1_S_MSB 7 to 3 -
2 to 0 VREF_F1_START[10:8]
Bit
Symbol
Access Value
Description
W
W
W
0 0000* not used
000*
00h*
vertical reference start for field 1:
index of the first blanking line for field 1,
and also the position of the rising edge of
VREF signal and the value of bit V in
SAV/EAV code; if 0, VREF stays LOW
AEh VREF_F1_S_LSB 7 to 0 VREF_F1_START[7:0]
AFh VREF_F1_WIDTH 7 to 0 VREF_F1_WIDTH[7:0]
W
00h*
vertical reference width for field 1:
width of the vertical blanking for field 1,
and also the width of VREF signal and
the value of bit V in SAV/EAV code; if 0,
VREF stays LOW
B0h
B1h
VREF_F2_S_MSB 7 to 3 -
2 to 0 VREF_F2_START[10:8]
W
W
W
0 0000* not used
000*
00h*
vertical reference start for field 2:
index of the first blanking line for field 2,
and also the position of the rising edge of
VREF signal and the value of bit V in
SAV/EAV code
VREF_F2_S_LSB 7 to 0 VREF_F2_START[7:0]
B2h
VREF_F2_WIDTH 7 to 0 VREF_F2_WIDTH[7:0]
W
00h*
vertical reference width for field 2:
width of the vertical blanking for field 2,
and also the width of VREF signal and
the value of bit V in SAV/EAV code
[1] In progressive case, bits VREF_F2_START[10:0] and VREF_F2_WIDTH[7:0] must be set to logic 0.
Table 33. Vertical sync registers (address B3h to BEh) bit description
Legend: * = default value
Addr Register
Bit
VS_F1_LINE_S_MSB 7 to 3 -
2 to 0 VS_F1_LINE_START[10:8] W
Symbol
Access Value
Description
B3h
W
0 0000* not used
000*
00h*
vertical sync line start for field 1:
position in number of lines of the VS
signal generated by the timing
generator for the field 1; if 0, VS
stays LOW
B4h
VS_F1_LINE_S_LSB 7 to 0 VS_F1_LINE_START[7:0]
W
B5h
VS_F1_LINE_WIDTH 7 to 0 VS_F1_LINE_WIDTH[7:0]
W
00h*
vertical sync line width for field
1: width in number of lines of the VS
signal generated by the timing
generator for field 1; if 0, VS stays
LOW
B6h
B7h
VS_F2_LINE_S_MSB 7 to 3 -
W
0 0000* not used
2 to 0 VS_F2_LINE_START[10:8] W
000*
00h*
vertical sync line start for field 2:
position in number of lines of the VS
signal generated by the timing
generator for the field 2[1]
VS_F2_LINE_S_LSB 7 to 0 VS_F2_LINE_START[7:0]
VS_F2_LINE_WIDTH 7 to 0 VS_F2_LINE_WIDTH[7:0]
W
W
B8h
00h*
vertical sync line width for field
2: width in number of lines of the VS
signal generated by the timing
generator for field 2[1]
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 33. Vertical sync registers (address B3h to BEh) bit description …continued
Legend: * = default value
Addr Register
Bit
Symbol
Access Value
Description
B9h
VS_F1_PIX_S_LSB
7 to 0 VS_F1_PIX_START[7:0]
7 to 4 VS_F1_PIX_START[11:8]
W
W
01h*
0h*
vertical sync pixel start for field
1: position in number of pixels of the
rising edge of the VS signal
BAh VS_F1_PIX_MSB
generated by the timing generator
for field 1; if 0, VS stays LOW
3 to 0 VS_F1_PIX_END[11:8]
7 to 0 VS_F1_PIX_END[7:0]
W
W
0h*
vertical sync pixel end for field 1
(LSB): position in number of pixels
of the falling edge of the VS signal
generated by the timing generator
for field 1; if 0, VS stays LOW
BBh VS_F1_PIX_E_LSB
01h*
BCh VS_F2_PIX_S_LSB
BDh VS_F2_PIX_MSB
7 to 0 VS_F2_PIX_START[7:0]
7 to 4 VS_F2_PIX_START[11:8]
W
W
01h*
0h*
vertical sync pixel start for field
2: position in number of pixels of the
rising edge of the VS signal
generated by the timing generator
for field 2
3 to 0 VS_F2_PIX_END[11:8]
7 to 0 VS_F2_PIX_END[7:0]
W
W
0h*
vertical sync pixel end for field 2:
position in number of pixels of the
falling edge of the VS signal
generated by the timing generator
for field 2
BEh VS_F2_PIX_E_LSB
01h*
[1] In progressive case bits VS_F2_LINE_START[12:0] and VS_F2_LINE_WIDTH[7:0] must be set to logic 0.
VREF
VREF_F1_START[10:0]
line 1
pixel 1
VREF_F1_WIDTH[7:0]
LOW during active video;
HIGH during vertical blanking period
active video
field 1
VREF_F2_START[10:0]
VREF_F2_WIDTH[7:0]
blanking
period
active video
field 2
(1)
VREF changes state at pixel 1
VREF_F1_START[10:0]
VREF_F1_WIDTH[7:0]
HREF
HIGH during active video;
LOW during horizontal blanking period
(1)
HREF_START[11:0]
HREF_END[11:0]
001aaa291
Fig 5. HREF and VREF in interlaced case
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
VREF
line 1
pixel 1
VREF_F1_WIDTH[7:0]
LOW during active video;
HIGH during vertical blanking period
blanking
period
active video
VREF_F2 registers must be set to 0
(1)
VREF changes state at pixel 1
VREF_F1_START[10:0]
VREF_F1_WIDTH[7:0]
HREF
HIGH during active video;
LOW during horizontal blanking period
(1)
HREF_START[11:0]
HREF_END[11:0]
001aaa292
Fig 6. HREF and VREF in progressive case
Table 34. Field reference registers (address BFh to C1h) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
BFh FREF_F1_S_LSB 7 to 0 FREF_F1_START[7:0]
W
00h* field reference for field 1 start (LSB): index
of the first line for field 1 which corresponds to
the line where the FREF signal toggles, see
register FREF_POL_MSB bit 6 to bit 4
C0h FREF_POL_MSB
7
FPOL
W
field polarity: defines the polarity of the
FREF signal and bit F in the SAV/EAV code
0*
1
field 1 is LOW and field 2 is HIGH
field 1 is HIGH and field 2 is LOW
6 to 4 FREF_F1_START[10:8] W
000* field reference for field 1 start (MSB): index
of the first line for field 1 which corresponds to
the line where the FREF signal toggles, see
register FREF_F1_S_LSB bit 7 to bit 0
3
-
W
0*
not used
2 to 0 FREF_F2_START[10:8] W
000* field reference for field 2 start: index of the
first line for field 2 which corresponds to the
line where the FREF signal toggles
C1h FREF_F2_S_LSB 7 to 0 FREF_F2_START[7:0]
W
00h*
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
line 1
FREF
pixel 1
FREF_F1_START[10:0]
LOW during field 1;
HIGH during field 2
(can be changed with bit FIELD_POL)
active video
field 1
blanking period
FREF_F2_START[10:0]
active video
field 2
FREF changes state at pixel 1
001aaa293
Fig 7. FREF in interlaced case
Table 35. Clamp signal registers (address C8h to CAh) bit description[1]
Legend: * = default value
Addr Register
C8h CLAMP_PIX_S_LSB 7 to 0 CLAMP_ PIX_ START[7:0]
C9h CLAMP_PIX_MSB 7 to 4 CLAMP_ PIX_ START[11:8] W
Bit
Symbol
Access Value Description
W
00h* clamp signal pixel start: position, in
number of pixels, of the beginning of
the clamp signal generated by the
timing generator
0h*
3 to 0 CLAMP_ PIX_ END[11:8]
CAh CLAMP_PIX_E_LSB 7 to 0 CLAMP_PIX_ END[7:0]
W
W
0h*
clamp signal pixel end: position, in
number of pixels, of the end of the
clamp signal generated by the timing
generator
00h*
[1] Minimum width of the clamp pulse is 40 pixels and it must be active only during the horizontal back porch.
Table 36. CLP_Fx_LINE_nnn registers (address CBh to D0h) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
CBh CLP_F1_LINE_S_MSB 7 to 3 -
W
W
W
0
not used
0000*
2 to 0 CLAMP_F1_ LINE_
000* clamp signal line start for
field 1 (LSB): position, in
START[10:8]
number of lines, from which no
CCh CLP_F1_LINE_S_LSB 7 to 0 CLAMP_F1_LINE_START[7:0]
00h*
clamp pulses are generated for
field 1, typically during the
vertical pulse in case of the
sync on green signal
CDh CLP_F1_LINE_WIDTH 7 to 0 CLAMP_F1_LINE_WIDTH[7:0]
W
00h* clamp signal line width for
field 1: width, in number of
lines, where no clamp pulses
are generated for field 1
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 36. CLP_Fx_LINE_nnn registers (address CBh to D0h) bit description …continued
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
CEh CLP_F2_LINE_S_MSB 7 to 3 -
W
0
not used
0000*
2 to 0 CLAMP_F2_LINE_START[10:8]
W
W
000* clamp signal line start for
field 2 (LSB): position, in
CFh CLP_F2_LINE_S_LSB 7 to 0 CLAMP_F2_LINE_START[7:0]
D0h CLP_F2_LINE_WIDTH 7 to 0 CLAMP_F2_LINE_WIDTH[7:0]
00h*
number of lines, from which no
clamp pulses are generated for
field 2, typically during the
vertical pulse in case of the
sync on green signal
W
00h* clamp signal line width for
field 2: width, in number of
lines, where no clamp pulses
are generated for field 2
Table 37. GAIN signal registers (address D1h to D3h) bit description[1]
Legend: * = default value
Address Register
Bit
GAIN_S_LSB 7 to 0 GAIN_START[7:0]
GAIN_MSB 7 to 4 GAIN_ START[11:8] W
Symbol
Access Value Description
D1h
D2h
W
00h* gain start signal: position of the gain signal
generated by the timing generator
0h*
3 to 0 GAIN_ END[11:8]
GAIN_E_LSB 7 to 0 GAIN_END[7:0]
W
W
0h*
gain end signal: position of the end of the gain
signal generated by the timing generator
D3h
51h*
[1] The minimum width of the gain pulse (GAIN_END − GAIN_START) is 80 pixels and can include the horizontal sync pulse. The gain
pulse and the clamp pulse should not overlap.
Table 38. Horizontal sync registers (address D4h to D6h) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
D4h FDW_S_LSB 7 to 0 FDW_START[7:0]
W
W
00h* frame detection window start: position of the start
of the frame detection window; the recommended
value is 7⁄8 of total number of pixels per line
D5h FDW_MSB
7 to 4 FDW_START[11:8]
3 to 0 FDW_END[11:8]
0h*
W
W
0h*
frame detection window end: position of the end of
the frame detection window; the recommended value
is 3⁄8 of total number of pixels per line
D6h FDW_E_LSB 7 to 0 FDW_END[7:0]
00h*
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 39. Measured lines and pixels registers (address D7h to DAh) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
D7h ASD_MEASLIN_MSB 7
INTD
R
interlaced detected: indicates an interlaced
or progressive signal
0*
1
progressive
interlaced
6
AUTO_OK
R
automatic detection: the number of
measured lines per frame
0*
1
correspond to 625 or 525 (±2 lines of
tolerance)
the timing generator is forced to 576i or
480i standard
5
525
R
R
interlaced detected: when AUTO_OK = 1
0*
1
is forced to 480i standard
525 (±2 lines of tolerance) lines per frame
are counted
4 to 3 -
not used
2 to 0 MEAS_LINES[10:8] R
000* measured number of lines: indicates the
number of lines per frame measured by the
timing generator
D8h MEASLIN_LSB
D9h MEASPIX_MSB
7 to 0 MEAS_LINES[7:0]
R
00h*
7 to 4 -
R
R
R
0h*
not used
3 to 0 MEAS_PIX[11:8]
7 to 0 MEAS_PIX[7:0]
0h*
measured number of pixels: indicates the
number of pixels per line measured by the
timing generator; in Analog mode, the value
is the same as the PLL division value
DAh MEASPIX_LSB
00h*
Table 40. Blanking code registers (address DCh to DFh) bit description[1]
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
DCh BLK_GY_LSB 7 to 2 BLK_GY[5:0] W
10h* blanking code of the G/Y channel (MSB), see address
DFh bit 7 to bit 6
1 to 0 -
W
not used
DDh BLK_BU_LSB 7 to 2 BLK_BU[5:0] W
80h* blanking code of the B/CB channel (MSB), see address
DFh bit 4 to bit 3
1 to 0 -
W
not used
DEh BLK_RV_LSB 7 to 2 BLK_RV[5:0] W
80h* blanking code of the R/CR channel (MSB), see address
DFh bit 1 to bit 0
1 to 0 -
W
not used
DFh BLK_MSB
7 to 6 BLK_GY[7:6] W
00*
blanking code bits 7 and 6 of the G/Y channel (MSB),
see address DCh
5
-
W
0*
not used
4 to 3 BLK_BU[7:6] W
10*
blanking code bits 7 and 6 of the B/CB channel (MSB),
see address DDh
2
-
W
0*
not used
1 to 0 BLK_RV[7:6] W
10*
blanking code bits 7 and 6 of the R/CR channel (MSB),
see address DEh
TDA9955HL_1
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Product data sheet
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33 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
[1] These register control the blanking code of the x/x channel; this code is output during the horizontal blanking (HREF is LOW) or the
vertical blanking (VREF is HIGH)
9.2.12 Prefiltering register (PRE_FILTERS)
This register is used to downsample the R/PR and B/PB channels for the YUV 4 : 2 : 2
semi-planar and ITU-R BT.656 formats.
Table 41. PRE_FILTER register (address E0h) bit description
Legend: * = default value
Bit
7 and 6 -
5 and 4 FILTER_BU[1:0] W
Symbol
Access Value Description
W
00*
not used
B/CB downsampling filter: enables the shape of the
prefilter for the B/CB channel
00
no filter (used in 4 : 4 : 4 mode)
average of two samples
01
10*
11
simple 7-taps filter
27 taps ITU-R BT.601 compliant half-band filter
not used
3 and 2 -
W
00*
1 and 0 FILTER_RV[1:0] W
R/CR downsampling filter: enables the shape of the
prefilter for the R/CR channel
00
01
10*
11
no filter (used in 4 : 4 : 4 mode)
average of two samples
simple 7-taps filter
27 taps ITU-R BT.601 compliant half-band filter
9.2.13 Range control registers
Table 42. Range control registers (address E1h to E4h) bit description
Legend: * = default value
Addr Register
Bit
Symbol
Access Value Description
E1h
E2h
E3h
E4h
OF_CCEIL
7 to 6 -
W
W
not used
5 to 0 C_CEIL[5:0]
C0h* chrominance ceiling level: fix the maximum code of B/CB
and R/CR channels[1]
OF_CFLOO 7 to 6 -
R
W
not used
5 to 0 C_FLOOR[5:0] W
40h* chrominance floor level: fix the minimum code of B/CB
and R/CR channels[2]
OF_YCEIL
7 to 6 -
W
W
not used
5 to 0 Y_CEIL[5:0]
ACh* luminance ceiling level: fix the maximum code of the
G/Y channel[1]
OF_YFLOO 7 to 6 -
R
W
not used
5 to 0 Y_FLOOR[5:0] W
40h* luminance floor level: fix the minimum code of G/Y
channel[2]
[1] The maximum level can be chosen between the code words C0h (00h programmed) and FFh (3Fh programmed), the 2 MSBs are set to
logic 1 by the device; all higher codes are truncated.
[2] The minimum level can be chosen between the code words 000h (00h programmed) and 0FFh (FFh programmed), the 2 MSBs are set
to logic 0 by the device; all lower codes are truncated.
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
9.2.14 Output formatter register
Table 43. OF_CTRL register (address E5h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7
OUT
W
output control: sets the outputs (VPA[11:0],
VPB[11:0], VPC[11:0], VCLK, HS, VS, CS, HREF,
VREF, FREF, DE, OR_R, OR_B, OR_G, CTL0 to
CTL3, PL)
0*
1
outputs active
outputs high-impedance
video ports LOW
6
VPL
W
0
forces the unused video port outputs to
high-impedance
1*
-
forces the unused video port outputs to LOW
not used
5
4
-
W
W
BLC
blanking codes
0*
1
inserts the blanking codes
removes the blanking codes
timing reference codes
3
TRC
W
0*
inserts the timing reference codes; the signals HREF
and VREF must be programmed into the VHREF
timing generator to insert the timing reference codes;
timing reference codes are inserted in all video port
streams and are present during the vertical blanking;
see Table 44
1
removes the timing reference codes
for test; must be set to logic 0 for proper operation
formatter selection
2
-
W
0*
1 and 0 FOR_SEL[1:0] W
00
01
10*
11
4 : 4 : 4 format[1]
4 : 2 : 2 semi-planar format[2]
4 : 2 : 2 ITU-R BT.656 format[3]
undefined
[1] In 4 : 4 : 4, the video is output on three video ports, one per color.
[2] In 4 : 2 : 2 semi-planar, the video is output on two video ports, one for luminance (Y) and one for
chrominance (CB and CR alternately).
[3] In 4 : 2 : 2 ITU-R BT.656, the video is output on one video port (CB-Y-CR-Y sequence).
Table 44. Timing reference codes
Codeword
3FFh
A9
1
A8
1
A7
1
A6
1
A5
1
A4
1
A3
1
A2
1
A1
1
A0
1
000h
0
0
0
0
0
0
0
0
0
0
000h
0
0
0
0
0
0
0
0
0
0
SAV/EAV[1]
1
F
V
H
P3
P2
P1
P0
0
0
[1] F = 0 during field 1; F = 1 during field 2; V = 1 during field blanking; V = 0 elsewhere; H = 0 in SAV, H = 1 in EAV and P0 to P3 are
protection bits.
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
9.2.15 Sync output selection registers
Table 45. CSVSHS_SEL register (address E8h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7 to 5
CS_SEL[2:0] W
composite sync selection: selects the signal outputs
on pin CS
000*
001
xxx
composite signal from the SDRS
combination of HS and VS
for test
4 to 3
VS_SEL[1:0] W
vertical sync selection: selects the signal outputs on
pin VS
00*
01
10
11
vertical sync from the SDRS
vertical sync from the VHREF timing generator
undefined
undefined
2 to 0
HS_SEL[2:0] W
horizontal sync selection: selects the signal outputs on
HS pin
000*
001
010
011
100
101
110
111
horizontal sync from the PLL output
for test
horizontal sync from the SDRS
horizontal sync from the HDMI receiver
HS signal generated by the VHREF timing generator
undefined
undefined
undefined
9.2.16 Output polarity control register
Table 46. POL_CTRL register (address E9h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7 to 6 -
W
W
not used
5
4
3
2
CS_POL
composite sync polarity: pin CS; composite sync signal
does not toggle; positive signal
0*
1
toggles; negative signal
HS_POL
VS_POL
W
W
horizontal sync polarity: pin HS; horizontal sync signal
does not toggle; positive signal
0*
1
toggles; negative signal
vertical sync polarity: pin VS; vertical sync signal
does not toggle; positive signal
0*
1
toggles; negative signal
FREF_POL W
field reference polarity: pin FREF; field reference signal
does not toggle; positive signal
0*
1
toggles; negative signal
TDA9955HL_1
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Product data sheet
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36 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 46. POL_CTRL register (address E9h) bit description …continued
Legend: * = default value
Bit
Symbol
Access Value Description
1
HREF_POL W
horizontal reference polarity: pin HREF; horizontal
reference signal
0*
1
does not toggle; positive signal
toggles; negative signal
0
VREF_POL W
vertical reference polarity: pin VREF; vertical reference
signal
0*
1
does not toggle; positive signal
toggles; negative signal
9.2.17 Video ports control register
Table 47. OUTPUT_CTRL register (address EAh) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7 and 6 -
W
not used
5 and 4 VPC_SEL[1:0] W
10*
01*
00*
video port C selection: select the data stream to be
output on video port C; see Table 48
3 and 2 VPB_SEL[1:0] W
video port B selection: select the data stream to be
output on video port B; see Table 48
1 and 0 VPA_SEL[1:0]
W
video port A selection: select the data stream to be
output on video port A; see Table 48
Table 48. Data stream selection
VPx_SEL[1:0]
4 : 4 : 4 RGB
4 : 4 : 4 YCBCR
4 : 2 : 2 YCBCR
semi-planar
4 : 2 : 2 YCBCR
ITU-R BT.656
00
01
10
11
R
V
CB-CR
CB-Y-CR-Y
B
U
not used (VPL)
Y
not used (VPL)
not used (VPL)
high-impedance
G
Y
high-impedance
high-impedance
high-impedance
9.2.18 Data enable signal control register
Table 49. DE_CTRL register (address EBh) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7
HR_PXQ
W
W
horizontal reference pixel qualification: HREF signals
the XAV-codes
0*
1
not signaled
signaled
6
HR_SEL
horizontal reference selection: HREF dependence of
VREF
0*
1
independent of VREF
logic combination (HREF AND VREF)
TDA9955HL_1
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Product data sheet
Rev. 01 — 17 March 2008
37 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 49. DE_CTRL register (address EBh) bit description …continued
Legend: * = default value
Bit
Symbol
Access Value Description
5
DE_PXQ
W
data enable pixel qualification: expands or not the data
enable signal to include the SAV/EAV codes
0*
1
does not expand
expands
4
DE_POL
W
data enable polarity: selects the signal outputs on pin DE
0*
1*
-
does not toggle
toggles
3 to 0 -
not used
apx : active panel
-
3FF 000 000 SAV apx apx
apx
apx 3FF 000 000 EAV
-
1
2
n−1
n
HREF_PXQ = 0
HREF
HREF_PXQ = 1
DE_PXQ = 0
DE_PXQ = 1
DE
001aaa509
Fig 8. Pixel qualification
9.2.19 Software reset registers
Table 50. RESET_CNTRL register (address F1h) bit description
Legend: * = default value
Bit
Symbol
Access Value
Description
7 to 5 -
W
-
not used
4
3
RST_MAN W
reset manual: activates the manual software reset for the
digital clamp loop, the video gain and the digital
processing
0*
1
automatic mode; the reset is enabled when no activity
is detected
manual mode
RST_AVI
W
W
software reset analog video interface: resets the digital
clamp loop and the registers depending on the CLKPIX
clock in manual mode
0*
1
normal operation
reset mode
2 to 0 -
-*
not used
TDA9955HL_1
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Product data sheet
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38 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Registers that are reset to the default value are as follows:
• Video gain registers (address 20h to 3Eh)
• Color space conversion registers (address 80h to 9Eh)
• VHREF timing registers (address A0h to DFh)
• Prefiltering registers (address E0h)
• Output formatter registers (address E1h to E5h)
• Output register (address E9h to EBh)
Register CSVBHS_SEL (address E8h) is not reset.
9.2.20 Power-down control registers
Table 51. PD_AVI_CTRL0 register (address F4h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
7 to 5 -
W
W
0*
not used
4
3
2
PD_SOG2
power-down SOG2: enables the power-down of the slicer
of input 2
0*
1
normal operation
Power-down mode
PD_SOG1
PD_DLL
W
W
power-down SOG1: enables the power-down of the slicer
of input 1
0*
1
normal operation
Power-down mode
power-down DLL: enables the power-down of the
delay-locked loop
0*
1
normal operation
Power-down mode
1
0
PD_PLL
PD_AVI
W
W
power-down PLL: enables the power-down of the PLL
normal operation
0*
1
Power-down mode
power-down AVI: enables the power-down of the analog
video interface
0*
1
normal operation
Power-down mode
Table 52. PD_AVI_CTRL1 register (address F5h) bit description
Legend: * = default value
Bit
7 to 3 -
PD_ADC_BU W
Symbol
Access Value Description
W
-
not used
2
power-down B/PB ADC: enables the power-down of the
blue channel (B/PB) ADC
0*
1
normal operation
Power-down mode
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 52. PD_AVI_CTRL1 register (address F5h) bit description …continued
Legend: * = default value
Bit
Symbol
Access Value Description
1
PD_ADC_GY W
power-down G/Y ADC: enables the power-down of the
green channel (G/Y) ADC
0*
1
normal operation
Power-down mode
0
PD_ADC_RV W
power-down R/PR ADC: enables the power-down of the
red channel (R/PR) ADC
0*
1
normal operation
Power-down mode
Table 53. FVH_SEL register (address F6h) bit description
Legend: * = default value
Bit
7 to 1 -
FVH_SEL
Symbol
Access Value Description
W
W
-
not used
0
timing signals: defiines the output on pins 15, 16 and 17
0
HREF; VREF; FREF
HS; VS; CS
1*
Table 54. LSB_OUT_SEL register (address F7h) bit description
Legend: * = default value
Bit
Symbol
Access Value Description
LSB signal: selects the signal on the LSB pin of each
7 to 0 LSB_SEL
W
digital port (pins 75, 88 and 100).
VPA[0]; VPB[0]; VPC[0]
HREF; VREF; FREF
00h*
81h
82h
ORGY; ORBU; ORRV
Table 55. ORX_SEL register (address F9h) bit description[1][2]
Legend: * = default value
Bit
Symbol Access Value Description
7 and 6
-
W
Orr signals: selects the signal applied on internal Orr (over
range channel red) signal
00
01
10
or_rv_agc: an ADC output underflow or overflow of the
range defined by the registers 22h and 23h
or_rv_datapath: an ADC output underflow or overflow of
the range defined by the registers E1h and E2h
gain: monitors the gain calibration signal. see Figure 12
and Figure 13
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 55. ORX_SEL register (address F9h) bit description[1][2] …continued
Legend: * = default value
Bit
Symbol Access Value Description
5 to 3
-
W
Org signals: selects the signal applied on internal Org (over
range channel green) signal
x00
x01
x10
or_gy_agc: an ADC output underflow or overflow of the
range defined by the registers 36h and 37h
or_gy_datapath: an ADC output underflow or overflow of
the range defined by the registers E3h and E4h
clamp: monitors the clamp calibration signal.
see Figure 12 and Figure 13
2 to 0
-
W
Orb signals: selects the signal applied on internal Orb (over
range channel blue) signal
x00
x01
or_bu_agc: an ADC output underflow or overflow of the
range defined by the registers 2Ch and 2Dh
or_bu_datapath: an ADC output underflow or overflow of
the range defined by the registers E1h and E2h
[1] Defines the internal signals on ORGY, ORBU and ORRV.
[2] The signals are not effected by changing the position of the digital output ports with register EAh.
10. Limiting values
Table 56. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
−0.5
-
Max
+4.6
+2.5
+0.5
Unit
V
VDDx(3V3) supply voltage on all 3.3 V pins
VDDx(1V8) supply voltage on all 1.8 V pins
V
∆VDD
supply voltage difference
input voltage
V
VI
VDD + 0.5 V
5 V tolerant
+6.0
35
V
IO
output current
mA
°C
°C
°C
V
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−40
0
+125
70
-
150
-
Vesd
electrostatic discharge voltage human body model
2000
11. Thermal characteristics
Table 57. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient in free air
29.7
K/W
TDA9955HL_1
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Product data sheet
Rev. 01 — 17 March 2008
41 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
12. Characteristics
Table 58. Characteristics
VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 °C to 70 °C; typical
values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 °C; unless
otherwise specified.
Symbol
Supplies
VDDA(3V3)
VDDA(1V8)
VDDI(3V3)
VDDC(1V8)
VDDO(3V3)
IDDA(1V8)
IDDA(3V3)
IDDI(3V3)
Parameter
Conditions
Min
Typ
Max Unit
analog supply voltage (3.3 V)
analog supply voltage (1.8 V)
input supply voltage (3.3 V)
core supply voltage (1.8 V)
output supply voltage (3.3 V)
analog supply current (1.8 V)
analog supply current (3.3 V)
input supply current (3.3 V)
output supply current (3.3 V)
core supply current (1.8 V)
3.15 3.3
1.75 1.8
3.15 3.3
1.75 1.8
3.15 3.3
3.45
1.85
3.45
1.85
3.45
160
40
V
V
V
V
V
-
-
-
-
-
151
33
48
48
96
mA
mA
mA
mA
mA
-
IDDO(3V3)
IDDC(1V8)
80
115
∆VDD(1V8-1V8) supply voltage difference between two start-up and established
1.8 V supplies conditions
−0.15 -
+0.15 V
∆VDD(3V3-3V3) supply voltage difference between two start-up and established
3.3 V supplies conditions
−0.3
-
-
+0.3
1.65
V
V
∆VDD(3V3-1V8) supply voltage difference between one start-up and established
1.35
3.3 V supply and one 1.8 V supply
conditions
P
power dissipation
power dissipation in power-down mode I2C-bus and activity detection
power-up
analog interface; fs = 170 MHz
-
-
750
47
945
74
mW
mW
Ppd
Analog inputs (R1, R2, G1, G2, B1, B2)
B−3dB
G
−3 dB bandwidth
channel plus multiplexer
minimum gain; code = 0
maximum gain; code = 4095
350
380
0
400
MHz
dB
gain
-
-
-
-
-
5
dB
∆G/(G×∆T)
Vi(p-p)
relative gain variation over temperature
peak-to-peak input voltage
input capacitance
0.003 0.008 ppm/°C
black-to-white
0.65 0.7
0.9
-
V
Ci
-
-
0.3
2.5
pF
%
MG(CTC)(rms)
channel-to-channel gain matching
(RMS value)
6.7
Sync on green/luminance inputs (SOG1, SOG2), see Figure 9
td
tr
delay time
rise time
sync pulse
-
-
108
320
-
-
ns
ns
10 % to 90 %; bi-level or tri-level
horizontal sync pulse; 4 clock
interval
tf
fall time
90 % to 10 %; bi-level or tri-level
horizontal sync pulse; 4 clock
interval
-
320
-
ns
TDA9955HL_1
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Product data sheet
Rev. 01 — 17 March 2008
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 58. Characteristics …continued
VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 °C to 70 °C; typical
values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 °C; unless
otherwise specified.
Symbol
Clamps
NCL
Parameter
Conditions
Min
Typ
Max Unit
clamping accuracy
-
-
0.1
1.8
LSB
MCL(CTC)
channel-to-channel clamp matching
1.14 1.20 LSB
Phase-locked loop (PLL) of analog video part
[1]
tjit(PLL)(p-p)
peak-to-peak PLL jitter time
number of pixels
fs = 170 MHz; during 3 s
pixels per line
-
0.16 1.60 ns
Npix
256
15
12.5
-
-
4095
65
-
fclk(ref)
reference clock frequency
PLL output clock frequency
phase difference
-
kHz
MHz
step
deg
fclk(o)(PLL)
-
170
4.2
∆ϕ
standard at 170 MHz
2.7
∆ϕstep
phase shift step
manual controls; Tamb = 25 °C
-
11.25 -
ADCs (+ AGCs)
fs
sampling frequency
integral non-linearity
differential non-linearity
signal-to-noise ratio
maximum
170
-
-
-
-
-
MHz
LSB
LSB
dB
INL
DNL
S/N
fs = 170 MHz
fs = 170 MHz
-
-
-
±0.5
±0.7
45
without harmonics; fi = 1 MHz;
sinewave input; fs = 170 MHz
Clock timing input (CKEXT)
fclk(max)
maximum clock frequency
clock duty cycle
170
-
-
-
-
MHz
%
δclk
50
Clock timing output (VCLK)
fclk(max)
maximum clock frequency
analog inputs; RGB/YUV/YUV
4 : 2 : 2
semi-planar/ITU-R BT.656
170
-
-
MHz
%
δclk
clock duty cycle
45
-
50
55
-
Horizontal timing output (HS)
td(pipe) pipeline delay time
horizontal sync pulse delay; in
phase with data outputs
15.4
clock
interval
Timing output (VPA0 to VPA7, VPB0 to VPB7, VPC0 to VPC7), see Figure 10
td(s)
sampling delay time
data output set-up time
data output hold time
referenced to VCLK
-
3.2
-
ns
ns
ns
tsu(Q)
th(Q)
-
-
-
4.5
-
2
TTL digital inputs (HCSYNC1, HCSYNC2, VSYNC1, VSYNC2 and CKEXT)
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
-
-
-
-
-
-
0.8
5.5
±5
3
V
2.0
V
VI = 0 V or VI = VDD
20 % to 80 %
-
-
-
µA
ns
ns
tr
rise time
tf
fall time
80 % to 20 %
3
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 58. Characteristics …continued
VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 °C to 70 °C; typical
values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
LV-TTL digital outputs (VPA0 to VPA7, VPB0 to VPB7, VPC0 to VPC7, VCLK, DE, HS, VS, CS, HREF, VREF, FREF)
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
VDDO = 3.0 V; IOL = 2 mA;
CL = 10 pF
-
-
-
0.4
-
V
V
VDDO = 3.0 V; IOH = −2 mA;
2.4
CL = 10 pF
I2C-bus (fast-mode, 5 V tolerant; SCL and SDA)
fSCL
Cb
SCL clock frequency
-
-
-
-
400
400
kHz
pF
capacitive load for each bus line
1
[1] 6σ = 6 × 0,02UI ×
Where UI = Unit Interval
----
f
s
SOG/Y
t
f
90%
10%
t
r
mgw806
Fig 9. Horizontal sync pulse on SOG/Y
VCLK
50 %
t
su(Q)
2.4 V
VPA[11:0]
VPB[11:0]
VPC[11:0]
0.4 V
001aaf542
t
h(Q)
Fig 10. Output timing
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
44 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Table 59. Output formats (register OUTPUT_CTRL = EAh)[1]
Signal
RGB
YUV
YUV 4 : 2 : 2
(semi-planar)
YUV 4 : 2 : 2 (ITU-R BT.656)
VPA0
VPA1
VPA2
VPA3
VPA4
VPA5
VPA6
VPA7
VPB0
VPB1
VPB2
VPB3
VPB4
VPB5
VPB6
VPB7
VPC0
VPC1
VPC2
VPC3
VPC4
VPC5
VPC6
VPC7
R0
R1
R2
R3
R4
R5
R6
R7
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
V0
V1
V2
V3
V4
V5
V6
V7
U0
U1
U2
U3
U4
U5
U6
U7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U0
V0
U0
U1
U2
U3
U4
U5
U6
U7
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Y00
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
V0
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
U1
V1
V1
U2
V2
V2
U3
V3
V3
U4
V4
V4
U5
V5
V5
U6
V6
V6
U7
V7
V7
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Y00
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
Z/L
[1] Z: high-impedance; L: LOW level.
VPA0 to VPA7
VPB0 to VPB7
VPC0 to VPC7
VCLK
R0
B0
G0
R1
B1
G1
R2
B2
G2
R3
B3
G3
R4
Rn − 1
Bn − 1
Gn − 1
Rn
Bn
Gn
B4
G4
001aag615
Fig 11. RGB 4 : 4 : 4 format data timing
TDA9955HL_1
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Product data sheet
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TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
VPA0 to VPA7
VPB0 to VPB7
VPC0 to VPC7
VCLK
V0
U0
Y0
V1
U1
Y1
V2
U2
Y2
V3
U3
Y3
V4
U4
Y4
Vn − 1
Un − 1
Yn − 1
Vn
Un
Yn
001aag616
Fig 12. YUV 4 : 4 : 4 format data timing
VPA0 to VPA7
VPB0 to VPB7
VPC0 to VPC7
U0
Y0
V0
Y1
U2
Y2
V2
Y3
U4
Y4
U2n
Y2n
V2n
+
Y2n
1
VCLK
HREF
start of
active line
end of
active line
001aag617
Fig 13. YUV 4 : 2 : 2 semi-planar format data timing
V
I
PL, MR, Dn
input
V
M
GND
t
t
PLH
PHL
V
OH
TCU, TCD
output
V
M
V
OL
001aag418
(1) With SAV/EAV timing codes
(2) Without SAV/EAV timing codes
Fig 14. YUV 4 : 2 : 2 ITU-R BT.656 format data timing with blanking code
TDA9955HL_1
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Product data sheet
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46 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Y
621
622
623
624
625
1
2
3
4
5
6
23
24
25
HREF
VREF
V = 0
V = 1
V = 0
FREF
1st field
F = 0
2nd field
F = 1
Y
310
311
312
313
314
315
316
317
318
319
335
336
HREF
VREF
FREF
V = 1
2nd field
F = 1
mgw813
Fig 15. 576i timing in automatic mode
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
47 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
Y
HREF
VREF
521
522
523
524
525
1
2
3
4
5
17
18
V = 1
FREF
1st field
F = 0
Y
258
259
260
261
262
263
264
265
266
267
268
279
280
281
HREF
VREF
V = 0
V = 1
V = 0
FREF
2nd field
F = 1
1st field
F = 0
001aah018
Fig 16. 480i timing in automatic mode
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
48 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
13. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 14.1 14.1
0.17 0.09 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-01
03-02-20
SOT407-1
136E20
MS-026
Fig 17. Package outline SOT407-1 (LQFP100)
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
49 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
14. Soldering
An in-depth account of reflow soldering can be found in Application Note AN10365
“Surface mount reflow soldering description”.
15. Revision history
Table 60. Revision history
Document ID
Release date
20080317
Data sheet status
Change notice
Supersedes
TDA9955HL_1
Product data sheet
-
-
TDA9955HL_1
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Product data sheet
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50 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
16.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9955HL_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 17 March 2008
51 of 52
TDA9955HL
NXP Semiconductors
Triple 8-bit analog-to-digital video converter for HDTV
18. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
9.2.11
9.2.12
9.2.13
9.2.14
9.2.15
9.2.16
9.2.17
9.2.18
9.2.19
9.2.20
Line and pixel counters . . . . . . . . . . . . . . . . . 26
Prefiltering register (PRE_FILTERS) . . . . . . . 34
Range control registers . . . . . . . . . . . . . . . . . 34
Output formatter register . . . . . . . . . . . . . . . . 35
Sync output selection registers . . . . . . . . . . . 36
Output polarity control register. . . . . . . . . . . . 36
Video ports control register . . . . . . . . . . . . . . 37
Data enable signal control register. . . . . . . . . 37
Software reset registers . . . . . . . . . . . . . . . . . 38
Power-down control registers. . . . . . . . . . . . . 39
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
10
11
12
13
14
15
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal characteristics . . . . . . . . . . . . . . . . . 41
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 49
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
Functional description . . . . . . . . . . . . . . . . . . . 7
Analog multiplexers. . . . . . . . . . . . . . . . . . . . . . 7
R/PR, B/PB and G/Y channels. . . . . . . . . . . . . . 7
Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic Gain Control (AGC) . . . . . . . . . . . . . 7
Sync slicing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Activity detection. . . . . . . . . . . . . . . . . . . . . . . . 8
Sync detection and selection . . . . . . . . . . . . . . 8
Sync Detection Recognition and Separation . . 8
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . 8
Sync multiplexers . . . . . . . . . . . . . . . . . . . . . . . 8
Color conversion. . . . . . . . . . . . . . . . . . . . . . . . 9
4 : 2 : 2 downsample filters. . . . . . . . . . . . . . . . 9
Range control . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 : 2 : 2 formatter . . . . . . . . . . . . . . . . . . . . . . . 9
Video port selection . . . . . . . . . . . . . . . . . . . . 10
Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . 10
VHREF timing generator. . . . . . . . . . . . . . . . . 10
I2C-bus serial interface . . . . . . . . . . . . . . . . . . 10
Power management . . . . . . . . . . . . . . . . . . . . 10
Sync timing measurement . . . . . . . . . . . . . . . 10
16
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
16.1
16.2
16.3
16.4
17
18
Contact information . . . . . . . . . . . . . . . . . . . . 51
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9
9.1
9.2
9.2.1
9.2.2
9.2.3
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 10
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 10
Registers definitions . . . . . . . . . . . . . . . . . . . . 11
Version register. . . . . . . . . . . . . . . . . . . . . . . . 17
Input selection register . . . . . . . . . . . . . . . . . . 17
Sync detection recognition and separation
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL registers. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pixel clocks generation registers . . . . . . . . . . 19
Pixel clocks generation registers . . . . . . . . . . 21
Clamp levels registers. . . . . . . . . . . . . . . . . . . 22
Video gain registers (GAIN_RV, GAIN_BU,
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
GAIN_GY). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sync timing measurement registers . . . . . . . . 23
Color space conversion registers . . . . . . . . . . 24
9.2.9
9.2.10
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 March 2008
Document identifier: TDA9955HL_1
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