TEA0675 [NXP]
Dual Dolby* B-type noise reduction circuit for playback applications; 双杜比*播放应用B型降噪电路
| 型号： | TEA0675 |
| 厂家： | 
NXP |
| 描述： | Dual Dolby* B-type noise reduction circuit for playback applications |
| 文件： | 总32页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA0675
Dual Dolby* B-type noise reduction
circuit for playback applications
1996 Jun 07
Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
This device also detects pauses of music in the Automatic
Music Search (AMS) scan mode, for applications with an
intelligent controlled tape driver, or AMS-latch mode, for
applications with a simple controlled tape driver. For both
modes, the delay time can be fixed externally by a resistor.
The device operates with power supplies in the range of
7.6 to 12 V, output overload level increasing with increase
in supply voltage.
FEATURES
• Dual noise reduction (NR) channels
• Head pre-amplifiers
• Reverse head switching
• Automatic Music Search (AMS)
• Music scan
Current drain varies with the following variables:
• Equalization with electronically switched time constants
• Dolby reference level = 387.5 mV
• 24 pins
supply voltage
noise reduction on/off
AMS on/off.
• Improved EMC behaviour.
Because of this current drain variation it is advisable to use
a regulated power supply or a supply with a long time
constant.
GENERAL DESCRIPTION
The TEA0675 is a bipolar integrated circuit that provides
two channels of Dolby B noise reduction for playback
applications in car radios. It includes head and
equalization amplifiers with electronically switchable time
constants. Furthermore it includes electronically
switchable inputs for tape drivers with reverse heads.
QUICK REFERENCE DATA
SYMBOL
VCC
PARAMETER
MIN.
7.6
TYP.
MAX.
12
UNIT
supply voltage
supply current
−
V
ICC
−
26
84
31
mA
dB
signal plus noise-to-noise ratio
78
−
S + N
--------------
N
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SOT234-1
SOT137-1
TEA0675
SDIP24
SO24
plastic shrink dual in-line package; 24 leads (400 mil)
TEA0675T
plastic small outline package; 24 leads; body width 7.5 mm
Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111,
USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby
Laboratories Licensing Corporation.
1996 Jun 07
2
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
BLOCK DIAGRAM
EM6D21
1996 Jun 07
3
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
PINNING
SYMBOL PIN
DESCRIPTION
output channel A
OUTA
INTA
CONTRA
HPA
1
2
3
4
5
6
7
8
9
integrating filter channel A
control voltage channel A
high-pass filter channel A
side chain channel A
handbook, halfpage
SCA
OUTA
INTA
OUTB
24
1
2
TD
delay time constant
INTB
23
22
21
20
EQA
EQFA
VCC
equalizing output channel A
equalizing input channel A
supply voltage
CONTRA
HPA
3
CONTRB
HPB
4
SCA
SCB
5
INA1
Vref
10 input channel A1 (forward or reverse)
11 reference voltage
TD
6
19 AMSEQ
EQB
TEA0675
INA2
INB2
HS
12 input channel A2 (reverse or forward)
13 input channel B2 (reverse or forward)
14 head switch input
EQA
18
17 EQFB
7
EQFA
8
V
GND
INB1
HS
9
16
15
14
13
CC
INB1
GND
EQFB
EQB
AMSEQ
SCB
15 input channel B1 (forward or reverse)
16 ground
INA1
10
11
V
ref
17 equalizing input channel B
18 equalizing output channel B
19 AMS output and EQ switch input
20 side chain channel B
INA2 12
INB2
MED622
HPB
21 high-pass filter channel B
CONTRB 22 control voltage channel B
INTB
23 integrating filter channel B
24 output channel B
Fig.2 Pin configuration.
OUTB
1996 Jun 07
4
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Equalization time constant switching (70 µs or 120 µs)
is achieved when pin AMSEQ is connected to GND via an
18 kΩ resistor (120 µs), or left open-circuit (70 µs).
This does not affect the AMS output signal during AMS
mode (see Fig.1).
FUNCTIONAL DESCRIPTION
Noise Reduction (NR) is enabled when pin HPB is
open-circuit and disabled when connected to GND via an
1.5 kΩ resistor.
Dolby B noise reduction only operates correctly if 0 dB
Dolby level is adjusted at 387.5 mV.
Head switching is achieved when pin HS is connected
(input IN2 active) to GND via a 27 kΩ resistor, or left
open-circuit (input IN1 active). The 10 µF capacitor at pin
HS sets the time constants for smooth switching.
Automatic Music Search (AMS) scan mode is enabled
when pin HPA is connected to VCC via an 1.5 kΩ resistor
and disabled when pin HPA is open-circuit. Switching AMS
on, internally NR is switched OFF simultaneously
In AMS mode the signals of both channels are rectified and
then added. This means, even if one channel signal
appears inverted to the other channel, the normal AMS
function is ensured. Pins HPB and HPA perform the
function of a logic input for AMS, respectively NR mode
switching in both channels and provide the frequency
dependent feedback of the control chain amplifier in the
corresponding channel. Thus it is important that no voltage
is applied to pins HPB and HPA during NR on/AMS off
mode, otherwise this will cause irregular NR
(see Figs 5 and 6 for principle timing in AMS-scan mode).
AMS-latch mode is enabled when pin HPA is connected
to GND via an 1.5 kΩ resistor and disabled when pin HPA
is open-circuit. Switching AMS on, NR is switched off
internally. In this mode the device detects a pause level
signal, when a music level signal has appeared first
(see Figs 7 and 8 for principle timing). Furthermore a
longer rise time constant is supplied for suppressing the
detection of plops on tape. The output signal at pin
AMSEQ in this mode may be applied to drive a tape driver
logic circuit.
characteristics.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
PARAMETER
CONDITIONS
MIN.
MAX.
14
UNIT
supply voltage
0
V
V
s
Vi
input voltage (except pin 11)
−0.3
−
+VCC
5
tshort
Tstg
pin 11 (Vref) to VCC short-circuiting duration
storage temperature
−55
−40
−2
+150
+85
+2
°C
°C
kV
V
Tamb
Ves
operating ambient temperature
electrostatic handling voltage for all pins
note 1
note 2
−500
+500
Notes
1. Human body model (1.5 kΩ, 100 pF).
2. Machine model (0 Ω, 200 pF).
1996 Jun 07
5
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
CHARACTERISTICS
VCC = 10 V; f = 20 Hz to 20 kHz; Tamb = 25 °C; all levels are referenced to 387.5 mV (RMS) (0 dB) at test point (TP)
pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 µs position; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
VCC supply voltage
UNIT
V
7.6
10
26
−
12
31
ICC
supply current
−
mA
dB
%
αm
channel matching
f = 1 kHz; Vo = 0 dB; NR off −0.5
+0.5
0.15
0.3
−
THD
total harmonic distortion
(2nd and 3rd harmonic)
f = 1 kHz; Vo = 0 dB
−
0.08
0.15
−
f = 10 kHz; Vo = 10 dB
−
%
HR
headroom at output
VCC = 7.6 V; THD = 1%;
f = 1 kHz
12
dB
signal plus noise-to-noise internal gain 40 dB, linear;
78
52
84
57
−
−
dB
dB
S + N
--------------
N
ratio
CCIR/ARM weighted;
decode mode; see Fig.25
PSRR
fo
power supply ripple
rejection
Vi(rms) = 0.25 V; f = 1 kHz;
see Fig.22
frequency response;
referenced to TP
encode mode; see Fig.25
Vo = −25 dB; f = 0.2 kHz −22.9
−24.4
0
−25.9
+1.5
−20.8
−21.1
−27.4
−
dB
dB
dB
dB
dB
dB
Vo = 0 dB; f = 1 kHz
−1.5
−17.8
−18.1
−24.4
57
Vo = −25 dB; f = 1 kHz
Vo = −25 dB; f = 5 kHz
Vo = −35 dB; f = 10 kHz
−19.3
−19.6
−25.9
63
αcs
αcc
RL
channel separation
Vo = 10 dB; f = 1 kHz;
see Fig.23
crosstalk between active f = 1 kHz; Vo = 10 dB;
and inactive input NR off; see Fig.23
70
10
29
77
−
−
dB
kΩ
dB
load resistance at output AC-coupled; f = 1 kHz;
Vo = 12 dB; THD = 1%
−
Gv
voltage gain of
pre-amplifier
from pin INA1 or INA2 to
pin EQFA and from
pin INB1 or
30
31
INB2 to pin EQFB;
f = 1 kHz
VI(offset)(DC) DC input offset voltage
−
2
−
mV
µA
kΩ
kΩ
Ii(bias)
REQ
Ri
input bias current
−
0.1
5.8
100
0.4
6.9
−
equalization resistor
4.7
60
input resistance head
inputs
Av
open-loop amplification
pin INA1 or
INA2 to pin EQA and
pin INB1 or INB2 to
pin EQB
f = 10 kHz
f = 400 Hz
80
86
−
−
dB
dB
104
110
1996 Jun 07
6
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.15
TYP.
MAX.
+0.15
UNIT
Vref − VOUT DC output offset voltage
NR off; pins INA1, INA2,
−
V
at pins OUTA and OUTB INB1 and INB2 connected
to Vref
IO
DC output current
pin OUTA to ground
pin OUTB to VCC
−2
0.3
−
−
−
mA
mA
Ω
−
−
Zo
output impedance
80
100
1.4
Vno(rms)
equivalent input noise
voltage (RMS value)
NR off; unweighted;
f = 20 Hz to 20 kHz;
Rsource = 0 Ω
−
0.7
µV
VTD
AMS timing (DC level)
resistor Rt connected to
pin TD
VCC − 3
−
VCC
V
EMC
DC offset voltage at
pins OUTA and OUTB
f = 900 MHz; Vi(rms)= 6 V;
see Figs 26, 27 and 28
−
40
−
mV
Switching thresholds
VNROFF voltage at HPB (pin 21)
INROFF
NR off
NR off
NR on
0.19VCC
0.23VCC 0.25VCC
V
output current
input current
−
−
−
−0.7
open
−
−1
mA
nA
V
INRON
200
VHPB(max)
maximum voltage
0.75VCC
HPA (PIN 4)
VAMSlON
IAMSlON
pin voltage
AMS-latch on
AMS-scan on
AMS off
0.19VCC
0.23VCC 0.25VCC
−0.7 −1
0.77VCC 0.81VCC
V
output current
pin voltage
−
mA
V
VAMSsON
IAMSsON
IAMSOFF
VHPA(max)
0.75VCC
input current
pin current
−
−
−
0.8
open
−
1
mA
nA
V
200
maximum voltage
0.75VCC
AMSEQ (PIN 19)
AMS output (AMS mode)
VOH
IOH1
IOH2
td
HIGH level output voltage
HIGH level output current note 1
HIGH level output current note 1
4
4.6
5
V
+10
+0.01
−
−
−150
−1
−
µA
mA
ms
−
minimum pulse width;
delay time range
see Table 1
23 to 160
VOL
IOL
tr
LOW level output voltage
−
0.1
−
0.7
+1
V
LOW level output current
−0.02
2
mA
ms
ms
dB
minimum pulse width rise AMS-scan mode
time
6
10
AMS-latch mode
130
−25
150
−22
170
−19
AM/P
signal level at output for
AMS switching
AMS mode; f = 10 kHz;
note 2; see Fig.24
music to pause
1996 Jun 07
7
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
−21
MAX.
−18
UNIT
AP/M
signal level at output for
AMS switching
AMS mode; f = 10 kHz;
−24
dB
pause to music
EQ switch input (not AMS mode)
IEQ70
IEQ120
IEQth
input current
time constant 70 µs active
−150
−
−
µA
µA
µA
input voltage
time constant 120 µs active −1000
−
−250
threshold current
note 1
−
−200
−
HEAD SWITCHING
VHSW
IHSW
pin voltage
input current
load current +90 to −90 µA
−
0.8VCC
−
V
VHSW = 0 to VCC
−170
1⁄2VCC + 0.5
−
−
+170
VCC
µA
V
VHSW(HIGH) HIGH level pin voltage
inputs INA1 and INB1
active; note 3
VHSW(LOW) LOW level pin voltage
inputs INA2 and INB2
active
0
−
1⁄2VCC − 0.5
V
Notes
1. In AMS off mode, pin AMSEQ is HIGH level, the equalization time constant will be switched by pulling approximately
200 µA out of pin AMSEQ. This means for the device connected to pin AMSEQ, a restriction of input current at HIGH
level less than 200 µA during AMS off; otherwise the selection of the equalization time constant is disabled and fixed
at 120 µs. If the connected devices consume more than 200 µA, this input has to be disconnected in AMS off mode.
(To ensure switching, the currents for the different switched modes are specified with a tolerance of ±50 µA in
Chapter “Characteristics”.) For an application with a fixed EQ time constant of 120 µs the equalizing network may be
applied completely external. Change 8.2 kΩ resistor to 14 kΩ the internal resistor REQ = 5.8 kΩ is short-circuited by
fixing the EQ switch input at the 70 µs position (IEQ70).
2. The high speed of the tape (FF, REW) at the tape head during AMS mode causes a transformation of level and
frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for
recorded frequencies from 500 Hz up to 4 kHz. So the threshold level of −22 dB corresponds to signal levels in Play
Back (PB) mode of approximately −32 dB. The AMS inputs for each channel are pin SCA and pin SCB. As the
frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF, REW,
the high-pass filter (4.7 nF/24 kΩ) removes the effect of offset voltages but does not affect the music search function.
In the application circuit (Fig.1) the frequency response of the system between tape heads input, e.g. pins INA2 and
INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see Fig.3).
3. To activate the inputs IN1, pin HS might be left open-circuit. In this event the DC level at pin HS is 0.775VCC
.
1996 Jun 07
8
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Table 1 Blank delay time set by resistor Rt at pin TD
RESISTOR VALUE Rt
DELAY TIME td
TYP. (ms)
TOLERANCE
(%)
(kΩ)
68
150
180
220
270
330
470
560
680
820
1000
23
42
20
15
15
15
10
10
10
10
10
10
10
48
56
65
76
98
112
126
142
160
General note
It is recommended to switch off VCC with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact
between tape and tape head while switching off.
MED623
−20
(1)
(dB)
−30
(2)
−40
−50
−60
2
3
4
5
10
10
10
10
(Hz)
(1) AMS threshold level for application circuit (Fig.1).
(2) AMS threshold level for test circuit (Fig.24).
Fig.3 AMS threshold level.
1996 Jun 07
9
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
respectively discharged. If the pause level of the input
signal remains for a certain time, the voltage at the
capacitor reaches a certain value, which corresponds to
an equivalent time value. The voltage at the capacitor will
be compared to a predefined time-equivalent voltage by
the second comparator (F), the time detector. If the pause
level of the input signal remains for this predefined time,
the time detector changes its output level for ‘pause found’
status.
Short description ‘music search’
A system for ‘music search’ mainly consists of a level and
a time detection (see Fig.4). For adapting and decoupling
the input signal will be amplified (A), then rectified (B) and
smoothed with a time constant (C). So the voltage at (C)
corresponds to the signal level and will be compared to the
predefined pause level at the first comparator (D), the level
detector. If the signal level becomes smaller than the
pause level, the level detector changes its output signal.
Due to the output level of the level detector the capacitor
of the second time constant (E) will be charged,
(A)
(B)
(C)
(D)
(E)
(F)
COMPARATOR 1
COMPARATOR 2
V
V
t
I
t
t
INPUT
OUTPUT
1
2
AMPLIFIER
RECTIFIER
LEVEL DETECTOR
TIME DETECTOR
MED624
Fig.4 Integrated ‘music search’ function.
1996 Jun 07
10
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5)
t : rise time
t
t <t
r
AMS on
b
r
r
t
t <t
p d
t : delay time
d
d
t : burst time
b
t
f
t : pause time
p
V
in
t : fall time
f
t
V
l
V : voltage at
l
level detector
level threshold
input
pin 3 (CONTRA)
V
REF
t
V
t
upper threshold
(hysteresis)
V : voltage at
t
time detector
input
pin 22 (CONTRB)
time threshold
t
V
AMSEQ
4.5 V
output signal
to microprocessor
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15
0
3
4
5
6
7
8
9
10
11 12
13 14
MED625
Fig.5 AMS-scan mode without initial input signal.
By activating AMS-scan mode, the AMS output level
directly indicates whether the input level corresponds to a
pause level (VAMSEQ = LOW) or not (VAMSEQ = HIGH).
At t0 the AMS-scan mode is activated. Without a signal at
Vin, the following initial procedure runs until the AMS
output changes to LOW level: due to no signal at Vin the
voltage at the level detector input VI (pin 3, CONTRA)
remains below the level threshold and the second time
constant will be discharged (time detector input Vt).
When Vt passes the time threshold level, the time detector
output changes to LOW level. Now the initial procedure is
completed.
threshold level after the rise time tr (at t4), the AMS output
changes to HIGH. If the signal burst ends at t5 the level
detector input VI falls to its LOW level. When passing the
level threshold at t6, the discharging of the second time
constant begins. Now the circuit measures the delay time
td, which is externally fixed by a resistor and defines the
length of a pause to be detected. If no signal appears at Vin
within the time interval td, the time detector output switches
the AMS output to LOW level at t7.
If a plop noise pulse appears at Vin (t8) with a pulse width
less than the rise time tr > tb, the plop noise will not be
detected as music. The AMS output remains LOW.
If a signal burst appears at t3, the level detector input
voltage rises immediately and causes its output to charge
the second time constant, which supplies the input voltage
Vt for the time detector. When Vt passes the upper
Similarly the system handles ‘no music pulses’ tp: when
music appears at t11 with a small interruption at t13, this
interruption will not affect the AMS output for tp < td.
1996 Jun 07
11
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6)
t : rise time
AMS on
r
t
d
t : delay time
d
t <t
b
r
t : burst time
b
t <t
t
p
r
f
V
t : pause time
p
in
t : fall time
f
t
V
l
V : voltage at
l
level detector
level threshold
input
pin 3 (CONTRA)
V
REF
t
V : voltage at
t
V
t
time detector
input
upper threshold
(hysteresis)
pin 22 (CONTRB)
time threshold
t
V
AMSEQ
4.5 V
output signal
to microprocessor
t
t
t
t
t
t
t
15
t
t
t
t
t
t t
13 14
0
1
5
6
7
8
9
10
11 12
MED626
Fig.6 AMS-scan mode with initial input signal.
At t0 the AMS-scan mode is activated. With an input signal
at Vin, the following initial procedure runs until the circuit
gets a steady state status.
to its maximum voltage level at t1. Now the initial
procedure is completed.
The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-scan mode without initial input signal
(see Fig.5)”.
Due to the signal at Vin the voltage at the level detector
input VI (pin 3, CONTRA) slides to a value which is defined
by a limiter. This voltage causes the level detector output
charging the second time constant (time detector input Vt)
1996 Jun 07
12
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7)
t : rise time
t
t <t
r
AMS on
b
r
r
t
t <t
p d
t : delay time
d
d
t : burst time
b
t
f
t : pause time
p
V
in
t : fall time
f
t
V
l
V : voltage at
l
level detector
level threshold
input
pin 3 (CONTRA)
V
REF
t
V
t
upper threshold
(hysteresis)
V : voltage at
t
time detector
input
pin 22 (CONTRB)
time threshold
t
H
internal
latch status
L
t
V
AMSEQ
4.5 V
output signal
to power FET
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15
0
3
4
5
6
7
8
9
10
11 12
13 14
MED627
Fig.7 AMS-latch mode without initial input signal.
This is similar to the description of the principle timing
diagram from AMS-scan mode. It only differs in its initial
behaviour and its rise time tr. (Please notice that the
different tr does not occur in the principle timing diagrams
for latch and scan mode).
A latch forces the AMS output to be HIGH until a signal
appears at Vin (t4). After t4 the latch will not affect the
output any more until AMS-latch mode is started again.
The existence of the latch appears necessary if the AMS
output for example drives a stop solenoid via a power FET.
The LOW output level will cause a drive of the stop
solenoid. This would happen after a maximum time of td
occurred without any input signal. If there is no music on
tape for a long time (e.g. at tape end), the AMS mode
would be activated repeatedly as long as there is no signal
at Vin. Thus the circuit waits until first music appears before
detecting the pauses.
Running in AMS-latch mode, the circuit may be simply
applied to drive a stop solenoid via a power FET. So the
AMS output signal has not to be processed by a controller.
Because there is no processor to make a decision whether
there is a plop noise or not, for this mode the rise time tr is
extended to approximately 150 ms.
By activating AMS-latch mode the AMS output will not
change to LOW level at t2 if there is no initial signal at Vin.
1996 Jun 07
13
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8)
t : rise time
AMS on
r
t
t
d
f
t : delay time
d
t <t
b
r
t : burst time
b
t <t
p
d
t : pause time
p
V
in
t : fall time
f
t
V
l
V : voltage at
l
level detector
level threshold
input
pin 3 (CONTRA)
V
REF
t
V : voltage at
t
V
t
time detector
input
upper threshold
(hysteresis)
pin 22 (CONTRB)
time threshold
t
t
H
internal
latch status
L
V
AMSEQ
4.5 V
output signal
to power FET
t
t
t
t
t
t
t
15
t
t
t
t
t
t t
13 14
0
1
5
6
7
8
9
10
11 12
MED628
Fig.8 AMS-latch mode with initial input signal.
This is similar to the description in Section “Description of
the principle timing diagram for AMS-scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time tr and
a release of its internal latch when voltage Vt passes the
upper threshold between t0 and t1. Now the initial
procedure is completed.
The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-latch mode without initial input signal
(see Fig.7)”.
1996 Jun 07
14
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
2
V
±0.23 V
ref
+
handbook, halfpage
1
+
5 V
65 Ω
65 Ω
MBH506
MBH507
Fig.9 Pins 1 and 24: output channel.
Fig.10 Pins 2 and 23: integrating filter.
handbook, halfpage
3
+
5 V
1.2 kΩ
3.4 kΩ
3.6 kΩ
handbook, halfpage
4
+
+
5 V
+
675 Ω
10 kΩ
MBH509
MBH508
Fig.11 Pins 3 and 22: control voltage.
Fig.12 Pins 4 and 21: high-pass filter.
1996 Jun 07
15
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
handbook, halfpage
5
handbook, halfpage
6
5 V
+
8 V
+
1 KΩ
MBH511
MBD510
Fig.13 Pins 5 and 20: side chain.
Fig.14 Pin 6: delay time constant.
handbook, halfpage
7
+
5 V
handbook, halfpage
8
+
5 V
10 kΩ
100 Ω
5.8 kΩ
1 pF
MBH513
MBH512
Fig.15 Pins 7 and 18: equalizing output.
Fig.16 Pins 8 and 17: equalizing input.
1996 Jun 07
16
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
handbook, halfpage
10
5 V
+
handbook, halfpage
9
10 V
220 Ω
12 pF
100 kΩ
5 V
MBH514
MBH515
Fig.17 Pin 9: supply voltage.
Fig.18 Pins 10, 12, 13 and 15: input channel.
handbook, halfpage
14
+
handbook, halfpage
8 V
+
2.5 kΩ
2.5 kΩ
5 V
11
MBH516
MBH517
Fig.19 Pin 11: reference voltage.
Fig.20 Pin 14: head switch input.
1996 Jun 07
17
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
+
handbook, halfpage
19
4.6 V
MBH518
Fig.21 Pin 19: AMS output and EQ switch input.
1996 Jun 07
18
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
TEST AND APPLICATION INFORMATION
EM6D29
1996 Jun 07
19
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
EM6D30
1996 Jun 07
20
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
EM6D31
a
1996 Jun 07
21
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
EM6D32
1996 Jun 07
22
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
BM4H97
a n f u l l p a g e w i d t h
1996 Jun 07
23
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
LAYOUT OF PRINTED-CIRCUIT BOARD FOR EMC TEST CIRCUIT (FOR TEA0675T)
63
52
10 kΩ
20 kΩ
24 kΩ
15 nF
100 nF
470 pF
200 Ω
200 Ω
470 pF
27 kΩ
180 kΩ
0 Ω
0 Ω
270 kΩ
4.7 nF
100 nF
40 Ω
TEA0675T
100 nF
4.7 nF
270 kΩ
10 Ω
0 Ω
0 Ω
R
t
180 kΩ
470 pF
200 Ω
200 Ω
470 pF
100 nF
15 nF
24 kΩ
20 kΩ
10 kΩ
MBH460
Dimensions in mm.
Fig.27 Top side with components.
24
1996 Jun 07
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
o
63
52
10 µF
10 µF
10 µF
S1
330 nF
MP
100 µF
X2
X4
100 µF
X3
MP
X1
MP
HFDR.
330 nF
10 µF
10 µF
MBH459
Dimensions in mm.
Fig.28 Bottom side with components.
25
1996 Jun 07
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
PACKAGE OUTLINES
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
D
M
E
A
2
A
A
L
1
c
(e )
w M
e
Z
1
b
1
M
H
b
24
13
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
1
(1)
(1)
Z
w
UNIT
b
b
c
D
E
e
e
L
M
M
1
1
E
H
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
3.2
2.8
10.7
10.2
12.2
10.5
mm
4.7
0.51
3.8
1.778
10.16
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT234-1
1996 Jun 07
26
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.42
0.39
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-24
SOT137-1
075E05
MS-013AD
1996 Jun 07
27
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
Several techniques exist for reflowing; for example,
SOLDERING
Introduction
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
SDIP
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1996 Jun 07
28
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jun 07
29
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
NOTES
1996 Jun 07
30
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit
for playback applications
TEA0675
NOTES
1996 Jun 07
31
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com/ps/
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
517021/50/04/pp32
Date of release: 1996 Jun 07
Document order number: 9397 750 00898
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