TEA5764HN_技术文档

TEA5764HN

FM radio + RDS

Rev. 02 — 9 August 2005

Product data sheet

1. General description

The TEA5764HN is a single chip electronically tuned FM stereo radio with Radio Data

System (RDS) and Radio Broadcast Data System (RBDS) demodulator and RDS/RBDS

decoder for portable application with fully integrated IF selectivity and demodulation.

The radio is completely adjustment free and only requires a minimum of small and low

cost external components.

The radio can tune to the European, US and Japanese FM bands. It has a low power

consumption and can operate at a low supply voltage.

2. Features

■ High sensitivity due to integrated low noise RF input ampliﬁer

■ FM mixer for conversion of the US/Europe (87.5 MHz to 108 MHz) and Japanese FM

band (76 MHz to 90 MHz) to IF

■ Preset tuning to receive Japanese TV audio up to 108 MHz

■ Auto search tuning, raster 100 kHz

■ RF automatic gain control circuit

■ LC tuner oscillator operating with low cost ﬁxed chip inductors

■ Fully integrated FM IF selectivity

■ Fully integrated FM demodulator;

■ no external discriminator

■ Crystal oscillator at 32768 Hz, or external reference frequency at 32768 Hz

■ PLL synthesizer tuning system

■ IF counter; 7-bit output via the I²C-bus

■ Level detector; 4-bit level information output via the I²C-bus

■ Soft mute: signal dependent mute function

■ Mono/stereo blend: gradual change from mono to stereo, depending on signal

■ Adjustment-free stereo decoder

■ Autonomous search tuning function

■ Standby mode

■ MPX output

■ One software programmable port

■ Fully integrated RDS/RBDS demodulator in accordance with EN50067

■ RDS/RBDS decoder with memory for two RDS data blocks provides block

synchronization and error correction; block data and status information are available

via the I²C-bus

■ Audio pause detector

TEA5764HN

Philips Semiconductors

FM radio + RDS

■ Interrupt ﬂag

3. Applications

■ FM stereo radio

4. Quick reference data

Table 1:

Electrical parameters general

The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 47; All RF input values

are deﬁned in potential difference, except when EMF is explicitly stated.

Symbol

Supplies

V_CCA

Parameter

Conditions

Min

Typ

Max

Unit

analog supply voltage

analog supply current

2.5

2.7

3.3

V

I_CCA

V_CCA= 2.5 V to 3.3 V

operating mode

Standby mode

12

0

13.7

0.1

16

1

mA

µA

V

V_CCD

I_CCD

digital supply voltage

digital supply current

2.5

2.7

3.3

V_CCD= 2.5 V to 3.3 V

operating mode

Standby mode

0.3

1

0.7

15

1.5

mA

22.5

µA

Reference voltage

V_VREFDIG

digital reference voltage

1.65

0

1.8

0.5

V_CCD

1

V

for I²C-bus interface

I_VREFDIG

digital reference supply

current

operating mode;

µA

V_VREFDIG= 1.65 V to V_CCD

General

f_i(FM)

FM input frequency

ambient temperature

76

-

108

+85

MHz

T_amb

−40

°C

FM and RDS overall system parameters

V_sens(EMF)

sensitivity EMF value

voltage

f_RF= 76 MHz to 108 MHz;

∆f = 22.5 kHz; f_mod= 1 kHz;

(S+N)/N = 26 dB; TC_deem= 75 µs;

A-weighting ﬁlter;

-

2.3

3.5

µV

B

_aud= 300 Hz to 15 kHz

∆f₁= 200 kHz; ∆f₂= 400 kHz;

_tune= 76 MHz to 108 MHz;

IP3_in

IP3_out

S

in-band 3rd-order

intercept point

78

87

93

-

dBµV

f

RF_agc= off

out-of-band 3rd-order

intercept point

∆f₁= 4 MHz; ∆f₂= 8 MHz;

f_tune= 76 MHz to 108 MHz;

RF_agc= off

[1]

selectivity

f_tune= 76 MHz to 108 MHz

high-side; ∆f = +200 kHz

low-side; ∆f = −200 kHz

V_RF= 1 mV; L = R; ∆f = 22.5 kHz;

39

32

55

43

36

66

-

dB

mV

-

V_VAFL

left audio output voltage

on pin VAFL

75

f_mod= 1 kHz; no pre-emphasis;

TC_deem= 75 µs

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Philips Semiconductors

FM radio + RDS

Table 1:

Electrical parameters general

The listed parameters are valid when a crystal is used that meets the requirements as stated in Table 47; All RF input values

are deﬁned in potential difference, except when EMF is explicitly stated.

Symbol

Parameter

right audio output voltage V_RF= 1 mV; L = R; ∆f = 22.5 kHz;

on pin VAFR _mod= 1 kHz; no pre-emphasis;

TC_deem= 75 µs

(S+N)/N(m) maximum signal-to-noise V_RF= 1 mV; ∆f = 22.5 kHz; L = R;

Conditions

Min

Typ

Max

Unit

V_VAFR

55

66

75

mV

f

54

50

57

54

-

dB

ratio, mono

f

B

_mod= 1 kHz; de-emphasis = 75 µs;

_AF= 300 Hz to 15 kHz; A-weighting

ﬁlter

(S+N)/N(s) maximum signal-to-noise

ratio, stereo

V_RF= 1 mV; ∆f = 67.5 kHz; L = R;

f_mod= 1 kHz; ∆f_pilot= 6.75 kHz;

de-emphasis = 75 µs; B_AF= 300 Hz

to 15 kHz; A-weighting ﬁlter

α_cs

channel separation

MST = 0; R = 1 and L = 0 or R = 0

and L = 1; V_RF= 30 µV; increasing

RF input level

27

-

33

-

dB

%

THD

total harmonic distortion

V_RF= 1 mV; ∆f = 75 kHz;

0.4

0.9

f_mod= 1 kHz; DTC = 0; B_aud= 300 Hz

to 15 kHz; A-weighting ﬁlter; mono;

L = R; no pilot deviation

V_sens

RDS sensitivity EMF

value

∆f = 22.5 kHz; f_AF= 1 kHz; L = R;

SYM1 = 0 and SYM0 = 0; average

over 2000 blocks; block quality

rate ≥ 95 %; ∆f_RDS= 2 kHz

-

15

26

µV

[1] Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.

5. Ordering information

Table 2:

Ordering information

Type number

Package

Name

Description

Version

TEA5764HN

HVQFN40

plastic thermal enhanced very thin quad ﬂat package; body

SOT618-1

6 × 6 × 0.9 mm

TEA5764HN_2

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Philips Semiconductors

FM radio + RDS

7. Pinning information

7.1 Pinning

terminal 1

index area

1

2

30

29

28

27

26

25

24

23

22

21

LOOPSW

CPOUT

LO1

GNDA

n.c.

3

GNDD

MPXIN

MPXOUT

VAFL

4

LO2

5

CD1

TEA5764HN

6

PILLP

7

SWPORT

BUSENABLE

VREFDIG

SCL

VAFR

8

TMUTE

INTCON1

n.c.

9

10

001aab459

Transparent top view

Fig 2. Pin conﬁguration

7.2 Pin description

Table 3:

Symbol

LOOPSW

CPOUT

LO1

Pin description

1

Description

synthesizer PLL loop ﬁlter switch output

charge pump output of synthesizer PLL

local oscillator coil connection 1

local oscillator coil connection 2

VCO supply decoupling capacitor

pilot PLL loop ﬁlter

2

3

LO2

4

CD1

5

PILLP

6

SWPORT

BUSENABLE

VREFDIG

SCL

7

software programmable port output

I²C-bus enable input

digital reference voltage for I²C-bus signals

I²C-bus clock line input

I²C-bus data line input and output

not connected

8

9

10

11

12

13

14

15

SDA

n.c.

GNDD

V_CCD

digital ground

digital supply voltage

internally connected

CD2/INTCON3 16

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FM radio + RDS

Table 3:

Symbol

n.c.

Pin description …continued

17

18

19

20

21

22

23

24

25

26

27

28

Description

not connected

INTCON2

GNDD

INTX

internally connected; leave open

digital ground

interrupt ﬂag output

not connected

n.c.

INTCON1

TMUTE

VAFR

internally connected; leave open

soft mute time-constant capacitor

right audio output

VAFL

left audio output

MPXOUT

MPXIN

GNDD

FM demodulator MPX output

MPX decoder and RDS decoder MPX input

digital ground; this pin has an internal pull-down resistor of 10 kΩ to

ground

n.c.

29

30

31

32

33

34

35

36

37

38

39

40

not connected

GNDA

n.c.

analog ground

not connected

FREQIN

XTAL

V_CCA

32.768 kHz reference frequency input

crystal oscillator input

analog supply voltage

V_CCAdecoupling capacitor

RF input 1

CD3

RFIN1

RFIN2

GNDRF

CAGC

n.c.

RF input 2

RF ground

RF AGC time-constant capacitor

not connected

8. Functional description

8.1 Low noise RF ampliﬁer

The LNA input impedance together with the LC RF input circuit deﬁnes an FM band ﬁlter.

The gain of the LNA is controlled by the RF AGC circuit.

8.2 FM I/Q mixer

FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to IF.

8.3 VCO

The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM

quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.

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FM radio + RDS

8.4 Crystal oscillator

The crystal oscillator can operate with a 32.768 kHz clock crystal. The oscillator can be

overridden via the FREFIN pin. When the FREFIN pin is used the oscillator is clocked

externally by a 32.768 kHz signal. Selection between a reference clock or a reference

crystal can be done via the I²C-bus. When a crystal is connected the FREFIN pin must be

left open-circuit, and when pin FREFIN is used a crystal may not be connected. It is not

possible to connect a crystal and apply a frequency via the FREFIN pin in the same

application.

The crystal oscillator generates the reference frequency for the following:

• Reference frequency divider for synthesizer PLL

• Timing for the IF counter

• Timing for the pause detector

• Free running frequency adjustment of the stereo decoder VCO

• Centre frequency for adjustment of the IF ﬁlters

• Clock frequency of the RDS/RBDS decoder

8.5 PLL tuning system

The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz reference

frequency generated by the crystal oscillator or a reference clock of 32.768 kHz fed into

the TEA5764HN. To tune the radio to the required frequency requires the PLL word to be

calculated and then programmed to the register. The PLL word is 14 bits long; see

Table 20 and Table 21. Calculation of this 14-bit word can be done as follows.

Formula for high-side injection:

4 × ( f _RF+ f _IF

)

N_DEC

=

(1)

(2)

--------------------------------------

f _ref

Formula for low-side injection:

4 × ( f _RF– f _IF

)

N_DEC

=

-------------------------------------

f _ref

where:

N_DEC= decimal value of PLL word

f_RF= wanted tuning frequency (Hz)

f_IF= intermediate frequency of 225 kHz

f_ref= the reference frequency of 32.768 kHz

Example for receiving a channel at 100.1 MHz:

4 × (100.1 × 10⁶+ 225 × 10³)

N_DEC

=

= 12246.704

(3)

------------------------------------------------------------------------

32768

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TEA5764HN

Philips Semiconductors

FM radio + RDS

The result found using Equation 1 or Equation 2 must always be rounded to the lowest

integer value. If rounded down to the lowest integer value of N_DEC= 12246, the PLL word

becomes 2FD6h.

This value can be written to register FRQSETLSB or FRQSETMSB via the I²C-bus and

the IC will then either start an autonomous search at this frequency or go to a preset

channel at this frequency. When the application is built according to the block diagram

shown in Figure 1, and with the preferred components, the PLL will settle to the new

frequency within 5 ms. The most accurate tuning is accomplished when a search is

followed by a preset to the same frequency.

The PLL is triggered by writing to any one of the bytes FRQSETMSB, FRQSETLSB,

TNCTRL1, TNCTRL2, TESTBITS, TESTMODE.

Accurate validation of the PLL locking on the new frequency can take 2 ms to 10 ms.

When a lock is detected, bit LD is set.

8.6 Band limits

The TEA5764HN can be switched either to the Japanese FM-band or to the US/Europe

FM-band. Setting bit BLIM to logic 0 the band range is 87.5 MHz to 108 MHz; setting bit

BLIM to logic 1 selects the Japanese band range of 76 MHz to 90 MHz.

8.7 RF AGC

The RF AGC (or wideband AGC) prevents overloading and limits the amount of

intermodulation products created by strong adjacent channels. The RF AGC is on by

default and can be turned off via the I²C-bus.

The TEA5764HN also has an in-band AGC to prevent overloading by the wanted channel.

The in-band AGC is always turned on.

8.8 Local or long distance receive

If bit LDX = 1, the LNA gain is reduced by 6 dB to prevent distortion when a transmitter is

very near. If bit LDX = 0, the LNA gain is normal to receive long distance (DX) stations.

8.9 IF ﬁlter

A fully integrated IF ﬁlter is built-in.

8.10 FM demodulator

The FM quadrature demodulator has an integrated resonator to perform the phase shift of

the IF signal.

8.11 IF counter

The received signal is mixed to produce an IF of 225 kHz. The result of the mixing is

counted. A good IF count result indicates that the radio is tuned to a valid channel instead

of an image or a channel with much interference. The IF counter outputs a 7-bit count

result via the I²C-bus. The IF counter is continuously active and can be read at any time

via the I²C-bus. It also activates a ﬂag when the IF count result is outside the IF count

valid result window; see Section 9.1.4.4.

TEA5764HN_2

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TEA5764HN

Philips Semiconductors

FM radio + RDS

Before a tuning cycle is initiated the IF count period can be set to 2 ms or to 15.6 ms by

bit IFCTC. When the IF count period is set to 2 ms, initiating the tuning algorithm with a

preset (bit SM = 0) will always give an RDS update as shown in Section 8.22.1. In case

the IF count time is set to 15.6 ms, the tuning ﬂowchart illustrated in Figure 3 is used.

Once tuned, the IF count period is always 15.6 ms.

8.12 Voltage level generator and analog-to-digital converter

The voltage level indicates the ﬁeld strength received by the antenna. The voltage level is

analog-to-digital converted to a 4-bit word and output via the I²C-bus. The ADC level is

continuously active and can be read at any time via the I²C-bus. It also activates a ﬂag

when the voltage level falls below a predeﬁned selectable threshold. Bit LHSW allows

either large or small hysteresis steps to be chosen; see Table 24 and Section 9.1.4.5.

When the ADC level is set to 3, its minimum value, the search algorithm will only stop at

channels having a RF level higher than, or equal to, ADC level 3. After completing the

search algorithm and being tuned to a station, due to hysteresis the effective limit will be

set to 0. This means that the continuous ADC level check will never set the LEVFLAG.

8.13 Mute

8.13.1 Soft mute

The low-pass ﬁltered voltage level drives the soft mute attenuator at low RF input levels:

the audio output is faded and hence also the noise (see Figure note 1 in Figure 15 and

Figure 17).

The soft mute function can also be switched off via the I²C-bus, using bit SMUTE.

8.13.2 Hard mute

The audio outputs VAFL and VAFR can be hard-muted by bit MU in byte TNCTRL2, which

means that they are put into 3-state. This can also be done by setting bits Left Hard Mute

(LHM) or Right Hard Mute (RHM) in byte TESTBITS, which allows either one or both

channels to be muted and forces the TEA5764HN to mono mode. When the TEA5764HN

is in Standby mode the audio outputs are hard-muted.

8.13.3 Audio frequency mute

The audio signal is muted by setting bit AFM of the TNCTRL1 register to logic 1. In the

soft mute attenuator the audio signal is blocked and so pins VAFL and VAFR will be at

their DC biasing point with no signal.

The audio is automatically muted during an RDS update as shown in the ﬂowchart of

Figure 3. When the audio must be muted during Search mode, it is done by setting bit

AFM to logic 1 before the search action and resetting it to logic 0 afterwards.

Setting bit AFM to logic 0 stops the RDS data.

8.14 MPX decoder

The PLL stereo decoder is adjustment free. It can be switched to mono via the I²C-bus.

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TEA5764HN

Philips Semiconductors

FM radio + RDS

8.15 Signal dependent mono/stereo blend (stereo noise cancellation)

If the RF input level decreases, the MPX decoder blends from stereo to mono to limit the

output noise. The continuous mono-to-stereo blend can also be programmed via the

I²C-bus to an RF level dependent switched mono-to-stereo transition. Stereo noise

cancellation can be switched off via the I²C-bus by bit SNC.

8.16 Software programmable port

One software programmable port (CMOS output) can be addressed via the I²C-bus:

Bit SWPM = 1, the software port functions as the output for the FRRFLAG.

Bit SWPM = 0, the software port outputs bit SWP of the registers.

In Test mode the software port outputs signals according to Table 27. Test mode is

selected, setting bit TM of byte TESTMODE to logic 1.

The software port cannot be disabled by the PUPD bits; see Section 8.17.

8.17 Standby mode

The radio can be put into Standby mode by the Power-Up / Power-Down (PUPD) bits. The

RDS part can be turned off separately or both the RDS and the FM part can be turned off.

The TEA5764HN is still accessible via the I²C-bus but takes only a low power from the

supply, in Standby mode, the audio outputs are hard-muted.

8.18 Power-on reset

After startup of V_CCAand V_CCDa power-on reset circuit will generate a reset pulse and the

registers will be set to their default values. The power-on reset is effectively generated by

V_CCD

.

After a power-on reset the TEA5764HN is in Standby mode and the PUPD bits are set to

logic 0. After a power-on reset the registers are reset to their default value, except for

byte12R to byte19R and ﬂags DAVFLG, LSYNCFLG and PDFLAG. To reset these, the

RDS part must be turned on by setting PUPD. After setting PUPD to logic 1, it will take

0.9 ms to start-up the TEA5764HN and set these registers to their default value.

The power supplies can be switched on in any order.

When the supply voltage V_CCAand V_CCDare at 0 V, all I/Os, the audio outputs and the

reference clock input are high-ohmic.

8.19 RDS/RBDS

8.19.1 RDS/RBDS demodulator

A fully integrated RDS/RBDS demodulator which uses the reference frequency

(32.678 Hz) of the PLL synthesizer tuning system. The RDS demodulator recovers and

regenerates the continuously transmitted RDS or RBDS data stream of the multiplex

signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) for further

processing by the integrated RDS decoder.

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TEA5764HN

Philips Semiconductors

FM radio + RDS

8.19.2 RDS data and clock direct

The RDS demodulator retrieves the RDS data and clock signals, this data can be put

directly onto pins VAFL and VAFR by setting bit RDSCDA to logic 1.

8.19.2.1 RDS/RBDS decoder

The RDS decoder provides block synchronization, error correction and ﬂywheel function

for reliable extraction of RDS or RBDS block data. Different modes of operation can be

selected to ﬁt different application requirements. Availability of new data is signalled by bit

DAVFLG and output pin INTX which generates an interrupt. Up to two blocks of data and

status information are available via the I²C-bus in a single transmission.

The behavior of the DAVFLG is described in Section 10.

8.20 Audio pause detector

The audio pause detector monitors the audio modulation for pauses and responds to low

levels. The modulation threshold can be adjusted in 4 steps of 4 dB by control bits PL[1:0].

The minimum time for detecting a pause can be adjusted by control bits PT[1:0] as shown

in Table 38. When a pause occurs, ﬂag PDFLAG is set to logic 1 and a hardware interrupt

is generated; see Section 9.1.4.6.

8.21 Auto search and Preset mode

In Search mode the TEA5764HN can search channels automatically; see Figure 3.

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TEA5764HN

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FM radio + RDS

start

during a preset mute is always active

search mode is default not muted

unless AHLSI is set

reset flags

set PLL frequency

wait for PLL to settle

false

level OK

set LEVFLAG

true

false

IF OK

true

false

AHLSI

true

false

search mode

true

false

search up

true

increment current_pll

by 100 kHz

decrement current_pll

by 100 kHz

false

band limit

true

BLFLAG = 0

FRRFLAG = 1

no mute

BLFLAG = 0

FRRFLAG = 1

mute

BLFLAG = 1

FRRFLAG = 1

no mute

001aab461

Fig 3. Flowchart auto search or preset

Before starting a search or a preset, the INTMSK register must be reset and only the

FRRMSK must be set. This allows the microprocessor to be interrupted only when the

search or preset algorithm is ready.

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8.21.1 Search mode

Search mode is initiated by setting bit SM in byte FRQSETMSB to logic 1. The search

direction is set by bit SUD; SUD = 0 (search down), bit SUD = 1 (search up). The tuner

starts searching at the frequency set in bytes FRQSETLSB and FRQSETMSB. The

Search Stop Level (SSL) bits deﬁne the ﬁeld strength level at which a desired channel is

detected. The tuner will stop on a channel with a ﬁeld strength equal to or higher than this

reference level and then checks the IF frequency; when both are valid, the search stops

(Note that this depends on bit AHLSI described in Figure 3). If the level check or the IF

count fails, the search continues. If no channels are found, the TEA5764HN stops

searching when it has reached the band limit, setting the BLFLAG HIGH. A search always

stops when the FRRFLAG is set and on the occurrence of a hardware interrupt, this

procedure is shown in Figure 3.

The search algorithm can stop at a frequency that is offset from the IF by up to a

maximum of 12 kHz. The maximum offset can be limited to 8 kHz by applying a preset.

For optimum tuning, it is recommended that a preset is applied after a search and when

the found frequency has an offset that is above 8 kHz.

After this interrupt the TEA5764HN will not update the tuner registers for a period of 15

ms. The state of the TEA5764HN can be checked by reading the bytes of INTFLAG,

FRQCHKMSB, FRQCHKLSB, TNCTRL1 and TNCTRL2. Table 4 shows the possible

states of these registers after an auto search.

Table 4:

IFFLAG BLFLAG FRRFLAG Comment

Tuner truth table^[1]

0

if pin INTX has gone LOW and only IFMSK, FRRMSK and

BLMSK were set then this cannot occur

0

1

0

1

channel found during search / preset; FRRMSK set

not a valid state

a valid channel found and the band limit has been reached

during a search; BLMSK or FRRMSK set

1

0

1

not a valid state

a preset or search has occurred but the wanted channel has a

valid RSSI level but fails the IF count when AHLSI was set to

logic 1; HLSI must be toggled and a new PLL value must be

programmed; FRRMSK set

1

0

1

not a valid state

band limit is reached during search; no valid channel found;

BLMSK or FRRMSK set

[1] This table is valid until 30.6 ms after the tuning cycle has completed. It shows the outcome of the ﬂag

register when a read is done after pin INTX goes LOW on condition that no mask bit other than FRRMSK is

set.

8.21.2 Preset mode

A preset occurs by setting bit SM to logic 0 and writing a frequency to byte FRQSETMSB.

The tuner jumps to the selected frequency and sets the FRRFLAG when it is ready.

After this interrupt the TEA5764HN will not update the tuner registers for a period of

15 ms. The state of the TEA5764HN can be checked by reading registers: INTFLAG,

FRQCHKLSB, FRQCHKMSB, TNCTRL1 and TNCTRL2. Table 4 shows the possible

states after a preset.

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TEA5764HN

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FM radio + RDS

8.21.3 Auto high-side and low-side injection stop switch

When a channel is searched or a preset is done, reception can sometimes improve when

injection is done at the other side of the wanted channel.

image on low-side

wanted channel

image on high-side

switch LO from high-side to low-side

001aab460

Fig 4. Switch LO from high-side injection to low-side injection using bit HLSI

The TEA5764HN has bit HLSI which toggles the injection of the local oscillator from

high-side (bit HLSI = 1) to low-side (bit HLSI = 0). When bit HLSI is toggled, a new PLL

setting must be sent to the TEA5764HN.

When bit AHLSI is set to logic 1, the search / preset algorithm will stop after a channel has

a valid RSSI level check but fails the IF count. The microprocessor can now respond by

toggling the HLSI switch and sending a new PLL value to the tuner.

8.21.4 Muting during search or preset

During a preset the tuner is always muted and this is implemented by the algorithm.

A search is not muted by default unless bit AFM = 1 or bit AHLSI = 1.

When bit AHLSI = 1 and the tuner stopped during a preset or a search because of a

wrong IF count, the tuner stays muted; this allows the microprocessor to switch from the

high to low setting quietly and wait for the new result.

The tuner is always muted if bit AFM = 1 and is independent of a search or a preset. A

search can be muted by setting bit AFM to logic 1 before a search is initiated and resetting

it to logic 0 when the tuner is ready (only set bit FRRMSK when initiating a search or

preset).

All these mute actions are done by blocking the audio signal inside the soft mute

attenuator, the audio output will keep its DC level and stay low-ohmic i.e. 50 Ω (a hard

mute set by bit MU will cause a plop).

8.22 RDS update/alternative frequency jump

A channel which transmits RDS data can have alternative channels which have the same

information. These alternative channel frequencies are in the RDS data, so the

microprocessor can read the alternative frequencies and store them in a memory.

The tuner can perform an RDS update. This is very similar to a preset, but with a 2 ms IF

count time. The tuner will jump to the alternative frequency and check the level and the IF

count using a 2 ms count time. When the RSSI level check is above the speciﬁed level and

the IF count result is within the limits, then the tuner will stay at the alternative frequency

and stay muted, the microprocessor can now decide what to do. If the alternative

frequency is not valid it will jump back to the frequency it came from.

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The algorithm will ﬁnish with the FRRFLAG being set and an interrupt is generated. After

this interrupt the TEA5764HN will not measure the IF count for a period of 15 ms. 15 ms

after completing a RDS jump, a measurement of the IF count will start and hence the IF

count result and the IFFLAG will be updated 30.6 ms after completing the algorithm. The

level measurement will start immediately after the tuning algorithm, so the LEVFLAG will

be updated 500 µs after the algorithm. The state of the TEA5764HN can be checked by

reading registers INTFLAG, FRQCHKLSB, FRQCHKMSB, IFCHK and LEVCHK. Table 5

shows the possible states after an auto search, Figure 5 shows how the RDS is updated.

8.22.1 Muting during RDS update

An RDS update (AF jump) is always muted. There are two possibilities for leaving the

algorithm:

• The tuner jumps to an alternative frequency which is not valid (according to the

speciﬁed SSL limit and ﬁxed IF counter limits) and jumps back, then it will

automatically unmute

• Or the tuner jumps to a valid alternative frequency and stays there. Now it does not

unmute. The microprocessor can unmute or it keeps the tuner muted and can check

for the presence of RDS data. The valid way to unmute is to apply a preset to the

current frequency (an IF count time of 15.6 ms is used at preset, which gives a more

accurate IF count result than the result obtained by the AF jump, where 2 ms is used)

Table 5:

IFFLAG BLFLAG FRRFLAG Comment

RDS update truth table^[1]

0

if pin INTX is LOW and only IFMSK, FRRMSK and BLMSK were

set then this cannot occur

0

1

alternative frequency jump successful; radio is tuned to the

alternative frequency and stays muted

0

1

0

1

0

1

not a valid state

AF jump has occurred but the wanted channel fails the IF count;

the PLL will be set back to the old value

1

0

1

not a valid state

if pin INTX is LOW and only IFMSK, FRRMSK and BLMSK were

set then this cannot occur

[1] This table is valid until 30.6 ms after an RDS update has completed. It shows the outcome of the ﬂag

register when a read is done after pin INTX has gone LOW and on condition that only mask bit FRRMSK is

set.

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start

set IF count time

to 2 ms

activate mute

store 'old' PLL setting

clear LEVFLAG

clear IFFLAG

set PLL to AF frequency

wait for PLL to settle

false

level OK

true

wait for IF counter

set LEVFLAG

false

IF OK

true

reset 'old' PLL setting

wait for PLL to settle

FRRFLAG = 1

BLFLAG = 0

FRRFLAG = 1

BLFLAG = 0

keep mute

not mute

(PLL is AF frequency)

(PLL is old frequency)

001aab462

Fig 5. Flowchart RDS update

9. Interrupt handling

9.1 Interrupt register

The ﬁrst two bytes of the I²C-bus register contain the interrupt masks and the interrupt

ﬂags. A ﬂag is set when it is a logic 1.

Table 6:

Bit

INTFLAG - byte0R

7

6

5

4

3

2

1

0

Symbol

DAVFLG

TESTBIT

LSYNCFLG

IFFLAG

LEVFLAG

PDFLAG

FRRFLAG

BLFLAG

Table 7:

Bit

INTMSK - byte0W / byte1R

7

6

5

4

3

2

1

0

Symbol

DAVMSK

-

LSYNCMSK

IFMSK

LEVMSK

PDMSK

FRRMSK

BLMSK

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The interrupt ﬂag register contains the ﬂags set according to the behavior outlined in

Section 9.1.4. When these ﬂags are set they can also cause the INTX to go active

(hardware interrupt line) depending on the status of the corresponding mask bit in Table 7.

A logic 1 in the mask register enables the hardware interrupt for that ﬂag.

Hence, it is conceivable that, with all the mask bits cleared, the software could operate in

a continuous polling mode that reads the interrupt ﬂag register for any bits that maybe set.

Interrupt mask bits are always cleared after reading the ﬁrst two bytes of the interrupt

register. This is to control multiple hardware interrupts (see Figure 6). Bit LSYNCMSK has

a different function and is not cleared after reading the interrupt register bytes; see also

Section 9.1.4.3.

9.1.1 Interrupt clearing

The interrupt ﬂag and mask bits are always cleared after:

• They have been read via the I²C-bus

• A power-on reset

9.1.2 Timing

The timing sequence for the general operation interrupts is shown in Figure 6 and shows

a read access of the interrupt bytes INTFLAG and INTMSK and a subsequent (though not

necessarily immediate) write to the mask register. It also indicates the two key timing

points A and B.

If an interrupt event occurs while the register is being accessed (after point A) it must be

held until after the mask register is cleared at the end of the read operation (point B).

Point A is after the R/W bit has been decoded and point B is where the acknowledge has

been received from the master after the ﬁrst two bytes have been sent.

The LOW time for the INTX line (t_LOW) has a maximum value speciﬁed in Section 15.

However it can be shorter if the read of the INTMSK and INTFLAG bytes occurs within

t_LOW

.

9.1.3 Reset

A reset can be performed at any time by a simple read of the interrupt bytes, byte0R and

byte0W, which automatically clears the interrupt ﬂags and masks.

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9.1.4 Interrupt ﬂags and behavior

9.1.4.1 Multiple interrupt events

If the interrupt mask register bit is set then the setting of an interrupt ﬂag for that bit

causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the

ﬂag is cleared, then this does not trigger any further hardware interrupts until that speciﬁc

ﬂag is cleared. However, two different events can occur in sequence and generate a

sequence of hardware interrupts. A second interrupt can be generated only after the

INTMSK byte is read, followed by a write as the ﬁrst interrupt blocks the input of the INTX

one-shot generator.

If subsequent interrupts occur within the INTX LOW period then these do not cause the

INTX period to extend beyond its speciﬁed maximum period (see Section 9.2).

9.1.4.2 Data available ﬂag

The DAVFLG is set when a new block of data is received according to Figure 9 to

Figure 12, where the different DAV modes are described. Once synchronized, this

continues for all subsequent received blocks (dependent on DAV mode) and in the

following situations:

• During sync search, in any DAV mode: two valid blocks in the correct sequence

received with BBC < BBL (synchronized).

• During synchronization search in DAVB mode if a valid A(C’)-block has been

detected. This mode can be used for fast search tuning (detection and comparison of

the PI code contained in the A or C’ block.

• If the pre-processor is synchronized and in mode DAVA and DAVB a new block has

been processed. This mode is the standard data processing mode if the decoder is

synchronized.

• If the pre-processor is synchronized and in DAVC mode, two new blocks have been

processed.

• If the decoder is synchronized and in any DAV mode, with LSYNCMSK = 0, loss of

synchronization is detected (ﬂywheel loss of synchronization, resulting in a restart of

synchronization search).

The DAVFLG is reset by a read of RDSLBLSB (byte15R) or RDSPBLSB (byte17R). An

interrupt is asserted each time a new block of data is decoded and when bit DAVMSK is

set; see Section 10.

9.1.4.3 RDS synchronization ﬂag

Bit SYNC, Table 29, shows the status of the RDS decoder. If it is a logic 1 then the

decoder is synchronized, if it is a logic 0 it is not.

The action of the TEA5764HN depends on the status of bit LSYNCMSK in Table 7. If this

is set then the loss of synchronization causes bit LSYNCFL to go to logic 1 when

synchronization is lost, and a hardware interrupt is asserted. The RDS part of the

TEA5764HN is set to idle and waits for the microprocessor to initiate a new

synchronization search by setting bit NWSY as described in Table 36.

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If bit LSYNCMSK is 0 and synchronization is lost, the ASIC automatically starts a new

synchronization search. It will not generate a hardware interrupt. The microprocessor can

wait until the RDS decoder is synchronized again, this will be indicated by the DAVFLG

and the SYNC status bit (this requires bit DAVMSK being set).

Bit LSYNCFL is reset by a read of the INTMSK byte1R.

Bit LSYNCMSK is not reset by a read of byte INTMSK, it must be set or reset by the

microprocessor. Resetting it automatically would change the status of the ASIC and cause

an automatic synchronization search as described above.

How the synchronization is deﬁned is explained in brief in Section 10.

9.1.4.4 IF frequency ﬂag

During an automatic frequency search, preset or AF update, the FM part of the

TEA5764HN performs a check of the received IF frequency as a measure of the level of

interference in the channel received. If an incorrect IF frequency is received, it indicates

the presence of either strong interferers or tuning to an image which sets bit IFFLAG in the

INTFLAG register. Also a preset to a channel with no signal will result in a wrong IF count

value and hence the setting of bit IFFLAG.

When a search, preset or AF update is ﬁnished, bit FRRFLAG will be set to indicate this

and will generate an interrupt. The microprocessor can now read the outcome of the

registers which will contain the IF count value and the IFFLAG status of the channel it is

tuned to. In the case of an AF update, the IF count value of the alternative frequency will

be in the registers and also when it jumps back, because it will then not start a new IF

count.

15 ms after the tuning algorithm has completed the IF counter will start a new count. So

30.6 ms after a failed AF update the IF count result will be equal again to that of the

channel from where the jump was initiated.

15 ms after the FRRFLAG has been set the IF counter will start to run continuously on the

tuned frequency and if the conditions for correct frequency are not met then this sets bit

IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt.

Bit IFFLAG is cleared by a read of byte1R, or by starting the tuning algorithm.

9.1.4.5 RSSI threshold ﬂag

The voltage level reﬂects the ﬁeld strength received by the antenna. The voltage level is

analog to digital converted to a 4-bit value and output via the I²C-bus, this 4-bit level value

can be compared to a threshold level set by the SSL bits in Table 19 or the LH bits in

Table 26.

The ADC level (which converts the analog value to digital) can be triggered to convert in

either of two ways:

1. During a tuning step, a search, a preset or an AF update, it is triggered by these

algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit

LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0];

see Table 19. The hardware interrupt is only generated if the corresponding mask bit

is set.

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2. After a search, a preset or an AF update, the threshold for comparison is switched to

the hysteresis level. The hysteresis level is set by the combination of bits SSL[1:0] and

bit LHSW; see Table 24. The result is a hysteresis as shown in Table 26. Then the

ADC level starts to run automatically and compares the level every 500 µs with the

hysteresis level. Bit LEVFLAG is set if the RSSI level drops below the threshold level

set by bits SSL[1:0] in combination with bit LHSW (see Table 26); the hardware

interrupt is only generated if the corresponding mask bit is set. Bit LHSW allows either

a small or a large hysteresis to be selected which results in the levels of the left RSSI

hysteresis threshold column for bit LHSW = 0 and the right RSSI hysteresis threshold

column; see Table 26. When a search or preset is done with the ADC level set to 3

then when the algorithm has ﬁnished, the threshold level is set to 0. Hence the

LEVFLAG will never be set.

Bit LEVFLAG is cleared by a read of the INTMSK byte1R, or by starting the tuning

algorithm.

9.1.4.6 Pause detection ﬂag

The pause detector monitors the amplitude of the audio signal and starts counting if it

drops below the reference level. When the counter reaches the speciﬁed count time, a

pause is detected and the PDFLAG is set and will generate an interrupt if bit PDMSK is

set to logic 1. The PDFLAG operates independently of bit PDMSK and is only active when

the RDS decoder is switched on when bit PUPD is set to logic 1 and when the RDS

decoder is not idle if synchronization is lost.

See Figure 7. When the peak audio level of the (L+R) drops below the threshold level at t₁

it counts the duration of the pause. If the pause lasts longer than the value set by the PT

bits, bit PDFLAG is set which in turn generates a hardware interrupt (bit PDMSK set to

logic 1). The threshold level at t₁is set by the PL bits shown in Table 38.

Bit PDFLAG is cleared by a read of byte1R on condition that the read action occurs more

than 500 µs after receiving the pause interrupt on the INTX line.

The circuit should ignore short transients where the audio level momentarily rises above

the threshold (at t₂).

A pause is detected by comparing the amplitude of the audio signal with the reference

level selected by the PL bits. The resultant signal PSCO produced by this comparison is

sampled at a frequency of 2341 Hz resulting in signal PSCOn. A pause is detected under

the conditions given by Equation 4 and Equation 5.

{SUM(0toN – 1)[PSCOn = 0] – 8 × SUM(0toN – 1)[PSCOn = 1]} > PT × 2341

t_pause– 8 × t_audio> PT

(4)

(5)

where N is the number of samples taken over time and PT is the pause time selected by

bus bits PT. When a pause is detected, the integrator will be reset. The integrator value

cannot be less than zero; therefore if in Equation 4, the value of the second SUM

becomes larger than the ﬁrst SUM, the output of the integrator remains at zero.

Suppose that PT = 20 ms, t_pause= 16 ms and t_audio= 1.5 ms. The pause detector will

count according to Equation 5 as shown in Equation 6:

2 × t_pause– 8 × t_audio= 20 ms ≥ 2 × 16 ms – 8 × 1.5 ms = 20 ms

(6)

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In Equation 6, the pause detector has measured 1 × 16 ms ‘pause’, 8 × 1.5 ms ‘no pause’

and 1 × 16 ms pause. Therefore on average the pause detector has measured 16 ms − 12

ms + 16 ms = 20 ms pause time and hence a pause will be detected.

The PSCOn signal goes directly to the software port. The PDFLAG is set by the integrator

and goes to the bus. The interrupt line is triggered by the PDFLAG.

+ reference level "PL" [mV] (1)

0

audio signal

− reference level "PL"

pause

PSCO

no pause

t

2

1

audio

PT x 2341

integrator

output

0

audio present

(2)

t

pause

audio

PSCOn

no audio present

001aac795

PDFLAG

t_np(min)> 5 ms.

(1) The reference level is deﬁned in kHz, but is internally transformed to mV e.g. 22.5 kHz = 75 mV; 1 kHz = 3.3 mV.

(2) The actual PSCO signal behaves as shown in the top diagram, in the bottom diagram it is assumed that all samples are

taken at peaks of the audio signal resulting in PSCOn.

Fig 7. Operation and timing of pause detection according to levels set in Table 38

9.1.4.7 Frequency ready ﬂag

The frequency ready ﬂag bit is set to logic 1 when the automatic tuning has ﬁnished a

search, a preset or an RDS AF update. This bit is described in Table 4 and Table 5. The

FRRFLAG is cleared by a read of byte1R.

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9.1.4.8 Band limit ﬂag

The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the

end of the tuning band or when the PLL cannot lock on a certain frequency. This bit is

described in Table 4 and Table 5. This bit is cleared by reading byte1R.

9.2 Interrupt output

The interrupt line driver is a MOS transistor with a nominal sink current of 680 µA, it is

pulled HIGH by an 18 kΩ resistor connected to pin VREFDIG. The interrupt line can be

connected to one other similar device with an interrupt output and an 18 kΩ pull-up

resistor providing a wired OR function. This allows any of the drivers to pull the line LOW

by sinking the current. When a ﬂag is set and not masked it generates an interrupt; see

Figure 8.

V

CCA

(1)

flag

INTX

< 10 ms

read clears INTX

< 10 ms

10 ms

read INTMSK

write INTMSK

001aab470

Read INTMSK clears ﬂag, INTMSK and INTX.

Write INTMSK enables INTX.

When ﬂag is set, the next interrupts are blocked until read / write INTMSK.

(1) Flag is set immediately after the reset, because event is still there.

Fig 8. Interrupt line behavior

10. RDS data processing

The RDS demodulator and decoder perform the following operations:

• Demodulation of the RDS/RDBS data stream from the MPX signal

• Symbol decoding

• Block and group synchronization

• Error detection and correction

• Store last and previous data block received with associated ID and error status

• Set the DAVFLG when new data is received

• Set the SYNC status bit according to the current synchronization state

• Set the LSYNCFL ﬂag when synchronization is lost

The RDS decoder can be set to different modes, each meant to look for speciﬁc

information.

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10.1 DAV-A processing mode

The DAV-A processing mode is the standard processing mode used. In this mode, when a

data block has been decoded, it is transferred to the I²C-bus registers. It generates

interrupts on the INTX line after every new block of RDS data that has been processed

and also sets the DAVFLG; see Figure 9. The DAVFLG is reset by a read of the I²C-bus

registers.

If a data block is decoded and a new one arrives, pin INTX goes LOW again, the DAVFLG

will be set and the last block will be shifted to the previous block and the last decoded

block will be put in the last block. This means that all RDS data is still available in the BL

and BP registers.

When the I²C-bus registers are not read the DAVFLG will not be reset. If a data block is

decoded and a new one arrives, pin INTX goes LOW and the last block will be shifted to

the previous block and the last decoded block will be put in the last block. This means that

all RDS data is still available in the BL and BP registers but must be read. This is indicated

by the setting of bit DOVF.

If the I²C-bus registers are still not read, data will be lost, except when this read is done

within 20 ms after the INTX line has gone LOW and 2 ms before the arrival of a new block.

If this read is done at least 2 ms before the arrival of a new block, then BL and BP are read

and the data in the decoder buffer is then instantaneously shifted to the BL register. All

data is now read and bit DOVF will be reset.

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21.9 ms

read BL

A

B

C

1

D

1

A

B

C

2

1

2

DAVFLG set

on falling edge

DAVN = 0, cleared

on read BL register

DAVFLG

INTX

9.98 ms

t

INT_RD

INT_RD < ≈ 10 ms

end read intmsk

read intflg + RDS on INTX

t

READ

> 2 ms

A

B

A

C

B

D

C

A

B

A

BL register

BP register

1

2

x

B

D

1

(1)

(3)

(2)

being decoded

decoder

registers:

B

A

C

D

C

A

B

1

2

1

2

in the decoder buffer

B

D

A

1

(4)

data overflow bit

(1)

(2)

(5)

001aab471

Bit DOVF set when 2 new blocks received in BL and BP registers

(1) If there is no read cycle, B₁is placed in the BP register and the new block C₁is now in the BL

register. Bit DOVF is set to indicate two blocks available.

(2) Data is not transferred to BL register at the end of the read period/clear DOVF, D₁is missed.

(3) In order not to lose D₁a read must be performed before D₁enters decoder buffer, thus read

ﬁnishes within 21 ms after DOVF set to logic 1.

(4) DOVF is cleared when the BL register is read. To be of use, DOVF has to be read before BL

and BP registers.

(5) To prevent DOVF being set again, an extra read of BL must be performed before A2 has been

decoded.

Fig 9. DAV-A timing diagram, DAV-A/B: normal

Figure 9 assumes that block synchronization has been achieved and that no other

interrupt ﬂags are being set.

10.2 DAV-B processing mode / fast PI search mode

This mode is used, for example, when the receiver has been re-tuned to a new station,

and a fast search of the PI code, always contained in the A or C’ block, is required. The

diagram shown in Figure 10, assumes that the RDS decoder is unsynchronized initially

and is performing a synchronization search.

During synchronization search the decoder does not set the DAVFLG until a valid A or C’

block is detected. If a valid B block is detected immediately, then the decoder is now

synchronized and bit SYNC is set to logic 1. In fact, if any 2 good blocks in a valid order

are detected, the RDS decoder will synchronize and give an interrupt.

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If for some reason a valid B block was not received then the next valid A or C’ block is

decoded and the DAVFLG set. The BP and BL registers record the A block history.

When the decoder is synchronized, each decoded block will set the DAVFLG (assuming it

was reset by a read action) and generate an interrupt.

21.9 ms

B

C'

1

D

1

A

B

C

2

1

2

bad

good

bad

good

good A or C' block detected

DAVFLG

INTX

read BL register

not synchronized

read intmsk

sync status bit

synchronized

Bus access - read

x

C'

B

C

B

BL register

BP register

1

2

x

C'

1

2

only valid blocks with no errors

are counted as good blocks

error correction applied

according to SYM bits

001aab472

When the number of blocks detected in the order: ‘bad’ ‘bad’ ‘good’ is 2, synchronization is

achieved if another good block followed by either 0, 1 or 2 bad blocks and another good block

are then received. If the order is 3 bad blocks, no synchronization is achieved and the counters

are reset.

Fig 10. DAV-A timing diagram, DAV B: with bad blocks detected during sync search

10.3 DAV-C reduced processing mode

The DAV-C processing mode is very similar to DAV-A mode with the main exception that a

data ﬂag is set only after two new blocks are received. Hence the update rate is reduced

by half.

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21.9 ms

being

decoded

A

B

1

C

1

D

1

A

B

2

1

2

DAVFLG cleared at end read BP register

and forced to zero till end read of RDS 4R

DAVFLG

INTX

t

INTX cleared at end read INTMSK

BL register copied to

INTX

BP register and C to

1

BL register

B

copied to BL register shortly

t

1

INT_RD

before C decoded

1

read access

(case 1)

t

read

001aab473

Fig 11. Normal DAV-C timing diagram

21.9 ms

A

B

1

C

1

D

1

A

B

2

1

2

instant copy C from decoder buffer

1

to BL, and BL to BP just before D

decoded due to read action

1

D

C

A

C

D

A

2

BL register

BP register

0

1

D

A

C

D

1

0

1

instant copy of A

from decoder

buffer to BL, and

BL to BP

2

DAVFLG not cleared as no read performed

DAVFLG

(case 2)

DAVFLG reset when

st

1

new block

nd

DAVFLG set when 2 new block

in decoder buffer

would have been copied

INTX

t

= 10 ms

INTX

read access

(case 2)

(a)

t

read

no read on INTX

so B will be lost

dashed line shows what would happen if no read

occurred at (a). DOVF bit set until the next read of BP

register, however D1, A2 would be lost

1

data

overflow bit

2 new blocks have arrived in BL/BP (C , D ) and a new block (A )

1

2

has entered the decoder buffer. Hence, DOVF is set again.

To prevent this, an extra read must be performed after reading (a)

001aab474

Fig 12. DAV-C timing diagram, late read of BL, BP register

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10.4 Synchronization

10.4.1 Conditions for synchronization

When the RDS decoder is turned on it must be synchronized to extract valid data from the

MPX signal. To do so the decoder automatically initiates a search for synchronization. The

conditions to meet synchronization and the status of this synchronization can be set and

checked by the following bits:

• BBL (Bad Blocks Lose): these bits can be set via the I²C-bus and have a value

between 0 to 63

• GBL (Good Blocks Lose): these bits can be set via the I²C-bus and have a value

between 0 to 63

• BBG (Bad Blocks Gain): these bits can be set via the I²C-bus and have a value

between 0 to 32

• GBC (Good Block Count): these bits can be read via the I²C-bus and have a value

between 0 to 63

• BBC (Bad Block Count): these bits can be read via the I²C-bus and have a value

between 0 to 63

When the decoder is not synchronized it will initiate a synchronization search. This

involves calculation of the syndrome for each block of 26 received bits on a bit-by-bit

basis. When a correct syndrome (and hence block ID) is received the decoder clocks the

next 26 bits into the internal registers and performs a second syndrome check.

Synchronization is found when a certain number of blocks have been decoded and two

good blocks have been found, this number of blocks is deﬁned by the BBG bits. If the ﬁrst

block needed for synchronization has been found and the expected second block (after 26

bits) is an invalid block, then the decoder module internal bad_blocks_counter is

incremented and the next expected block is calculated; exception: if RBDS mode is

selected and the ﬁrst block is E, then the next expected block is always block A, until

synchronization is found or the maximum bad_blocks_counter value is reached. If the

decoder module internal bad_blocks_counter reaches the value of BBG[4:0], then a new

synchronization search (bit-by-bit) is started immediately to ﬁnd a new ﬁrst block.

The synchronization is monitored by two ﬂywheel counters, GBC and BBC. These are

6-bit counters that can be preset by bits GBL and BBL to values between 0 and 63. Each

time a block is decoded and recognized as a bad block the Bad Block Counter value,

BBC, is incremented by 1. When the BBC value is equal to the BBL value, synchronization

is lost. Bit SYNC will become 0 and bit LSYNCFL is set to indicate the loss of

synchronization. The TEA5764HN will now automatically initiate a new synchronization

search.

Each time a good block is decoded, the GBC value is incremented. When the GBC value

is equal to the GBL value, both counters, BBC and GBC, are set to 0 and a new count

starts. The GBC counter is only incremented when the decoder is synchronized.

TEA5764HN_2

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28 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

10.4.2 Data overﬂow

During synchronization, after RDS data is read from the registers, new available blocks

are shifted to the registers as described in Section 10.1 to Section 10.3. If the registers

are not read in time, the decoder cannot shift any new available block to the registers and

hence a data overﬂow will occur, this is indicated by bit DOVF which is set to 1. Bit DOVF

is reset by a read of the registers or if bit NWSY = 1 which results in the start of a new

synchronization search.

Each time when a RDS data block is decoded, bit DAVN goes to logic 0 to indicate the

presence of a new data block. Bit DAVN also triggers the interrupt output INTX. In

principle the microprocessor must now start reading and must have read all RDS data

(byte12R to byte19R) before the arrival of a new RDS data block. In the application it is

possible that there is too large a delay between the arrival of a new block and reading this

block. This can have various causes such as a microprocessor that has to start-up from

Sleep mode or when polling is used instead of interrupt based read actions. Figure 13

shows the behavior of bit DAVFLG and bit DAVN when polling, where reading can occur at

any time. Note: Bit DAVN sets the INTX oneshot generator when DAVMSK = 1. Unlike

INTX, bit DAVN is not cleared by a read of the mask register.

TEA5764HN_2

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TEA5764HN

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FM radio + RDS

10.6 Error detection and reporting

The TDA5764HN must report information on the number of errors corrected in the last and

previously decoded blocks. This is reported in bits ELB and EPB as shown in Table 29.

During synchronization search the error correction is disabled for detection of the ﬁrst

block and is enabled for processing of the second block according to the mode set by the

SYM bits as described in Table 36.

10.7 RDS test modes

In Test mode the raw RDS clock and RDS data can be recovered directly from pins VAFL

and VAFR when bit RDSCDA = 1.

10.8 Reading RDS data from the registers

To read RDS data the microprocessor must read byte12R to byte19R. All 8 bytes must be

read to reset the status bytes 12R and 13R, i.e. effectively the status bits can be updated

by the decoder after reading the last bit of byte19R. Bit DOVF is cleared after reading the

last bit of byte19R and the status of bit SYNC does not depend on reading the register, bit

SYNC indicates if the decoder is synchronized or not. When starting a read action from

byte12R, the decoder blocks updates from the RDS bytes until byte19R has been read.

RDS byte12R to byte19R must be read in one read action.

11. I²C-bus interface

The I²C-bus interface is based on “The I²C-bus speciﬁcation”, version 2.1 January 2000,

expanded by the following deﬁnitions.

11.1 Write and read mode

Table 8:

S

I²C-bus FM write mode

Byte 1

As Byte 2

As

Byte n

As

Byte 8

As

P

START chip address

0010 000

R/W ACK byte0W

ACK .....

ACK byte6W

xxxx xxxx

ACK STOP

0

xxxx xxxx

Table 9:

S

I²C-bus RDS write mode

Byte 1 As Byte 2

Am Byte n

As

Byte 8

As

P

START chip address

R/W ACK byte7W

ACK .....

ACK byte10W

non

STOP

ACK

0010 001

0

xxxx xxxx

When writing all bytes, byte0W to byte10W can be written with one write action.

Table 10: I²C-bus FM read mode

S

Byte 1

As Byte 2

Am Byte n

Am Byte 17

NAm

P

START chip address

R/W ACK byte0R

ACK .....

ACK byte15R

non

STOP

ACK

0010 000

1

xxxx xxxx

TEA5764HN_2

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TEA5764HN

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FM radio + RDS

Table 11: I²C-bus RDS read mode

S

Byte 1

As Byte 2

Am Byte n

Am Byte 17

NAm

P

START chip address

R/W ACK byte12R

ACK .....

ACK byte27R

non

STOP

ACK

0010 001

1

xxxx xxxx

Table 12: I²C-bus transfer description

Label

S

Deﬁnition

START condition

Byte 1

I²C-bus chip address (7 bits)

R/W = 0 for write action and R/W = 1 for read action

acknowledge from slave TEA5764HN (SDA is LOW)

data byte (8 bits)

As

Byte 2, etc.

P

STOP condition

Am

NAm

NA

acknowledge from master microcontroller (SDA is LOW)

non acknowledge from master microcontroller (SDA is HIGH)

non acknowledge (SDA is HIGH)

When the TEA5764HN is addressed by the FM radio address, the RDS part (byte12R to

byte27R) can be read in one read action. A read does not have to stop at byte11R.

Therefore, by effectively only using the RDS part of the address, ignores some bytes

which reduces I²C-bus access.

11.2 Data transfer

Structure of the I²C-bus:

• Slave transceiver

• Subaddresses not used

• Maximum LOW-level input voltage: V_IL= 0.3 × V_VREFDIG

• Minimum HIGH-level input voltage: V_IH= 0.7 × V_VREFDIG

Remark: The I²C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to

connect the TEA5764HN to a I²C-bus operating at a higher clock rate.

Data transfer to the IC:

• Bit 7 of each byte is considered the MSB and has to be transferred as the ﬁrst bit of

the byte

• The LSB indicates the write or read action

• The data becomes valid byte-wise at the appropriate falling edge of the SCL clock

• A STOP condition after any byte can shorten transmission times. When writing to the

transceiver by using the STOP condition before completion of the whole transfer:

– The remaining bytes will contain the old information

– If the transfer of a byte is not completed the new bits will be used, but a new tuning

cycle will not be started

TEA5764HN_2

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TEA5764HN

Philips Semiconductors

FM radio + RDS

To speed up RDS trafﬁc it is possible to read all the RDS data and then only write back

byte INTMSK to set the appropriate mask(s) again.

I²C-bus activity:

• With bits PUPD the TEA5764HN can be switched in a low current Standby mode. The

I²C-bus is then still active

• When the I²C-bus interface is deactivated, by making pin BUSENABLE LOW and

without programmed Standby mode, the TEA5764HN keeps its normal operation, but

is isolated from the I²C-bus lines

• It is possible to operate the TEA5764HN with BUSENABLE hard wired to pin

VREFDIG, and have the bus interface always active.

SDA

SCL

t

f

t

BUF

t

r

t

P

S

Sr

t

SU;STO

t

SU;STA

HD;STA

SU;DAT

HD;DAT

HIGH

LOW

t

HO;BUSEN

SU;BUSEN

BUS

ENABLE

001aac796

t_f= fall time of both SDA and SCL signals: 20 + 0.1 C_b< t_f< 300 ns, where C_b= total capacitance on bus line in pF.

t_r= rise time of both SDA and SCL signals: 20 + 0.1 C_b< t_f< 300 ns, where C_b= total capacitance on bus line in pF.

t_HD;STA= hold time (repeated) START condition. After this period, the ﬁrst clock pulse is generated: > 600 ns.

t_HIGH= HIGH period of the SCL clock: > 600 ns.

t_SU;STA= setup time for a repeated START condition: > 600 ns.

t_HD;DAT= data hold time: 300 < t_HD;DAT< 900 ns.

Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.

t_SU;DAT= data setup time: t_SU;DAT> 100 ns. If ASIC is used in a standard mode I²C-bus system, t_SU;DAT> 250 ns.

t_SU;STO= setup time for STOP condition: > 600 ns.

t_BUF= bus free time between a STOP and a START condition: > 600 ns.

C_b= capacitive load of one bus line: < 400 pF.

t_SU;BUSEN= bus enable setup time: t_SU;BUSEN> 10 µs.

t_HO;BUSEN= bus enable hold time: t_HO:BUSEN> 10 µs.

Fig 14. I²C-bus timing diagram

TEA5764HN_2

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TEA5764HN

Philips Semiconductors

FM radio + RDS

11.3 Register map

Table 13: Register overview

Byte

Read

0R

Byte name

Access

Reset value

Reference

Write

INTFLAG

INTMSK

R

00

80

00

08

D2

-

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 28

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

Table 36

Table 37

Table 38

Table 39

Table 40

Table 41

Table 42

Table 43

1R

0W

1W

2W

3W

4W

R/W

2R

FRQSETMSB R/W

FRQSETLSB R/W

3R

4R

TNCTRL1

TNCTRL2

FRQCHKMSB

FRQCHKLSB

IFCHK

R/W

R

5R

6R

7R

R

-

8R

R

-

9R

LEVCHK

R

-

10R

11R

12R

13R

14R

15R

16R

17R

18R

19R

20R

21R

22R

23R

24R

25R

26R

27R

5W

6W

TESTBITS

TESTMODE

RDSSTAT1

RDSSTAT2

RDSLBMSB

RDSLBLSB

RDSPBMSB

RDSPBLSB

RDSBBC

R/W

R

00

-

R

-

R

-

R

-

R

-

R

-

R

-

RDSGBC

R

-

7W

8W

9W

10W

RDSCTRL1

RDSCTRL2

PAUSEDET

RDSBBL

R/W

R

00

10

00

50

2B

57

64

MANID1

MANID2

R

CHIPID1

R

CHPID2

R

11.4 Byte description

Table 14: INTFLAG - byte0R description

Bit

7

Symbol

DAVFLG

TESTBIT

LSYNCFL

IFFLAG

Access

Reset

Functional description

1 = RDS data is available

internal use

R

0

6

5

1 = synchronization is lost

1 = IF count is not correct

4

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TEA5764HN

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FM radio + RDS

Table 14: INTFLAG - byte0R description …continued

Bit

Symbol

Access

Reset

Functional description

3

LEVFLAG

R

0

continuous checking of the RSSI level

1 = RSSI level has dropped below

(V_SSL[1:0]− V_hys

)

during a tuning period (preset or search)

1 = RSSI level has dropped below V_SSL[1:0]

1 = pause is detected

2

1

0

PDFLAG

FRRFLAG

BLFLAG

R

0

1 = tuner state machine is ready

1 = during a search the band limit has been

reached or time out

Table 15: INTMSK - byte1R and byte0W description

Bit

7

Symbol

DAVMSK

-

Access

R/W

Reset

Functional description

masks bit DAVFLG

reserved

0

6

5

LSYMSK

IFMSK

LEVMSK

PDMSK

FRMSK

BLMSK

masks bit LSYNCFL

masks bit IFFLAG

masks bit LEVFLAG

masks bit PDFLAG

masks bit FRRFLAG

masks bit BLFLAG

4

3

2

1

0

Table 16: FRQSETMSB - byte2R and byte1W description

Bit

Symbol

Access

Reset

Functional description

1 = search up

7

SUD

R/W

1

0 = search down

6

SM

R/W

0

1 = Search mode

0 = Preset mode

5

4

3

2

1

0

FR13

FR12

FR11

FR10

FR09

FR08

R/W

0

PLL frequency set bits; see Section 8.5

TEA5764HN_2

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FM radio + RDS

Table 17: FRQSETLSB - byte3R and byte2W description

Bit

7

Symbol

FR07

FR06

FR05

FR04

FR03

FR02

FR01

FR00

Access

R/W

Reset

Functional description

PLL frequency set bits; see Section 8.5

0

6

5

4

3

2

1

0

Table 18: TNCTRL1 - byte4R and byte3W description

Bit

Symbol

Access

Reset

Functional description

power-up and power-down

00 = FM off and RDS off

01 = FM on and RDS off

10 = not used

7 and 6

PUPD[1:0] R/W

00

11 = FM on and RDS on

1 = Japan FM band 76 MHz to 90 MHz

5

BLIM

R/W

0

0 = US / Europe FM band 87.5 MHz to

108 MHz

4

3

2

1

0

SWPM

IFCTC

AFM

R/W

0

1

0

1 = software port is output of FRRFLAG

0 = SWP

1 = IF count time = 15.02 ms

0 = IF count time = 2.02 ms

1 = left and right audio muted

0 = audio not muted

SMUTE

SNC

1 = soft mute on

0 = soft mute off

1 = stereo noise cancellation on

0 = stereo noise cancellation off

Table 19: TNCTRL2 - byte5R and byte4W description

Bit

Symbol

Access

Reset

Functional description

1 = left and right audio hard-muted

0 = no hard mute

search stop level

00 = ADC3

7

MU

R/W

1

6 and 5

SS[1:0]

R/W

10

01 = ADC5

10 = ADC7

11 = ADC10

4

HLSI

1

1 = high-side injection

0 = low-side injection

TEA5764HN_2

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FM radio + RDS

Table 19: TNCTRL2 - byte5R and byte4W description …continued

Bit

Symbol

Access

Reset

Functional description

3

MST

R/W

0

1 = forced mono

0 = stereo on

2

1

0

SWP

DTC

R/W

0

1

0

1 = pin SWPORT is HIGH

0 = pin SWPORT is LOW

1 = de-emphasis time constant = 50 µs

0 = de-emphasis time constant = 75 µs

AHLSI

see Section 8.21.3 for the functionality of

this bit

Table 20: FRQCHKMSB - byte6R description

Bit

7

Symbol

-

Access

Reset

Functional description

reserved

-

6

-

reserved

5

PLL13

PLL12

PLL11

PLL10

PLL09

PLL08

R

output frequency MSB

output frequency

4

3

2

1

0

Table 21: FRQCHKLSB - byte7R description

Bit

7

Symbol

PLL07

PLL06

PLL05

PLL04

PLL03

PLL02

PLL01

PLL00

Access

Reset

Functional description

output frequency

output frequency LSB

R

-

6

5

4

3

2

1

0

Table 22: IFCHK - byteR8 description

Bit

7

Symbol

IF6

IF5

IF4

IF3

IF2

IF1

IF0

-

Access

Reset

Functional description

IF count MSB

IF count

R

-

6

5

IF count

4

IF count

3

IF count

2

IF count

1

IF count LSB

reserved

0

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FM radio + RDS

Table 23: LEVCHK - byte9R description

Bit

7

Symbol

LEV3

LEV2

LEV1

LEV0

LD

Access

Reset

Functional description

R

-

level count MSB

level count bit

6

5

level count bit

4

level count LSB

1 = PLL is locked

0 = PLL is not locked

3

[1]

2

STEREO

R

-

1 = pilot detected

0 = no pilot detected

reserved

1

0

-

reserved

[1] This bit does not switch the radio to mono or stereo, this depends on the RF input level as shown in sections

‘Mono stereo blend’ or ‘mono stereo switched’ in Table 47.

Table 24: TESTBITS - byte10R and byte5W description

Bit

Symbol

Access

Reset

Functional description

7

LHM

R/W

0

1 = left audio output is hard muted

0 = left audio output is not hard muted

1 = right audio output is hard muted

0 = right audio output is not hard muted

6

5

RHM

R/W

0

RDSCDA

1 = pin VAFL is RDS clock and pin VAFR is

RDS data

0 = normal operation

4

3

LHSW

R/W

0

1 = level hysteresis is large

0 = level hysteresis is small

TRIGFR

1 = reference frequency selected pin

FREQIN

0 = crystal as reference pin XTAL

1 = local DX on, −6 dB gain of LNA

0 = local DX off, LNA has normal gain

1 = RFAGC off

2

1

0

LDX

R/W

0

RFAGC

INTCTRL

0 = RFAGC on

when this bit is set to logic 1 an interrupt is

generated on pin INTX

Table 25: TESTMODE - byte11R and byte6W description

Bit

7 to 5

4

Symbol

Access

R/W

Reset

Functional description

-

0

reserved

TM

R/W

1 = oscillator output and programmable

divider output are enabled

0 = normal operation

TEA5764HN_2

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FM radio + RDS

Table 25: TESTMODE - byte11R and byte6W description …continued

Bit

3

Symbol

TB3

Access

R/W

Reset

Functional description

0

test bits: Table 27 describes selection of

signals output to the SWPORT when

SWPM = 0; when TM = 1; TB_[3:0] = 0;

which effectively is an AND function.

2

TB2

R/W

1

TB1

R/W

0

TB0

R/W

Table 26: LH - RSSI level hysteresis

RSSI ADC search stop level

RSSI hysteresis threshold

LHSW = 0

LHSW = 1

3

0

2

4

7

0

1

3

5

7

10

Table 27: Test bits (SWPM = 0)

TB3

0

TB2

0

TB1

0

TB0

0

SWPORT output signal

bit SWP of byte4W, depending on bits SWPM and SWP

0

1

oscillator output 32.768 kHz; when TM = 1

lock detect bit LD

stereo bit STEREO

programmable divider; when TM = 1

PSCOn; see Section 9.1.4.6

57 kHz clock

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3-state

1

0

output of RDS comparator

reserved

1

0

1

0

1

0

reserved

1

0

1

reserved

1

0

reserved

Table 28: RDSSTAT1 - byte12R description

Bit

7

Symbol

-

Access

Reset

Functional description

reserved

-

6 to 4

BLID[2:0]

R

block ID of last block

000 = A

001 = B

010 = C

011 = D

100 = C’

101 = E

110 = invalid block E (RBDS)

111 = invalid block

TEA5764HN_2

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FM radio + RDS

Table 28: RDSSTAT1 - byte12R description …continued

Bit

Symbol

Access

Reset

Functional description

3

-

2

-

1 and 0

ELB[1:0]

R

number of errors for last processed block

00 = no errors

01 = maximum 2 bits

10 = maximum 5 bits

11 = uncorrectable

Table 29: RDSTAT2 - byte13R description

Bit

Symbol

Access

Reset

Functional description

block ID of previous block

000 = A

7 to 5

BPID[2:0]

R

-

001 = B

010 = C

011 = D

100 = C’

101 = E

110 = invalid block E (RBDS)

111 = invalid block

4 and 3

EPB[1:0]

R

-

number of errors for previous processed

block

00 = no errors

01 = maximum 2 bits

10 = maximum 5 bits

11 = uncorrectable

2

1

0

SYNC

RSTD

DOVF

R

-

1 = RDS bitstream is synchronized

0 = not synchronized

1 = power-on reset detected

0 = no power-on reset detected

1 = data overﬂow occurred during read

operation

0 = normal operation

Table 30: RDSRLBMSB - byte14R description

Bit

7

Symbol

BL15

BL14

BL13

BL12

BL11

Access

Reset

Functional description

last RDS data byte - MSB

last RDS data byte

R

-

6

5

last RDS data byte

4

last RDS data byte

3

last RDS data byte

TEA5764HN_2

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FM radio + RDS

Table 30: RDSRLBMSB - byte14R description …continued

Bit

2

Symbol

BL10

BL9

Access

Reset

Functional description

R

-

last RDS data byte

1

0

BL8

Table 31: RDSLBLSB - byte15R description

Bit

7

Symbol

BL7

Access

Reset

Functional description

last RDS data byte

last RDS data byte - LSB

R

-

6

BL6

5

BL5

4

BL4

3

BL3

2

BL2

1

BL1

0

BL0

Table 32: RDSPBMSB - byte16R description

Bit

7

Symbol

BP15

BP14

BP13

BP12

BP11

BP10

BP9

Access

Reset

Functional description

previous RDS data byte - MSB

previous RDS data byte

R

-

6

5

4

3

2

1

0

BP8

Table 33: RDSPBLSB - byte17R description

Bit

7

Symbol

BP7

Access

Reset

Functional description

previous RDS data byte

previous RDS data byte - LSB

R

-

6

BP6

5

BP5

4

BP4

3

BP3

2

BP2

1

BP1

0

BP0

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FM radio + RDS

Table 34: RDSBBC - byte18R description

Bit

7

Symbol

BBC5

BBC4

BBC3

BBC2

BBC1

BBC0

GBC5

GBC4

Access

Reset

Functional description

R

-

bad block count MSB

bad block count

6

5

bad block count

4

bad block count

3

bad block count

2

bad block count LSB

good block count MSB

good block count

1

0

Table 35: RDSGBC - byte19R description

Bit

Symbol

GBC3

GBC2

GBC1

GBC0

-

Access

Reset

Functional description

good block count

good block count LSB

reserved

7

R

-

6

5

4

3 to 0

Table 36: RDSCTRL1 - byte20R and byte7W description

Bit

Symbol

Access

Reset

Functional description

1 = start new synchronization

0 = normal processing

error correction

7

NWSY

R/W

0

6 and 5

SYM[1:0]

R/W

00

00 = no correction

01 = maximum 2 bits

10 = maximum 5 bits

11 = no correction

1 = RBDS processing mode

0 = RDS processing mode

RDS data output mode

00 = DAVA

4

RBDS

R/W

0

3 and 2

DAC[1:0]

00

01 = DAVB

10 = DAVC

11 = not used

1 and 0

-

reserved

Table 37: RDSCTRL2 - byte21R and byte8W description

Bit

7 to 5

4

Symbol

-

Access

-

Reset

Functional description

reserved

-

BBG4

BBG3

R/W

1

0

bad blocks gain MSB

bad blocks gain

3

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

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TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 37: RDSCTRL2 - byte21R and byte8W description …continued

Bit

2

Symbol

BBG2

BBG1

BBG0

Access

R/W

Reset

Functional description

0

bad blocks gain

1

R/W

bad blocks gain

0

R/W

bad blocks gain LSB

Table 38: PAUSEDET - byte22R and byte9W description

Bit

Symbol

Access

Reset

Functional description

pause time

7 and 6

PT[1:0]

R/W

00

00 = 20 ms

01 = 40 ms

10 = 80 ms

11 = 160 ms

5 and 4

PL[1:0]

R/W

00

pause level L = R

00 = 1 kHz

01 = 1.6 kHz

10 = 2.5 kHz

11 = 4.0 kHz

3

2

1

0

GBL5

GBL4

GBL3

GBL2

R/W

0

number of good blocks lose MSB

number of good blocks lose

Table 39: RDSBBL - byte23R and byte10W description

Bit

7

Symbol

GBL1

GBL0

BBL5

BBL4

BBL3

BBL2

BBL1

BBL0

Access

R/W

Reset

Functional description

0

number of good blocks lose

number of good blocks lose LSB

number of bad blocks lose MSB

number of bad blocks lose

number of bad blocks lose LSB

6

5

4

3

2

1

0

Table 40: MANID1 - byte24R description

Bit

7

Symbol

Access

Reset

Functional description

version code MSB

version code

VERSION3

VERSION2

VERSION1

VERSION0

MANID10

R

0

1

0

1

0

6

5

version code

4

version code LSB

manufacturer ID code MSB

3

TEA5764HN_2

Product data sheet

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TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 40: MANID1 - byte24R description …continued

Bit

2

Symbol

MANID9

MANID8

MANID7

Access

Reset

Functional description

R

0

manufacturer ID code

1

0

Table 41: MANID2 - byte25R description

Bit

7

Symbol

MANID6

MANID5

MANID4

MANID3

MANID2

MANID1

MANID0

IDAV

Access

Reset

Functional description

manufacturer ID code

R

0

1

0

1

0

1

6

manufacturer ID code

5

manufacturer ID code

4

manufacturer ID code

3

manufacturer ID code

2

manufacturer ID code

1

manufacturer ID code LSB

1 = manufacturer ID available

0 = no manufacturer ID available

0

Table 42: CHIPID1 - byte26R description

Bit

7

Symbol

Access

Reset

Functional description

chip identiﬁcation code MSB

chip identiﬁcation code

CHIP ID15

CHIP ID14

CHIP ID13

CHIP ID12

CHIP ID11

CHIP ID10

CHIP ID9

CHIP ID8

R

0

1

0

1

0

1

6

5

4

3

2

1

0

Table 43: CHIPID2 - byte27R description

Bit

7

Symbol

Access

Reset

Functional description

chip identiﬁcation code

chip identiﬁcation code LSB

CHIP ID7

CHIP ID6

CHIP ID5

CHIP ID4

CHIP ID3

CHIP ID2

CHIP ID1

CHIP ID0

R

0

1

0

1

0

6

5

4

3

2

1

0

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

44 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

12. Limiting values

Table 44: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+8

Unit

V

V_LO1

V_LO2

V_CCD

V_CCA

V_I/O(n)

VCO tuned circuit output 1

−0.3

VCO tuned circuit output 2

digital supply voltage

+8

V

+5.5

+8

V

analog supply voltage

V

voltage on all inputs and

outputs

with respect to ground

+5.5

V

T_stg

storage temperature

ambient temperature

−55

+150

+85

°C

V

T_amb

V_esd

−40

[1]

[2]

electrostatic discharge voltage MM

HBM

−200

+200

all pins except PILLP, RFIN1,

−2000

+2000

V

RFIN2

[2]

[3]

pin PILLP only

pins RFIN1 and RFIN2

−1000

−1500

−500

+2000

+500

V

CDM

[1] Machine model I (L = 0.75 mH, R = 10 Ω, C = 200 pF).

[2] Human body model (R = 1.5 kΩ, C = 100 pF).

[3] Charged device model (JEDEC standard JESD22-C101C).

13. Thermal characteristics

Table 45: Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

K/W

R_th(j-a)

thermal resistance from junction to ambient

in free air

80

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

45 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

14. Static characteristics

Table 46: Characteristics

The minimum and maximum values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V and T_amb= −20 °C to +85 °C; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply voltages

V_CCA

V_CCD

analog supply voltage

digital supply voltage

2.5

2.7

1.8

3.3

V

2.5

3.3

V_VREFDIGdigital reference voltage for

I²C-bus interface on pin

VREFDIG

1.65

V_CCD

Supply currents

I_CCA

analog supply current

V_CCA= 2.5 V to 3.3 V

operating mode

Standby mode

12

0

13.7

0.1

16

1

mA

µA

I_CCD

digital supply current

V_CCD= 2.5 V to 3.3 V

operating mode

Standby mode

0.3

1

0.7

15

1.5

22.5

1

mA

µA

I_VREFDIG

digital reference supply current operating mode;

0

0.5

V_VREFDIG= 1.65 V to V_CCD

DC operating points

V_LOOPSWvoltage on pin LOOPSW

V

_CD3− 0.2

-

V_CD3

V

V_CPOUT

V_LO1

voltage on pin CPOUT

voltage on pin LO1

voltage on pin LO2

voltage on pin PILLP

voltage on pin TMUTE

0.1

-

V

_CD3− 0.1

V

_CD3− 0.1

-

V_CD3

1.65

0.8

V

V_LO2

-

V

V_PILLP

V_TMUTE

1.09

0.6

1.37

0.7

V

V_RF= 0 V, measured with

respect to pin CD3

mV

V_VAFL

V_VAFR

voltage on pin VAFL

voltage on pin VAFR

f_RF= 98 MHz; V_RF= 1 mV;

no modulation

800

830

0.2

850

900

0.4

940

950

0.5

mV

V

f_RF= 98 MHz; V_RF= 1 mV;

no modulation

V_MPXOUTvoltage on pin MPXOUT

f_RF= 98 MHz; V_RF= 1 mV;

no modulation

V_MPXIN

voltage on pin MPXIN

voltage on pin FREQIN

f_RF= 98 MHz; V_RF= 1 mV;

no modulation

V_FREQIN

TRIGFR = 1

TRIGFR = 0

TRIGFR = 1

TRIGFR = 0

1.3

0

1.5

1.7

0.1

1.3

1.2

680

2

V

0.05

1.17

1

V

V_XTAL

voltage on pin XTAL to CD3

0.9

0.8

420

1

V

V_RFIN1

V_RFIN2

V_CAGC

voltage on pin RFIN1

voltage on pin RFIN2

voltage on pin CAGC

530

1.57

mV

V

V_RF= 0 V

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

46 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

15. Dynamic characteristics

Table 47: Characteristics

See Figure 1; all AC values are given in RMS; the minimum and maximum values include spread due to V_CCA= V_CCD= 2.5 V

to 3.3 V and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference,

except when EMF is explicitly stated.

Symbol

Voltage controlled oscillator

f_oscoscillator frequency

Reference frequency input; pin FREQIN

Parameter

Conditions

Min

Typ

Max

Unit

150

-

217

MHz

R_i

input resistance

500

5

-

kΩ

pF

C_i

input capacitance

resonance frequency

6

7

f_rsn

∆f_rsn

-

32.768

-

kHz

ppm

%

resonance frequency deviation T_amb= 25 °C

T_amb= −20 °C to +85 °C

square wave

−20

−150

30

-

+20

+150

70

V_CC

0.55

-

δ

duty cycle

V_IH

V_IL

C/N

HIGH-level input voltage

LOW-level input voltage

carrier-to-noise ratio

square wave

at 10 kHz

1.15

0

V

−151

dBc/

Hz

Crystal oscillator 32.768 kHz; pin XTAL

f_rsn

resonance frequency

resonance frequency deviation

shunt capacitance

T_amb= 25 °C

-

32.768

-

kHz

ppm

pF

∆f_rsn

C_shunt

C_m

−20

-

+20

3.5

3.0

75

motional capacitance

series resistance

1.5

-

fF

R_s

kΩ

Synthesizer

Programmable divider

D/D_prog

programmable divider ratio

FRQSETMSB[15:8] = XX11

1111; FRQSETLSB[7:0] =

1111 1110

-

8191

FRQSETMSB[15:8] = XX00

1000; FRQSETLSB[7:0] =

0000 0000

2048

-

D_step(prog)programmable divider step size

-

1

Charge pump; pin CPOUT; V_LOOPSW= 0.2 V to (V_LO2− 0.2) V; f_VCO> f_ref× divider ratio

I_M(sink)

I_M(source)

IF counter

N

peak sink current

250

500

1000

nA

peak source current

length

-

7

-

bit

V_sens

n_count

T

sensitivity voltage

count result for search stop

period

-

5.5

15

3C

-

µV

Hex

µs

10 µV < V_RF< 1 V

IFCTC = 1

31

-

15625

1953

4096

IFCTC = 0

-

µs

f_res

frequency resolution

-

Hz

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

47 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 47: Characteristics …continued

See Figure 1; all AC values are given in RMS; the minimum and maximum values include spread due to V_CCA= V_CCD= 2.5 V

to 3.3 V and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference,

except when EMF is explicitly stated.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Logic pins; pins BUSENABLE, SCL and SDA

R_i

input resistance

10

-

MΩ

V_IH

HIGH-level input voltage

input switching level up

0.7V_VREFDIG

V_VREFDIG

0.3

+

V

V_IL

LOW-level input voltage

input switching level down

−0.3

-

0.3V_VREFDIG

V

Software programmable port; pin SWPORT

V_O(max)

maximum output voltage

I_load= 150 µA

V_VREFDIG

0.2

−

V_VREFDIG

V_O(min)

minimum output voltage

maximum sink current

I_load= 150 µA

0

-

0.2

V

I_sink(max)

400

500

−1.0

2000

1100

+1.0

µA

I_source(max)maximum source current

I_L(max)maximum leakage current

V_SWPORT= 0 V to 5 V

Interrupt ﬂag; pin INTX; V_VREFDIG= 1.65 V to 1.95 V; I_load(max)= 200 µA or R_puof second device connected to pin

INTX is 18 kΩ ± 20 %

V_O(max)

maximum output voltage

V_VREFDIG

0.2

−

-

V_VREFDIG

V

V_O(min)

I_pd

minimum output voltage

pull-down current

pull-up resistance

LOW time

0.130

500

0.215

680

18

0.4

V

1200

22.5

10

µA

kΩ

ms

R_pu

t_L

14.4

9.9

one-shot pulse time

9.98

Table 48: FM signal channel characteristics

See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V

and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference, except when

EMF is explicitly stated.

Symbol

Parameter

Conditions

Min Typ Max Unit

FM RF input; pins RFIN1 and RFIN2

R_i

input resistance

connected to pin GNDRF

75

2.5

-

100 125

Ω

C_i

input capacitance

4

6

pF

µV

V_sens(EMF)

sensitivity EMF value voltage f_RF= 76 MHz to 108 MHz;

∆f = 22.5 kHz; f_mod= 1 kHz;

2.3

3.5

(S+N)/N = 26 dB; TC_deem= 75 µs;

A-weighting ﬁlter;

B

_aud= 300 Hz to 15 kHz

∆f₁= 200 kHz; ∆f₂= 400 kHz;

_tune= 76 MHz to 108 MHz;

IP3_in

in-band 3rd-order intercept

point

78

87

93

-

dBµV

f

RF_agc= off

IP3_out

out-of-band 3rd-order

intercept point

∆f₁= 4 MHz; ∆f₂= 8 MHz;

f_tune= 76 MHz to 108 MHz;

RF_agc= off

In-band AGC

V_i(AGC)(min)

minimum RF AGC input

voltage

f_RF= 98 MHz; ∆V_th(mute)

∆V_sens(EMF)< 4 mV/dBµV

/

55

61

67

dBµV

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

48 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 48: FM signal channel characteristics …continued

See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V

and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference, except when

EMF is explicitly stated.

Symbol

Parameter

Conditions

Min Typ Max Unit

Wideband AGC

V_i(RF)

RF input voltage

f_RF= 93 MHz; f_RF2= 98 MHz;

66

72

78

dBµV

V_RF2= 50 dBµV; ∆V_th(mute)/

∆V_sens(EMF)< 4 mV/dBµV; radio tuned

to 98 MHz

IF ﬁlter

f_center

B

center frequency

bandwidth

215 225 235 kHz

85

94

102 kHz

[1]

S

selectivity

f_tune= 76 MHz to 108 MHz

high-side; ∆f = +200 kHz

low-side; ∆f = −200 kHz

high-side; ∆f = +100 kHz

low-side; ∆f = −100 kHz

f_tune= 76 MHz to 108 MHz;

39

32

8

43

36

12

30

-

dB

8

IR

image rejection

24

V_RF= 50 dBµV

FM IF level detector and mute voltage

V_IF

IF voltage

V_RF= 0 µV

1.5

1.6

1.55 1.6

1.61 1.7

V

V_RF= 3 µV

V_IF(slope)

V_ADC(start)

G_step

slope of IF voltage level

ADC start voltage

∆V_level/ ∆V_RF; V_RF= 10 µV to 500 µV

130 170 210 mV/20dB

2

3

5

µV

step resolution gain

dB

R_TMUTE

pin TMUTE output resistance

280 400 520 kΩ

FM demodulator

V_o

output voltage

V_RF= 1 mV; L = R; ∆f = 22.5 kHz;

55

70

75

mV

f_mod= 1 kHz; DTC = 0; B_aud= 300 Hz

to 15 kHz

R_o

output resistance

sink current

-

500

Ω

I_sink

30

54

-

µA

dB

(S+N)/N

maximum signal-to-noise ratio f_RF= 76 MHz to 108 MHz;

_RF= 1 mV; L = R; ∆f = 22.5 kHz;

_mod= 1 kHz; TC_deem= 75 µs;

57

V

f

A-weighting ﬁlter; B_aud= 300 Hz to

15 kHz

THD

total harmonic distortion

V_RF= 1 mV; L = R; ∆f = 75 kHz;

-

0.4

-

0.9

1

%

f_mod= 1 kHz; DTC = 0; A-weighting

ﬁlter; B_aud= 300 Hz to 15 kHz;

see Figure 17

V_RF= 1 mV; L = R; ∆f = 100 kHz;

THD_OD

total harmonic distortion

overdrive

f_mod= 1 kHz; DTC = 0; A-weighting

ﬁlter; B_aud= 300 Hz to 15 kHz;

see Figure 17

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

49 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 48: FM signal channel characteristics …continued

See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V

and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference, except when

EMF is explicitly stated.

Symbol

Parameter

Conditions

Min Typ Max Unit

AM_sup

AM suppression

L = R; ∆f = 22.5 kHz; f_mod= 1 kHz;

−40

-

dB

V_RF= 100 µV to 10 mV; m = 0.3;

DTC = 0; B_aud= 300 Hz to 15 kHz

Soft mute; SMUTE = 1; ∆f = 22.5 kHz; f_mod= 1 kHz

V_start(mute)

mute start voltage

relative to V_VAFLat V_RF= 1 mV;

α_mute= 3 dB

3

5

10

30

µV

α_mute

mute attenuation

V_RF= 1 µV; L = R; DTC = 0;

10

20

dB

B_aud= 300 Hz to 15 kHz

MPX decoder

V_VAFL

left audio output voltage on pin V_RF= 1 mV; L = R; ∆f = 22.5 kHz;

55

66

75

mV

VAFL

f_mod= 1 kHz; no pre-emphasis;

TC_deem= 75 µs

V_VAFR

right audio output voltage on

pin VAFR

V_RF= 1 mV; L = R; ∆f = 22.5 kHz;

f_mod= 1 kHz; no pre-emphasis;

TC_deem= 75 µs

R_VAFL

output resistance on pin VAFL RDSCDA = 0

MU = LHM = RHM = 0

MU = LHM = RHM = 1

output resistance on pin VAFR RDSCDA = 0

50

-

100

-

Ω

500

kΩ

R_VAFR

MU = LHM = RHM = 0

MU = LHM = RHM = 1

50

-

100

-

Ω

500

200

4

kΩ

I_sink(VAFL)

I_sink(VAFR)

α_ODi

sink current on pin VAFL

sink current on pin VAFR

input overdrive range

300 µA

THD = 3 % relative to f_MPX= 1 kHz;

-

dB

V

_MPX= 250 mV

V_RF= 1 mV; L = R; ∆f = 75 kHz

between pins VAFL and VAFR including 9 % pilot deviation;

_mod= 1 kHz

∆V_O(VAFL-VAFR)output voltage difference

−0.5

-

+0.5 dB

f

α_cs

channel separation

V_RF= 1 mV; ∆f = 75 kHz including 9 %

pilot deviation; R = 1; L = 0 or R = 0;

L = 1; f_mod= 1 kHz; MST = 0;

27

-

dB

SNC = 1; B_aud= 300 Hz to 15 kHz

f_u

f_l

upper 3 dB bandwidth

lower 3 dB bandwidth

V_RF= 1 mV; ∆f = 22.5 kHz;

pre-emphasis = 75 µs; DTC = 0;

L = R; with C between pin 27 and

pin 26 = 33 nF ± 5 %

13

20

15

30

17

50

kHz

Hz

(S+N)/N(m)

(S+N)/N(s)

maximum signal-to-noise ratio, V_RF= 1 mV; ∆f = 22.5 kHz; L = R;

mono _mod= 1 kHz; de-emphasis = 75 µs;

_AF= 300 Hz to 15 kHz; A-weighting

ﬁlter

54

50

57

54

-

dB

f

B

maximum signal-to-noise ratio, V_RF= 1 mV; ∆f = 67.5 kHz; L = R;

stereo _mod= 1 kHz; ∆f_pilot= 6.75 kHz;

f

de-emphasis = 75 µs; B_AF= 300 Hz to

15 kHz; A-weighting ﬁlter

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

50 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

Table 48: FM signal channel characteristics …continued

See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V

and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference, except when

EMF is explicitly stated.

Symbol

Parameter

Conditions

Min Typ Max Unit

THD

total harmonic distortion

V_RF= 1 mV; L = 1; R = 0; ∆f = 75 kHz

including 9 % pilot deviation;

f

_mod= 1 kHz; DTC = 0; B_aud= 300 Hz

to 15 kHz; A-weighting ﬁlter

mono; L = R; no pilot deviation

-

0.4

0.9

2.5

%

stereo; L = 1, R = 0; 9 % pilot

deviation; see Figure 17

α_sup(pilot)

pilot suppression

measured at pins VAFL and VAFR;

related to ∆f = 75 kHz including 9 %

pilot deviation; f_mod= 1 kHz; DTC = 0

40

50

-

dB

∆f_pilot

pilot frequency deviation

V_RF= 1 mV

Table note [2]

α_hys(pilot)

TC_deem

pilot tone detection hysteresis V_RF= 1 mV

2

-

6

dB

de-emphasis time constant

V_RF= 1 mV

DTC = 1

38

57

50

75

62

93

µs

DTC = 0

Mono stereo blend; SNC = 1

[3]

V_start(blend)

blend start voltage

channel separation

α_cs= 0.5 dB

2

4

7

15

16

µV

α_cs

V_RF= 30 µV; ∆f = 75 kHz including

9 % pilot deviation; R = 1 and L = 0 or

R = 0 and L = 1; f_mod= 1 kHz;

MST = 0; SNC = 1

10

dB

Mono stereo switching; ∆f = 75 kHz including 9 % pilot deviation; f_mod= 1 kHz; SNC = 0

α_cs

channel separation

MST = 0; R = 1 and L = 0 or R = 0 and

L = 1

V_RF= 30 µV; increasing RF input

level

27

-

33

-

dB

V_RF= 10 µV; decreasing RF input

1

level

[4]

V_sw

hys

switching voltage

hysteresis

17

3

25

45

4

µV

3.5

dB

Bus driven mute functions

Tuning mute; AFM = 1

α_mute(VAFR)

α_mute(VAFL)

α_mute

mute depth on pin VAFR

AFM = 1 or RHM = 1; ∆f = 75 kHz;

mono; B_aud= 300 Hz to 15 kHz;

A-weighting ﬁlter

−60

−80

-

dB

mute depth on pin VAFL

AFM = 1 or LHM = 1; ∆f = 75 kHz;

mono; B_aud= 300 Hz to 15 kHz;

A-weighting ﬁlter

mute depth on pins VAFL and MU = 1; ∆f = 75 kHz; mono;

VAFR _aud= 300 Hz to 15 kHz; A-weighting

B

ﬁlter

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

51 of 64

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Table 48: FM signal channel characteristics …continued

See Figure 1; all AC values are given in RMS; the min. and max. values include spread due to V_CCA= V_CCD= 2.5 V to 3.3 V

and T_amb= −20 °C to +85 °C; unless otherwise speciﬁed. All RF input values are deﬁned in potential difference, except when

EMF is explicitly stated.

Symbol

Parameter

Conditions

Min Typ Max Unit

RDS demodulator/decoder; ∆f = 22.5 kHz; f_AF= 1 kHz; L = R; TC_deem= 50 µs; DTC = 1; SYM1 = 0 and SYM0 = 0; average

over 2000 blocks

I_RDS

RDS current

I_CCDcurrent when RDS is running

0.3

0.7

1.5

mA

V_sens

RDS sensitivity EMF value

∆f = 22.5 kHz; f_AF= 1 kHz; L = R;

SYM1 = 0 and SYM0 = 0

block quality rate ≥ 85 %;

∆f_RDS= 1.2 kHz

-

24.7 32.5 µV

15 26 µV

57.5 kHz

block quality rate ≥ 95 %;

∆f_RDS= 2 kHz

f_center

ﬁlter center frequency

Bandwidth

56.5 57

B

2.5

3

3.5

kHz

Pause detector

f_{th(det)(pause)}

pause detection threshold

frequency

f_mod= 1 kHz; L = R; PL0 = 0; PL1 = 0

0.7

1.0

1.4

kHz

[1] Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.

[2] When bit STEREO is at logic 1 the frequency is between 2.5 kHz and 5.8 kHz; when bit STEREO is at logic 0 the frequency is 0 kHz.

[3] With increasing input levels the radio switches gradually from mono to stereo.

[4] The mono stereo switching level is the RF input level for switching from mono to stereo.

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001aac797

4.0

0

(1)

(2)

THD, N

(%)

(dB)

−20

−40

−60

−80

3.0

2.0

1.0

(3)

0

−7

−6

−5

−4

−3

−2

−1

10

1

V

(V)

RF

(1) Mono signal, soft mute off (f_FM= 22.5 kHz; f_AF= 1 kHz)

(2) Noise in mono mode, soft mute off

(3) Total harmonic distortion, ∆f = 75 kHz (f_FM= 75 kHz; f_AF= 1 kHz)

V_CCA= 2.7 V; T_amb= 25 °C; AF_out: A-weighting ﬁlter, BP ﬁlter: 300 Hz to 15 kHz

0 dB = 72 mV at 2 µV RF

−3 dB = 0.8 µV

26 dB = 1.2 µV

RF = 98 MHz

Measurements/decade: 12

Fig 15. Mono characteristics

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001aac798

4.0

0

(1)

(2)

THD, N

(%)

(dB)

−20

−40

−60

−80

3.0

2.0

1.0

(3)

(4)

0

−7

−6

−5

−4

−3

−2

−1

10

1

V

(V)

RF

(1) V_AFLsignal, soft mute off (∆f_R= 67.5 kHz; f_AF= 1 kHz; ∆f_pilot= 6.75 kHz)

(2) V_AFRsignal, soft mute off (∆f_L= 67.5 kHz; f_AF= 1 kHz; ∆f_pilot= 6.75 kHz)

(3) Noise in stereo mode, soft mute off (∆f_L= 0 kHz; f_AF= 1 kHz; ∆f_pilot= 6.75 kHz)

(4) Total harmonic distortion, ∆f = 75 kHz (∆f_R= 67.5 kHz; f_AF= 1 kHz; ∆f_pilot= 6.75 kHz)

V_CCA= 2.7 V; T_amb= 25 °C; AF_out: A-weighting ﬁlter, BP ﬁlter: 300 Hz to 15 kHz; SNC = on

0 dB = 233 mV at 470 µV RF

26 dB = 1.1 µV

RF = 98 MHz

Measurements/decade: 12

Fig 16. Stereo characteristics

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001aac799

4.0

0

(1)

THD, N

(%)

(dB)

−20

−40

−60

−80

3.0

2.0

1.0

(2)

(3)

0

−7

−6

−5

−4

−3

−2

−1

10

1

V

(V)

RF

(1) Mono signal, soft mute on (f_FM= 22.5 kHz; f_AF= 1 kHz)

(2) Noise in mono mode, soft mute on

(3) Total harmonic distortion, ∆f = 100 kHz (f_FM= 100 kHz; f_AF= 1 kHz)

V_CCA= 2.7 V; T_amb= 25 °C; AF_out: A-weighting ﬁlter, BP ﬁlter: 300 Hz to 15 kHz; soft mute on

0 dB = 71 mV at 10 µV RF

26 dB = 1.3 µV

RF = 98 MHz

Measurements/decade: 12

Fig 17. Soft mute and overdrive characteristics

001aac800

−3

10

V

,

RFIN1

V

RFIN2

(V)

−4

10

−5

−6

−7

10

0

4

8

12

16

ADC output

Fig 18. ADC conversion levels

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16. Application information

Table 49: List of components

Symbol

D1, D2

L1

Parameter

Type

Manufacturer

Philips

varicap diode for VCO tuning

RF band ﬁlter coil

VCO coil

BB202

120 nH; Q_min= 20; tolerance: ±5 % Coilcraft; Murata

L2, L3

X1

33 nH; Q_min= 40; tolerance: ±2 %

Coilcraft; Murata

ACT

32.768 kHz crystal

ACT200; C_L= 12 pF;

∆f/f₀= ±20 ppm; see Section 15

R

C

10 kΩ; 47 kΩ; 100 kΩ

±10 % max

27 pF; 47 pF; 100 pF; 12 pF;

10 nF(2×); 33 nF(8×)

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17. Package outline

HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6 x 6 x 0.85 mm

SOT618-1

D

B

A

terminal 1

index area

A

E

1

c

detail X

C

e

1

y

1/2 e

e

v

M

C

b

C

A

B

1

11

20

w

L

21

10

e

E

h

2

1/2 e

1

30

terminal 1

index area

40

31

D

X

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

6.1

5.9

4.25

3.95

6.1

5.9

4.25

3.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

4.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT618-1

- - -

MO-220

- - -

Fig 19. Package outline SOT618-1 (HVQFN40)

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18. Soldering

18.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

18.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

18.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

18.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

18.5 Package related soldering information

Table 50: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

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[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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19. Revision history

Table 51: Revision history

Document ID

TEA5764HN_2

Modiﬁcations:

TEA5764HN_1

Release date Data sheet status

20050809 Product data sheet

Change notice Doc. number

Supersedes

-

TEA5764HN_1

• Speciﬁcation status changed from objective data sheet to product data sheet.

20050707 Objective data sheet 9397 750 13453

-

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20. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

21. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

23. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — wordmark and logo are trademarks of Koninklijke Philips

Electronics N.V.

22. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

24. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

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25. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

9

9.1

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 16

Interrupt clearing . . . . . . . . . . . . . . . . . . . . . . 17

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Interrupt ﬂags and behavior . . . . . . . . . . . . . . 19

Multiple interrupt events . . . . . . . . . . . . . . . . . 19

Data available ﬂag . . . . . . . . . . . . . . . . . . . . . 19

RDS synchronization ﬂag. . . . . . . . . . . . . . . . 19

IF frequency ﬂag . . . . . . . . . . . . . . . . . . . . . . 20

RSSI threshold ﬂag . . . . . . . . . . . . . . . . . . . . 20

Pause detection ﬂag. . . . . . . . . . . . . . . . . . . . 21

Frequency ready ﬂag . . . . . . . . . . . . . . . . . . . 22

Band limit ﬂag. . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 23

9.1.1

9.1.2

9.1.3

9.1.4

9.1.4.1

9.1.4.2

9.1.4.3

9.1.4.4

9.1.4.5

9.1.4.6

9.1.4.7

9.1.4.8

9.2

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

Functional description . . . . . . . . . . . . . . . . . . . 6

Low noise RF ampliﬁer . . . . . . . . . . . . . . . . . . 6

FM I/Q mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7

PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 7

Band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Local or long distance receive . . . . . . . . . . . . . 8

IF ﬁlter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 8

IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Voltage level generator and analog-to-digital

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hard mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Audio frequency mute. . . . . . . . . . . . . . . . . . . . 9

MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Signal dependent mono/stereo blend (stereo

noise cancellation) . . . . . . . . . . . . . . . . . . . . . 10

Software programmable port . . . . . . . . . . . . . 10

Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

RDS/RBDS . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RDS/RBDS demodulator . . . . . . . . . . . . . . . . 10

RDS data and clock direct . . . . . . . . . . . . . . . 11

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.11

8.12

10

RDS data processing . . . . . . . . . . . . . . . . . . . 23

DAV-A processing mode. . . . . . . . . . . . . . . . . 24

DAV-B processing mode / fast PI search mode 25

DAV-C reduced processing mode . . . . . . . . . 26

Synchronization . . . . . . . . . . . . . . . . . . . . . . . 28

Conditions for synchronization . . . . . . . . . . . . 28

Data overﬂow . . . . . . . . . . . . . . . . . . . . . . . . . 29

RDS ﬂag behavior during read action . . . . . . 30

Error detection and reporting . . . . . . . . . . . . . 31

RDS test modes. . . . . . . . . . . . . . . . . . . . . . . 31

Reading RDS data from the registers . . . . . . 31

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 31

Write and read mode . . . . . . . . . . . . . . . . . . . 31

Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 32

Register map . . . . . . . . . . . . . . . . . . . . . . . . . 34

Byte description . . . . . . . . . . . . . . . . . . . . . . . 34

10.1

10.2

10.3

10.4

10.4.1

10.4.2

10.5

10.6

10.7

10.8

8.13

8.13.1

8.13.2

8.13.3

8.14

11

11.1

11.2

11.3

11.4

8.15

8.16

8.17

8.18

8.19

8.19.1

8.19.2

12

13

14

15

16

17

18

18.1

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45

Thermal characteristics . . . . . . . . . . . . . . . . . 45

Static characteristics . . . . . . . . . . . . . . . . . . . 46

Dynamic characteristics. . . . . . . . . . . . . . . . . 47

Application information . . . . . . . . . . . . . . . . . 56

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 57

8.19.2.1 RDS/RBDS decoder . . . . . . . . . . . . . . . . . . . . 11

8.20

8.21

8.21.1

8.21.2

8.21.3

Audio pause detector . . . . . . . . . . . . . . . . . . . 11

Auto search and Preset mode . . . . . . . . . . . . 11

Search mode . . . . . . . . . . . . . . . . . . . . . . . . . 13

Preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Auto high-side and low-side injection stop

switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Muting during search or preset. . . . . . . . . . . . 14

RDS update/alternative frequency jump. . . . . 14

Muting during RDS update . . . . . . . . . . . . . . . 15

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 58

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 58

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 59

Package related soldering information. . . . . . 59

18.2

18.3

18.4

18.5

8.21.4

8.22

8.22.1

19

20

Revision history . . . . . . . . . . . . . . . . . . . . . . . 61

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 62

continued >>

TEA5764HN_2

Product data sheet

Rev. 02 — 9 August 2005

63 of 64

TEA5764HN

Philips Semiconductors

FM radio + RDS

21

22

23

24

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Contact information . . . . . . . . . . . . . . . . . . . . 62

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 9 August 2005

Document number: TEA5764HN_2

Published in The Netherlands


型号：	TEA5764HN
厂家：	NXP
描述：	FM radio + RDS FM收音机+ RDS 消费电路商用集成电路接收器集成电路
文件：	总64页 (文件大小：276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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