TJA1041T/N1,518 [NXP]
TJA1041 - High-speed CAN transceiver with standby and sleep mode SOIC 14-Pin;
| 型号： | TJA1041T/N1,518 |
| 厂家： | 
NXP |
| 描述： | TJA1041 - High-speed CAN transceiver with standby and sleep mode SOIC 14-Pin 电信 光电二极管 电信集成电路 |
| 文件： | 总26页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1041
High speed CAN transceiver
Rev. 06 — 5 December 2007
Product data sheet
1. General description
The TJA1041 provides an advanced interface between the protocol controller and the
physical bus in a Controller Area Network (CAN) node. The TJA1041 is primarily intended
for automotive high-speed CAN applications (up to 1 Mbit/s). The transceiver provides
differential transmit capability to the bus and differential receive capability to the CAN
controller. The TJA1041 is fully compatible to the ISO 11898 standard, and offers
excellent ElectroMagnetic Compatibility (EMC) performance, very low power
consumption, and passive behavior when supply voltage is off. The advanced features
include:
• Low-power management, supporting local and remote wake-up with wake-up source
recognition and the capability to control the power supply in the rest of the node
• Several protection and diagnosis functions including short circuits of the bus lines and
first battery connection
• Automatic adaptation of the I/O-levels, in line with the supply voltage of the controller
2. Features
2.1 Optimized for in-vehicle high speed communication
I Fully compatible with the ISO 11898 standard
I Communication speed up to 1 Mbit/s
I Very low ElectroMagnetic Emission (EME)
I Differential receiver with wide common-mode range, offering high ElectroMagnetic
Immunity (EMI)
I Passive behavior when supply voltage is off
I Automatic I/O-level adaptation to the host controller supply voltage
I Recessive bus DC voltage stabilization for further improvement of EME behavior
I Listen-only mode for node diagnosis and failure containment
I Allows implementation of large networks (more than 110 nodes)
2.2 Low-power management
I Very low-current in Standby and Sleep mode, with local and remote wake-up
I Capability to power-down the entire node, still allowing local and remote wake-up
I Wake-up source recognition
TJA1041
NXP Semiconductors
High speed CAN transceiver
2.3 Protection and diagnosis (detection and signalling)
I TXD dominant clamping handler with diagnosis
I RXD recessive clamping handler with diagnosis
I TXD-to-RXD short-circuit handler with diagnosis
I Overtemperature protection with diagnosis
I Undervoltage detection on pins VCC, VI/O and VBAT
I Automotive environment transient protected bus pins and pin VBAT
I Short-circuit proof bus pins and pin SPLIT (to battery and to ground)
I Bus line short-circuit diagnosis
I Bus dominant clamping diagnosis
I Cold start diagnosis (first battery connection)
3. Quick reference data
Table 1.
Symbol
VCC
Quick reference data
Parameter
Conditions
Min
4.75
2.8
5
Typ
Max
5.25
5.25
27
Unit
V
DC voltage on pin VCC
DC voltage on pin VI/O
DC voltage on pin VBAT
VBAT input current
operating range
-
-
-
-
-
-
-
VI/O
operating range
V
VBAT
operating range
V
IBAT
VBAT = 12 V
10
30
µA
V
VCANH
VCANL
VSPLIT
Vesd
DC voltage on pin CANH
DC voltage on pin CANL
DC voltage on pin SPLIT
electrostatic discharge voltage
0 V < VCC < 5.25 V; no time limit
0 V < VCC < 5.25 V; no time limit
0 V < VCC < 5.25 V; no time limit
Human Body Model (HBM)
pins CANH, CANL and SPLIT
pins TXD, RXD, VI/O and STB
all other pins
−27
−27
−27
+40
+40
+40
V
V
[1]
−6
-
-
-
-
-
+6
kV
kV
kV
ns
°C
−3
+3
−4
+4
tPD(TXD-RXD) propagation delay TXD to RXD
Tvj virtual junction temperature
VSTB = 0 V
40
−40
255
+150
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground).
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
SO14
-
Description
Version
SOT108-1
-
TJA1041T
TJA1041U
plastic small outline package; 14 leads; body width 3.9 mm
bare die; 1930 × 3200 × 380 µm
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
2 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
5. Block diagram
V
V
V
BAT
CC
3
I/O
5
10
TJA1041
7
1
INH
TXD
TEMPERATURE
PROTECTION
TIME-OUT
LEVEL
ADAPTOR
6
EN
13
12
CANH
CANL
DRIVER
14
STB
V
BAT
V
CC
9
8
WAKE
COMPARATOR
WAKE
MODE
CONTROL
+
FAILURE
DETECTOR
+
11
SPLIT
SPLIT
V
I/O
ERR
WAKE-UP
DETECTOR
V
BAT
RXD
RECESSIVE
DETECTION
LOW POWER
RECEIVER
V
I/O
V
CC
4
RXD
NORMAL
RECEIVER
2
mgu166
GND
Fig 1. Block diagram
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
3 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
14
13
12
11
10
9
TXD
STB
GND
CANH
CANL
SPLIT
V
CC
RXD
TJA1041T
V
V
BAT
I/O
EN
WAKE
ERR
8
INH
001aag909
Fig 2. Pin configuration
6.2 Pin description
Table 3.
Symbol
TXD
Pin description
Pin
1
Description
transmit data input
ground
GND
VCC
2
3
transceiver supply voltage input
RXD
4
receive data output; reads out data from the bus lines
I/O-level adapter voltage input
VI/O
5
EN
6
enable control input
INH
7
inhibit output for switching external voltage regulators
error and power-on indication output (active LOW)
local wake-up input
ERR
8
WAKE
VBAT
9
10
11
12
13
14
battery voltage input
SPLIT
CANL
CANH
STB
common-mode stabilization output
LOW-level CAN bus line
HIGH-level CAN bus line
standby control input (active LOW)
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
4 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
7. Functional description
The primary function of a CAN transceiver is to provide the CAN physical layer as
described in the ISO 11898 standard. In the TJA1041 this primary function is
complemented with a number of operating modes, fail-safe features and diagnosis
features, which offer enhanced system reliability and advanced power management
functionality.
7.1 Operating modes
The TJA1041 can be operated in five modes, each with specific features. Control pins
STB and EN select the operating mode. Changing between modes also gives access to a
number of diagnostics flags, available via pin ERR. The following sections describe the
five operating modes. Table 4 shows the conditions for selecting these modes. Figure 3
illustrates the mode transitions when VCC, VI/O and VBAT are present.
Table 4.
Control pins Internal flags
Operating mode selection[1]
Operating mode
Pin INH
STB
EN
UVNOM
UVBAT
pwon;
wake-up
X
X
set
X
X[2]
Sleep mode[3]
floating
H
cleared
set
one or both set Standby mode
both cleared
no change from Sleep mode floating
Standby mode from any
other mode
H
L
L
L
cleared
cleared
cleared
cleared
one or both set Standby mode
both cleared
H
no change from Sleep mode floating
Standby mode from any
other mode
H
H
one or both set Standby mode
H
both cleared
no change from Sleep mode floating
go-to-sleep command mode H[4]
from any other mode[4]
H
H
L
cleared
cleared
cleared
cleared
X
X
pwon/listen-only mode
normal mode[5]
H
H
H
[1] X = don’t care.
[2] Setting the pwon flag or the wake-up flag will clear the UVNOM flag.
[3] The transceiver directly enters Sleep mode and pin INH is set floating when the UVNOM flag is set (so after
the undervoltage detection time on either VCC or VI/O has elapsed before that voltage level has recovered).
[4] When go-to-sleep command mode is selected for longer than the minimum hold time of the go-to-sleep
command, the transceiver will enter Sleep mode and pin INH is set floating.
[5] On entering normal mode the pwon flag and the wake-up flag will be cleared.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
5 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
STB = H
and
EN = H
STB = H
and
EN = L
PWON/LISTEN-
ONLY MODE
NORMAL
MODE
STB = H
and
EN = H
STB = H
and
STB = H
and
STB = H
and
EN = L
EN = L
EN = H
STB = L
and
(EN = L or flag set)
STB = L
and
EN = H
STB = L and EN = H
and
flags cleared
STB = L
and
EN = L
GO-TO-SLEEP
COMMAND
MODE
STB = L and EN = H
and
STANDBY
MODE
flags cleared
STB = L
and
(EN = L or flag set)
flags cleared
and
STB = L
and
flag set
STB = H and EN = H
and
STB = H and EN = L
and
cleared
t > t
h(min)
UV
cleared
NOM
UV
NOM
SLEEP
MODE
LEGEND:
mgu983
= H, = L
flag set
flags cleared
logical state of pin
setting pwon and/or wake-up flag
pwon and wake-up flag both cleared
Fig 3. Mode transitions when VCC, VI/O and VBAT are present
7.1.1 Normal mode
Normal mode is the mode for normal bidirectional CAN communication. The receiver will
convert the differential analog bus signal on pins CANH and CANL into digital data,
available for output to pin RXD. The transmitter will convert digital data on pin TXD into a
differential analog signal, available for output to the bus pins. The bus pins are biased at
0.5VCC (via Ri(cm)). Pin INH is active, so voltage regulators controlled by pin INH (see
Figure 4) will be active too.
7.1.2 Pwon/listen-only mode
In pwon/listen-only mode the transmitter of the transceiver is disabled, effectively
providing a transceiver listen-only behavior. The receiver will still convert the analog bus
signal on pins CANH and CANL into digital data, available for output to pin RXD. As in
normal mode the bus pins are biased at 0.5VCC, and pin INH remains active.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
6 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
7.1.3 Standby mode
The Standby mode is the first-level power saving mode of the transceiver, offering reduced
current consumption. In Standby mode the transceiver is not able to transmit or receive
data and the low-power receiver is activated to monitor bus activity. The bus pins are
biased at ground level (via Ri(cm)). Pin INH is still active, so voltage regulators controlled
by this pin INH will be active too.
Pins RXD and ERR will reflect any wake-up requests (provided that VI/O and VCC are
present).
7.1.4 Go-to-sleep command mode
The go-to-sleep command mode is the controlled route for entering Sleep mode. In
go-to-sleep command mode the transceiver behaves as if in Standby mode, plus a
go-to-sleep command is issued to the transceiver. After remaining in go-to-sleep
command mode for the minimum hold time (th(min)), the transceiver will enter Sleep mode.
The transceiver will not enter the Sleep mode if the state of pins STB or EN is changed or
the UVBAT, pwon or wake-up flag is set before th(min) has expired.
7.1.5 Sleep mode
The Sleep mode is the second-level power saving mode of the transceiver. Sleep mode is
entered via the go-to-sleep command mode, and also when the undervoltage detection
time on either VCC or VI/O elapses before that voltage level has recovered. In Sleep mode
the transceiver still behaves as described for Standby mode, but now pin INH is set
floating. Voltage regulators controlled by pin INH will be switched off, and the current into
pin VBAT is reduced to a minimum. Waking up a node from Sleep mode is possible via the
wake-up flag and (as long as the UVNOM flag is not set) via pin STB.
7.2 Internal flags
The TJA1041 makes use of seven internal flags for its fail-safe fallback mode control and
system diagnosis support. Table 4 shows the relation between flags and operating modes
of the transceiver. Five of the internal flags can be made available to the controller via pin
ERR. Table 5 shows the details on how to access these flags. The following sections
describe the seven internal flags.
Table 5.
Accessing internal flags via pin ERR
Internal flag Flag is available on pin ERR[1]
Flag is cleared
UVNOM
no
no
by setting the pwon or wake-up
flag
UVBAT
pwon
when VBAT has recovered
on entering normal mode
in pwon/listen-only mode (coming from
Standby mode, go-to-sleep command mode,
or Sleep mode)
wake-up
in Standby mode, go-to-sleep command
mode, and Sleep mode (provided that VI/O
and VCC are present)
on entering normal mode, or by
setting the pwon or UVNOM flag
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
7 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
Table 5.
Accessing internal flags via pin ERR …continued
Internal flag Flag is available on pin ERR[1]
Flag is cleared
wake-up
source
in normal mode (before the fourth dominant to on leaving normal mode, or by
recessive edge on pin TXD[2])
setting the pwon flag
bus failure
in normal mode (after the fourth dominant to on re-entering normal mode
recessive edge on pin TXD[2]
local failure
in pwon/listen-only mode (coming from
normal mode)
on entering normal mode or when
RXD is dominant while TXD is
recessive (provided that all local
failures are resolved)
[1] Pin ERR is an active-LOW output, so a LOW level indicates a set flag and a HIGH level indicates a cleared
flag. Allow pin ERR to stabilize for at least 8 µs after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 µs per dominant-recessive cycle.
7.2.1 UVNOM flag
UVNOM is the VCC and VI/O undervoltage detection flag. The flag is set when the voltage
on pin VCC drops below VCC(sleep) for longer than tUV(VCC) or when the voltage on pin VI/O
drops below VI/O(sleep) for longer than tUV(VI/O). When the UVNOM flag is set, the transceiver
will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage
regulators connected to pin INH are disabled, avoiding the extra power consumption in
case of a short-circuit condition. After a waiting time (fixed by the same timers used for
setting UVNOM) any wake-up request or setting of the pwon flag will clear UVNOM and the
timers, allowing the voltage regulators to be reactivated at least until UVNOM is set again.
7.2.2 UVBAT flag
UVBAT is the VBAT undervoltage detection flag. The flag is set when the voltage on pin VBAT
drops below VBAT(stb). When UVBAT is set, the transceiver will try to enter Standby mode to
save power and not disturb the bus. UVBAT is cleared when the voltage on pin VBAT has
recovered. The transceiver will then return to the operating mode determined by the logic
state of pins STB and EN.
7.2.3 Pwon flag
Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT has
recovered after it dropped below VBAT(pwon), particularly after the transceiver was
disconnected from the battery. By setting the pwon flag, the UVNOM flag and timers are
cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage
regulator connected to pin INH is activated when the node is reconnected to the battery. In
pwon/listen-only mode the pwon flag can be made available on pin ERR. The flag is
cleared when the transceiver enters normal mode.
7.2.4 Wake-up flag
The wake-up flag is set when the transceiver detects a local or a remote wake-up request.
A local wake-up request is detected when a logic state change on pin WAKE remains
stable for at least twake. A remote wake-up request is detected when the bus remains in
dominant state for at least tBUS. The wake-up flag can only be set in Standby mode,
go-to-sleep command mode or Sleep mode. Setting of the flag is blocked during the
UVNOM flag waiting time. By setting the wake-up flag, the UVNOM flag and timers are
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
8 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
cleared. The wake-up flag is immediately available on pins ERR and RXD (provided that
VI/O and VCC are present). The flag is cleared at power-on, or when the UVNOM flag is set
or the transceiver enters normal mode.
7.2.5 Wake-up source flag
Wake-up source recognition is provided via the wake-up source flag, which is set when
the wake-up flag is set by a local wake-up request via pin WAKE. The wake-up source flag
can only be set after the pwon flag is cleared. In normal mode the wake-up source flag
can be made available on pin ERR. The flag is cleared at power-on or when the
transceiver leaves normal mode.
7.2.6 Bus failure flag
The bus failure flag is set if the transceiver detects a bus line short-circuit condition to
VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, when
trying to drive the bus lines dominant. In normal mode the bus failure flag can be made
available on pin ERR. The flag is cleared when the transceiver re-enters normal mode.
7.2.7 Local failure flag
In normal mode or pwon/listen-only mode the transceiver can recognize five different local
failures, and will combine them into one local failure flag. The five local failures are: TXD
dominant clamping, RXD recessive clamping, a TXD-to-RXD short circuit, bus dominant
clamping, and overtemperature. The nature and detection of these local failures is
described in Section 7.3 “Local failures”. In pwon/listen-only mode the local failure flag can
be made available on pin ERR. The flag is cleared when entering normal mode or when
RXD is dominant while TXD is recessive, provided that all local failures are resolved.
7.3 Local failures
The TJA1041 can detect five different local failure conditions. Any of these failures will set
the local failure flag, and in most cases the transmitter of the transceiver will be disabled.
The following sections give the details.
7.3.1 TXD dominant clamping detection
A permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communication. The TXD dominant time-out function prevents such a network lock-up by
disabling the transmitter of the transceiver if pin TXD remains at a LOW level for longer
than the TXD dominant time-out tdom(TXD). The tdom(TXD) timer defines the minimum
possible bit rate of 40 kbit/s. The transmitter remains disabled until the local failure flag is
cleared.
7.3.2 RXD recessive clamping detection
An RXD pin clamped to HIGH level will prevent the controller connected to this pin from
recognizing a bus dominant state. So the controller can start messages at any time, which
is likely to disturb all bus communication. RXD recessive clamping detection prevents this
effect by disabling the transmitter when the bus is in dominant state without RXD reflecting
this. The transmitter remains disabled until the local failure flag is cleared.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
9 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
7.3.3 TXD-to-RXD short-circuit detection
A short-circuit between pins RXD and TXD would keep the bus in a permanent dominant
state once the bus is driven dominant, because the low-side driver of RXD is typically
stronger than the high-side driver of the controller connected to TXD. The TXD-to-RXD
short-circuit detection prevents such a network lock-up by disabling the transmitter. The
transmitter remains disabled until the local failure flag is cleared.
7.3.4 Bus dominant clamping detection
A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The local failure flag is set if the dominant state on the bus persists for
longer than tdom(bus). By checking this flag, the controller can determine if a clamped bus is
blocking network communication. There is no need to disable the transmitter. Note that
the local failure flag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
7.3.5 Overtemperature detection
To protect the output drivers of the transceiver against overheating, the transmitter will be
disabled if the virtual junction temperature exceeds the shutdown junction temperature
Tj(sd). The transmitter remains disabled until the local failure flag is cleared.
7.4 Recessive bus voltage stabilization
In recessive state the output impedance of transceivers is relatively high. In a partially
powered network (supply voltage is off in some of the nodes) any deactivated transceiver
with a significant leakage current is likely to load the recessive bus to ground. This will
cause a common-mode voltage step each time transmission starts, resulting in increased
EME. Using pin SPLIT of the TJA1041 in combination with split termination (see Figure 5)
will reduce this step effect. In normal mode and pwon/listen-only mode pin SPLIT provides
a stabilized 0.5VCC DC voltage. In Standby mode, go-to-sleep command mode and Sleep
mode, pin SPLIT is set floating.
7.5 I/O level adapter
The TJA1041 is equipped with a built-in I/O-level adapter. By using the supply voltage of
the controller (to be supplied at pin VI/O) the level adapter ratio-metrically scales the
I/O-levels of the transceiver. For pins TXD, STB and EN the digital input threshold level is
adjusted, and for pins RXD and ERR the HIGH-level output voltage is adjusted. This
allows the transceiver to be directly interfaced with controllers on supply voltages between
2.8 V and 5.25 V, without the need for glue logic.
7.6 Pin WAKE
Pin WAKE of the TJA1041 allows local wake-up triggering by a LOW-to-HIGH state
change as well as a HIGH-to-LOW state change. This gives maximum flexibility when
designing a local wake-up circuit. To keep current consumption at a minimum, after a twake
delay the internal bias voltage of pin WAKE will follow the logic state of this pin. A HIGH
level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
10 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
followed by an internal pull-down towards GND. To ensure EMI performance in
applications not using local wake-up it is recommended to connect pin WAKE to pin VBAT
or to pin GND.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
−0.3
4.75
−0.3
2.8
Max
Unit
V
VCC
DC voltage on pin VCC
no time limit
operating range
no time limit
operating range
no time limit
operating range
load dump
+6
5.25
V
VI/O
DC voltage on pin VI/O
DC voltage on pin VBAT
+6
V
5.25
V
VBAT
−0.3
5
+40
V
27
V
-
40
V
VTXD
VRXD
VSTB
VEN
DC voltage on pin TXD
DC voltage on pin RXD
DC voltage on pin STB
DC voltage on pin EN
DC voltage on pin ERR
DC voltage on pin INH
DC voltage on pin WAKE
DC current on pin WAKE
DC voltage on pin CANH
DC voltage on pin CANL
DC voltage on pin SPLIT
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
-
VI/O + 0.3
VI/O + 0.3
VI/O + 0.3
VI/O + 0.3
VI/O + 0.3
VBAT + 0.3
VBAT + 0.3
−15
V
V
V
V
VERR
VINH
V
V
VWAKE
IWAKE
VCANH
VCANL
VSPLIT
Vtrt
V
mA
V
0 V < VCC < 5.25 V; no time limit
0 V < VCC < 5.25 V; no time limit
0 V < VCC < 5.25 V; no time limit
−27
−27
−27
−200
+40
+40
V
+40
V
transient voltages on pins CANH,
CANL, SPLIT and VBAT
according to ISO 7637; see
Figure 6
+200
V
[1]
Vesd
electrostatic discharge voltage
Human Body Model (HBM)
pins CANH, CANL and SPLIT
pins TXD, RXD, VI/O and STB
all other pins
−6
+6
kV
kV
kV
V
−3
+3
−4
+4
[2]
[3]
Machine Model (MM)
−200
−40
−55
+200
+150
+150
Tvj
virtual junction temperature
storage temperature
°C
°C
Tstg
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (6 kV level with pin GND connected to ground).
[2] Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor and a 10 Ω series resistor.
[3] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tvj = Tamb + P × Rth(vj-amb), where Rth(vj-amb) is a fixed
value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
11 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
9. Thermal characteristics
Table 7.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance from junction SO14 package; in
to ambient free air
Conditions
Typ
Unit
120
K/W
Rth(j-s)
thermal resistance from junction bare die; in free air
to substrate
40
K/W
10. Characteristics
Table 8.
Characteristics
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless specified
otherwise; all voltages are defined with respect to ground; positive currents flow into the device.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies (pins VBAT, VCC and VI/O
)
VCC(sleep)
VI/O(sleep)
VBAT(stb)
VBAT(pwon)
ICC
VCC undervoltage detection
level for forced Sleep mode
VBAT = 12 V (fail-safe)
2.75
0.5
2.75
2.5
25
3.3
1.5
3.3
3.3
55
6
4.5
2
V
VI/O undervoltage detection
level for forced Sleep mode
V
VBAT voltage level for fail-safe
fallback mode
VCC = 5 V (fail-safe)
VCC = 0 V
4.5
4.1
80
10
V
VBAT voltage level for setting
pwon flag
V
VCC input current
VI/O input current
VBAT input current
normal mode; VTXD = 0 V
(dominant)
mA
mA
normal or pwon/listen-only
mode; VTXD = VI/O (recessive)
2
Standby or Sleep mode
-
1
10
µA
µA
II/O
normal mode; VTXD = 0 V
(dominant)
100
350
1000
normal or pwon/listen-only
mode; VTXD = VI/O (recessive)
15
80
200
µA
Standby or Sleep mode
-
0
5
µA
µA
IBAT
normal or pwon/listen-only
mode
15
30
40
Standby mode; VCC > 4.75 V;
10
10
20
20
30
30
µA
µA
VI/O = 2.8 V;
VINH = VWAKE = VBAT = 12 V
Sleep mode;
VINH = VCC = VI/O = 0 V;
VWAKE = VBAT = 12 V
Transmitter data input (pin TXD)
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
0.7VI/O
−0.3
−5
-
VCC + 0.3
+0.3VI/O
+5
V
-
V
normal or pwon/listen-only
mode; VTXD = VI/O
0
µA
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
12 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
Table 8.
Characteristics …continued
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless specified
otherwise; all voltages are defined with respect to ground; positive currents flow into the device.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL
LOW-level input current
normal or pwon/listen-only
mode; VTXD = 0.3VI/O
−70
−250
−500
µA
Ci
input capacitance
not tested
-
5
10
pF
Receiver data output (pin RXD)
IOH
IOL
HIGH-level output current
LOW-level output current
VRXD = VI/O − 0.4 V; VI/O = VCC
−1
−3
−6
mA
mA
VRXD = 0.4 V; VTXD = VI/O; bus
dominant
2
5
12
Standby and enable control inputs (pins STB and EN)
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
LOW-level input current
0.7VI/O
-
VCC + 0.3
+0.3VI/O
10
V
−0.3
-
V
VSTB = VEN = 0.7VI/O
VSTB = VEN = 0 V
1
-
4
0
µA
µA
IIL
−1
Error and power-on indication output (pin ERR)
IOH
IOL
HIGH-level output current
LOW-level output current
VERR = VI/O − 0.4 V; VI/O = VCC
−4
−20
−50
µA
VERR = 0.4 V
0.1
0.2
0.35
mA
Local wake-up input (pin WAKE)
IIH
IIL
HIGH-level input current
LOW-level input current
threshold voltage
VWAKE = VBAT − 1.9 V
VWAKE = VBAT − 3.1 V
VSTB = 0 V
−1
−5
−10
µA
µA
V
1
5
10
Vth
VBAT − 3
VBAT − 2.5
VBAT − 2
Inhibit output (pin INH)
∆VH
|IL|
HIGH-level voltage drop
leakage current
IINH = −0.18 mA
0.05
-
0.2
0
0.8
5
V
Sleep mode
µA
Bus lines (pins CANH and CANL)
VO(dom)
dominant output voltage
VTXD = 0 V
pin CANH
pin CANL
3
3.6
1.4
-
4.25
V
V
V
0.5
−0.1
1.75
VO(dom)(m)
VO(dif)(bus)
matching of dominant output
voltage (VCC - VCANH - VCANL
+0.15
)
differential bus output voltage VTXD = 0 V (dominant);
1.5
-
3.0
V
(VCANH - VCANL
)
45 Ω < RL < 65 Ω
VTXD = VI/O (recessive); no load
−50
-
+50
3
mV
V
VO(reces)
recessive output voltage
short-circuit output current
normal or pwon/listen-only
mode; VTXD = VI/O; no load
2
0.5VCC
Standby or Sleep mode; no load −0.1
0
+0.1
V
IO(sc)
VTXD = 0 V (dominant)
pin CANH; VCANH = 0 V
pin CANL; VCANL = 40 V
−27 V < VCAN < 32 V
−45
45
−70
70
-
−95
95
mA
mA
mA
IO(reces)
recessive output current
−2.5
+2.5
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
13 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
Table 8.
Characteristics …continued
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless specified
otherwise; all voltages are defined with respect to ground; positive currents flow into the device.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdif(th)
differential receiver threshold
voltage
normal or pwon/listen-only
mode; see Figure 7;
0.5
0.7
0.9
V
−12 V < VCANH < 12 V;
−12 V < VCANL < 12 V
Standby or Sleep mode;
−12 V < VCANH < 12 V;
−12 V < VCANL < 12 V
0.4
50
0.7
70
1.15
100
V
Vhys(dif)
differential receiver hysteresis normal or pwon/listen-only
mV
voltage
mode; see Figure 7;
−12 V < VCANH < 12 V;
−12 V < VCANL < 12 V
ILI
input leakage current
VCC = 0 V; VCANH = VCANL = 5 V
100
15
170
25
250
35
µA
kΩ
Ri(cm)
common-mode input
resistance
Ri(cm)(m)
common-mode input
resistance matching
VCANH = VCANL
−3
0
+3
%
Ri(dif)
Ci(cm)
differential input resistance
25
-
50
-
75
20
kΩ
common-mode input
capacitance
VTXD = VCC; not tested
pF
Ci(dif)
differential input capacitance
VTXD = VCC; not tested
normal mode
-
-
-
10
50
pF
Rsc(bus)
detectable short-circuit
0
Ω
resistance between bus lines
and VBAT, VCC and GND
Common-mode stabilization output (pin SPLIT)
Vo
output voltage
normal or pwon/listen-only
mode;
0.3VCC
0.5VCC
0.7VCC
V
−500 µA < ISPLIT < 500 µA
|IL|
leakage current
Standby or Sleep mode;
-
0
5
µA
−22 V < VSPLIT < 35 V
Timing characteristics; see Figure 8 and Figure 9
td(TXD-BUSon) delay TXD to bus active
td(TXD-BUSoff) delay TXD to bus inactive
td(BUSon-RXD) delay bus active to RXD
normal mode
25
10
15
70
50
65
110
95
ns
ns
ns
normal mode
normal or pwon/listen-only
mode
115
td(BUSoff-RXD) delay bus inactive to RXD
normal or pwon/listen-only
mode
35
100
160
ns
tPD(TXD-RXD) propagation delay TXD to RXD VSTB = 0 V
40
5
-
255
ns
tUV(VCC)
undervoltage detection time on
VCC
10
12.5
ms
tUV(VI/O)
undervoltage detection time on
VI/O
5
10
12.5
ms
tdom(TXD)
tdom(bus)
th(min)
TXD dominant time-out
bus dominant time-out
VTXD = 0 V
Vdif > 0.9 V
300
300
20
600
600
35
1000
1000
50
µs
µs
µs
minimum hold time of
go-to-sleep command
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
14 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
Table 8.
Characteristics …continued
VCC = 4.75 V to 5.25 V; VI/O = 2.8 V to VCC; VBAT = 5 V to 27 V; RL = 60 Ω; Tvj = −40 °C to +150 °C; unless specified
otherwise; all voltages are defined with respect to ground; positive currents flow into the device.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBUS
dominant time for wake-up via Standby or Sleep mode;
0.75
1.75
5
µs
bus
V
BAT = 12 V
Standby or Sleep mode;
BAT = 12 V
twake
minimum wake-up time after
receiving a falling or rising
edge
5
25
50
µs
V
Thermal shutdown
Tj(sd) shutdown junction temperature
155
165
180
°C
[1] All parameters are guaranteed over the virtual junction temperature range by design, but only 100 % tested at Tamb = 125 °C for dies on
wafer level and in addition to this, 100 % tested at Tamb = 125 °C for cased products, unless specified otherwise. For bare dies, all
parameters are only guaranteed with the reverse side of the die connected to ground.
11. Application information
3 V
5 V
BAT
V
V
V
I/O
BAT
CC
INH
V
CC
STB
EN
WAKE
GND
Port x, y, z
ERR
MICRO-
CONTROLLER
TJA1041
RXD
TXD
RXD
TXD
CANH
CANL
SPLIT
mgu173
CAN bus wires
Fig 4. Typical application with 3 V microcontroller
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
15 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
V
CC
TJA1041
CANH
SPLIT
CANL
R
60 Ω
V
= 0.5V
CC
SPLIT
V
in normal mode
and pwon/listen-only
mode;
SPLIT
R
60 Ω
otherwise floating
mgu169
GND
Fig 5. Stabilization circuitry and application
+12 V
+5 V
47 µF
100 nF
V
I/O
V
CC
V
10 µF
BAT
5
3
10
1 nF
TXD
EN
CANH
CANL
1
13
12
TRANSIENT
GENERATOR
6
1 nF
STB
14
9
WAKE
SPLIT
ERR
INH
TJA1041
11
8
500 kHz
7
RXD
4
2
GND
mgw337
The waveforms of the applied transients will be in accordance with ISO 7637 part 1, test pulses
1, 2, 3a, 3b, 5, 6 and 7.
Fig 6. Test circuit for automotive transients
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
16 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
V
RXD
HIGH
LOW
hysteresis
0.5
0.9
V
(V)
i(dif)(bus)
mgs378
Vi(dif)(bus) = VCANH - VCANL
.
Fig 7. Hysteresis of the receiver
+12 V
+5 V
47 µF
100 nF
V
V
V
BAT
10 µF
I/O
CC
5
3
10
TXD
EN
CANH
1
13
R
60 Ω
C
L
100 pF
L
6
STB
CANL
SPLIT
ERR
INH
14
9
12
11
8
WAKE
TJA1041
7
RXD
4
2
15 pF
mgw338
GND
Fig 8. Test circuit for timing characteristics
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
17 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
HIGH
LOW
TXD
CANH
CANL
dominant
(BUS on)
0.9 V
0.5 V
(1)
V
i(dif)(bus)
recessive
(BUS off)
HIGH
0.7V
CC
RXD
0.3V
CC
LOW
t
t
d(TXD-BUSon)
t
d(TXD-BUSoff)
t
d(BUSon-RXD)
d(BUSoff-RXD)
t
t
PD(TXD-RXD)
PD(TXD-RXD)
mgs377
(1) Vi(dif)(bus) = VCANH - VCANL
.
Fig 9. Timing diagram
12. Test information
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for
use in automotive applications.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
18 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
13. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
19 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
14. Bare die outline
1
14
2
3
13
12
4
TJA1041U
11
10
5
9
x
0
6
7
8
0
mgu984
y
The reverse side of the bare die must be connected to ground.
Fig 11. Bonding pad locations
Table 9.
Symbol
Bonding pad locations
Pad
Coordinates[1]
x
y
TXD
GND
VCC
1
664.25
75.75
115.5
115.5
115.5
264.5
667.75
1076.75
1765
1765
1765
1765
1751
940.75
3004.5
3044.25
2573
1862.75
115.5
114
2
3
RXD
VI/O
4
5
EN
6
INH
7
85
ERR
WAKE
VBAT
SPLIT
CANL
CANH
STB
8
115.5
85
9
10
11
12
13
14
792.5
1442.25
2115
3002.5
3004.5
[1] All x/y coordinates represent the position of the center of each pad (in µm) with respect to the left hand
bottom corner of the top aluminium layer.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
20 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
15. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
21 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 11. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
22 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
23 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
16. Revision history
Table 12. Revision history
Document ID
TJA1041_6
Modifications:
TJA1041_5
TJA1041_4
TJA1041_3
TJA1041_N_2
TJA1041_1
Release date
20071205
Data sheet status
Change notice
Supersedes
Product data sheet
-
TJA1041_5
• Table 1 and Table 6: changed conditions electrostatic discharge voltage
20070831
20031014
20030213
20021223
20011218
Product data sheet
-
-
-
-
-
TJA1041_4
TJA1041_3
TJA1041_N_2
TJA1041_1
-
Product specification
Product specification
Preliminary specification
Preliminary specification
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
24 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Limiting values — Stress above one or more limiting values (as defined in
17.2 Definitions
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
17.3 Disclaimers
Bare die — All die are tested on compliance with all related technical
specifications as stated in this data sheet up to the point of wafer sawing for a
period of ninety (90) days from the date of delivery by NXP Semiconductors.
If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There are no post-packing tests performed on
individual die or wafers.
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TJA1041_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 5 December 2007
25 of 26
TJA1041
NXP Semiconductors
High speed CAN transceiver
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
15
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Introduction to soldering. . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22
15.1
15.2
15.3
15.4
2
2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Optimized for in-vehicle high speed
communication . . . . . . . . . . . . . . . . . . . . . . . . . 1
Low-power management . . . . . . . . . . . . . . . . . 1
Protection and diagnosis (detection and
2.2
2.3
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . 24
signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
17
Legal information . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
17.1
17.2
17.3
17.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 25
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pwon/listen-only mode . . . . . . . . . . . . . . . . . . . 6
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Go-to-sleep command mode . . . . . . . . . . . . . . 7
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Internal flags. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wake-up flag. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Wake-up source flag. . . . . . . . . . . . . . . . . . . . . 9
Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . . 9
Local failure flag . . . . . . . . . . . . . . . . . . . . . . . . 9
Local failures. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TXD dominant clamping detection . . . . . . . . . . 9
RXD recessive clamping detection. . . . . . . . . . 9
TXD-to-RXD short-circuit detection . . . . . . . . 10
Bus dominant clamping detection. . . . . . . . . . 10
Overtemperature detection. . . . . . . . . . . . . . . 10
Recessive bus voltage stabilization . . . . . . . . 10
I/O level adapter . . . . . . . . . . . . . . . . . . . . . . . 10
Pin WAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal characteristics. . . . . . . . . . . . . . . . . . 12
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 15
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Quality information . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 20
9
10
11
12
12.1
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 December 2007
Document identifier: TJA1041_6
相关型号：
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