TZA3012AHW [NXP]
30 Mbits/s up to 3.2 Gbits/s A-rateTM Fibre Optic Receiver; 30兆位/秒高达3.2 Gb / s的A- rateTM光纤接收器
| 型号： | TZA3012AHW |
| 厂家： | 
NXP |
| 描述： | 30 Mbits/s up to 3.2 Gbits/s A-rateTM Fibre Optic Receiver |
| 文件： | 总60页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TZA3012AHW
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
Product specification
2003 May 21
Supersedes data of 2002 Sep 10
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
FEATURES
• Single 3.3 V power supply
• I2C-bus and pin programmable fibre optic receiver.
Dual limiter features
• Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
• Dual limiting input with 12 mV sensitivity
• Received Signal Strength Indicator (RSSI)
• Loss Of Signal (LOS) indicator with threshold adjust
• Differential overvoltage protection.
• Reversible pin designations of parallel data bus bits for
optimum connectivity
• Slice level adjustment to improve Bit Error Rate (BER)
• Mute function for a forced logic 0 output state
• Programmable parity
Data and clock recovery features
• Supports SHD/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC)
• Programmable 32-bit frame detection.
• Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
• Supports Fibre Channel at 1062.5 and 2125 Mbits/s
• ITU-T compliant jitter tolerance
APPLICATIONS
• Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
• Frequency lock indicator
• Physical interface IC in receive channels
• Transponder applications
• Stable clock signal when input data absent
• Outputs for recovered data and clock loop mode.
• Dense Wavelength Division Multiplexing (DWDM)
Demultiplexer features
systems.
• 1:16, 1:10, 1:8 or 1:4 demultiplexing ratio
• LVPECL or CML demultiplexer outputs
• Frame detection for SDH/SONET and GE frames
• Parity bit generation
GENERAL DESCRIPTION
The TZA3012AHW is a fully integrated optical network
receiver containing a dual limiter, Data and Clock
Recovery (DCR) and a demultiplexer with demultiplexing
ratios 1:16, 1:10, 1:8 or 1:4.
• Loop mode inputs to demultiplexer.
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The receiver supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the receiver is
Additional features with the I2C-bus
• A-rateTM(1) supports any bit rate from 30 Mbits/s to
3.2 Gbits/s with one reference frequency
• Programmable frequency resolution of 10 Hz
• Four reference frequency ranges
• Adjustable swing of data, clock and parallel outputs
• Programmable polarity of all RF I/Os
programmable by pin or via the I2C-bus.
(1) A-rate is a Trademark of Koninklijke Philips Electronics N.V.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TZA3012AHW
HTQFP100
plastic thermal enhanced thin quad flat package; 100 leads;
SOT638−1
body 14 × 14 × 1 mm; exposed die pad
2003 May 21
2
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CLOOP
DLOOPQ CLOOPQ
DLOOP
DMXR0
ENBA DMXR1
LOS1
5
ENLINQ
91
RSSI1
6
87 88 84 85
52 30 31
7
38
39
PARITY
PARITYQ
LOSTH1
LOS
44, 46, 48, 53
55, 57, 59, 61,
64, 66, 68, 70
72, 77, 79, 81
RSSI
LIM
12
9
INSEL
IN1
PARITY
GENERATOR
AND
TZA3012AHW
c
16
16
D00
to D15
DMX
1 : 4
1 : 8
1 : 10
1 : 16
d
10
BUS SWAP
IN1Q
16
45, 47, 49, 54
56, 58, 60, 62,
65, 67, 69, 71
73, 78, 80, 82
SWITCH
PHASE
DETECTOR
2
2
d
c
16
17
IN2
D00Q
to D15Q
LIM
IN2Q
41
42
POCLK
2
POCLKQ
LPF
2
36
37
FP
RSSI
LOS
FPQ
FREQUENCY
WINDOW DETECTOR
19
94
95
COUT
LOSTH2
COUTQ
24
23
SCL(DR2)
SDA(DR1)
97
98
2
DOUT
I C-BUS
22
4
CS(DR0)
UI
DOUTQ
92
INTERRUPT
INT
CONTROLLER
28, 29
14
2
i.c.
1, 35, 40, 43, 51
75, 76, 83, 86,
89, 93, 96, 99
RREF
26, 50, 63,
74, 100
8, 11,
15, 18
20
21 13 33 34 27
2
3
90
32
25
MGU314
13
V
4
RSSI2
LOS2
CREFQ
CREF
WINSIZE INWINDOW
PRSCLOQ
V
DD
V
V
V
EE
PRSCLO
CCA
CCD
CCO
ENLOUTQ
LIM = Limiting amplifier.
RSSI = Receiving Signal Strength Indicator.
LOS = Loss Of Signal detector.
LPF = Low-Pass Filter.
DMX = Demultiplexer.
Fig.1 Simplified block diagram.
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PINNING
SYMBOL
PIN
DESCRIPTION
SYMBOL
VEE
PIN
DESCRIPTION
VCCO
CREF
CREFQ
VCCD
FP
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
supply voltage (clock generator)
reference clock input
die pad common ground plane
VCCD
1
2
3
4
5
supply voltage (digital part)
prescaler output
reference clock inverted input
supply voltage (digital part)
frame pulse output
PRSCLO
PRSCLOQ
UI
prescaler inverted output
user interface select
FPQ
frame pulse inverted output
parity output
LOS1
first input channel loss of signal
output
PARITY
PARITYQ
VCCD
POCLK
POCLKQ
VCCD
D00
parity inverted output
RSSI1
6
7
first input channel received
signal strength indicator output
supply voltage (digital part)
parallel clock output
LOSTH1
first input channel loss of signal
threshold input
parallel clock inverted output
supply voltage (digital part)
parallel data 00 output
VCCA
8
supply voltage (analog part)
first channel input
IN1
9
D00Q
D01
parallel data 00 inverted output
parallel data 01 output
IN1Q
10
11
12
13
first channel inverted input
supply voltage (analog part)
input selector
VCCA
D01Q
D02
parallel data 01 inverted output
parallel data 02 output
INSEL
WINSIZE
wide and narrow frequency
detect window select
D02Q
VEE
parallel data 02 inverted output
ground
RREF
VCCA
14
15
16
17
18
19
reference resistor input
VCCD
ENBA
D03
supply voltage (digital part)
byte alignment enable input
parallel data 03 output
supply voltage (analog part)
second channel input
IN2
IN2Q
VCCA
second channel inverted input
supply voltage (analog part)
D03Q
D04
parallel data 03 inverted output
parallel data 04 output
LOSTH2
second input channel loss of
signal threshold input
D04Q
D05
parallel data 04 inverted output
parallel data 05 output
RSSI2
LOS2
20
21
second input channel received
signal strength indicator output
D05Q
D06
parallel data 05 inverted output
parallel data 06 output
LOS output of second input
channel
D06Q
D07
parallel data 06 inverted output
parallel data 07 output
CS(DR0)
22
23
chip select (data rate select 0)
I2C-bus serial data (data rate
select 1)
I2C-bus serial clock (data rate
select 2)
SDA(DR1)
D07Q
VEE
parallel data 07 inverted output
ground
SCL(DR2)
24
D08
parallel data 08 output
D08Q
D09
parallel data 08 inverted output
parallel data 09 output
VDD
25
26
27
supply voltage (digital part)
ground
VEE
D09Q
D10
parallel data 09 inverted output
parallel data 10 output
INWINDOW
frequency window detector
output
i.c.
28
29
30
31
internally connected
D10Q
D11
parallel data 10 inverted output
parallel data 11 output
i.c.
internally connected
DMXR0
DMXR1
demultiplexing ratio select 0
demultiplexing ratio select 1
D11Q
D12
parallel data 11 inverted output
parallel data 12 output
2003 May 21
4
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
D12Q
VEE
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
parallel data 12 inverted output
ground
ENLOUTQ
90
line loop back enable input
(active LOW)
ENLINQ
91
diagnostic loop back enable
input (active LOW)
VCCD
supply voltage (digital part)
supply voltage (digital part)
parallel data 13 output
VCCD
INT
92
93
94
95
96
97
98
99
100
interrupt output
D13
VCCD
supply voltage (digital part)
recovered clock output
recovered clock inverted output
supply voltage (digital part)
recovered data output
recovered data inverted output
supply voltage (digital part)
ground
D13Q
D14
parallel data 13 inverted output
parallel data 14 output
COUT
COUTQ
VCCD
D14Q
D15
parallel data 14 inverted output
parallel data 15 output
DOUT
DOUTQ
VCCD
D15Q
VCCD
parallel data 15 inverted output
supply voltage (digital part)
loop mode clock input
CLOOP
CLOOPQ
VCCD
VEE
loop mode clock inverted input
supply voltage (digital part)
loop mode data input
DLOOP
DLOOPQ
VCCD
loop mode data inverted input
supply voltage (digital part)
2003 May 21
5
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
V
1
2
3
4
5
6
7
8
9
V
V
75
74
CCD
CCD
EE
PRSCLO
PRSCLOQ
UI
73 D12Q
D12
72
71
LOS1
D11Q
RSSI1
70 D11
LOSTH1
D10Q
69
68
67
V
D10
CCA
IN1
D09Q
IN1Q 10
11
66 D09
V
D08Q
65
64
63
CCA
INSEL 12
WINSIZE 13
RREF 14
D08
V
TZA3012AHW
EE
62 D07Q
V
15
D07
61
60
59
CCA
IN2 16
IN2Q 17
18
D06Q
D06
V
58 D05Q
CCA
LOSTH2 19
RSSI2 20
D05
57
56
D04Q
LOS2 21
55 D04
CS(DR0) 22
SDA(DR1) 23
SCL(DR2) 24
54 D03Q
D03
53
52
51
ENBA
V
25
V
DD
CCD
MGU315
Fig.2 Pin configuration.
6
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
FUNCTIONAL DESCRIPTION
Table 3 Truth table for selecting bit rate in
pre-programmed mode (pin UI = VEE
)
The TZA3012AHW receives data from an incoming bit
stream having a bit rate from 30 Mbits/s up to 3.2 Gbits/s.
Two line inputs with limiting amplifiers are available.
An internal DCR synchronizes the internal clock generator
to the incoming data. The recovered serial data and clock
are demultiplexed at ratios of 1:16, 1:10, 1:8 or 1:4.
BIT RATE
(Mbits/s)
DR2
DR1
DR0
PROTOCOL
LOW
LOW
LOW
LOW
LOW
LOW
LOW
STM1/OC3
155.52
622.08
HIGH STM4/OC12
STM16/OC48
HIGH HIGH STM16 + FEC
HIGH LOW
2488.32
2666.06
1250.00
3125.00
1062.50
2125.00
Choice of user interface
The TZA3012AHW can be controlled either via the I2C-bus
or using programming pins DR0 to DR2. Pin UI selects the
user interface required. I2C-bus control and A-rate
functionality are enabled when pin UI is either open circuit
or connected to VCC. Pre-programmed mode is enabled
when pin UI is connected to VEE; see Table 1.
HIGH LOW
LOW
HIGH 10GE
Fibre Channel
HIGH HIGH HIGH Fibre Channel
GE
HIGH LOW
HIGH HIGH LOW
After power-up, the TZA3012AHW initiates a Power-On
Reset (POR) sequence to restore the default settings of
the I2C-bus registers, irrespective of the level on pin UI.
The default settings are shown in Table 12.
Table 1 Truth table for pin UI
UI
MODE
PIN 22
DR0
CS
PIN 23 PIN 24
LOW
pre-programmed
DR1
SDA
DR2
SCL
HIGH I2C-bus control
Limiting amplifiers
The TZA3012AHW has two switchable RF line inputs.
Each input has a limiting amplifier (limiter) which provides
optimum receiver sensitivity at any bit rate. The bandwidth
of each limiter is automatically adjusted in accordance with
the input bit rate. This ensures that wideband noise
present in the optical front-end (photo-detector and
transimpedance amplifier) is reduced at low input bit rates.
The maximum bandwidth is selected by default at
power-up. The bandwidth can be set independently of
input bit rate using bits AMPOCT in I2C-bus register
LIMCNF (address C2H).
In I2C-bus control mode, the chip is configured using the
I2C-bus pins SDA and SCL. During I2C-bus read or write
actions, pin CS must be HIGH. When pin CS is LOW, the
programmed configuration remains active but signals SDA
and SCL are ignored. This allows several TZA3012AHWs
in the application with the same I2C-bus address to be
selected separately. The I2C-bus address of the
TZA3012AHW is shown in Table 2.
Table 2 I2C-bus address of the TZA3012AHW
Normally, only one limiter is activated at any one time so
that only the RF signal applied to the active channel is
routed to the DCR. The unused limiter automatically enters
a sleep mode to reduce power dissipation. A limiter is
selected by pin INSEL as shown in Table 4.
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
1
0
0
0
0
X
The function and content of the I2C-bus registers are
described in Section “I2C-bus registers”. Some functions in
the TZA3012AHW can be controlled either by the I2C-bus
or a designated pin. The method required is specified by
an extra bit named I2C<pin name> in the corresponding
I2C-bus register, for example, bit I2CDMXR in
Table 4 Truth table for pin INSEL
PIN
INSEL
SELECTED
INPUTS
SELECTED CHANNEL
HIGH
LOW
channel 1; limiter 1 active IN1 and IN1Q
channel 2; limiter 2 active IN2 and IN2Q
register DMXCNF. The default is enable by pin.
If the application has no I2C-bus control, the IC must
operate with reduced functionality in pre-programmed
mode. In pre-programmed mode, pins DR0 to DR2 are
standard CMOS inputs that allow the selection of up to
eight pre-programmed bit rates using an external
reference clock frequency of typically 19.44 MHz;
see Table 3.
A limiter can also be selected by setting bit I2CINSEL in
I2C-bus register LIMCNF, and specifying bit INSEL as
shown in Table 5.
2003 May 21
7
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 5 Channel selection
Received Signal Strength Indicator (RSSI)
I2C BIT
The strength of signal present at each RF input is
measured by a logarithmic detector and represented by an
analog voltage at pins RSSI1 and RSSI2 for channels 1
and 2, respectively. The RSSI has a sensitivity of
17 mV/dB typical for an input voltage swing Vi(p-p) range of
5 mV to 500 mV; see Fig.4. RSSI output voltage VRSSI can
be calculated using the following formula:
PIN
INSEL
SELECTED CHANNEL
I2CINSEL INSEL
0
0
1
1
X
X
0
1
LOW channel 2; limiter 2 active
HIGH channel 1; limiter 1 active
X
X
channel 2; limiter 2 active
channel 1; limiter 1 active
Vi(p-p)
VRSSI = VRSSI(32 mV) + SRSSI × 20log
----------------
32 mV
Both limiters can be made active by setting bit BOTHON in
I2C-bus register LIMCNF. This allows ‘hot switching’,
where the second channel can be selected quickly if the
first channel loses its signal. Note that even when both
limiters are active, only one channel is selected at any
time; see Table 6.
Both logarithmic detectors are always active to allow the
input with the strongest signal to be selected.
Loss Of Signal (LOS) indicator
In addition to the analog RSSI output, the TZA3012AHW
also provides a digital LOS indication output on pins LOS1
and LOS2. The RSSI level is internally compared with a
LOS threshold voltage level, which can be set either by an
external resistor connected to pins LOSTH1 and LOSTH2,
or by using an internal D/A converter. The method used is
determined by bit I2CREFLVL1 in I2C-bus
register LIMLOS1CNF (address BDH) for channel 1, or
bit I2CREFLVL2 in I2C-bus register LIMLOS2CNF
(address BFH) for channel 2. Using the internal
D/A converter requires a value representing the threshold
voltage to be programmed into I2C-bus registers
LIMLOS1TH (address BCH) or LIMLOS2TH
When only one limiter is active, the time taken to
deactivate its limiter and activate the limiter in the other
channel takes 4 µs typical.
Table 6 Channel and limiter selection with bit BOTHON
I2C BIT
BOTHON INSEL
PIN
SELECTED
CHANNEL
SELECTED
INPUTS
0
HIGH channel 1;
IN1 and IN1Q
limiter 1 active
1
HIGH channel 1;
IN1 and IN1Q
limiters 1 and 2
active
(address BEH). This allows separate LOS threshold levels
to be specified per channel.
0
1
LOW channel 2;
limiter 2 active
LOW channel 2;
IN2 and IN2Q
IN2 and IN2Q
If the received signal strength is below the default
hysteresis value of 3 dB, the corresponding LOS pin will
be HIGH. Alternative hysteresis values from 0 to 7 dB in
steps of 1 dB can be specified using bits HYS1 and HYS2
in I2C-bus registers LIMLOS1CNF and LIMLOS2CNF
respectively. If required, the polarity of the LOS indicator
outputs can be inverted by setting bits LOS1POL
and LOS2POL in the same registers. The LOS function
can be disabled by setting bit LOS1 or LOS2 to logic 0 for
channel 1 or channel 2 respectively.
limiters 1 and 2
active
handbook, halfpage
V
CCA
IN
The LOS function is also available using I2C-bus registers
INTERRUPT and STATUS; see Sections “Interrupt
register” and “Status register”. If bit LOS1 or LOS2 in
register INTERRUPT is not masked, a loss of signal
condition will generate an interrupt signal at pin LOS1 or
pin LOS2. Bits LOS1 and LOS2 are masked by default;
see Section “Interrupt generation”.
50 Ω
50 Ω
INQ
V
EE
MDB385
Fig.3 Limiter input termination configuration.
2003 May 21
8
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL555
1.2
V
RSSI
(V)
S
0.9
RSSI
0.6
0.3
0
5
32
300
500
2
3
10
10
10
V
(mV)
i(p-p)
Fig.4 VRSSI as a function of Vi(p-p)
.
Setting LOSTH reference level by external resistor
If the internal D/A converter is not used, the reference
voltage level on pin LOSTH1 (or LOSTH2) can be set by
connecting an external resistor (R2) from the relevant pin
to ground. The voltage on the pin is determined by the ratio
between R2 and R1; see Fig.5. For resistor R1 a value of
10 to 20 kΩ is recommended, giving a current of
120 to 60 µA.
V
CCA
RSSI
R2
R1
The LOSTH voltage equals
× V
ref
-------
LOS
LOS
compare
1.2 V
Voltage Vref represents a temperature stabilized and
accurate reference voltage of 1.2 V. The minimum
threshold level corresponds to 0 V and the maximum to
1.2 V. Hence, the value of R2 may not be higher than R1.
The accuracy of the LOSTH voltage depends mainly on
carefully choosing the values of the two external resistors.
V
ref
LOSTH1
LOSTH2
RREF
R1
10 kΩ
I
R2
GND
MGU318
Instead of using resistors (R1 and R2) to set the LOS
threshold, an accurate external voltage source can also be
used.
If no resistor is connected to LOSTH1 (or LOSTH2), or an
external voltage higher than 2⁄3 × VCC is applied to the pin,
the LOS detection circuit (including the RSSI reading for
that channel) is automatically switched off to reduce power
dissipation. This ‘auto power off’ only works if UI = VEE, i.e.
manual control of the TZA3012AHW. In I2C-bus mode,
several I2C-bus bits allow flexible configuration.
Fig.5 Setting the LOSTH reference level by
external resistors.
2003 May 21
9
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Slice level adjustment
The FWD is a conventional frequency locked PLL, which,
at power-up, initially applies a coarse adjustment to the
free running VCO frequency. The FWD checks the VCO
frequency, which has to be within a 1000 ppm (parts per
million) window around the desired frequency. The FWD
then compares the divided VCO frequency (also available
on pins PRSCLO and PRSCLOQ) with the reference
frequency, usually 19.44 MHz, on pins CREF and
CREFQ. If the VCO frequency is found to be outside this
window, the FWD disables the Data Phase Detector
(DPD) and forces the VCO to a frequency within the
window. As soon as the ‘in window’ condition occurs,
which is visible on pin INWINDOW, the DPD starts
acquiring lock on the incoming bit stream. Since the VCO
frequency is very close to the expected bit rate, the phase
acquisition will be almost instantaneous, resulting in quick
phase lock to the incoming data stream.
The TZA3012AHW uses a slice level circuit to counter the
affects of asymmetrical noise that can occur in some
optical transmission systems. The slice level circuit
improves pre-detection signal-to-noise ratio by adding a
DC offset to the input signal. The offset required will
depend on the characteristics of the photo detector in the
optical front-end and the amplitude of the received signal.
The slice level is adjustable between −50 mV and +50 mV
in 512 steps of 0.2 mV.
The slice level function is enabled by setting bits SL1
and SL2 in I2C-bus registers LIMLOS1CNF
(address BDH) and LIMLOS2CNF (address BFH) for
channel 1 and channel 2 respectively. The slice level is set
by sign and magnitude convention. The sign, either
positive or negative (polarity), is set by I2C-bus
bits SL1SGN and SL2SGN. The magnitude, 0 to 50 mV in
256 steps, is set by an 8-bit D/A converter via I2C-bus
register LIMSLICE1 (address C0H) and
Although the VCO is now locked to the incoming bit
stream, the FWD is still supervising the VCO frequency
and takes over control if the VCO drifts outside the
predefined frequency window. This might occur during a
‘loss of signal’ situation. Due to the FWD, the VCO
frequency is always close to the required bit rate, enabling
rapid phase acquisition if the lost input signal returns.
LIMSLICE2 (C1H) for channel 1 and channel 2
respectively.
The introduced offset is not present at inputs IN and INQ
to prevent the logarithmic RSSI detector from detecting the
offset as a valid input signal.
The default frequency window of 1000 ppm means that
the reference frequency does not need to be highly
accurate or stable. Any crystal-based oscillator that
generates a reasonably accurate frequency, such
as 100 ppm, is suitable.
Data and Clock Recovery (DCR)
The TZA3012AHW recovers the clock and data contents
from the incoming bit stream; see Fig.6. The DCR uses a
combined frequency and phase locking scheme, providing
reliable and quick data acquisition at any bit rate between
30 Mbits/s and 3.2 Gbits/s. The DCR contains a Voltage
Controlled Oscillator (VCO), Frequency Window Detector
(FWD), octave divider M, main divider N, fractional
divider K, reference divider R, and a phase detector.
The internal VCO is phase-locked to a reference clock
signal of typically 19.44 MHz applied to pins CREF and
CREFQ.
2003 May 21
10
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
LIMITING
RECOVERED DATA DOUT(Q)
to
AMPLIFIER
DEMULTIPLEXER
RECOVERED CLOCK COUT(Q)
DATA IN
DATA PHASE
DETECTOR
up
CHARGE PUMP
down
OCTAVE
DIVIDER
÷M
[
]
[
]
N 8:0
K 21:0
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
9
22
LOOP FILTER
+
MAIN
DIVIDER
FRACTION
CALCULATOR
÷N
up
REFERENCE
DIVIDER
FREQUENCY
WINDOW
DETECTOR
CHARGE PUMP
down
CREF(Q)
÷R
REFERENCE
INPUT
PRSCLO(Q)
PRESCALER
OUTPUT
MGU346
Fig.6 Block diagram of data and clock recovery.
Fractional N synthesizer
I2C-bus control operation allows any one of four possible
reference clock frequency ranges to be selected by
programming reference divider R using bits REFDIV in
I2C-bus register DCRCNF (address B6 H).
The REFDIV bit settings, reference clock frequency
ranges, and division factor are shown in Table 7.
The reference frequency is always divided internally to the
lowest range of 18 to 21 MHz.
The DCR uses a fractional N-type synthesizer to provide
the A-rate functionality that allows the DCR to synchronize
to incoming data, regardless of its bit rate.
The DCR has a 22-bit fractional N capability which allows
any combination of bit rate and reference frequency
between 18 × R and 21 × R MHz, where R is the reference
division factor. The LSB (bit k[0]) of the fractional divider,
should be set to logic 1 to avoid limit cycles. These are
cycles of less than maximum length that generate spurs in
the frequency spectrum. This leaves 21 bits (k[21:1])
available for programming the fraction, allowing a
resolution frequency of approximately 10 Hz at a fixed
reference frequency.
Table 7 Truth table for bits REFDIV in I2C-bus register
DCRCNF
SDH/SONET
REFERENCE FREQUENCY
FREQUENCY
(MHz)
REFERENCE
R
REFDIV DIVISION
FACTOR
RANGE
(MHz)
Programming the reference clock
00
01
10
11
1
2
4
8
19.44
38.88
77.76
155.52
18 to 21
36 to 42
Pre-programmed operation requires a reference clock
frequency of between 18 and 21 MHz connected to
pins CREF and CREFQ. However, to obtain the bit rates in
Table 3, the reference clock frequency must be
19.44 MHz. For SDH/SONET applications, a reference
clock frequency of 19.44 × R MHz is preferred.
72 to 84
144 to 168
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Programming the DCR
Table 9 Common optical transmission protocols and
corresponding octaves
The following dividers are used to program the clock
synthesizer: the main divider N, the fractional divider K
and the octave divider M.
BIT RATE
(Mbits/s)
PROTOCOL
10GE
OCTAVE
3125.00
2970.00
2666.06
2488.32
2380.00
2125.00
1485.00
1380.00
1300.00
1250.00
1062.50
1062.50
1062.50
622.08
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
3
3
4
4
4
4
4
5
6
The division factor for M is obtained by first determining in
which octave the desired bit rate belongs as shown in
Figure 7 and Tables 8 and 9.
2xHDTV
STM16/OC48 + FEC
STM16/OC48
DV-6000
Fibre Channel
HDTV
6
5
4
3
2
1
0
handbook, halfpage
D-1 Video
DV-6010
Gigabit Ethernet (GE)
Fibre Channel
OptiConnect
ISC
28.125 56.25 112.5
225
450
900
1800
Mbits/s
3200
STM4/OC12
DV-6400
MGU316
595.00
Fibre Channel
OptiConnect
Fibre Channel
ESCON/SBCON
STM1/OC3
FDDI
425.00
Fig.7 Allocation of octaves for common bit rates
shown on a logarithmic scale.
265.63
212.50
200.00
Table 8 Octave designation and M division factor
155.52
LOWEST
BIT RATE
(Mbits/s)
HIGHEST
BIT RATE
(Mbits/s)
M DIVISION
FACTOR
125.00
OCTAVE
Fast Ethernet
Fibre Channel
OC1
125.00
106.25
1800
900
3200
1800
900
0
1
2
3
4
5
6
1
2
51.84
450
4
Once the octave and M division factor are known, the
division factors for N and K can be calculated for a given
reference frequency using the Flowchart in Fig.8.
225
450
8
112.5
56.25
28.125
225
16
32
64
112.5
56.25
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
CALCULATE
N and K
bit rate × M × R
n, k =
f
ref
n is integer part
k is fractional part
yes
k = 0 ?
no
NILFRAC = 1
NILFRAC = 0
no
<
<
0.25
k
0.75
no
yes
k ≤ 0.25 ?
no
yes
k ≥ 0.75 ?
yes
k = k + 0.5
k = k − 0.5
N = 2 × n
N = 2 × n
N = 2 × n − 1
N = 2 × n + 1
j = 21
k = k × 2
no
k ≥ 1 ?
yes
K = 1
K = 0
j
j
decimal to binary
conversion of
fractional part
k = k − 1
j = j − 1
no
j = 0 ?
yes
K = 1
j
Write K into registers B3H, B4H and B5H
j
Convert N to binary
and write into registers B1H and B2H
END
MGW570
Fig.8 Flowchart for calculating N and K for the required bit rate.
13
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
The following examples refer to the flowchart in Fig.8.
Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbits/s (STM16/OC48) that corresponds to octave 0 and
an M division factor of 1. If the reference frequency fref at pins CREF and CREFQ is 77.76 MHz, the division factor R is
required to be 4. The initial values for integer n and fractional part k are calculated using the equation:
bit rate × M × R
---------------------------------------
fref
2488.32 Mbits × 1 × 4
--------------------------------------------------------
77.76 MHz
n.k =
=
= 128
In this example, n = 128 and k = 0. Since k is 0, fractional functionality is not required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 1; see Table 19. N = n × 2 = 256 with no further correction required. The resulting
values of R = 4, M = 1 and N = 256 are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1
(Table 17) and MAINDIV0 (Table 18).
Example 2: An SDH or SONET link has a bit rate of 2666.057143 Mbits/s (15/14 × 2488.32 Mbits/s) (STM16/OC48 link
with FEC) that corresponds to octave 0 and an M division factor of 1. If fref at pins CREF and CREFQ is 38.88 MHz, the
division factor R is required to be 2. The values for n and k are calculated as follows:
bit rate × M × R
---------------------------------------
fref
2666.05714283 Mbits × 1 × 2
----------------------------------------------------------------------------
38.88 MHz
n.k =
=
= 137.1428571
In this example, n = 137 and k = 0.1428571. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is less than 0.25, k is corrected to k = k + 0.5 = 0.6428571, and N is
corrected to N = n × 2 − 1 = 273. The resulting values of R = 2, M = 1, N = 273 and K = 10 1001 0010 0100 1001 0011
are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). The FEC bit rate is usually rounded up to
2666.06 Mbits/s, which actually gives a different value for k than in this example.
Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbits/s that corresponds to octave 1 and an M division factor
of 2. If fref at pins CREF and CREFQ is 19.44 MHz, the division factor R is required to be 1. The values for n and k are
bit rate × M × R
---------------------------------------
fref
1062.50 Mbits × 2 × 1
--------------------------------------------------------
19.44 MHz
calculated as follows: n.k =
=
= 109.3106996
In this example, n = 109 and k = 0.3107. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2
should be set to logic 0. Since k is greater than 0.25 and less than 0.75, k does not need to be corrected. N is corrected
to N = n × 2 = 218. The resulting values of R = 1, M = 2, N = 218 and K = 01 0011 1110 0010 1000 0001 are set by
I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2
(Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
Example 4: A non standard transmission link has a bit rate of 3012 Mbits/s that corresponds to octave 0 and an
M division factor of 1. If fref at pins CREF and CREFQ is 20.50 MHz, the division factor R is required to be 1. The values
bit rate × M × R
---------------------------------------
fref
3012 Mbits × 1 × 1
------------------------------------------------
20.50 MHz
for n and k are calculated as follows: n.k =
=
= 146.9268293
In this example, n = 146 and k = 0.9268293. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is greater than 0.75, k is corrected to k = k − 0.5 = 0.4268293, and N
is corrected to N = n × 2 + 1 = 293. The resulting values of R = 1, M = 1, N = 293 and K = 01 1011 0101 0001 0010 1011
are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
If the I2C-bus is not used, the clock synthesizer can be set up for the eight pre-programmed bit rates shown in Table 3,
by pins DR0, DR1 and DR2 using an external reference clock frequency of 19.44 MHz.
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Prescaler outputs
Accurate clock generation during loss of signal
The frequency of prescaler outputs PRSCLO and
PRSCLOQ is the VCO frequency divided by a ratio of N.K.
If the synthesizer is in-lock, the frequency of the prescaler
output is equal to the reference frequency at CREF and
CREFQ divided by R which also corresponds to the
recovered data rate. This provides an accurate reference
that can be used by other phase locked loops in the
application. If required, the polarity of the prescaler outputs
can be inverted by setting bit PRSCLOINV in I2C-bus
register IOCNF0 (address CBH) to logic 1. If no prescaler
information is required, its output can be disabled by
setting bit PRSCLOEN in the same register to logic 0.
In addition, the prescaler output can be set for type of
output, termination mode and signal amplitude. These
parameter settings also apply to the parallel output
clock POCLK and POCLKQ and parity error
During a loss of signal, there is no data present for clock
recovery to use. A frequency acquisition window size of
zero will make the recovered clock frequency equal to the
reference frequency, including its tolerance.
Setting bit AUTOWIN in I2C-bus register DCRCNF makes
the window size dependent on the LOS status of the active
limiter channel. If the optical input signal is lost, the FWD
automatically selects the 0 ppm window size, so that the
VCO is directly phase-locked to the reference signal.
This ensures that the output clock signal remains stable
during loss of signal, and automatically reverts to normal
DCR operation when the input signal returns.
Note that the accuracy of the reference frequency must be
better than 20 ppm for the application to comply with ITU-T
recommendations.
output PARERR and PARERRQ. For programming
details, These parameter settings also apply to the parallel
demultiplexer outputs. For programming details;
INWINDOW signal
The status of the FWD circuit is indicated by the level on
pin INWINDOW. A HIGH level indicates that the VCO is
within the defined frequency acquisition window size, and
a LOW level indicates that the VCO is outside the defined
window size. The status of the FWD circuit is also
indicated by bit INWINDOW in I2C-bus
see Section “Configuring the parallel interface”.
Programming the FWD
The default window for frequency acquisition is 1000 ppm
around the desired bit rate. The size of window determines
the amount of variation in the frequency of the applied
reference clock, and VCO, that is tolerated by the FWD.
The window size can be set to other predefined values
between 250 and 2000 ppm by bits WINDOWSIZE in
I2C-bus register DCRCNF (address B6H).
registers INTERRUPT and STATUS.
Jitter performance
The clock synthesizer is optimized for minimum jitter
generation. For all SDH/SONET bit rates, the generated
jitter complies with ITU-T standard G.958 using a pure
reference clock. To ensure negligible loss of performance
when a reference clock is used, the reference signal
should have a single sideband phase noise of better than
−140 dBc/Hz, at frequencies of more than 12 kHz from the
carrier. If reference divider R is used, this negative value is
allowed to increase at approximately 20 × log (R).
An additional feature allows the size of the frequency
acquisition window to be set to 0 ppm, which effectively
removes the ‘dead zone’ from the FWD, converting it to a
classical PLL. The VCO will then be directly phase-locked
to the reference signal instead of the incoming bit stream.
This is implemented by either applying a LOW level to
pin WINSIZE, or by setting bit WINSIZE to logic 0 and
bit I2CWINSIZE to logic 1 in I2C-bus register DCRCNF;
see Table 10.
Demultiplexer
The demultiplexer converts the serial input bit stream to
parallel formats of 1:16, 1:10, 1:8, and 1:4. The output data
is available on a scalable bus, of which the output driver
type can be either LVPECL or CML. In addition to the
deserializing function, the demultiplexer comprises a parity
calculator and a frame header detection circuit.
A calculated parity of EVEN is output at pins PARITY and
PARITYQ. A detected frame header pattern in the data
stream results in a 1 clock cycle wide pulse on outputs FP
and FPQ.
Table 10 Truth table for pin WINSIZE
WINSIZE
LOW
WINDOW SIZE (ppm)
0
HIGH
1000
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Making pin ENBA HIGH automatically aligns the parallel
output into logical bytes or words. The same function is
implemented by setting bit ENBA in I2C-bus
register DMXCNF (address A8H).
depends on the demultiplexing ratio selected by
pins DMXR0 and DMXR1 or by bits DMXR in I2C-bus
register DMXCNF (address A8 H). Any unused parallel
data bus outputs are disabled. The configuration settings
and active outputs for each demultiplexing ratio are shown
in Table 11.
To support most commonly used transmission systems
and protocols, the demultiplexing ratio can be set to 1:16,
1:10, 1:8, and 1:4, and the frame header pattern
programmed to any 32 or 10-bit pattern; see Section
“Frame detection”.
In I2C-bus control mode, the default demultiplexing ratio
is 16:1.
To allow optimum layout connectivity, the pin designations
of the parallel data bus bits can be reversed so that the
default designated pin for D15 (MSB) is exchanged with
the default designated pin for D0 (LSB). This is
implemented by bit BUSSWAP in I2C-bus
If required, the demultiplexer output can be forced into a
fixed logic 0 state by bit DMXMUTE in I2C-bus
register DMXCNF.
Adjustable demultiplexing ratio
register DMXCNF (address A8H).
For optimum layout connectivity, the physical positions of
parallel data bus pins D00 to D15 and D00Q to D15Q on
the chip are located either side of pin VEE (pin 63).
The number of parallel data bus outputs that are used
The highest supported speed for the parallel data bus is
400 Mbits/s. Therefore a demultiplexing ratio of 4:1 will
support bit rates of up to 1.6 Gbits/s.
Table 11 Setting demultiplexing ratio
BITS DMXR
(REG DMXCNF)
DEMULTIPLEXING
RATIO
ACTIVE OUTPUTS
LSB to MSB
PIN DMXR1
PIN DMXR0
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
00
01
10
11
1:4
1:8
D06 to D09
D04 to D11
D03 to D12
D00 to D15
1:10
1:16
Frame detection
Any bit position can be programmed with a ‘don’t care’ to
give a frame header pattern that is either much shorter
than 32 or 10 bits, or has gaps. The “don’t care” bits are
produced by programming a pattern into I2C-bus registers
HEADERX0 to HEADERX3 which is used to mask the
programmed frame header pattern as shown in the
example Fig.9.
Byte alignment is enabled if the Enable Byte Alignment
input (pin ENBA) is HIGH, or if bit I2CENBA and bit ENBA
are both logic 1 in I2C-bus register DMXCNF
(address A8H). Whenever the incoming data has a 32-bit
or 10-bit sequence that matches the programmed frame
header pattern, the data is formatted into logical bytes or
words, and a frame pulse is generated on differential
outputs FP and FPQ. Any frame header pattern can be
programmed in I2C-bus registers HEADER0
The default frame header pattern is F6F62828H,
corresponding to the middle section of the standard
SDH/SONET frame header (the last two A1 bytes plus the
first two A2 bytes).
to HEADER3.
2003 May 21
16
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MSB HEADER
LSB HEADER
BIT32
0
BIT1
0
HEADER3
0
0
0
0
0
0
1
0
1
0
0
0
1
1
X
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
X
HEADER0
1
1
HEADERX3
HEADERX0
X
X
received
data
data stream
MGU548
‘X’ = “don’t care”
‘MSB’ = Most Significant Byte.
Fig.9 Example of programming the frame header pattern.
If ENBA is LOW, no active alignment takes place.
However, if the frame header pattern occurs in the
formatted data, a frame pulse will still be output on pins FP
and FPQ.
Receiver framing in SDH/SONET applications
Figure 10 shows a typical SDH/SONET reframe sequence
involving byte alignment. Frame and byte boundary
detection is enabled on the rising edge of ENBA and
remains enabled while ENBA is HIGH. Boundaries are
recognized on receipt of the second A2 byte and FP goes
HIGH for one POCLK cycle.
For 10-bit oriented protocols, such as Gigabit Ethernet,
the frame header detection operates on a 10-bit pattern
sequence. These 10 bits should be programmed into
I2C-bus registers HEADER3 and the two MSBs of
HEADER2; the remaining 22 bits are ignored. A ‘don’t
care’ pattern overlay can be programmed in I2C-bus
register HEADERX3 and the two MSBs of HEADERX2.
In 1:16 mode, the first two A2 bytes in the frame header
are the first data word to be reported with the correct
alignment on the outgoing data bus (D00 to D15). In 1:8
mode the first A2 byte is the first aligned data byte (D04 to
D11), while in 1:4 mode the most significant nibble of the
first A2 byte is the first aligned data (D06 to D09).
Since some 10-bit oriented protocols use a DC balancing
code, the detection pattern could appear in
complementary form in the data stream. By setting
bit CMPL in I2C-bus register DMXCNF (address A8H), the
header detection scans the data stream for both the
programmed pattern and its complement simultaneously.
Either occurrence produces a ‘byte’ alignment and a
corresponding frame pulse on pins FP and FPQ.
When interfacing with a section terminating device, ENBA
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct;
see Fig.11. Byte boundary detection is disabled on the first
FP pulse after ENBA has gone LOW.
The default pattern (after power-up) is ‘0011111010’ or
K28.5 character plus alternating 010. This is the only
pattern containing five consecutive bits of the same sign.
Figure 12 shows frame and byte boundary detection
activated on the rising edge of ENBA, and deactivated by
the first FP pulse after ENBA has gone LOW.
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
serial clock
ENBA
32 bits
serial data
A1
A1
A1
A2
A2
valid data
invalid data
1 : 16
A2
A2
D00 to D15
(1:16)
28 28
POCLK
(1:16)
FP
(1:16)
1 : 4
A2
A2
D06 to D09
(1:4)
2
8
2
8
POCLK
(1:4)
FP
(1:4)
MGU550
Fig.10 Frame and byte detection in SDH/SONET application.
boundary detection
enabled
boundary detection enabled
handbook, halfpage
ENBA
handbook, halfpage
ENBA
FP
FP
MGU340
MGU341
Fig.11 ENBA timing with section terminating
device.
Fig.12 Alternate ENBA timing.
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Parity generation
Loop mode I/Os
Outputs PARITY and PARITYQ provide the even parity of
the byte/word that is currently available on the parallel bus.
Odd parity can be output by setting bit PARINV to logic 1
in I2C-bus register IOCNF2 (address C9H). If no parity
output is required, and/or to reduce output power, set
bit PAREN, in the same register, to logic 0.
In line loopback mode, the internal data and clock routing
switch routes the received serial data and recovered clock
to outputs DOUT, DOUTQ COUT and COUTQ instead of
to the demultiplexer. Line loopback mode is activated by a
LOW level on pin ENLOUTQ. Line loopback mode is also
selected by setting bit ENLOOPOUT and
bit I2CLOOPMODE in I2C-bus register DIVCNF
(address B0H).
Configuring the parallel interface
There are several options for configuring the parallel
interface which comprises the parallel data bus and
associated outputs. The options for parallel data
output D00 to D15 and D00Q to D15Q, parallel clock
output POCLK and POCLKQ, parity output PARITY and
PARITYQ, frame pulse output FP and FPQ, and prescaler
output PRSCLO and PRSCLOQ are: output driver type,
termination mode, output amplitude, signal polarity, and
selective enabling or disabling. The parallel data bus pin
designations can also be reversed and/or muted. These
options are set in I2C-bus registers IOCNF3
In diagnostic loopback mode, the demultiplexer selects the
serial data and clock signals at loop mode input
pins DLOOP, DLOOPQ and CLOOP, CLOOPQ instead of
from the DCR. Diagnostic loopback mode is activated by a
LOW level on pin ENLINQ. Diagnostic loopback mode is
also selected by setting bit ENLOOPIN and
bit I2CLOOPMODE in I2C-bus register DIVCNF
(address B0H).
Configuring the RF I/Os
The polarity of specific RF serial data and clock I/O signals
can be inverted using I2C-bus register IOCNF1
(address CAH).
(address C8H) and IOCNF2 (address C9H), IOCNF0
(address CBH) and DMXCNF (address A8H).
I2C-bus register IOCNF3, bit MFOUTMODE selects either
the CML or LVPECL output driver. The default is LVPECL.
Bit MFOUTTERM sets the output termination mode to
either standard LVPECL or floating termination, or in CML
mode, to either DC or AC-coupled. In all cases, bits MFS
adjust the amplitude. The default output amplitude is
800 mV (p-p) single-ended.
To allow easier connection to other ICs, the pin
designations for input data can be exchanged with the pin
designations for input clock. The pin designations for
output data and output clock can also be exchanged.
The default pin designations for Loop mode input data and
clock are exchanged by setting bit CDINSWAP in I2C-bus
register IOCNF1 so that signals at pins CLOOP and
CLOOPQ are treated as data and signals at pins DLOOP
and DLOOPQ are treated as clock.
In I2C-bus register IOCNF2, setting bit PDEN to logic 0
disables the parallel interface output driver. This is not the
same effect as setting bit DMXMUTE in I2C-bus
register DMXCNF (address A8H), which forces the
outputs to a logic 0 state. Setting bit PDINV to logic 1 in
I2C-bus register IOCNF2 (address C9H) inverts the
polarity of the parallel data. Setting bit POCLKINV to
logic 1 in the same register inverts the clock output so that
the clock edge is shifted by half a clock cycle, changing the
rising edge to a falling edge. This function can be used to
resolve a parallel data bus timing problem. The parallel
bus clock is disabled by setting bit POCLKEN to logic 0 in
the same register. Control bits in the same register and in
register IOCNF0 (address CBH) also apply the same
options to the parity, frame pulse and prescaler outputs.
The default pin designations for Loop mode output data
and clock are exchanged by setting bit CDOUTSWAP in
I2C-bus register IOCNF1 so that signals at pins COUT and
COUTQ are treated as data and signals at pins DOUT and
DOUTQ are treated as clock.
The amplitude of the RF serial output signals in CML drive
mode, is adjustable (in 16 steps) between 60 mV (p-p) and
1000 mV (p-p), single-ended, controlled by bits RFS
and RFSWING in I2C-bus register IOCNF0
(address CBH). The default amplitude is 80 mV (p-p),
single-ended. The RF serial outputs are AC-coupled.
2003 May 21
19
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
CMOS control inputs
Status register
CMOS control inputs UI, INSEL, WINSIZE, DMXR0,
DMXR1, ENBA, ENLOUTQ, ENLINQ and CS(DR0) have
an internal pull-up resistor so that these pins go HIGH
when open circuit, and only go LOW when deliberately
forced. This is also true for pins DR1 and DR2 in
pre-programmed mode (pin UI is LOW). In I2C-bus control
mode (pin UI is HIGH), pins SCL and SDA comply with the
I2C-bus interface standard.
The current status of the conditions that are recorded by
register INTERRUPT are indicated by setting the
appropriate bit(s) in I2C-bus register STATUS
(address 01H). A bit is set only for the period that the
condition is active and resets when the condition clears.
Register STATUS is polled by an I2C-bus read action.
Interrupt generation
An interrupt is generated if an interrupt condition sets a bit
in I2C-bus register INTERRUPT (address 00H) and if the
bit is not masked by I2C-bus register INTMASK
Power supply connections
Four separate supply domains (VDD, VCCD, VCCO and
VCCA) provide isolation between the various functional
blocks. Each supply domain should be connected to a
common VCC using a separate filter. All supply pins,
including the exposed die pad, must be connected.
The die pad connection to ground must have the lowest
possible inductance. Since the die pad is also used as the
main ground return of the chip, this connection must also
have a low DC impedance. The voltage supply levels
should be in accordance with the values specified in
Chapters “Characteristics” and “Limiting values”.
(address CCH). Only the high junction temperature
interrupt bit is not masked by default. A generated interrupt
is indicated by an active logic level at pin INT. The active
output level used is set by bit INTPOL in I2C-bus
register INTMASK. The default is an active LOW level.
Bit INTOUT sets the output mode at pin INT to either
open-drain or to standard CMOS. The default is
open-drain. An active LOW output in open-drain mode
allows several receivers to be connected together, and
requires only one 3.3 kΩ pull-up resistor.
All external components should be surface mounted, with
a preferable size of 0603 or smaller. The components
must be mounted as close to the IC as possible.
Interrupt register
The following events are recorded by setting the
appropriate bit(s) in I2C-bus register INTERRUPT
(address 00 H):
• Loss of signal on channel 1
• Loss of signal on channel 2
• DCR frequency locked or unlocked
• Limiter channel switching enabled or disabled
• High junction temperature.
When register INTERRUPT is polled by an I2C-bus read
action, any set bits are reset. If a condition is still active, the
corresponding bit remains set.
2003 May 21
20
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
Refer to Fig.13. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.13 Bit transfer.
Start and stop conditions
Refer to Fig.14. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition (P).
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.14 Definition of start and stop conditions.
2003 May 21
21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
System configuration
Refer to Fig.15. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’.
The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.15 System configuration.
Acknowledge
Refer to Fig.16. Only one data byte is transferred between the start and stop conditions during a write from the transmitter
to the receiver. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put
on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition; see Fig.19.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.16 Acknowledgment on the I2C-bus.
2003 May 21
22
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
I2C-BUS PROTOCOL
Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The address byte is
sent after the start condition.
The master transmitter/receiver either reads from the read-registers or writes to the write-registers. It is not possible to
read from and write to the same register. Figure 17 shows how the slave and register address bytes are defined.
MSB
MSB
1
LSB
LSB
R/W
Slave address
Register address
MDB070
Fig.17 Slave and register addresses.
Read/Write protocols
The protocol for writing to a single register is shown in Fig.18. The transmitter sends the address of the slave device,
waits for an acknowledge from the slave, sends register address, waits for an acknowledge from the slave, sends data
byte, waits for an acknowledge from the slave, followed by a stop condition.
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
MSB
1
MSB
A
LSB
R/W
0
SLAVE
ADDRESS
REGISTER
ADDRESS
DATA
S
A
P
A
one byte transferred
MDB386
Fig.18 Write protocol.
The protocol for reading one or more registers is shown in Fig.19. The receiver sends the address of the slave device,
waits for an acknowledge from the slave, receives data byte(s) from the slave (the TZA3012AHW starts sending data
after asserting an acknowledge), after receiving the data, the receiver sends an acknowledge or, if finished, a
not-acknowledge, followed by a stop condition.
2003 May 21
23
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
acknowledge
acknowledge
acknowledge
acknowledge
from slave
(1)
(1)
(1)
from master
from master
from master
R/W MSB
LSB
MSB
LSB
SLAVE
ADDRESS
S
1
A
DATA
A
A
DATA
A
P
first byte
last byte
MDB387
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave.
Fig.19 Read protocol.
I2C-bus registers
The I2C-bus registers are accessed in I2C-bus control mode by setting pin UI HIGH or leaving pin UI open circuit.
Address and read/write data are transferred serially via pin SDA and clocked via pin SCL when pin CS (chip select) is
HIGH. The I2C-bus registers are listed in Table 12.
2003 May 21
24
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 12 I2C-bus registers
ADDRESS
NAME
DEFAULT READ/
FUNCTION
(HEX)(1)
VALUE
WRITE
00
01
A0
INTERRUPT Interrupt register; see Table 13
−
−
R
R
STATUS
Status register; see Table 14
HEADER3
Programmable header, most significant byte
1111 0110
W
1:10 ratio
0011 1110
1111 0110
A1
HEADER2
Programmable header
W
1:10 ratio
10X XXXX
0010 1000
0010 1000
0000 0000
A2
A3
A4
HEADER1
HEADER0
HEADERX3
Programmable header
W
W
W
Programmable header, least significant byte
Programmable header, don’t care, most significant byte
1:10 ratio
0000 0000
0000 0000
A5
HEADERX2
Programmable header, don’t care
W
1:10 ratio
00XX XXXX
0000 0000
0000 0000
0000 1011
0000 0000
0000 0001
A6
A7
A8
B0
B1
HEADERX1
HEADERX0
DMXCNF
DIVCNF
Programmable header, don’t care
W
W
W
W
W
Programmable header, don’t care, least significant byte
Demultiplexer configuration register; see Table 15
Octave and loop mode configuration register; see Table 16
MAINDIV1
Main divider division factor N; most significant byte; range
128 to 511; see Table 17
B2
B3
B4
B5
B6
BC
BD
BE
BF
C0
C1
C2
C8
C9
CA
CB
CC
MAINDIV0
FRACN2
Main divider division factor N; least significant byte; see Table 18 0000 0000
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Fractional divider division factor K; see Table 19
Fractional divider division factor K; see Table 20
Fractional divider division factor K; see Table 21
DCR configuration register; see Table 22
1000 0000
0000 0000
0000 0000
0000 1100
0000 0000
0000 1101
0000 0000
0000 1101
0000 0000
0000 0000
0000 1000
0000 1100
1010 1010
0000 0000
0010 0011
0101 0000
FRACN1
FRACN0
DCRCNF
LIMLOS1TH
Limiter 1 loss of signal threshold register; range 0 to 255
LIMLOS1CNF Limiter 1 loss of signal configuration register; see Table 23
LIMLOS2TH Limiter 2 loss of signal threshold register; range 0 to 255
LIMLOS2CNF Limiter 2 loss of signal configuration register; see Table 24
LIMSLICE1
LIMSLICE2
LIMCNF
Limiter 1 slice level register; range 0 to 255
Limiter 2 slice level register; range 0 to 255
Limiter configuration register; see Table 25
IOCNF3
Parallel interface output configuration register 3; see Table 26
Parallel interface output configuration register 2; see Table 27
RF serial I/O configuration register 1; see Table 28
RF serial output configuration register 0; see Table 29
Interrupt masking register; see Table 30
IOCNF2
IOCNF1
IOCNF0
INTMASK
Notes
1. Addresses not shown must not be accessed.
2. X = don’t care.
2003 May 21
25
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 13 Register INTERRUPT (address 00H)
BIT
PARAMETER
DESCRIPTION
loss of signal on channel 1
7
6
5
4
3
2
1
0
NAME
LOS1
1
0
no signal present (loss of signal condition)
signal present
loss of signal on channel 2
no signal present (loss of signal condition)
signal present
LOS2
1
0
DCR frequency indication
INWINDOW
1
0
frequency outside predefined window
(unlocked)
frequency inside predefined window (locked)
auto-switching between channels
LIMSW
1
0
enabled (active limiter indicated in Status
register)
disabled (no auto-switching between
channels)
high junction temperature
junction temperature ≥130 °C
junction temperature <130 °C
reserved
TALARM
1
0
0
0
0
2003 May 21
26
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 14 Register STATUS (address 01H)
BIT
PARAMETER
DESCRIPTION
loss of signal on channel 1
7
6
5
4
3
2
1
0
NAME
LOS1
1
0
no signal present (loss of signal condition)
signal present
loss of signal on channel 2
no signal present (loss of signal condition)
signal present
LOS2
1
0
DCR frequency indication
INWINDOW
1
0
frequency inside predefined window
(locked)
frequency outside predefined window
(unlocked)
active limiter indication
limiter 1 active
LIMSEL
1
0
limiter 2 active
high junction temperature
junction temperature ≥130 °C
junction temperature <130 °C
reserved
TALARM
1
0
0
0
0
2003 May 21
27
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 15 Register DMXCNF (address A8H); default value 0BH
BIT
PARAMETER
DESCRIPTION
demultiplexing ratio
7
6
5
4
3
2
1
0
NAME
DMXR
1
1
0
0
1
0
1
0
1:16
1:10
1:8
1:4
demultiplexing ratio programming
via I2C-bus interface
I2CDMXR
CMPL
1
0
via pins DMXR0 and DMXR1
frame header detection in 1:10 Gigabit
Ethernet mode
1
0
simultaneously check for complementary
header
check programmed header only
parallel data bus bit designations
D00 = MSB, D15 = LSB (reversed)
D15 = MSB, D00 = LSB (normal)
BUSSWAP
1
0
demultiplexer mute parallel interface outputs DMXMUTE
1
0
mute; parallel interface outputs forced to
logic 0
no mute
enable/disable byte alignment
enabled
ENBA
1
0
disabled
ENBA control
I2CENBA
1
0
0
via I2C-bus interface
via pin ENBA
0
0
0
1
0
1
1
default value
2003 May 21
28
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 16 Register DIVCNF (address B0H); default value 00H
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
octave divider division factor M, octave
selection
DIV_M
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
M = 1, octave number 0
M = 2, octave number 1
M = 4, octave number 2
M = 8, octave number 3
M = 16, octave number 4
M = 32, octave number 5
M = 64, octave number 6
reserved
0
0
enable/disable loop mode inputs
enabled
ENLOOPIN
1
0
disabled
enable/disable loop mode outputs
enabled
ENLOOPOUT
I2CLOOPMODE
1
0
disabled
loop mode control
1
0
0
via I2C-bus interface
via pin ENLINQ and/or pin ENLOUTQ
default value
0
0
0
0
0
0
0
Table 17 Register MAINDIV1 (address B1H); default value 01H
BIT
PARAMETER
DESCRIPTION
N8 main divider division factor N; N8 = MSB
default value
7
6
5
4
3
2
1
0
NAME
−
−
−
−
−
−
−
DIV_N
0
0
0
0
0
0
0
1
Table 18 Register MAINDIV0 (address B2H); default value 00H
BIT
PARAMETER
DESCRIPTION
N0 main divider division factor N; N0 = LSB
default value
7
N7
0
6
N6
0
5
N5
0
4
N4
0
3
N3
0
2
N2
0
1
N1
0
0
NAME
DIV_N
0
2003 May 21
29
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 19 Register FRACN2 (address B3H); default value 80H
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
NF
X
K21 K20 K19 K18 K17 K16 fractional divider division value K;
K21 = MSB
DIV_K
NILFRAC control bit
NILFRAC
1
0
1
no fractional N functionality
fractional N functionality
0
0
0
0
0
0
0
default value
Note
1. X = don’t care.
Table 20 Register FRACN1 (address B4H); default value 00H
BIT
PARAMETER
DESCRIPTION
K8 fractional divider division value K
default value
7
6
5
4
3
2
1
0
NAME
K15 K14 K13 K12 K11 K10 K9
DIV_K
0
0
0
0
0
0
0
0
Table 21 Register FRACN0 (address B5H); default value 00H
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
K7
0
K6
0
K5
0
K4
0
K3
0
K2
0
K1
0
K0 fractional divider division value K; K0 = LSB DIV_K
default value
0
2003 May 21
30
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 22 Register DCRCNF (address B6H); default value 0CH
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
FWD window size; relative to bit rate
WINDOWSIZE
0
1
1
1
1
0
0
1
1
0
1
0
2000 ppm
1000 ppm
500 ppm
250 ppm
FWD window size select; WINDOWSIZE
value or zero
WINSIZE
1
0
window size specified by ‘WINDOWSIZE’;
PLL frequency allowed to vary around the
reference frequency
window size = 0 ppm; PLL frequency
directly synthesized from reference
frequency
WINSIZE control bit
via I2C-bus interface
via pin WINSIZE
automatic window size select
enabled
I2CWINSIZE
AUTOWIN
1
0
1
0
disabled
reference divider division factor R; reference REFDIV
frequency
1
1
0
0
0
1
0
1
0
0
R = 8; 155.52 MHz
R = 4; 77.76 MHz
R = 2; 38.88 MHz
R = 1; 19.44 MHz
default value
0
0
1
1
0
0
2003 May 21
31
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 23 Register LIMLOS1CNF (address BDH); default value 0DH
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
loss of signal detection on channel 1
LOS1
1
0
enabled
disabled
loss of signal threshold level control bit on
channel 1
I2CREFLVL1
1
0
via I2C-bus interface by internal DAC;
register LIMLOS1TH
via analog voltage on pin LOSTH1
loss of signal detection hysteresis on
channel 1
HYS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
7 dB
slice level on channel 1
enabled
SL1
1
0
disabled
slice level sign on channel 1
positive
SL1SGN
LOS1POL
1
0
negative
polarity of LOS on channel 1
inverted
1
0
0
normal
0
0
0
1
1
0
1
default value
2003 May 21
32
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 24 Register LIMLOS2CNF (address BFH); default value 0DH
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
loss of signal detection on channel 2
LOS2
1
0
enabled
disabled
loss of signal threshold level control bit on
channel 2
I2CREFLVL2
1
0
via I2C-bus interface by internal DAC;
register LIMLOS2TH
via analog voltage on pin LOSTH2
loss of signal detection hysteresis on
channel 2
HYS2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
7 dB
slice level on channel 2
enabled
SL2
1
0
disabled
slice level sign on channel 2
positive
SL2SGN
LOS2POL
1
0
negative
polarity of LOS on channel 2
inverted
1
0
0
normal
0
0
0
1
1
0
1
default value
2003 May 21
33
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 25 Register LIMCNF (address C2H); default value 08H
BIT
PARAMETER
DESCRIPTION
amplifier octave selection
7
6
5
4
3
2
1
0
NAME
AMPOCT
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
octave number 0; 1800 to 3200 Mbits/s
octave number 1; 900 to 1800 Mbits/s
octave number 2; 450 to 900 Mbits/s
octave number 3; 225 to 450 Mbits/s
octave number 4; 30 to 225 Mbits/s
channel selection
INSEL
1
0
channel 1 selected; limiter 1 active
channel 2 selected; limiter 2 active
channel selection control bit
via I2C-bus interface; bit INSEL
via pin INSEL
I2CINSEL
BOTHON
1
0
single/dual limiter selection
both limiters active
1
0
single limiter active, specified by bit INSEL
reserved
0
0
0
0
0
0
1
0
0
0
default value
Note
1. X = don’t care.
2003 May 21
34
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 26 Register IOCNF3 (address C8H); default value 0CH
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
parallel output signal amplitude
60 mV (p-p)
MFS
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
minimum; 120 mV (p-p)
default; 800 mV (p-p)
maximum; 1000 mV (p-p)
reserved
0
0
parallel output termination
MFOUTTERM
MFOUTMODE
1
0
LVPECL mode: floating; CML mode:
AC-coupled
LVPECL mode: standard; CML mode:
DC-coupled
parallel output mode
1
0
Current Mode Logic (CML)
Low Voltage Positive Emitter Coupled
Logic (LVPECL)
0
0
0
0
1
1
0
0
default value
2003 May 21
35
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 27 Register IOCNF2 (address C9H); default value AAH
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
parallel data output polarity
inverted
PDINV
1
0
normal
parallel data output enable
enabled
PDEN
1
0
disabled
parallel clock output polarity
inverted
POCLKINV
POCLKEN
PARINV
PAREN
FPINV
1
0
normal
parallel clock output enable
enabled
1
0
disabled
parity output polarity
inverted
1
0
normal
parity output enable
enabled
1
0
disabled
frame pulse output polarity
inverted
1
0
normal
frame pulse output enable
enabled
FPEN
1
0
1
disabled
0
1
0
1
0
1
0
default value
2003 May 21
36
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 28 Register IOCNF1 (address CAH); default value 00H
BIT
PARAMETER
DESCRIPTION
7
6
5
4
3
2
1
0
NAME
loop mode clock input polarity
CININV
1
0
inverted
normal
loop mode data input polarity
DININV
1
0
inverted
normal
loop mode clock and data inputs swap
CDINSWAP
COUTINV
DOUTINV
CDOUTSWAP
1
0
clock and data input pairs swapped
normal
loop mode clock output polarity
1
0
inverted
normal
loop mode data output polarity
1
0
inverted
normal
loop mode clock and data outputs swap
1
0
clock and data output pairs swapped
normal
0
0
0
0
reserved
0
0
0
0
0
0
default value
2003 May 21
37
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 29 Register IOCNF0 (address CBH); default value 23H
BIT
PARAMETER
DESCRIPTION
RF serial output signal amplitude
7
6
5
4
3
2
1
0
NAME
RFS
0
0
1
0
0
1
0
1
1
0
1
1
minimum: 20mV (p-p); 60 mV (p-p) high
swing
default: 80mV (p-p); 250 mV (p-p) high
swing
maximum: 300mV (p-p); 1000 mV (p-p)
high swing
prescaler output polarity
inverted
PRSCLOINV
PRSCLOEN
RFSWING
1
0
normal
prescaler output enable
enabled
1
0
disabled
RF serial output swing
high swing
1
0
low swing
0
0
reserved
0
1
0
0
0
1
1
default value
2003 May 21
38
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 30 Register INTMASK (address CCH); default value A0H
BIT
PARAMETER
DESCRIPTION
mask LOS1 signal
7
6
5
4
3
2
1
0
NAME
MLOS1
1
0
not masked
masked; note 1
mask LOS2 signal
not masked
MLOS2
1
0
masked; note 1
mask INWINDOW signal
not masked
MINWINDOW
MLIMSEL
MTALARM
1
0
masked; note 1
mask LIMSEL signal
not masked
1
0
masked; note 1
mask high junction temperature
not masked
1
0
masked; note 1
0
reserved
pin INT polarity mode
inverted; active LOW output
normal; active HIGH output
pin INT output mode
standard CMOS output
open-drain output
INTPOL
INTOUT
1
0
1
0
0
1
0
1
0
0
0
0
default value
Note
1. Signal is not processed by the interrupt controller.
2003 May 21
39
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
TZA3012AHW FEATURES IN PRE-PROGRAMMED
MODE
• Loop mode serial input and output configuration:
pins ENLINQ and ENLOUTQ
• Automatic byte alignment for SDH/SONET or Gigabit
Ethernet (ENBA)
Although the TZA3012AHW is primarily intended to be
programmed via the I2C-bus (pin UI HIGH), many of the
TZA3012AHW functions can be accessed via the external
chip pins in pre-programmed mode (pin UI LOW) as
follows:
• Frame detection for SDH/SONET (pattern is
A1A1A2A2) or Gigabit Ethernet
• EVEN parity generation
• Choice of four pre-programmed SDH/SONET bit rates:
STM1/OC3, STM4/OC12, STM16/OC48,
STM16/OC48 + FEC; pins DR0 to DR2
• LVPECL outputs on parallel interface with 800 mV (p-p),
single-ended signal, (DC-coupled termination to
VCC − 2 V)
• Choice of four pre-programmed bit rates; Fibre Channel,
double Fibre Channel, Gigabit Ethernet, 10-Gigabit
Ethernet; pins DR0 to DR2
• CML serial RF outputs with typical 80 mV (p-p),
single-ended signal, (AC-coupled load)
• In window detection (INWINDOW)
• Choice of four demultiplexing ratios; 1:16, 1:10, 1:8 or
1:4 pins DMUXR1 and DMUXR0
• FWD window size select, WINDOWSIZE value ppm or
0 ppm (WINSIZE)
• Input channel selection (INSEL)
• High junction temperature indication (pin INT;
open-drain)
• Received signal strength indicator, independently for
channels 1 and 2
• 18 to 21 MHz reference frequency supported.
• Loss of signal detection threshold for each input channel
individually (LOSTH1 and LOSTH2)
• Automatic disable of unused logarithmic detector
(LOSTH1 and LOSTH2)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER
MIN.
−0.5
MAX.
+3.6
UNIT
V
V
CCA, VCCD
CCO, VDD
,
supply voltages
V
Vn
DC voltage on pins
D00 to D15, D00Q to D15Q, POCLK, POCLKQ, FP, FPQ,
PARITY, PARITYQ, PRSCLO and PRSCLOQ
VCC − 2.5
VCC + 0.5
V
LOSTH1, LOSTH2 and RREF
RSSI1 and RSSI2
−0.5
−0.5
−0.5
VCC + 0.5
VCC + 0.5
VCC + 0.5
V
V
V
UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENBA,
ENLOUTQ and ENLINQ
LOS1, LOS2 and INWINDOW
−0.5
−0.5
V
CC + 0.5
CC + 0.5
V
V
INT
V
In
input current on pins
IN1, IN1Q, IN2 and IN2Q
CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ
INT
−30
−20
−2
+30
+20
+2
mA
mA
mA
°C
Tamb
Tj
ambient temperature
−40
−
+85
+125
+150
junction temperature
°C
Tstg
storage temperature
−65
°C
2003 May 21
40
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
thermal resistance from junction to ambient
CONDITIONS
VALUE
UNIT
Rth(j-a)
notes 1 and 2
16
K/W
Notes
1. In compliance with JEDEC standards JESD51-5 and JESD51-7.
2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and
fourth layer in the PCB.
CHARACTERISTICS
VCC = 3.14 to 3.47 V; Tamb = −40 to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings
(note 1); all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ICCA
ICCD
ICCO
IDD
analog supply current
digital supply current
oscillator supply current
digital supply current
total supply current
15
20
27
mA
see Figs 20 and 22
270
20
350
25
450
33
mA
mA
mA
mA
W
0
0
1
ICC(tot)
Ptot
note 2
note 2
305
0.96
395
1.3
511
1.77
total power dissipation
CMOS input: pins UI, DR0, DR1, DR2, INSEL, WINSIZE, DMXR0, DMXR1, ENBA, ENLOUTQ and ENLINQ
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
−
−
−
−
−
0.2VCC
V
0.8VCC
−200
−
−
V
VIL = 0 V
VIH = VCC
−
µA
µA
IIH
10
CMOS output: pins LOS1, LOS2, INWINDOW and INT
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = 1 mA
0
−
−
0.2
V
V
IOH = −0.5 mA
V
CC − 0.2
VCC
Open-drain output: pin INT
VOL
IOH
LOW-level output voltage
HIGH-level output current
IOL = 1 mA
VOH = VCC
0
−
−
0.2
10
V
−
µA
Serial output: pins COUT, COUTQ, DOUT and DOUTQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
50
80
110
mV
(peak-to-peak value)
external load;
ENLOUTQ = LOW;
see Figs 23 and 27; note 3
Zo
tr
output impedance
rise time
single-ended to VCC
20% to 80%
80
−
100
100
100
120
−
Ω
ps
ps
tf
fall time
80% to 20%
−
−
2003 May 21
41
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SYMBOL
tD-C
PARAMETER
CONDITIONS
MIN
TYP
140
MAX
200
UNIT
ps
data-to-clock delay
(COUT, COUTQ and DOUT, 80
DOUTQ) between
differential crossovers;
see Fig.29
δ
duty cycle COUT and
COUTQ
between differential
crossovers
40
50
50
60
%
Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ
Vi(p-p)
input voltage
single-ended
−
1000
mV
(peak-to-peak value)
Vi
Zi
td
tsu
th
δ
DC input voltage
input impedance
clock delay
V
CC − 1
−
V
CC + 0.25 V
single-ended to VCC
see Fig.30
40
260
15
15
40
50
340
30
30
50
60
400
60
60
60
Ω
ps
ps
ps
%
set-up time
see Fig.30
hold time
see Fig.30
duty cycle signals CLOOP
and CLOOPQ
between differential
crossovers
CML mode parallel output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
650
800
1000
mV
(peak-to-peak value)
external load to VCC;
AC-coupled; see Fig.27 or
DC-coupled; see Fig.28;
note 4
Zo
tr
output impedance
rise time
single-ended to VCC
20% to 80%
70
95
110
350
350
400
Ω
200
200
−
250
250
−
ps
tf
fall time
80% to 20%
ps
fPBR
parallel bit rate
Mbits/s
LVPECL mode parallel output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
VOH
HIGH-level output voltage
50 Ω termination to
CC − 2V; see Fig.24
50 Ω termination to
CC − 2V; see Fig.24
default output voltage swing LVPECL floating; Fig.21;
V
CC − 1.2
V
CC − 1.0 VCC − 0.9
V
V
VOL
LOW-level output voltage
VCC − 2.0
VCC − 1.9 VCC − 1.7
V
V
Vo(p-p)
700
900
1150
mV
(peak-to-peak value)
single-ended with 50 Ω
external load to VCC
;
AC-coupled; see Fig.26 or
DC-coupled; see Fig.25;
note 4
tr
rise time
20% to 80%
80% to 20%
300
300
−
350
350
−
400
400
400
ps
tf
fall time
ps
fpar
parallel bit rate
Mbits/s
2003 May 21
42
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Parallel timing output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
tD-C
data-to-clock delay
D00 to D15/POCLK
DMX 1:16, 1:10, 1:8;
see Fig.31; note 5
−100
100
250
ps
tD-C
data-to-clock delay
D06 to D09/POCLK
DMX 1:4; see Fig.31; note 5 150
180
250
ps
δ
duty cycle POCLK
40
50
60
%
skew
channel to channel skew
D00 and Dn (between
channels)
DMX 1:16, 1:10, 1:8; note 5
DMX 1:4; note 5
−
−
−
200
ps
skew
channel to channel skew
D06 and D09 (between
channels)
−
50
ps
V
Reference: pin RREF
Vref
reference voltage
10 to 20 kΩ resistor to VEE 1.17
1.21
1.26
I2C-bus pins SCL and SDA
VIL
LOW-level input voltage
−
−
−
−
0.2VCC
V
V
V
VIH
Vhys
HIGH-level input voltage
0.8VCC
−
−
hysteresis of Schmitt trigger
inputs
0.05VCC
VOL
SDA LOW-level output
voltage (open-drain)
IOL = 3 mA
0
−
0.4
V
IL
leakage current
−10
−
−
+10
µA
Ci
input capacitance
−
10
pF
I2C-bus timing
fSCL
SCL clock frequency
−
−
−
−
−
−
100
−
kHz
µs
tLOW
SCL LOW time
1.3
0.6
0.6
0.6
tHD;STA
tHIGH
tSU;STA
hold time START condition
SCL HIGH time
−
µs
−
µs
set-up time START
condition
−
µs
tHD;DAT
tSU;DAT
tSU;STO
tr
data hold time
0
−
−
−
−
−
−
0.9
−
µs
ns
µs
ns
ns
µs
data set-up time
100
0.6
20
20
1.3
set-up time STOP condition
SCL and SDA rise time
SCL and SDA fall time
−
300
300
−
tf
tBUF
bus free time between
STOP and START
Cb
capacitive load on each bus
line
−
−
−
400
50
pF
ns
tSP
pulse width of allowable
spikes
0
2003 May 21
43
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SYMBOL
VnL
VnH
PARAMETER
CONDITIONS
MIN
0.1VCC
0.2VCC
TYP
MAX
UNIT
noise margin at LOW-level
noise margin at HIGH-level
−
−
−
−
V
V
RF input: pins IN1, INQ1, IN2 and IN2Q
Vi(p-p)
input voltage swing
(peak-to-peak value)
single-ended; note 6
12
−
−
500
mV
Vsl
Zi
typical slice level range
input impedance
note 7
−50
80
−
+50
120
−
mV
Ω
differential
100
60
αiso
between channel isolation
dB
Received Signal Strength Indicator (RSSI)
Vi(p-p)
input voltage swing
(peak-to-peak value)
single-ended
5
−
500
mV
SRSSI
VRSSI
RSSI sensitivity
output voltage
see Fig.4
15
17
20
mV/dB
mV
Vi(p-p) = 32 mV (p-p);
PRBS (231−1)
580
680
780
∆Vo(RSSI)
output voltage variation
input 30 to 3200 Mbits/s;
PRBS (231−1);
−50
−
+50
mV
VCC = 3.14 to 3.47 V;
∆T = 120 °C
Output: pins RSSI1 and RSSI2
Zo
output impedance
output source current
output sink current
−
−
−
1
−
−
10
1
Ω
IO(source)
IO(sink)
mA
mA
0.4
LOS detector
hys
ta
hysteresis
note 8
−
−
−
3
−
−
−
5
5
dB
µs
µs
assert time
de-assert time
∆Vi(p-p) = 3 dB
∆Vi(p-p) = 3 dB
td
Reference frequency input: pins CREF and CREFQ
Vi(p-p)
input voltage
single-ended
50
−
1000
mV
(peak-to-peak value)
Vi
DC input voltage
input impedance
V
CC − 1
−
V
CC + 0.25 V
Zi
single-ended to VCC
40
50
−
60
+20
Ω
∆fCREF
reference clock frequency
accuracy
SDH/SONET requirement
−20
ppm
fCREF
reference clock frequency
see Table 7; R = 1, 2, 4 or 8 18 × R
19.44 × R 21 × R
MHz
PLL characteristics
tacq
acquisition time
30 Mbits/s
30 Mbits/s
−
−
−
−
200
10
µs
tacq(pc)
acquisition time at power
cycle
ms
tacq(o)
TDR
acquisition time octave
change
30 Mbits/s
30 Mbits/s
−
−
−
10
µs
transitionless data run
1000
−
bits
2003 May 21
44
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Jitter tolerance
Jtol(p-p)
jitter tolerance
(peak-to-peak value)
STM1/OC3 mode
(ITU-T G.958);
PRBS (231−1); note 9
f = 6.5 kHz
f = 65 kHz
f = 1 MHz
3
10
1
−
−
−
UI
0.3
0.3
UI
UI
0.5
STM4/OC12 mode
(ITU-T G.958);
PRBS (231−1); note 10
f = 25 kHz
f = 250 kHz
f = 5 MHz
3
10
1
−
−
−
UI
UI
UI
0.3
0.3
0.5
STM16/OC48 mode
(ITU-T G.958);
PRBS (231−1); note 11
f = 100 kHz
f = 1 MHz
3
10
1
−
−
−
UI
UI
UI
0.3
0.3
f = 20 MHz
0.5
Notes
1. Default settings: UI = LOW (pre-programmed mode; see Table 1); DR0 = LOW, DR1 = HIGH, DR2 = LOW
(STM16/OC48); INSEL = HIGH (limiter 1 active); WINSIZE = HIGH (1000 ppm); ENBA = HIGH (automatic byte
alignment); ENLOUTQ = HIGH (DOUT, COUT disabled); ENLINQ = HIGH (DLOOP, CLOOP disabled);
DMXR0 = HIGH, DMXR1 = HIGH (DMX ratio 1:16); CREF and CREFQ = 19.44 MHz; LOSTH2 not connected
(LOS2 switched off); D00 to D15 and D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ, PRSCLO
and PRSCLOQ not connected.
2. The total supply current and power dissipation is dependent on the IC setups such as swing and loop modes and
termination conditions.
3. The output swing is adjustable in 16 steps controlled by bits RFS in I2C-bus register CBH.
4. The output swing is adjustable in 16 steps controlled by bits MFS in I2C-bus register IOCNF3 (address C8H). In
standard LVPECL mode only swing = 12 (default) should be used.
5. With 50% duty cycle.
6. The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that
both inputs carry a complementary signal of the specified peak-to-peak value.
7. The slice level is adjustable in 256 steps controlled by I2C-bus registers LIMSLICE1 (address C0H) and LIMSLICE2
(address C1H).
8. The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I2C-bus registers LIMLOS1CNF
(address BDH) and LIMLOS2CNF (address BFH).
9. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 65 kHz and 1 MHz.
10. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 250 kHz and 5 MHz.
11. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 1 MHz and 20 MHz.
2003 May 21
45
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL556
50
CCD
I
(mA)
40
LVPECL standard
30
20
10
CML AC
LVPECL floating
CML DC
10
0
0
5
15
value of address C8H, bit 3 to bit 0
Fig.20 Supply current per parallel output.
MBL557
1000
o(p-p)
V
DEFAULT
(mV)
800
LVPECL standard
600
400
200
0
CML AC/DC
LVPECL floating
0
5
10
15
value of address C8H, bit 3 to bit 0
Fig.21 Output voltage swing of parallel output.
46
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL558
50
CCD
I
(mA)
40
CML AC
30
20
10
low swing
0
0
5
10
15
value of address CBH, bit 3 to bit 0
Serial outputs are off (default).
Fig.22 Supply current per serial output.
MBL559
1000
o(p-p)
(mV)
V
800
600
400
200
0
CML AC
(clock 2.4 GHz)
low swing
(ENLOUTQ = LOW)
0
5
10
15
value of address CBH, bit 3 to bit 0
Fig.23 Output voltage swing of serial output.
47
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SWING CONTROL
V
CC
V
2 V
term
optional
AC coupling
transmission
lines
OUT
to high-
impedance
input
50 Ω
50 Ω
OUTQ
I
swing
50 Ω
50 Ω
in
on-chip
off-chip
MBL562
Fig.24 Standard PECL mode.
SWING CONTROL
V
CC
transmission lines
OUT
to high-
impedance
input
50 Ω
100 Ω
50 Ω
OUTQ
I
swing
in
on-chip
off-chip
MBL560
Fig.25 Floating PECL mode (DC-coupled).
48
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SWING CONTROL
V
CC
V
bias
AC coupling
transmission
lines
50 Ω
50 Ω
OUT
to high-
impedance
input
50 Ω
50 Ω
OUTQ
I
swing
in
on-chip
off-chip
MBL561
Fig.26 Floating LVPECL mode (AC-coupled).
recommended for
serial outputs
SWING CONTROL
V
CC
V
bias
120
Ω
100 Ω
100 Ω
50 Ω
transmission
50 Ω
100 Ω
100 Ω
lines
OUT
to high-
impedance
input
50 Ω
50 Ω
OUTQ
I
swing
in
on-chip
off-chip
MBL563
Fig.27 CML mode (AC-coupled).
49
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SWING CONTROL
V
CC
100 Ω
100 Ω
50 Ω
transmission
50 Ω
lines
OUT
to high-
impedance
input
50 Ω
50 Ω
OUTQ
I
swing
in
on-chip
off-chip
MBL564
Fig.28 CML mode (DC-coupled).
COUT
t
D-C
DOUT
MGU345
The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential).
Fig.29 Loop mode output timing.
2003 May 21
50
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
handbook, halfpage
CLOOP
DLOOP
t
d
t
t
h
su
MBL554
The timing is measured from the crossover point of the clock input signal to the crossover point of the data input.
Fig.30 Loop mode input timing.
POCLK
t
D-C
D00 to D15,
FP, PARITY
MGU343
The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential).
Fig.31 Parallel bus output timing.
2003 May 21
51
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PACKAGE OUTLINE
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;
body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c
y
exposed die pad side
X
D
h
A
75
51
50
76
Z
E
e
H
E
E
E
(A )
3
A
h
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
detail X
26
100
1
25
w M
Z
v
v
M
M
A
B
D
b
p
e
D
B
H
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
D
E
E
e
H
H
L
L
p
v
w
y
Z
Z
E
θ
1
2
3
p
h
h
D
E
D
max.
0.15 1.05
0.05 0.95
0.27 0.20 14.1 7.1 14.1 7.1
0.17 0.09 13.9 6.1 13.9 6.1
16.15 16.15
15.85 15.85
0.75
0.45
1.15 1.15
0.85 0.85
7°
0°
mm
1.2
0.25
0.5
1
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-03-30
03-04-07
SOT638-1
2003 May 21
52
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
SOLDERING
To overcome these problems the double-wave soldering
method was specifically developed.
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material.
The top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 220 °C (SnPb process) or below 245 °C
(Pb-free process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all the BGA packages
Manual soldering
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the
lead. Contact time must be limited to 10 seconds at up to
300 °C.
volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C
(Pb-free process) for packages with a thickness
< 2.5 mm and a volume < 350 mm3 so called small/thin
packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 May 21
53
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 May 21
54
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 May 21
55
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 May 21
56
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
57
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
58
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
59
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/02/pp60
Date of release: 2003 May 21
Document order number: 9397 750 10905
相关型号：
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