MSM66Q573LY-XXLA [OKI]
Microcontroller, 16-Bit, FLASH, 14MHz, CMOS, PBGA144, 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144;
| 型号： | MSM66Q573LY-XXLA |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Microcontroller, 16-Bit, FLASH, 14MHz, CMOS, PBGA144, 11 X 11 MM, 0.80 MM PITCH, PLASTIC, LFBGA-144 时钟 微控制器 外围集成电路 |
| 文件： | 总28页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PEDL66573-03
This version:
Previous version: Aug.1999
Mar. 2000
1
Semiconductor
MSM66573 Family
Preliminary
16-Bit Microcontroller
GENERAL DESCRIPTION
The MSM66573 family of highly functional CMOS 16-bit single chip microcontrollers utilize the nX-8/500S,
Oki's proprietary CPU core.
A wide variety of internal multi-functioned timers provide timer functions such as compare out, capture input,
event counter, auto reload, and PWM, and can be used for periodic and timed measurements.
And features such as a clock gear function, dual clock function, STOP/HALT mode, programmable pull-up ports
in which individual bits can be programmed, and a small, thin package, the MSM66573 family of microprocessors
is optimally suited for the system control of small-sized low power devices.
A three channel serial interface and a high-speed bus interface that has separate address and data buses and does
not require external address latches are provided as interfaces to external devices.
With a 16-bit CPU core that enables high-speed 16-bit arithmetic computations and a variety of bit processing
functions, this general-purpose microcontroller is optimally suited for Digital Audio devices such as a Mini-Disc
and an MP3 player.
The flash ROM version (MSM66Q573LY) programmable with a single 3V power supply (2.7 to 3.3V) and flash
ROM version (MSM66Q573Y) programmable with a single 5V power supply (4.5 to 5.5V) are also included in the
family. These versions are easily adaptable to sudden specification changes and to new product versions.
APPLICATIONS
Digital Audio Control Systems
PC peripheral Control Systems
Office Electronics Control Systems
ORDERING INFORMATION
Order Code or Product Name
Package
Remark
MSM66573L-xxTB *1
MSM66573-xxTB *1
MSM66Q573LY-NTB *2
MSM66Q573Y-NTB *2
MSM66P573-NTB*2
MSM66573L-xxWA *1
MSM66573L-xxLA *1
MSM66Q573LY-NLA *2
Low voltage mask ROM version (2.4 to 3.6 V)
5V mask ROM version (4.5 to 5.5 V)
MSM66573L flash ROM version (2.7 to 3.3 V)
MSM66573 flash ROM version (4.5 to 5.5 V)
MSM66573 OTP ROM version (2.7 to 5.5 V)
MSM66573L Chip version (2.4 to 3.6 V)
MSM66573L BGA package version (2.4 to 3.6 V)
MSM66Q573LY BGA package version
(2.7 to 3.3 V)
100-pin plastic TQFP
(TQFP 100-P-1414-0.50-K)
Chip
144-pin plastic LFBGA
(P-LFBGA144-1111-0.80)
*1 : The “xx” of “-xx” stands for the code number.
*2 : The “N” of “-N” stands for the flash ROM and the OTP ROM, blank version.
When OKI programs and ship the flash ROM and OTP, the part number is changed from ”–N” to ”–XX” (code
number ) , for example, MSM66Q573LY-999TB.
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PEDL66573-03
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Semiconductor
MSM66573 Family
FEATURES
Name
MSM66573L
MSM66573
Operating temperature
Power supply voltage/ maximum
frequency
–30°C to +70°C
VDD=2.4 to 3.6 V / f=14 MHz
VDD=4.5 to 5.5 V / f=30 MHz
143 ns at 14 MHz (2.4 to 3.6 V)
67ns at 30 MHz (4.5 to 5.5 V)
Minimum instruction execution
time
61µs at 32.768 kHz (2.4 to 3.6/4.5 to 5.5 V)
Internal ROM size (max. external)
Internal RAM size (max. external)
64 KB (1 MB)
4 KB (1 MB)
75 I/O pins
I/Oports
Timers
(with programmable pull-up resistors)
8 input-only pins
16-bit free running timer × 1ch
Compare out/capture input × 2ch
16-bit timer (auto reload/timer out) × 1ch
8-bit auto reload timer × 1ch
8-bit auto reload timer × 3ch
(also fumctions as serial communication baud rate generator)
8-bit auto reload timer (also functions as Watchdog timer)
Watch timer (real-time counter) × 1ch
8-bit PWM × 4ch
(can also be used as 16-bit PWM × 2ch)
UART × 1ch
Serial port
Synchronous × 1ch
UART/ Synchronous × 1ch
A/D converter
10-bit A/D converter, 8-ch multiplexer × 1ch
Non-maskable × 1ch
Maskable × 6ch
External interrupt
Interrrupt priority
3 levels
External bus interface (Separate address and data busses)
Bus release function
Others
Dual clocks function
Clock gear function
MSM66P573
OTP ROM version
Flash ROM version
(VDD=2.7 to 3.6V, Max. f = 12MHz / VDD=4.5 to 5.5V, Max. f = 24MHz)
MSM66Q573LY
(VDD=2.7 to 3.3V)
MSM66Q573Y
(Max. f = 26MHz)
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Semiconductor
MSM66573 Family
SPECIAL FEATURES
1. High-performance CPU
The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical
addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.
2. A variety of power saving modes
Attaching a 32.768-kHz crystal produces a real-time clock signal from the internal clock timer. Use of a single
clock in place of dual clocks is possible.
The clock gear function allows a 1/2 × or 1/4 × main clock to be selected for the CPU operating clock.
Switching the CPU clock to 32.768-kHz signal, 1/2 × main clock, or 1/4 × main clock, then produces operation in
a low power consumption mode.
The family provides a wide range of standby control functions. In addition to the usual STOP mode that stops the
oscillator, there are the quick restart STOP mode that shuts down the CPU and peripherals but leaves the oscillator
running, and the HALT mode that shuts down the CPU but leaves the peripherals running.
3. MSM66Q573LY and MSM66Q573Y with flash memory programmable with single power supply
In addition to the regular mask ROM version, the family includes these versions with 64KB of flash memory that
can be programmed using a single power supply.
For the MSM66Q573LY, an internal booster circuit derives the necessary program voltage from the device's low
(2.7 to 3.3 V) power supply, and the program voltage for the MSM66Q573Y is provided with a single 5 V power
supply (4.5 to 5.5 V).
4. Multifunction, high-precision A/D converter
The family includes a high-precision 10-bit analog-to-digital converter with eight channels and is ideal for such
analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and
controlling battery use in portable equipment. Each channel has its own result register readily accessible from the
software. In addition to single-channel conversions, there is also a scan function offering automatic conversion
from the user's choice of starting channel through to the last channel.
5. Multifunction PWM
The family supports both 8- and 16-bit PWM operation.
Choosing between the time-base counter output or overflow from an 8-bit auto-reload timer as the PWM counter
clock source provides a wide number of possibilities over a broad frequency range. The 16-bit PWM
configuration supports a high-speed synchronization mode that generates a high-precision output signal with less
ripple suitable for digital-to-analog control applications.
6. Programmable pull-up resistors
Building the pull-up resistors into the chip contributes to overall design compactness.
Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system
design. These programmable pull-up resistors are available for all I/O pins not already assigned specific functions
(such as the oscillator connection pins).
7. High-speed bus interface
The interface to external devices uses separate data and address buses.
This arrangement permits rapid bus access for controlling the system from the microcontroller.
8. Wide support for external interrupts
There are a total of seven interrupt channels for use in communicating with external devices: six for maskable
interrupts and one for non-maskable interrupts.
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PEDL66573-03
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Semiconductor
MSM66573 Family
BLOCK DIAGRAM
TM0OUT
16 bit Timer0
TM0EVT
CPU Core
XT0
XT1
OSC0
CLKOUT
XTOUT
Peripheral
System
OSC1
HOLD
HLDACK
RES
Control
RXD0
TXD0
RXC0
SIO0
(UART)
ALU
Control
Registers
TM3OUT
TM3EVT
8 bit Timer3/BRG
SSP
LRB
PSW
PC
ALU Control
ACC
RXD1
TXD1
RXC1
DSR TSR CSR
SIO1
(UART/SYNC)
8 bit Time4/BRG
TM4OUT
Memory Control
Pointing Registers
Local Registers
SIOI3
Instruction
Decoder
SIO3
(SYNC)
SIOO3
SIOCK3
8 bit Timer5/BRG
8 bit Timer6/WDT
EA
PSEN
RD
WR
WAIT
TM5EVT
RAM 4K
ROM 64K
PWMOUT0
PWMOUT2
PWMOUT1
PWMOUT3
8 bit PWM0
8 bit PWM1
D0
to
D7
A0
to
A19
TM9OUT
TM9EVT
8 bit Timer9
CAP/CMP
16 bit FRC
P0
P1
P2
P3
P4
P5
P6
P7
TBC
RTC
CPCM0
CPCM1
VREF
AGND
AI0 to AI7
10 bit A/D
Converter
P8
P9
P10
P11
P12
NMI
EXINT0
to
Interrupt
EXINT5
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Semiconductor
MSM66573 Family
PIN CONFIGURATION (TOP VIEW)
P10-4
P10-5
P1-7/A15
P1-6/A14
P1-5/A13
P1-4/A12
P1-3/A11
P1-2/A10
P1-1/A9
P1-0/A8
P4-7/A7
P4-6/A6
P4-5/A5
P4-4/A4
P4-3/A3
P4-2/A2
P4-1/A1
P4-0/A0
GND
P0-7/D7
P0-6/D6
P0-5/D5
P0-4/D4
P0-3/D3
P0-2/D2
P0-1/D1
P0-0/D0
1
5
75
70
65
60
55
TM5EVT/P10-7
RXD1/P8-0
TXD1/P8-1
RXC1/P8-2
TXC1/P8-3
TM4OUT/P8-4
PWM2OUT/P8-6
PWM3OUT/P8-7
PWM0OUT/P7-6
PWM1OUT/P7-7
VDD
10
15
20
25
GND
HLDACK/P9-7
EXINT4/P9-0
EXINT5/P9-1
P9-2
P9-3
EXINT0/P6-0
EXINT1/P6-1
EXINT2/P6-2
EXINT3/P6-3
P6-4
P6-5
100-pin Plastic TQFP
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Semiconductor
MSM66573 Family
PIN CONFIGURATION (TOP VIEW)
NC
NC
NC
P3-2 P11-7 P11-2 P11-0
NC
XT0
P5-7 P5-4 P6-6
NC
EA
N
M
L
P3-3 P3-1 P11-1 VDD
GND
VDD
NMI
P5-6
NC
NC
OSC1
XT1
NC
NC
P0-0 P0-2
NC
P11-6 P11-3 OSC0 NC
P5-5 P6-7 P6-4 P6-5
RES
P0-3 P0-5 P0-1
P0-6 P0-7 P0-4
GND P4-0 P4-1
P4-4 P4-2 P4-3
P1-0 P4-6 P4-5
P1-2 P4-7 P1-3
P1-5 P1-1 P1-4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P6-2 P9-3 P6-3
P6-1 P9-1 P6-0
P9-7 P9-0 P9-2
K
J
H
G
F
VDD
P7-7 GND
P7-6 P8-7 P8-6
P8-1 P8-4 P8-3
E
D
C
B
A
NC
NC
NC
NC
NC
NC
NC
NC P10-5 P8-2 P8-0
P1-7 P1-6 P2-1 P2-3 P12-0 P12-6 NC
NC
NC P10-7 P10-4
NC
NC
NC
VDD P12-1 P12-3 P12-5 P12-7 P7-0 P7-1 P7-2 P10-0 P10-2 NC
P2-0 P2-2
VREF P12-2 P12-4 AGND GND P7-4 P7-5 P10-1 P10-3 NC
13 12 11 10 9
8
7
6
5
4
3
2
1
144-pin Plastic LFBGA
[Note] Don’t connect NC pins with others.
6/28
PEDL66573-03
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Semiconductor
MSM66573 Family
PIN DESCRIPTIONS
In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.
Function
Classification
Port
Symbol
P0_0/D0
Type
I/O
Primary function
8-bit I/O port
10 mA sink capability
Type
I/O
Secondary function
External memory access
Data I/O port
to
Pull-up resistors can be
specified for each individual bit
P0_7/D7
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
External memory access
Address output port
P1_0/A8
to
P1_7/A15
P2_0/A16
to
P2_3/A19
P3_1/PSEN
I/O
I/O
I/O
O
O
O
4-bit I/O port
Pull-up resistors can be
specified for each individual bit
External memory access
Address output port
3-bit I/O port
External program memory
access
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
Read strobe output pin
External memory access
Read strobe output pin
External memory access
Write strobe output pin
External memory access
Address output port
O
O
O
P3_2/RD
P3_3/WR
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
P4_0/A0
to
P4_7/A7
I/O
I/O
4-bit I/O port
Pull-up resistors can be
specified for each individual bit
Capture 0 input / Compare
0 output pin
Capture 1 input / Compare
1 output pin
I/O
I/O
P5_4/CPCM0
P5_5/CPCM1
P5_6/TM0OUT
P5_7/TM0EVT
O
I
Timer 0 timer output pin
Timer 0 external event input pin
External interrupt 0 input pin
External interrupt 1 input pin
External interrupt 2 input pin
External interrupt 3 input pin
None
8-bit I/O port
Pull-up resistors can be
specified for each individual bit
I/O
P6_0/EXINT0
P6_1/EXINT1
P6_2/EXINT2
P6_3/EXINT3
P6_4 to P6_7
I
I
I
I
—
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Semiconductor
MSM66573 Family
Function
Type
Classification
Port
Symbol
Type
I/O
Primary function
7-bit I/O port
Pull-up resistors can be
Secondary function
I
O
I
P7_0/RXD0
P7_1/TXD0
SIO0 receive data input pin
SIO0 transmit data output pin
SIO0 external clock input pin
Timer 3 timer output pin
Timer 3 external event input pin
PWM0 output pin
specified for each individual bit
P7_2/RXC0
O
I
P7_4/TM3OUT
P7_5/TM3EVT
P7_6/PWM0OUT
P7_7/PWM1OUT
P8_0/RXD1
O
O
I
PWM1 output pin
7-bit I/O port
I/O
SIO1 receive data input pin
SIO1 transmit data output pin
SIO1 receive clock I/O pin
SIO1 transmit clock I/O pin
Timer 4 timer output pin
PWM2 output pin
Pull-up resistors can be
specified for each individual bit
O
I/O
I/O
O
O
P8_1/TXD1
P8_2/RXC1
P8_3/TXC1
P8_4/TM4OUT
P8_6/PWM2OUT
P8_7/PWM3OUT
P9_0/EXINT4
P9_1/EXINT5
P9_2, P9_3
O
I
PWM3 output pin
5-bit I/O port
I/O
I/O
External Interrupt 4 input pin
External Interrupt 5 input pin
None
Pull-up resistors can be
specified for each individual bit
I
—
O
I/O
I
P9_7/HLDACK
P10_0/SIOCK3
P10_1/SIOI3
P10_2/SIOO3
P10_3 to P10_5
P10_7/TM5EVT
P11_0/WAIT
HOLD mode output pin
SIO3 transmit-receive clock I/O pin
SIO3 receive data input pin
SIO3 transmit data output pin
None
7-bit I/O port
Pull-up resistors can be
specified for each individual bit
O
—
I
Timer 5 external event input pin
External data memory access
wait input pin
6-bit I/O port
I/O
I
10 mA sink capability
Pull-up resistors can be
specified for each individual bit
I
P11_1/HOLD
P11_2/CLKOUT
P11_3/XTOUT
P11_6/TM9OUT
P11_7/TM9EVT
HOLD mode request input pin
Main clock pulse output pin
Sub clock pulse output pin
Timer 9 timer output pin
O
O
O
I
Timer 9 external event input pin
P12_0/AI0
to
8-bit input port
A/D converter analog input port
I
I
P12_7/AI7
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PEDL66573-03
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Semiconductor
MSM66573 Family
Classification
Power
Symbol
VDD
Type
I
Function
Power supply pin
supply
Connect all VDD pins to the power supply.*
GND
I
GND pin
Connect all GND pins to GND.*
Analog reference voltage pin
VREF
I
AGND
XT0
I
I
Analog GND pin
Sub clock oscillation input pin
Oscillation
Connect to a crystal oscillator of f = 32.768 kHz.
O
I
Sub clock oscillation output pin
XT1
Connect to a crystal oscillator of f = 32.768 kHz.
The clock output is opposite in phase to XT0.
Main clock oscillation input pin
OSC0
Connect to a crystal or ceramic oscillator. Or, input an external
clock.
O
Main clock oscillation output pin
OSC1
Connect to a crystal or ceramic oscillator.
The clock output is opposite in phase to OSC0.
Leave this pin unconnected when an external clock is used.
Reset input pin
Non-maskable interrupt input pin
External program memory access input pin
If the EA pin is enabled (low level), the internal program memory is
masked and the CPU executes the program code in external
program memory through all address space.
Reset
Other
I
I
I
RES
NMI
EA
* Each of the family devices has unique pattern routes for the internal power and ground. Connect the
power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one
or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it
can not be guaranteed for normal operation.
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Semiconductor
MSM66573 Family
ABSOLUTE MAXIMUM RATINGS
Parameter
Digital power supply voltage
Input voltage
Symbol
VDD
VI
Condition
Rated value
Unit
V
–0.3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VREF
650
V
GND=AGND=0V
Ta=25°C
Output voltage
VO
V
Analog reference voltage
Analog input voltage
VREF
VAI
V
V
100-pin TQFP
144-pin LFBGA
100-pin TQFP
144-pin LFBGA
mW
mW
mW
mW
Ta=70°C
per package
750
Power dissipation
PD
Ta=50°C
(MSM66Q573LY)
per package
800
950
—
Storage temperature
TSTG
–50 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Rated value
4.5 to 5.5
4.5 to 5.5
2.4 to 3.6
2.7 to 3.3
Unit
V
MSM66573
f
f
f
f
OSC≤30 MHz
OSC≤26 MHz
OSC≤14 MHz
OSC≤14 MHz
MSM66Q573Y
MSM66573L
MSM66Q573LY
Dogital power supply
voltage
VDD
f
f
OSC≤24 MHz
OSC≤12 MHz
4.5 to 5.5
2.7 to 3.6
MSM66P573
Analog reference voltage
Analog input voltage
Memory hold voltage
VREF
VAI
—
—
VDD–0.3 to VDD
AGND to VREF
V
V
V
VDDH
fOSC=0Hz
2.0 to 5.5
2 to 30
2 to 26
2 to 14
2 to 14
MSM66573
MSM66Q573Y
MSM66573L
VDD=4.5 to 5.5 V
VDD=4.5 to 5.5 V
VDD=2.4 to 3.6 V
VDD=2.7 to 3.3 V
fOSC
MHz
MSM66Q573LY
Operating frequency
VDD=4.5 to 5.5 V
VDD=2.7 to 3.6 V
2 to 24
2 to 12
32.768
–30 to +70
–20 to +50
20
MSM66P573
fXT
Ta
—
KHz
°C
°C
—
Except MSM66Q573LY
MSM66Q573LY
MOS load
Ambient temperature
Fan out
P0, P3, P11
P1, P2, P4, P5,
P6, P7, P8, P9, P10
6
—
N
TTL load
1
—
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PEDL66573-03
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Semiconductor
MSM66573 Family
ALLOWABLE OUTPUT CURRENT VALUES
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6V, Ta=–30 to +70°C)
Parameter
Pin
Symbol
IOH
Min.
—
Typ.
—
Max.
–2
Unit
“H” output pin (1 pin)
All output pins
Sum total of all output
pins
“H” output pins (sum total)
—
—
–40
∑ IOH
10
5
P0, P3, P11
“L” output pin (1 pin)
IOL
—
—
Other ports
80
mA
Sum total of P0, P3, P11
Sum total of P1, P2, P4
Sum total of P5, P6, P9
50
“L” output pins (sum total)
[Note]
—
—
∑ IOL
Sum total of P7, P8, P10
Sum total of all output
pins
140
Each of the family devices has unique pattern routes for the internal power and ground. Connect the
power supply voltage to all VDD pins and the ground potential to all GND pins. If a device may have one
or more VDD or GND pins to which the power supply voltage or the ground potential is not connected, it
can not be guaranteed for normal operation.
INTERNAL FLASH ROM PROGRAMMING CONDITIONS
Parameter
Supply Voltage
Symbol
VDD
Condition
MSM66Q573Y
Rating
4.5 to 5.5
Unit
V
MSM66Q573LY
2.7 to 3.3
V
During
Read
MSM66Q573Y
MSM66Q573LY
-30 to +70
-20 to +50
+0 to +50
100
°C
°C
°C
Cycles
bytes
Ambient Temperature
Ta
During Programming
Endurance
Blocks size
CEP
—
—
—
128
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Semiconductor
MSM66573 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5 V)
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
“H” input voltage
“H” input voltage
Symbol
VIH
Condition
Min.
Typ.
—
Max.
Unit
0.44 VDD
VDD+0.3
*1
—
0.80 VDD
–0.3
—
—
—
VDD+0.3
0.16 VDD
0.2 VDD
*2, *3, *4, *5, *6
“L” input voltage
“L” input voltage
*1
VIL
—
–0.3
*2, *3, *4, *5, *6
IO=–400 µA
IO=–2.0 mA
IO=–200 µA
IO=–2.0 mA
IO=3.2 mA
IO=10.0 mA
IO=1.6 mA
IO=5.0 mA
VDD–0.4
VDD–0.6
VDD–0.4
VDD–0.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
“H” output voltage *1, *4
V
VOH
—
“H” output voltage
“L” output voltage
“L” output voltage
*2
*1, *4
*2
—
0.4
—
0.8
VOL
—
0.4
—
0.8
Input leakage current
Input current
*3
*5
*6
—
1/–1
1/–250
15/–15
IIH/IIL
VI=VDD/0 V
VO=VDD/0 V
—
µA
µA
Input current
—
output leakage current
*1, *2, *4
ILO
—
—
±10
100
Except
MSM66Q573Y
MSM66Q573Y
25
50
kΩ
kΩ
VI=
0 V
Rpull
Pull-up resistance
15
—
30
5
100
—
CI
Input capacitance
Output capacitance
f=1 MHz, Ta=25°C
pF
CO
—
—
—
7
—
4
During A/D operation
When A/D is stopped
—
—
mA
Analog reference supply
current
IREF
10
µA
*1: Applicable to P0
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10
*3: Applicable to P12, EA, NMI
*4: Applicable to P3, P11
*5: Applicable to RES
*6: Applicable to OSC0
12/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
Supply current (VDD=4.5 to 5.5 V)
• MSM66573
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Symbol
Condition
f=30 MHz
Min.
Typ.
Max.
Unit
mA
µA
Mode
—
36
55
CPU operation mode *1
HALT mode *2
IDD
—
60
160
35
f=32.768 kHz
f=30 MHz
IDDH
—
23
mA
—
—
5
1
110
100
OSC is
stopped
XT is used
XT is not used
STOP mode *3
IDDS
µA
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
• MSM66Q573Y
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Symbol
IDD
Condition
Min.
Typ.
Max.
Unit
Mode
—
42
70
mA
f=26 MHz
f=32.768 kHz
f=26 MHz
CPU operation mode *1
—
40
1000
40
µA
IDDH
—
24
mA
HALT mode *2
STOP mode *3
—
—
30
20
950
900
OSC is
stopped
XT is used
XT is not used
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C
IDDS
µA
—
15
200
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
• MSM66P573
(VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Mode
Symbol
IDD
Condition
f=24 MHz
Min.
—
Typ.
60
Max.
80
Unit
mA
µA
CPU operation mode *1
—
114
30
300
40
f=32.768 kHz
f=24 MHz
IDDH
—
mA
HALT mode *2
STOP mode *3
—
—
6
1
120
100
OSC is
stopped
XT is used
XT is not used
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
13/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
DC Characteristics 2 (VDD=2.4 to 3.6 V)
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
“H” input voltage
“H” input voltage
Symbol
VIH
Condition
—
Min.
Typ.
—
Max.
Unit
0.44VDD
VDD+0.3
*1
0.80VDD
–0.3
—
—
—
VDD+0.3
0.16 VDD
0.2 VDD
*2, *3, *4, *5, *6
“L” input voltage
“L” input voltage
*1
VIL
—
–0.3
*2, *3, *4, *5, *6
V
DD–0.4
DD–0.8
—
—
—
—
—
—
—
—
—
—
IO=–400 µA
IO=–2.0 mA
IO=–200 µA
IO=–1.0 mA
IO=3.2 mA
IO=5.0 mA
IO=1.6 mA
IO=2.5 mA
“H” output voltage *1, *4
V
V
VOH
VDD–0.4
—
“H” output voltage
“L” output voltage
*2
*1, *4
*2
VDD–0.8
—
—
0.5
0.9
0.5
0.9
—
VOL
—
“L” output voltage
—
Input leakage current
—
—
1/–1
*3
*5
*6
IIH/IIL
VI=VDD/0 V
µA
—
—
—
—
1/–250
15/–15
Input current
Input current
output leakage current
*1, *2, *4
ILO
VO=VDD/0 V
—
—
±10
200
µA
kΩ
Except
MSM66Q573LY
MSM66Q573LY
40
100
VI=
0 V
Rpull
Pull-up resistance
20
—
50
5
200
—
CI
Input capacitance
Output capacitance
f=1 MHz, Ta=25°C
pF
CO
—
—
—
7
—
2
—
—
mA
During A/D operation
When A/D is stopped
Analog reference supply
current
IREF
5
µA
*1: Applicable to P0
*2: Applicable to P1, P2, P4, P5, P6, P7, P8, P9, P10
*3: Applicable to P12, EA, NMI
*4: Applicable to P3, P11
*5: Applicable to RES
*6: Applicable to OSC0
14/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
Supply current (VDD=2.4 to 3.6 V)
• MSM66573L
(VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
Symbol
IDD
Condition
Min.
Typ.
12
30
7
Max.
Unit
mA
µA
Mode
—
20
f=14 MHz
f=32.768 kHz
f=14 MHz
CPU operation mode
—
130
11
IDDH
—
mA
HALT mode
STOP mode
—
—
2
1
110
100
OSC is
stopped
XT is used*
XT is not used*
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C*
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
• MSM66Q573LY
(VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
Mode
Symbol
IDD
Condition
f=14 MHz
Min.
—
Typ.
13
30
7
Max.
22
Unit
MA
CPU operation mode
—
130
11
µA
f=32.768 kHz
f=14 MHz
IDDH
—
MA
HALT mode
STOP mode
—
—
3
1
110
100
OSC is
stopped
XT is used*
XT is not used*
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C*
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
• MSM66P573
(VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Mode
Symbol
IDD
Condition
f=12 MHz
Min.
—
Typ.
17
65
8
Max.
24
Unit
mA
µA
CPU operation mode
—
160
12
f=32.768 kHz
f=12 MHz
IDDH
—
mA
HALT mode
STOP mode
—
—
3
1
110
100
OSC is
stopped
XT is used*
XT is not used*
OSC is stopped, XT is not used
VDD=2 V, Ta=25°C*
IDDS
µA
—
0.2
10
[Note] Ports used as inputs are at VDD or 0 V. Other ports are unloaded.
*1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated.
*3. CPU and all the peripheral functions are deactivated (The clock timer is being activated when the XT is used).
15/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
AC Characteristics 1 (VDD = 4.5 to 5.5 V)
(1) External program memory control
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Condition
Min.
33.3 / 38.5
13
Max.
—
Unit
fOSC=30 / 26 MHz
Cycle time
—
tφWH
tφWL
tPW
tPD
tAS
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
PSEN pulse width
PSEN pulse delay time
Address setup time
Address hold time
13
—
—
2tφ–15
—
45
—
ns
CL=50 pF
tφ–25
0
25*1
tAH
tIS
—
—
Instruction setup time
Instruction hold time
Read data access time
tIH
0
—
3tφ–65*2
tACC
—
Note: tφ=tcyc/2
*1: MSM66P573= 30
*2: MSM66P573= 3tφ–70
tcyc
CPUCLK
tφWH
tφWL
PSEN
tPD
tPW
PC0 to 19
A0 to A19
D0 to D7
tAS
tAH
INST0 to 7
tIS
tACC
tIH
Bus timing during no wait cycle time
16/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
(2) External data memory control
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Condition
Min.
33.3 / 38.5
13
Max.
—
Unit
fOSC=30 / 26 MHz
Cycle time
—
tφWH
tφWL
tRW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
13
—
—
2tφ–15
2tφ–15
—
tWW
tRD
tWD
tAS
—
WR pulse width
45
45
—
RD pulse delay time
WR pulse delay time
Address setup time
Address hold time
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
—
ns
CL=50 pF
tφ–25
tφ–3
25*1
tAH
—
tRS
—
tRH
0
—
3tφ–65*2
tACC
tWS
—
—
—
2tφ–30
tφ–3
tWH
Note: tφ=tcyc/2
*1: MSM66P573= 30
*2: MSM66P573= 3tφ–70
tcyc
CPUCLK
tφWH
tφWL
RD
tRD
tRW
RAP0 to 19
tAS
A0 to A19
tAH
DIN0 to 7
tRS
D0 to D7
tACC
tWD
tAS
tRH
WR
tWW
RAP0 to 19
A0 to A19
D0 to D7
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
17/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
(3) Serial port control
Master mode
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
33.3 / 38.5
4tcyc
Max.
—
Unit
fOSC=30 / 26 MHz
tSCKC
—
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
2tφ–5
5tφ–10
13
ns
CL=50 pF
—
—
0
—
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
18/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
Slave mode
Parameter
MSM66573/Q573Y/P573 (VDD=4.5 to 5.5 V, Ta=–30 to +70°C)
Symbol
tcyc
Condition
Min.
33.3 / 38.5
4tcyc
Max.
—
Unit
fOSC=30 / 26 MHz
Cycle time
tSCKC
—
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
2tφ–15
4tφ–10
13
ns
CL=50 pF
—
—
3
—
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
Measurement points for AC timing (except the serial port)
VDD
2.0 V
2.0 V
0.8 V
0.8 V
0 V
Measurement points for AC timing (the serial port)
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0V
19/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
AC Characteristics 2 (VDD = 2.4 to 3.6 V)
(1) External program memory control
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Condition
Min.
71.4
28
Max.
—
Unit
fOSC=14 MHz
Cycle time
—
tφWH
tφWL
tPW
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
PSEN pulse width
28
2tφ–25*1
—
—
tPD
—
75
PSEN pulse delay time
Address setup time
ns
tAS
CL=50 pF
—
tφ–40
-8*2
tAH
—
Address hold time
tIS
60
-8*2
—
Instruction setup time
Instruction hold time
tIH
—
tACC
—
3tφ–120
Read data access time
Note: tφ=tcyc/2
*1: MSM66P573= 2tφ–20
*2: MSM66P573=0
tcyc
CPUCLK
tφWH
tφWL
PSEN
tPD
tPW
PC0 to 19
A0 to A19
D0 to D7
tAS
tAH
INST0 to 7
tIS
tACC
tIH
Bus timing during no wait cycle time
20/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
(2) External data memory control
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
28
Max.
—
Unit
fOSC=14 MHz
—
tφWH
tφWL
tRW
tWW
tRD
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
RD pulse width
28
—
2tφ–25*1
2tφ–25*1
—
—
—
WR pulse width
75
RD pulse delay time
WR pulse delay time
Address setup time
Address hold time
tWD
tAS
—
75
ns
CL=50 pF
—
tφ–40
tφ–8*2
60
tAH
—
tRS
—
Read data setup time
Read data hold time
Read data access time
Write data setup time
Write data hold time
tRH
0
—
tACC
tWS
tWH
—
2tφ–40*3
3tφ–120
—
—
tφ–6
Note: tφ=tcyc/2
*1: MSM66P573=2 tφ–20
*1: MSM66Q573LY=2 tφ–30
*2: MSM66P573= tφ–6
*3: MSM66Q573LY= 2tφ–50
tcyc
CPUCLK
tφWH
tφWL
RD
tRD
tRW
RAP0 to 19
A0 to A19
tAS
tAH
DIN0 to 7
tRS
D0 to D7
tACC
tWD
tAS
tRH
WR
tWW
RAP0 to 19
A0 to A19
D0 to D7
tAH
DOUT0 to 7
tWS
tWH
Bus timing during no wait cycle time
21/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
(3) Serial port control
Master mode
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
71.4
4 tcyc
2tφ–10
5tφ–20
21
Max.
—
Unit
fOSC=14 MHz
tSCKC
—
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
ns
CL=50 pF
—
—
0
—
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
22/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
Slave mode
MSM66573L (VDD=2.4 to 3.6 V, Ta=–30 to +70°C)
MSM66Q573LY (VDD=2.7 to 3.3 V, Ta=–20 to +50°C)
MSM66P573 (VDD=2.7 to 3.6 V, Ta=–30 to +70°C)
Parameter
Symbol
tcyc
Condition
Min.
71.4
4tcyc
Max.
—
Unit
fOSC=14 MHz
Cycle time
tSCKC
—
Serial clock cycle time
Output data setup time
Output data hold time
Input data setup time
Input data hold time
tSTMXS
tSTMXH
tSRMXS
tSRMXH
—
2tφ–30
4tφ–20
21
ns
CL=50 pF
—
—
7
—
Note: tφ=tcyc/2
tcyc
CPUCLK
TXC/
RXC
tSCKC
SDOUT
(TXD)
tSTMXH
tSTMXS
SDIN
(RXD)
tSRMXS
tSRMXH
Measurement points for AC timing of MSM66573L/Q573LY (except the serial port)
VDD
0.44VDD 0.44VDD
0.16VDD 0.16VDD
0V
Measurement points for AC timing of MSM66P573 (except the serial port)
VDD
2.0 V
0.8 V
2.0 V
0.8 V
0 V
Measurement points for AC timing (the serial port)
VDD
0.8VDD
0.8VDD
0.2VDD
0.2VDD
0V
23/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
A/D Converter Characteristics 1 (VDD=4.5 to 5.5 V)
MSM6573/Q573Y/P573 (Ta=–30 to +70°C, VDD=VREF=4.5 to 5.5 V, AGND=GND=0 V)
Symbol
Condition
Min.
Typ.
10
—
Max.
Unit
Parameter
Resolution
n
—
—
Bit
Refer to measurement
circuit 1
Analog input source
impedance
EL
—
±3
Linearity error
ED
—
—
±2
Differential Linearity error
Zero scale error
EZS
EFS
—
—
+3
RI≤5 kΩ
CONV=10.7 µs
LSB
t
—
—
–3
Full-scale error
Refer to measurement
circuit 2
Set according to ADTM set
data
ECT
—
—
—
±1
—
Cross talk
tCONV
10.7
µs/ch
Conversion time
A/D Converter Characteristics 2 (VDD=2.4 to 3.6 V)
MSM66573L (Ta=–30 to +70°C, VDD=VREF=2.4 to 3.6 V, AGND=GND=0 V)
MSM66Q573LY (Ta=–20 to +50°C, VDD=VREF=2.7 to 3.3 V, AGND=GND=0 V)
MSM66P573 (Ta=–30 to +70°C, VDD=VREF=2.7 to 3.6 V, AGND=GND=0 V)
Condition
Min.
Typ.
10
—
Max.
Unit
Parameter
Resolution
Symbol
n
—
—
Bit
Refer to measurement
circuit 1
Analog input source
impedance
EL
—
±4
Linearity error
ED
—
—
±3
Differential Linearity error
Zero scale error
EZS
EFS
—
—
+4
RI≤5 kΩ
CONV=27.4 µs
LSB
t
—
—
–4
Full-scale error
Refer to measurement
circuit 2
Set according to ADTM set
data
ECT
—
—
—
±2
—
Cross talk
tCONV
27.4
µs/ch
Conversion time
Reference
voltage
VREF
VDD
+5 V
+
+
0.1
µF
47
µF
0.1
µF
47
µF
RI
–
+
AI0 to AI7
AGND
GND
0 V
Analog input
CI
RI (impedance of analog input source) ≤5 kΩ
CI 0.1 µF
Measurement Circuit 1
24/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
Cross talk is the difference
5 k
Ω
–
+
between the A/D conversion
results when the same
analog input is applied to
AI0 through AI7 and the A/D
conversion results of the
circuit to the left.
AI0
AI1
Analog input
0.1 F
µ
to
AI7
VREF or AGND
Measurement Circuit 2
Definition of Terminology
1. Resolution
Resolution is the value of minimum discernible analog input.
With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible.
2. Linearity error
Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics
of a 10-bit A/D converter (not including quantization error).
Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024
equal steps.
3. Differential linearity error
Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog
input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024.
Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion
range.
4. Zero scale error
Zero scale error is the difference between ideal conversion characteristics and actual conversion
characteristics at the point where the digital output changes from 000H to 001H.
5. Full-scale error
Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics
at the point where the digital output changes from 3FEH to 3FFH.
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PEDL66573-03
1
Semiconductor
MSM66573 Family
PACKAGE DIMENSIONS
(Unit: mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.27 TYP.
4/Nov. 28, 1996
5
Notes for Mounting the Surface Mount Type Packages
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
26/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
PACKAGE DIMENSIONS
(Unit: mm)
P-LFBGA144-1111-0.80
Package material
Ball material
Epoxy resin
Sn/Pb
Package weight (g)
0.3 TYP.
5
Rev. No./Last Revised 1/Aug.25,1999
Notes for Mounting the Surface Mount Type Packages
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
27/28
PEDL66573-03
1
Semiconductor
MSM66573 Family
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as
an explanation for the standard action and performance of the product. When planning to use the
product, please ensure that the external conditions are reflected in the actual circuit, assembly, and
program designs.
3. When designing your product, please use our product below the specified maximum ratings and
within the specified operating ranges including, but not limited to, operating voltage, power
dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or
accident, improper handling, or unusual physical or electrical stress including, but not limited to,
exposure to parameters beyond the specified maximum ratings or operation outside the specified
operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc.
is granted by us in connection with the use of the product and/or the information and drawings
contained herein. No responsibility is assumed by us for any infringement of a third party’s right
which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for
commercial applications (e.g., office automation, communication equipment, measurement
equipment, consumer electronics, etc.). These products are not authorized for use in any system or
application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to
particular countries. The purchaser assumes the responsibility of determining the legality of export
of these products and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
Copyright 2000 Oki Electric Industry Co., Ltd.
28/28
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