CAV24M01 [ONSEMI]
EEPROM Serial 1-Mb I2C;型号: | CAV24M01 |
厂家: | ONSEMI |
描述: | EEPROM Serial 1-Mb I2C 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总14页 (文件大小:269K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAV24M01
EEPROM Serial 1-Mb I2C
-ꢀAutomotive Grade 1
Description
2
The CAV24M01 is a EEPROM Serial 1−Mb I C, internally
organized as 131,072 words of 8 bits each.
It features a 256−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I C protocol.
www.onsemi.com
2
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to four
CAV24M01 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
SOIC−8
W SUFFIX
CASE 751BD
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
TSSOP−8
Y SUFFIX
CASE 948AL
2
• Supports Standard, Fast and Fast−Plus I C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 256−Byte Page Write Buffer
PIN CONFIGURATION
• Hardware Write Protection for Entire Memory
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
1
NC
V
CC
(SCL and SDA)
A
1
WP
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• 8−pin SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SCL
SDA
A
2
V
SS
SOIC (W), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
V
CC
PIN FUNCTION
Pin Name
A , A
Function
Device Address
1
2
SCL
SDA
SCL
WP
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
CAV24M01
SDA
A , A
2
1
WP
V
CC
V
SS
V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
May, 2018 − Rev. 2
CAV24M01/D
CAV24M01
MARKING DIAGRAMS
M01C
AYMXXX
24M01A
AYMXXX
G
(TSSOP−8)
M01C = Specific Device Code
(SOIC−8)
A
= Assembly Location
24M01A = Specific Device Code
Y
M
XXX
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of
= Assembly Lot Number
= Pb−Free Microdot
A
Y
M
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
XXX = Last Three Digits of
XXX = Assembly Lot Number
G
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
–0.5 to +6.5
°C
Voltage on any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Notes 3, 4)
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Test Condition: Page Mode, V = 5 V, 25°C.
CC
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.
CC
A
Symbol
Parameter
Read Current
Test Conditions
= 400 kHz / 1 MHz
Min
Max
1
Units
mA
mA
mA
mA
V
I
Read, f
SCL
CCR
I
Write Current
V
CC
= 5.5 V
5.0
5
CCW
I
SB
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
All I/O Pins at GND or V
T = −40°C to +125°C
A
CC
I
L
Pin at GND or V
T = −40°C to +125°C
A
2
CC
V
−0.5
0.3 V
CC
IL1
IH1
OL1
V
0.7 V
V
+ 0.5
V
CC
CC
V
I
OL
= 3.0 mA
0.4
V
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2
CAV24M01
Table 4. PIN IMPEDANCE CHARACTERISTICS V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.
CC
A
Symbol
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input Current (A , A )
Conditions
= 0 V
Max
8
Units
pF
C
C
(Note 5)
(Note 5)
V
IN
V
IN
V
IN
V
IN
V
IN
IN
IN
= 0 V
< V , V = 5.5 V
6
pF
I
, I (Note 6)
75
50
2
mA
WP
A
1
2
IH
CC
< V , V = 3.3 V
IH
IH
CC
> V
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A , A pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
1
2
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.
CC
Table 5. A.C. CHARACTERISTICS (Note 7) V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.
CC
A
Fast−Plus
T
A
= −405C to +855C
Standard
Fast
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Clock Frequency
Units
kHz
ms
F
SCL
100
400
1,000
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
0.25
0.45
0.40
0.25
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
50
ns
SU:DAT
t
(Note 8)
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
1,000
300
300
300
100
100
ns
R
t (Note 8)
ns
F
t
4
0.6
1.3
0.25
0.5
ms
SU:STO
t
Bus Free Time Between
STOP and START
4.7
ms
BUF
t
SCL Low to Data Out Valid
Data Out Hold Time
3.5
50
0.9
50
0.40
50
ms
ns
ns
AA
t
50
50
50
DH
T (Note 8)
Noise Pulse Filtered at SCL
and SDA Inputs
i
t
WP Setup Time
0
0
0
1
ms
ms
SU:WP
t
WP Hold Time
2.5
2.5
HD:WP
t
Write Cycle Time
Power-up to Ready Mode
5
5
5
ms
ms
WR
t
(Notes 8, 9)
0.1
0.1
0.1
PU
7. Test conditions according to “A.C. Test Conditions” table.
8. Tested initially and after a design or process change that affects this parameter.
9. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
≤ 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA; C = 100 pF
L
L
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3
CAV24M01
Power-On Reset (POR)
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
The CAV24M01 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
The device will power up into Standby mode after V
exceeds the POR trigger level and will power down into
CC
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
Reset mode when V drops below the POR trigger level.
CC
This bi−directional POR behavior protects the device
against brown−out failure, following a temporary loss of
power.
STOP
Pin Description
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when following a
Write command) or sends the Slave into standby mode
(when following a Read command).
SCL: The Serial Clock input pin accepts the Serial Clock
signal generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 2 bits, A2, A1, select one of 4 possible memory
A and A : The Address pins accept the device address.
1
2
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor.
2
devices connected on a single I C bus. The A2 and A1 bits
must match the state of the external address pins. The
seventh bit, a16 is the most significant internal address bit.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed. To select an internal memory
location (data byte) a 17−bit address word is required:
a16 bit from the Slave address byte followed by two address
bytes.
Functional Description
The CAV24M01 supports the Inter−Integrated Circuit
2
(I C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAV24M01 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 4 devices may be connected to
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the byte address and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. If
the Master acknowledges the data, then the Slave continues
transmitting. The Master terminates the session by not
acknowledging the last data byte (NoACK) and by sending
a STOP to the Slave. Bus timing is illustrated in Figure 5.
the bus as determined by the device address inputs A and
A .
2
1
I2C Bus Protocol
2
The I C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V supply via pull−up
CC
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
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4
CAV24M01
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
a
16
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Acknowledge Timing
t
t
F
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
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5
CAV24M01
Acknowledge Polling
WRITE OPERATIONS
Acknowledge polling can be used to determine if the
CAV24M01 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAV24M01 will not acknowledge the Slave address,
as long as internal Write is in progress.
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be written
(Figure 6). The Slave acknowledges all 4 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAV24M01. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAV24M01 will not acknowledge the data byte
and the Write request will be rejected.
Page Write
The CAV24M01 contains 131,072 bytes of data, arranged
in 512 pages of 256 bytes each. The most significant 9 bits
of the address word (a16 from the Slave Address byte and
most significant Address byte) identify the page and the last
8 bits identify the byte within the page. The 17−bit address
word (a16 from the Slave Address byte followed by two
address bytes) points to the first byte to be written. Up to 256
bytes can be written in one Write cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 256 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Delivery State
The CAV24M01 is shipped erased, i.e., all bytes are FFh.
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6
CAV24M01
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
BYTE ADDRESS
8
O
P
ADDRESS
DATA
a
15
− a
a − a
7 0
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Figure 6. Byte Write Timing
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
START
CONDITION
ADDRESS
CONDITION
Figure 7. Write Cycle Timing
S
T
A
R
T
BUS
ACTIVITY:
MASTER
S
T
SLAVE
ADDRESS
BYTE ADDRESS
− a a − a
7 0
O
P
a
15
DATA n
DATA n+1
DATA n+x
8
S
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
A
A
A
C
K
C
K
C
K
Figure 8. Page Write Timing
ADDRESS
BYTE
DATA
BYTE
1
1
8
9
8
d
SCL
a
a
0
d
7
SDA
WP
7
0
t
SU:WP
t
HD:WP
Figure 9. WP Timing
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7
CAV24M01
READ OPERATIONS
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Immediate Address Read
In standby mode, the CAV24M01 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1st memory byte, etc.
When, following a START, the CAV24M01 is presented
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAV24M01, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
S
T
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
O
P
SDA LINE
S
P
A
C
K
N
O
A
C
K
DATA
SCL
SDA
8
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
S
T
BUS ACTIVITY:
MASTER
A
R
T
BYTE ADDRESS
− a a − a
7 0
SLAVE
SLAVE
O
P
ADDRESS
ADDRESS
a
15
DATA
8
S
S
P
SDA LINE
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 11. Selective Read Timing
S
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
O
P
DATA n
DATA n+1
DATA n+2
DATA n+x
P
SDA LINE
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 12. Sequential Read Timing
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8
CAV24M01
ORDERING INFORMATION (Note 10)
Specific
Device
Marking
Device Order
Number
Temperature
Range
Lead
Finish
†
Package Type
SOIC−8, JEDEC
TSSOP−8
Shipping
CAV24M01WE−GT3
CAV24M01YE−GT3
24M01A
M01C
−40°C to +125°C
−40°C to +125°C
NiPdAu
NiPdAu
Tape & Reel, 3,000 Units / Reel
Tape & Reel, 3,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.All packages are RoHS-compliant (Lead-free, Halogen-free).
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
98AON34272E
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REFERENCE:
DESCRIPTION: SOIC 8, 150 MILS
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34272E
PAGE 2 OF 2
ISSUE
REVISION
DATE
19 DEC 2008
O
RELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
751BD
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
DATE 19 DEC 2008
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
98AON34428E
ON SEMICONDUCTOR STANDARD
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
REFERENCE:
DESCRIPTION: TSSOP8, 4.4X3
PAGE 1 OF2
DOCUMENT NUMBER:
98AON34428E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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© Semiconductor Components Industries, LLC, 2008
Case Outline Number:
December, 2008 − Rev. 01O
948AL
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