CAV93C66VE-GT3 [ONSEMI]
EEPROM 串行 4-Kb 微丝 - 汽车级;
| 型号： | CAV93C66VE-GT3 |
| 厂家： | 
ONSEMI |
| 描述： | EEPROM 串行 4-Kb 微丝 - 汽车级 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAV93C66
EEPROM Serial 4-Kb
Microwire - Automotive
Grade 1
Description
The CAV93C66 is an EEPROM Serial 4−Kb Microwire
Automotive Grade 1 device which is organized as either 256 registers
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of 16 bits (ORG pin at V ) or 512 registers of 8 bits (ORG pin at
CC
GND). Each register can be written (or read) serially by using the DI
(or DO) pin. The device features sequential read and self−timed
internal write with auto−clear. On−chip Power−On Reset circuitry
protects the internal logic against powering up in the wrong state.
SOIC−8
V SUFFIX
TSSOP−8
Y SUFFIX
CASE 751BD
CASE 948AL
Features
• Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified
• High Speed Operation: 2 MHz
PIN CONFIGURATIONS
• 2.5 V to 5.5 V Supply Voltage Range
• Selectable x8 or x16 Memory Organization
• Self−timed Write Cycle with Auto−clear
• Sequential Read
1
V
CS
CC
SK
NC
DI
DO
ORG
GND
SOIC (V), TSSOP (Y)
(Top View)
• Software Write Protection
• Power−up Inadvertent Write Protection
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
PIN FUNCTION
Pin Name
Function
• 8−lead SOIC and TSSOP Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
CS
SK
DI
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
V
CC
DO
V
CC
ORG
CS
SK
GND
ORG
NC
Memory Organization
No Connection
DO
CAV93C66
DI
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
GND
Figure 1. Functional Symbol
Note: When the ORG pin is connected to V , the x16 organization is
CC
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2019 − Rev. 2
CAV93C66/D
CAV93C66
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
−65 to +150
−0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may
CC
undershoot to no less than −1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
(Note 3)
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V = 5 V, 25°C.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = +2.5 V to +5.5 V, T =−40°C to +125°C unless otherwise specified.)
CC
A
Symbol
Parameter
Test Conditions
Min
Max
1
Units
mA
mA
I
Supply Current (Write)
Supply Current (Read)
V
= 5.0 V
CC1
CC2
CC
I
DO open, f = 2 MHz, V = 5.0 V
500
5
SK
CC
I
Standby Current
(x8 Mode)
V
IN
= GND or V
CC
CS = GND, ORG = GND
mA
SB1
I
Standby Current
(x16 Mode)
V
= GND or V
3
mA
SB2
IN
CC
CS = GND,
ORG = Float or V
CC
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
V
= GND to V
CC
2
2
mA
mA
V
LI
IN
I
LO
= GND to V CS = GND
CC
OUT
V
IL1
4.5 V ≤ V < 5.5 V
−0.1
2
0.8
CC
V
IH1
Input High Voltage
Input Low Voltage
4.5 V ≤ V < 5.5 V
V + 1
CC
V
CC
V
2.5 V ≤ V < 4.5 V
0
V x 0.2
CC
V
IL2
IH2
CC
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
2.5 V ≤ V < 4.5 V
V
V
x 0.7
V + 1
CC
V
CC
CC
V
OL1
OH1
4.5 V ≤ V < 5.5 V, I = 3 mA
0.4
V
CC
OL
V
4.5 V ≤ V < 5.5 V, I = −400 mA
2.4
V
CC
OH
V
OL2
OH2
2.5 V ≤ V < 4.5 V, I = 1 mA
0.2
V
CC
OL
V
2.5 V ≤ V < 4.5 V, I = −100 mA
− 0.2
CC
V
CC
OH
Table 4. PIN CAPACITANCE (T = 25°C, f = 1.0 MHz, V = +5.0 V)
A
CC
Symbol
(Note 4)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
= 0 V
Min
Typ
Max
5
Units
pF
C
V
OUT
OUT
C
(Note 4)
V
IN
= 0 V
5
pF
IN
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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2
CAV93C66
Table 5. POWER−UP TIMING (Notes 5, 6)
Symbol
Parameter
Max
1
Units
ms
t
Power−up to Read Operation
Power−up to Write Operation
PUR
t
1
ms
PUW
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
6. t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
4.5 V ≤ V ≤ 5.5 V
CC
Timing Reference Voltages
Input Pulse Voltages
4.5 V ≤ V ≤ 5.5 V
CC
0.2 V to 0.7 V
2.5 V ≤ V ≤ 4.5 V
CC
CC
CC
Timing Reference Voltages
Output Load
0.5 V
2.5 V ≤ V ≤ 4.5 V
CC
CC
Current Source I
/I
; CL = 100 pF
OLmax OHmax
Table 7. A.C. CHARACTERISTICS (V = +2.5 V to +5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
CC
Symbol
Parameter
Min
50
Max
Units
ns
t
CS Setup Time
CSS
CSH
t
CS Hold Time
0
ns
t
DI Setup Time
100
100
ns
DIS
t
DI Hold Time
ns
DIH
t
Output Delay to 1
0.25
0.25
100
5
ms
PD1
PD0
t
Output Delay to 0
ms
t
(Note 7)
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
HZ
t
ms
ms
EW
t
0.25
0.25
0.25
CSMIN
t
ms
SKHI
t
ms
SKLOW
t
0.25
ms
SV
SK
DC
2000
kHz
MAX
7. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
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3
CAV93C66
Device Operation
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
The CAV93C66 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAV93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The device operates on a single
power supply and will generate on chip, the high voltage
required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
Table 8. INSTRUCTION SET
Address
Data
x8
x16
x8
x16
Instruction
READ
Start Bit
Opcode
10
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
1
1
1
1
1
1
1
A8−A0
A7−A0
ERASE
WRITE
EWEN
EWDS
ERAL
11
A8−A0
A7−A0
01
A8−A0
A7−A0
D7−D0
D15−D0
00
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
00
Write Disable
00
Clear All Addresses
Write All Addresses
WRAL
00
D7−D0
D15−D0
t
t
t
SKHI
SKLOW
CSH
SK
t
t
DIH
DIS
VALID
VALID
DI
t
CSS
CS
t
, t
t
t
PD0 PD1
CSMIN
DIS
DO
DATA VALID
Figure 2. Synchronous Data Timing
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4
CAV93C66
Read
Upon receiving a READ command and an address
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 3.
(clocked into the DI pin), the DO pin of the CAV93C66 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
Erase/Write Enable and Disable
The device powers up in the write disable state. Any
writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAV93C66 write and
erase instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from the
device regardless of the write enable/disable status. The
EWEN and EWDS instructions timing is shown in Figure 4.
specified time delay (t
or t ).
PD0
PD1
For the CAV93C66 after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
SK
CS
Don’t Care
A
N
A
N−1
A
0
DI
1
1
0
t
PD0
HIGH−Z
DO
Dummy 0
D
D
0
Address + 1 Address + 2 Address + n
15 . . .
or
D
D
0
D
D
0
D
15 . . .
15 . . .
15 . . .
D
D
0
or
or
or
7 . . .
D
D
0
D
D
0
D
7 . . .
7 . . .
7 . . .
Figure 3. READ Instruction Timing
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5
CAV93C66
Write
Erase
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t . The falling edge of CS will start the
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t
(Figure 6). The falling edge of CS will start the self
CSMIN
CSMIN
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAV93C66 can
be determined by selecting the device and polling the DO
pin. Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAV93C66 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
SK
t
CSMIN
STANDBY
CS
DI
STATUS
VERIFY
A
N
A
N−1
A
0
D
D
0
N
1
0
1
t
SV
t
HZ
BUSY
HIGH−Z
DO
READY
HIGH−Z
t
EW
Figure 5. Write Instruction Timing
SK
STANDBY
CS
DI
STATUS
VERIFY
t
CS
A
N
A
N−1
A
0
1
1
1
t
t
SV
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 6. Erase Instruction Timing
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6
CAV93C66
Erase All
Write All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
. The falling edge of CS will start the self clocking
t
(Figure 8). The falling edge of CS will start the self
CSMIN
CSMIN
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
device can be determined by selecting the device and polling
the DO pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the device can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
SV
t
HZ
HIGH−Z
BUSY
DO
READY
HIGH−Z
t
EW
Figure 7. ERAL Instruction Timing
SK
CS
DI
STANDBY
STATUS VERIFY
t
CSMIN
1
0
0
0
1
D
D
0
N
t
SV
t
HZ
DO
BUSY
READY
HIGH−Z
t
EW
Figure 8. WRAL Instruction Timing
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7
CAV93C66
ORDERING INFORMATION
Specific
Device
Lead
†
Finish
Marking
Device Order Number
Package Type
Temperature Range
Shipping
CAV93C66VE−GT3
93C66D
SOIC−8, JEDEC
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAV93C66YE−GT3
M66D
TSSOP−8
−40°C to +125°C
NiPdAu
Tape & Reel,
3,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8, 150 mils
CASE 751BD
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.51
0.25
5.00
6.20
4.00
c
E1
E
D
E
E1
e
h
L
θ
1.27 BSC
0.25
0.40
0º
0.50
1.27
8º
PIN # 1
IDENTIFICATION
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34272E
SOIC 8, 150 MILS
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP8, 4.4x3.0, 0.65P
CASE 948AL
ISSUE A
DATE 20 MAY 2022
q
q
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
XXX = Specific Device Code
Y
= Year
WW = Work Week
A
G
= Assembly Location
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34428E
TSSOP8, 4.4X3.0, 0.65P
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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