ESD7331 [ONSEMI]
ESD Protection Diode;
| 型号： | ESD7331 |
| 厂家： | 
ONSEMI |
| 描述： | ESD Protection Diode |
| 文件： | 总5页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7331
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESD7331 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, the
part is well suited for use in high frequency designs such as USB 2.0
high speed applications.
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1
2
Cathode
Anode
Features
• Low Capacitance 0.4 pF (Typ)
• Low Clamping Voltage
MARKING
DIAGRAM
PIN 1
• Small Body Outline Dimensions: 0.60 mm x 0.30 mm
• Low Body Height: 0.3 mm
• Stand−off Voltage: 3.3 V
6
X3DFN2
CASE 152AF
M
• IEC61000−4−2 Level 4 ESD Protection
6
= Specific Device Code
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
(Rotated 180°)
= Date Code
Compliant
M
Typical Applications
• USB 2.0/3.0
• MHL 2.0
ORDERING INFORMATION
†
Device
ESD7331MUT5G
Package
Shipping
• eSATA
X3DFN2
15000 / Tape &
Reel
(Pb−Free)
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Contact
Air
15
15
kV
Total Power Dissipation on FR−5 Board
°P °
250
mW
D
(Note 1) @ T = 25°C
A
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
Junction and Storage Temperature Range T , T
J
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
April, 2017 − Rev. 0
ESD7331/D
ESD7331
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR RWM
V
Clamping Voltage @ I
V
C
V
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
PP
I
T
Bi−Directional TVS
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
ESD Clamping Voltage
Junction Capacitance
Dynamic Resistance
Symbol
Conditions
Min
Typ
Max
Unit
V
V
RWM
3.3
V
BR
I = 1 mA
4.0
V
T
I
R
V
RWM
= 3.3 V
1.0
7.5
mA
V
V
C
I
PP
= 1 A
V
C
Per IEC61000−4−2
= 0 V, f = 1 MHz
See Figures 1 and 2
C
V
R
0.4
0.75
pF
W
J
R
TLP Pulse
0.26
DYN
Insertion Loss
f = 100 MHz
f = 8.5 GHz
0.003
1.79
dB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T = 25°C, per IEC61000−4−5 waveform.
A
160
140
120
100
80
10
0
−10
−20
−30
−40
−50
−60
−70
60
40
20
0
−20
−20
0
20
40
60
80
100 120
140
−20
0
20
40
60
80
100 120
140
TIME (ns)
TIME (ns)
Figure 1. ESD Clamping Voltage Positive 8 kV
Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Negative 8 kV
Contact per IEC61000−4−2
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2
ESD7331
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−10 −8
−6
−4 −2
0
2
4
6
8
10
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
V
R
(V)
VBias (V)
Figure 3. Reverse Leakage Current
Figure 4. Line Capacitance, f = 1 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
0.0
−10
0.E+00
2.E+09
4.E+09
6.E+09
8.E+09 1.E+10
1.E+07
1.E+08
1.E+09
1.E+10
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. RF Insertion Loss
Figure 6. Capacitance over Frequency
22
20
18
16
14
12
10
8
−22
−20
−18
−16
−14
−12
−10
−8
6
−6
4
−4
2
−2
0
0
0
0
2
4
6
8
10
12 14 16 18 20
(V)
−2 −4 −6 −8 −10 −12 −14 −16 −18 −20
V
V
CTLP
(V)
CTLP
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
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3
ESD7331
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 9. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 10. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 11. 8 X 20 ms Pulse Waveform
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4
ESD7331
PACKAGE DIMENSIONS
X3DFN2, 0.62x0.32, 0.355P, (0201)
CASE 152AF
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A B
D
2. CONTROLLING DIMENSION: MILLIMETERS.
PIN 1
INDICATOR
(OPTIONAL)
MILLIMETERS
DIM MIN
MAX
0.33
0.05
0.28
0.66
0.36
A
A1
b
D
E
0.25
−−−
E
TOP VIEW
0.22
0.58
0.28
e
0.355 BSC
0.23
L2 0.17
0.05
0.05
C
C
A
RECOMMENDED
MOUNTING FOOTPRINT*
2X
A1
SIDE VIEW
SEATING
PLANE
C
2X
0.30
0.74
1
e
2X b
1
2
2X
0.31
DIMENSIONS: MILLIMETERS
M
0.05
C A B
2X L2
See Application Note AND8398/D for more mounting details
M
0.05
C A B
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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ESD7331/D
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