ESDL2011PFCT5G [ONSEMI]
高速数据线保护，双向(1 V — Thunderbolt 3.0) ，0.2 pF;
| 型号： | ESDL2011PFCT5G |
| 厂家： | 
ONSEMI |
| 描述： | 高速数据线保护，双向(1 V — Thunderbolt 3.0) ，0.2 pF 局域网 测试 光电二极管 |
| 文件： | 总7页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDL2011
ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESDL2011 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, the
part is well suited for use in high speed data line applications.
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1
2
Features
• Low Capacitance 0.17 pF (Typ)
• Low Clamping Voltage
MARKING
DIAGRAM
• Small Body Outline Dimensions: 0.60 mm x 0.30 mm
• Low Body Height: 0.2 mm
• Stand−off Voltage: 1.0 V
DSN2
(Side wall isolated)
CASE 152AX
A
• IEC61000−4−2 Level 4 ESD Protection
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
A
= Specific Device Code
Compliant
Typical Applications
• USB 3.x
ORDERING INFORMATION
• Thunderbolt 3.0
†
Device
ESDL2011PFCT5G
Package
Shipping
DSN2
(Pb−Free)
10000 / Tape &
Reel
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Symbol
Value
Unit
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Contact
Air
15
15
kV
Total Power Dissipation on FR−4 Board
°P °
D
313
mW
(Note 1) @ T = 25°C
A
Thermal Resistance, Junction−to−Ambient
R
400
−55 to +150
260
°C/W
°C
q
JA
Junction and Storage Temperature Range
T , T
J stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
1. FR−4 = 28 mm 1 oz. Cu JEDEC JESD51−3 two layer PCB.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2019 − Rev. 2
ESDL2011/D
ESDL2011
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
I
PP
Symbol
Parameter
I
Maximum Reverse Peak Pulse Current
PP
I
T
I
V
R
BR RWM
V
Clamping Voltage @ I
V
C
V
C
PP
V
I
V
V
V
R
T
RWM BR C
V
RWM
Working Peak Reverse Voltage
I
I
R
Maximum Reverse Leakage Current @ V
RWM
V
Breakdown Voltage @ I
Test Current
BR
T
I
PP
I
T
Bi−Directional Surge Protector
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)
A
Parameter
Symbol
Conditions
Min
Typ
Max
1.0
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
I/O Pin to GND
I = 1 mA, I/O Pin to GND
V
BR
1.4
1.65
30
2.3
V
T
Reverse Leakage Current
Clamping Voltage (Note 2)
I
R
V
RWM
= 1.0 V
500
nA
V
V
C
IEC61000−4−2, 8 kV Contact
Figures 1 and 2
Clamping Voltage
200 ns TLP
V
V
I
= 4 A
IEC61000−4−2 Level 1 Equivalent
C
PP
3.5
4.0
6.0
( 2 kV Contact, 4 kV Air)
I
PP
= 8 A
IEC61000−4−2 Level 2 Equivalent
( 4 kV Contact, 8 kV Air)
4.8
4.5
Reverse Peak Pulse Current
per Figure 12
I
PP
per IEC61000−4−5 (1.2/50 ms), R = 12 W
3.5
A
V
V
eq
Clamping Voltage 1.2/50 ms
Waveform per Figure 12
V
V
I
= 2.1 A, IEC61000−4−5 (1.2/50 ms),
= 12 W
2.9
3.6
3.5
4.0
C
PP
R
eq
Clamping Voltage 1.2/50 ms
Waveform per Figure 12
I
= 3.5 A, IEC61000−4−5 (1.2/50 ms),
= 12 W
C
PP
R
eq
Dynamic Resistance (TLP)
Junction Capacitance
Insertion Loss
R
I/O Pin to GND (4 A to 8 A, 200 ns TLP)
= 0 V, f = 1 MHz
0.34
0.17
0.5
W
DYN
C
V
R
0.20
pF
dB
J
I
L
f = 5 GHz
f = 10 GHz
0.165
0.34
0.20
0.40
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For test procedure see application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 200 ns, t = 4 ns, averaging window; t = 170 ns to t = 190 ns.
0
p
r
1
2
100
90
80
70
60
50
40
30
10
0
−10
−20
−30
−40
−50
−60
20
10
−70
−80
−90
0
−10
−100
−25
−25
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TIME (ns)
TIME (ns)
Figure 1. IEC61000−4−2 + 8 kV Contact ESD
Figure 2. IEC61000−4−2 − 8 kV Contact ESD
Clamping Voltage
Clamping Voltage
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2
ESDL2011
TYPICAL CHARACTERISTICS
1.E−02
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
1.E−12
1.E−13
1.E−14
−1.5
−1
−0.5
0
0.5
1
1.5
V
R
(V)
Figure 3. IV Characteristics
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
0.1
0
0.E+00
−0.9
−1.0
1.E+07
5.E+09
1.E+10
FREQUENCY (Hz)
2.E+10
3.E+10
1.E+08
1.E+09
1.E+10
FREQUENCY (Hz)
Figure 4. Insertion Loss
Figure 5. Typical Capacitance over Frequency
16
15
14
13
12
11
10
9
−16
−15
−14
−13
−12
−11
−10
−9
8
−8
7
−7
6
−6
5
−5
4
−4
3
−3
2
−2
1
−1
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10−11−12−13−14−15−16
VOLTAGE (V)
VOLTAGE (V)
Figure 6. Positive 200 ns TLP IV Curve
Figure 7. Negative 200 ns TLP IV Curve
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3
ESDL2011
TYPICAL CHARACTERISTICS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(A)
I
PK
I
PK
Figure 8. Positive Clamping Voltage vs. Peak Pulse
Figure 9. Negative Clamping Voltage vs. Peak Pulse
Current (per IEC61000−4−5 (tp = 1.2/50 ms, Req = 12 W))
Current (per IEC61000−4−5 (tp = 1.2/50 ms, Req = 12 W))
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4
ESDL2011
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 10. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 11. Diagram of ESD Test Setup
ESD Voltage Clamping
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
t = rise time to peak value [1.2 ms]
r
t = decay time to half value [50 ms]
f
Peak
Value
100
Half Value
50
0
0 t
r
t
f
t, TIME (ms)
Figure 12. IEC61000−4−5 1.2/50 ms Pulse
Waveform
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X4DFN2, 0.60x0.30, 0.36P
CASE 152AX
ISSUE G
SCALE 8:1
DATE 12 APR 2019
A
B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN 1
2. CONTROLLING DIMENSION: MILLIMETERS.
INDICATOR
MILLIMETERS
E
DIM MIN
NOM MAX
A
A1
b
D
E
e
L
0.175 0.200 0.225
0.018 REF
0.205 0.215 0.225
0.575 0.600 0.625
0.275 0.300 0.325
0.36 BSC
TOP VIEW
SIDE VIEW
A
0.02
0.01
C
C
0.145 0.155 0.165
A1
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
C
X
X
e
b
X
= Specific Device Code
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present. Some products may
not follow the Generic Marking.
1
M
0.05
C A B
2X
L
C A B
M
0.05
BOTTOM VIEW
RECOMMENDED
SOLDER FOOTPRINT*
0.65
2X
0.27
1
2X
0.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON06808G
X4DFN2, 0.60x0.30, 0.36P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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