ESDR7534W1T2G [ONSEMI]

ESD 保护器，4 线路，采用 SC88 封装;


型号：	ESDR7534W1T2G
厂家：	ONSEMI
描述：	ESD 保护器，4 线路，采用 SC88 封装
文件：	总7页 (文件大小：163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ESDR7534

ESD Protection Diode

Low Capacitance ESD Protection for

LVDS Interfaces

The ESDR7534 surge protection is designed to protect high speed

data lines from ESD, EFT, and lightning.

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Features

PIN CONFIGURATION

AND SCHEMATIC

• Low Capacitance (2 pF Maximum Between I/O Lines and GND)

• Protection for the Following IEC Standards:

IEC 61000−4−2 (ESD) Level 4 − 30 kV (Contact); 30 kV (Air)

• This is a Pb−Free Device

CH4

CH3

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

CH1

CH2

Rating

Symbol

Value

300

Unit

(Top View)

Peak Power Dissipation (Note 1)

Maximum Peak Pulse Current

2/10 ms @ T = 25°C

MARKING

DIAGRAM

Operating Junction Temperature Range

Storage Temperature Range

−55 to +125

−55 to +150

260

°C

stg

7RMG

SC−88

S7 SUFFIX

CASE 419B

Lead Solder Temperature −

Maximum (10 Seconds)

IEC 61000−4−2 Contact

IEC 61000−4−2 Air

ISO 10605 330 pF / 330 W Contact

ISO 10605 330 pF / 2 kW Contact

ISO 10605 150 pF / 2 kW Contact

ESD

= Specific Device Code

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

ORDERING INFORMATION

1. P calculated. P = V x I .

†

Device

Package

Shipping

Table 1. PIN DESCRIPTIONS

ESDR7534W1T2G

SC−88

(Pb−Free)

3,000 / Tape &

Reel

4−Channel, 6−Lead SC70−6

Type Description

Name

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

CH1

I/O

GND

I/O

ESD Channel

Negative Voltage Supply Rail

ESD Channel

CH2

CH3

I/O

ESD Channel

PWR

I/O

Positive Voltage Supply Rail

ESD Channel

CH4

Publication Order Number:

August, 2018 − Rev. 5

ESDR7534/D

ESDR7534

ELECTRICAL CHARACTERISTICS

(T = 25°C unless otherwise noted)

Symbol

Parameter

Maximum Reverse Peak Pulse Current

Clamping Voltage @ I

Working Peak Reverse Voltage

RWM

BR RWM

Maximum Reverse Leakage Current @ V

RWM

Breakdown Voltage @ I

Test Current

Forward Current

Forward Voltage @ I

Peak Power Dissipation

Capacitance @ V = 0 and f = 1.0 MHz

Uni−Directional

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (T =25°C unless otherwise specified)

Parameter

Reverse Working Voltage

Breakdown Voltage

Symbol

Conditions

Min

Typ

Max

5.0

9.5

3.0

1.6

Unit

RWM

(Note 1)

I = 1 mA, (Note 2)

6.0

8.0

Reverse Leakage Current

Forward Voltage

RWM

= 5 V

I = 100 mA

Clamping Voltage

= 10 A (2/10 ms Waveform)

Maximum Peak Pulse Current

Junction Capacitance

2/10 ms Waveform

= 0 V, f = 1 MHz between I/O Pins and GND

1.3

0.7

2.0

1.0

= 0 V, f = 1 MHz between I/O Pins, V floating

1. Surge protection devices are normally selected according to the working peak reverse voltage (V

than the DC or continuous peak operating voltage level.

), which should be equal or greater

RWM

2. V is measured at pulse test current I .

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

15.0

t = rise time to peak value [2 ms]

t = decay time to half value [10 ms]

Peak

Value

12.5

10.0

7.5

100

Half Value

5.0

2.5

10 12 14 16 18 20

Ipp (A)

0 t

TIME (ms)

Figure 1. Exponential Decay Pulse Waveform

Figure 2. Clamping Voltage vs. Peak Pulse

Current (tp = 2/10 ms, R = 8 W)

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ESDR7534

IEC61000−4−2 Waveform

IEC 61000−4−2 Spec.

peak

First Peak

Current

(A)

100%

90%

Test Volt-

age (kV)

Current at

30 ns (A)

Current at

60 ns (A)

Level

7.5

I @ 30 ns

22.5

I @ 60 ns

10%

= 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Device

Under

Test

Oscilloscope

ESD Gun

50 W

Cable

50 W

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

1.E−02

1.E−03

1.E−04

1.E−05

1.E−06

1.E−07

1.E−08

1.E−09

1.E−10

1.E−11

−1

VOLTAGE (V)

VBias (V)

Figure 5. IV Characteristic Curve

Figure 6. CV Characteristic Curve

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ESDR7534

APPLICATIONS INFORMATION

Option 2

The new ESDR7534 is a low capacitance surge protection

diode array designed to protect sensitive electronics such as

communications systems, computers, and computer

peripherals against damage due to ESD events or transient

overvoltage conditions. Because of its low capacitance, it

can be used in high speed I/O data lines. The integrated

design of the ESDR7534 offers low capacitance steering

Protection of four data lines with bias and power supply

isolation resistor.

I/O 1

I/O 2

diodes and an internal surge protection diode (V diode)

10 k

integrated in a single package. If a transient condition

occurs, the steering diodes will drive the transient to the

positive rail of the power supply or to ground. The surge

protection device protects the power line against

overvoltage conditions to avoid damage to the power supply

and any downstream components.

I/O 3

I/O 4

ESDR7534 Configuration Options

The ESDR7534 can be isolated from the power supply by

The ESDR7534 is able to protect up to four data lines

against transient overvoltage conditions by driving them to

a fixed reference point for clamping purposes. The steering

diodes will be forward biased whenever the voltage on the

connecting a series resistor between pin 5 and V . A 10 kW

resistor is recommended for this application. This will

maintain a bias on the V and steering diodes, reducing their

capacitance.

protected line exceeds the reference voltage (V or

+ V ). The diodes will force the transient current to

Option 3

bypass the sensitive circuit.

Protection of four data lines using the V diode as

reference.

Data lines are connected at pins 1, 3, 4 and 6. The negative

reference is connected at pin 2. This pin must be connected

directly to ground by using a ground plane to minimize the

PCB’s ground inductance. It is very important to reduce the

PCB trace lengths as much as possible to minimize parasitic

inductances.

I/O 1

I/O 2

Option 1

Protection of four data lines and the power supply using

as reference.

I/O 1

I/O 2

I/O 3

I/O 4

In applications lacking a positive supply reference or

those cases in which a fully isolated power supply is

required, the V can be used as the reference. For these

applications, pin 5 is not connected. In this configuration,

the steering diodes will conduct whenever the voltage on the

protected line exceeds the V of the I/O (CHX) pin.

I/O 3

I/O 4

For this configuration, connect pin 5 directly to the

positive supply rail (V ), the data lines are referenced to

the supply voltage. The V diode prevents overvoltage on

the supply rail. Biasing of the steering diodes reduces their

capacitance.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

SCALE 2:1

aaa H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-

SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.

4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY AND DATUM H.

5. DATUMS A AND B ARE DETERMINED AT DATUM H.

6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE

LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.

7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN

EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-

TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OF THE FOOT.

GAGE

PLANE

DETAIL A

aaa

2X 3 TIPS

bbb H

MILLIMETERS

DIM MIN NOM MAX

−−−

INCHES

MIN

−−−

NOM MAX

−−− 0.043

−−− 0.004

6X b

TOP VIEW

−−−

1.10

A1 0.00

A2 0.70

0.10 0.000

ddd

C A-B D

0.90

0.20

0.15

2.00

2.10

1.25

0.65 BSC

0.36

1.00 0.027 0.035 0.039

0.25 0.006 0.008 0.010

0.22 0.003 0.006 0.009

2.20 0.070 0.078 0.086

2.20 0.078 0.082 0.086

1.35 0.045 0.049 0.053

0.026 BSC

0.15

0.08

1.80

2.00

DETAIL A

E1 1.15

0.26

0.46 0.010 0.014 0.018

0.006 BSC

0.15 BSC

0.15

aaa

bbb

ccc

ddd

0.006

0.012

0.004

0.30

0.10

ccc C

SEATING

PLANE

SIDE VIEW

END VIEW

GENERIC

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT*

0.30

XXXMG

0.66

2.50

XXX = Specific Device Code

= Date Code*

= Pb−Free Package

0.65

(Note: Microdot may be in either location)

PITCH

*Date Code orientation and/or position may

vary depending upon manufacturing location.

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42985B

SC−88/SC70−6/SOT−363

PAGE 1 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

STYLE 1:

PIN 1. EMITTER 2

2. BASE 2

STYLE 2:

CANCELLED

STYLE 3:

CANCELLED

STYLE 4:

STYLE 5:

STYLE 6:

PIN 1. ANODE 2

2. N/C

PIN 1. CATHODE

2. CATHODE

3. COLLECTOR

4. EMITTER

5. BASE

PIN 1. ANODE

2. ANODE

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

3. COLLECTOR

3. CATHODE 1

4. ANODE 1

5. N/C

4. EMITTER

5. BASE

6. COLLECTOR 2

6. ANODE

6. CATHODE

6. CATHODE 2

STYLE 7:

STYLE 8:

CANCELLED

STYLE 9:

STYLE 10:

STYLE 11:

STYLE 12:

PIN 1. SOURCE 2

2. DRAIN 2

3. GATE 1

PIN 1. EMITTER 2

2. EMITTER 1

3. COLLECTOR 1

4. BASE 1

PIN 1. SOURCE 2

2. SOURCE 1

3. GATE 1

PIN 1. CATHODE 2

2. CATHODE 2

3. ANODE 1

PIN 1. ANODE 2

2. ANODE 2

3. CATHODE 1

4. ANODE 1

5. ANODE 1

6. CATHODE 2

4. SOURCE 1

5. DRAIN 1

6. GATE 2

4. DRAIN 1

5. DRAIN 2

6. GATE 2

4. CATHODE 1

5. CATHODE 1

6. ANODE 2

5. BASE 2

6. COLLECTOR 2

STYLE 13:

PIN 1. ANODE

2. N/C

STYLE 14:

PIN 1. VREF

2. GND

STYLE 15:

STYLE 16:

STYLE 17:

STYLE 18:

PIN 1. VIN1

2. VCC

PIN 1. ANODE 1

2. ANODE 2

PIN 1. BASE 1

2. EMITTER 2

3. COLLECTOR 2

4. BASE 2

PIN 1. BASE 1

2. EMITTER 1

3. COLLECTOR 2

4. BASE 2

3. COLLECTOR

4. EMITTER

5. BASE

3. GND

3. ANODE 3

3. VOUT2

4. VIN2

5. GND

6. VOUT1

4. IOUT

5. VEN

6. VCC

4. CATHODE 3

5. CATHODE 2

6. CATHODE 1

5. EMITTER 1

6. COLLECTOR 1

5. EMITTER 2

6. COLLECTOR 1

6. CATHODE

STYLE 19:

PIN 1. I OUT

2. GND

STYLE 20:

STYLE 21:

PIN 1. ANODE 1

2. N/C

STYLE 22:

PIN 1. D1 (i)

2. GND

STYLE 23:

PIN 1. Vn

2. CH1

3. Vp

STYLE 24:

PIN 1. CATHODE

2. ANODE

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

3. GND

3. ANODE 2

4. CATHODE 2

5. N/C

3. D2 (i)

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

4. V CC

4. EMITTER

5. COLLECTOR

6. COLLECTOR

4. D2 (c)

5. VBUS

6. D1 (c)

4. N/C

5. V EN

5. CH2

6. N/C

6. V REF

6. CATHODE 1

STYLE 30:

STYLE 25:

STYLE 26:

PIN 1. SOURCE 1

2. GATE 1

STYLE 27:

PIN 1. BASE 2

2. BASE 1

STYLE 28:

PIN 1. DRAIN

2. DRAIN

3. GATE

STYLE 29:

PIN 1. ANODE

2. ANODE

PIN 1. SOURCE 1

2. DRAIN 2

3. DRAIN 2

4. SOURCE 2

5. GATE 1

PIN 1. BASE 1

2. CATHODE

3. COLLECTOR 2

4. BASE 2

3. DRAIN 2

4. SOURCE 2

5. GATE 2

3. COLLECTOR 1

4. EMITTER 1

5. EMITTER 2

6. COLLECTOR 2

3. COLLECTOR

4. EMITTER

5. BASE/ANODE

6. CATHODE

4. SOURCE

5. DRAIN

6. DRAIN

5. EMITTER

6. COLLECTOR 1

6. DRAIN 1

Note: Please refer to datasheet for

style callout. If style type is not called

out in the datasheet refer to the device

datasheet pinout or pin assignment.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98ASB42985B

SC−88/SC70−6/SOT−363

PAGE 2 OF 2

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

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For additional information, please contact your local Sales Representative at

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

ESDR7534W1T2G [ONSEMI]

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