FAD3151MXA [ONSEMI]
110V, 2.5A, SOIC-8, Single Channel Floating Gate Drivers with Desaturation Protection;
| 型号： | FAD3151MXA |
| 厂家： | 
ONSEMI |
| 描述： | 110V, 2.5A, SOIC-8, Single Channel Floating Gate Drivers with Desaturation Protection 栅 |
| 文件： | 总15页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Typical Applications
110 V 2.5 A Single Channel
Floating Gate Drivers with
Desaturation Protection
and Charge Pump
Gate Driver for 80V and 100V MOSFETs
48 V Belt Starter Generator
48 V Auxiliary Motor Control (A/C com-
pressor, e−turbo, )
48 V Battery Switches
48 V DC−DC converter
PTC Heater, Active Discharge Circuit etc.
FAD3151MXA, FAD3171MXA
The FAD3151MXA and FAD3171MXA are single channel floating
automotive gate drivers suitable for driving high−speed power
MOSFETs up to 110 V. Designed in a SOI technology, the drivers are
ideal for applications that require noise immunity against severe
negative transients and ground offset up to −80 V.
The FAD3151MXA/71 drivers have an integrated desaturation
detection to protect the power switches during short−circuit and
over−current conditions. The drivers are also equipped with a soft
shutdown feature, which initiates a soft shutdown of driver outputs
upon desat detection, thus preventing possible overvoltage across
power MOSFETs during a heavy−load condition.
The FAD3151MXA/71 drivers are equipped with bidirectional fault
reporting pin that can generate a fault output during desat and
under−voltage lockout (UVLO) condition. The bidirectional nature of
the fault−reporting pin allows the driver to respond to external fault
commands, thereby facilitating fault communication across the
system. In addition, the FAD3171MXA has an integrated charge pump
to support 100% duty cycle operation of high side MOSFETs.
In summary, the FAD3151MXA/71 are versatile drivers with
features like desat detection, soft shutdown, fault reporting capability,
UVLO protection, and charge pump.
SOIC−8
CASE 751EB
ORDERING INFORMATION
†
Device
Package
Shipping
FAD3151MXA
SOIC−8
(Pb−Free)
Tape & Reel
FAD3171MXA
SOIC−8
(Pb−Free)
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
SAFETY SUPPORT
Features
Support integration into customer’s safety
application with a set of safety documents
including FMEDA and a hardware−software
interface document.
Single Channel Gate Driver with 110 V floating Vs capability
Negative Transient Capability up to −80 V
2.5 A Output Source and Sink Current
MOSFET Drain−Source Desaturation Detection with Soft Shutdown
Integrated Charge Pump to support 100% Duty Cycle Operation
(FAD3171MXA only)
Under−voltage Lock Out for both Input Logic and Output Stage
Bi−directional Fault Reporting Pin
High Speed Driver with Short Propagation Delay
dV /dt Immune to min 50 V/ns
s
3.3 V and 5 V Input Logic Compatible
Up to V Swing on Input Pins
DD
SOIC−8 package
Automotive Qualified to AEC Q100
These Devices are Pb−Free and are RoHS Compliant
This document, and the information contained herein,
is CONFIDENTIAL AND PROPRIETARY and the
property of Semiconductor Components Industries,
LLC., dba onsemi. It shall not be used, published,
disclosed or disseminated outside of the Company,
in whole or in part, without the written permission of
onsemi. Reverse engineering of any or all of the
information contained herein is strictly prohibited.
E 2022, SCILLC. All Rights Reserved.
Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
December, 2022 − Rev. 0
FAD3152MXA/D
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
48V
15V
RBOOT
DBOOT
R1 D1
R4
R3
1. VDD
2. IN
8. VB
CBOOT
RG
7. HO
IN−High
FLT−High
3. FLT 6. Desat
R2
CBL
P1
4. CO M
5. VS
FAD3171MXA (with charge pump)
Optional
Load
D1
R1
1. VDD
2. IN
8. VB
CBOOT
RG
IN−Low
7. HO
FLT−Low
3. FLT 6. Desat
R2
CBL
P1
4. CO M
5. VS
FAD3151MXA
Figure 1. Application Schematic with FAD3171MXA as High Side and FAD3151MXA as Low Side drivers
VDD
Charge Pump
(F AD3171only)
UVLO(VDD)
Regulator(VDD)
VBS
Regulator(VBS)
UVLO(VBS)
IN
Q
S
R
Level Shifter
UP
FLT
HO
Fault
Soft
Shutdown
VBS
IDESAT
Desat
Level Shifter
DOWN
COM
VDESAT,TH
VS
Figure 2. FAD3151MXA and FAD3171MXA (with charge pump) Block Diagram
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2
CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
PIN FUNCTION DESCRIPTION
1. VDD
2. IN
8. VB
7. HO
3. FLT
6. Desat
5. VS
4. COM
Figure 3. Pin Connection
(Top View)
PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
V
Power supply for logic stage
DD
IN
Input command
FLT
Bi−directional fault pin
Ground for logic stage
Floating source connection
COM
V
S
Desat
HO
Drain to source desaturation detection pin
Output
V
Floating power supply for power stage
B
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
MAXIMUM RATINGS
T = −40C ~ 125C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted.
A
Rating
Symbol
Value
Unit
V
Logic Power Supply
V
DD
−0.3 to 20
Logic Input Voltage (IN, FLT)
Floating Source Voltage
Floating Bootstrap Supply Voltage
Output Voltage
V
−0.3 to (V + 0.3)
V
IN
DD
V
−115 to 115
V
S
V
(V – 0.3) to (V + 20)
V
B
S
S
V
HO
(Vs – 0.3) to (V + 0.3)
V
B
Desaturation Voltage
V
DESAT
(Vs – 0.3) to (V + 0.3)
V
B
Allowable Offset Voltage Slew Rate
Maximum Junction Temperature
dVs/dt
+/−50
V/ns
C
C/W
W
T
J
150
Thermal Resistance, Junction−to−Ambient (Note 1)
Rth
200
JA
Power Dissipation at T = 25C
P
D
0.625
A
Storage Temperature Range
T
−55 to 150
C
kV
V
STG
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
ESD
ESD
2
HBM
500 for all pins
CDM
750 for corner pins
Moisture Sensitivity Level
MSL
3
−
Lead Temperature Soldering
T
SLD
260
C
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to the following standards:
JESD51−2: Integral circuits thermal test method environmental conditions – natural convection
JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012
ESD Charged Device Model tested per JESD22−C101
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
RECOMMENDED OPERATING RANGES
T = −40C ~ 125C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted.
A
Rating
Symbol
Min
Max
18
Unit
V
Power Supply
V
DD
V
DDUV+
Logic Input Voltage (IN, FLT)
V
IN
0
18
V
High−Side Vs Floating Supply Offset Voltage
High−side V Bootstrap Voltage
V
−80
110
18
V
S
V
BS
V
BSUV+
V
BS
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
ELECTRICAL CHARACTERISTICS
V
BIAS
(V , V ) = 15 V, V = 0 V unless otherwise noted, T = −40C to 125C. Voltage potentials are referenced to COM unless
DD
BS
S
A
otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
POWER SUPPLY SECTION
V
BS
V
BS
V
BS
V
DD
V
DD
Under−Voltage Positive−going Threshold
Under−Voltage Negative−going Threshold
Slew Rate During Startup (Note 4)
V
V
6
8
10.5
9.7
V
BSUV+
BSUV−
BS(SR)
DDUV+
DDUV−
5.5
2.5
7.5
V
V
V
V/ms
V
Under−Voltage Positive−going Threshold
Under−Voltage Negative−going Threshold
6
2.2
3.9
Offset Supply Leakage Current
Quiescent V Supply Current
V
= V = 80 V
I
LK1
5
mA
mA
B
S
V
= 0 V or 5 V
= 0 V or 5 V
= 0 V or 5 V;
I
QDD
270
525
250
500
1000
600
DD
IN
IN
Quiescent V Supply Current
V
I
I
BS
QBS
PDD
Operating V Supply Current
V
IN
DD
f
f
= 20 kHz; C = 1 nF
SW
L
Operating V Supply Current
V
= 0 V or 5 V;
I
PBS
1000
2000
BS
IN
= 20 kHz; C = 1 nF
SW
L
4. This limitation applies only to temperatures exceeding 105C.
LOGIC INPUT SECTION
Logic “1” Input threshold for IN, FLT
Logic “0” Input threshold for IN, FLT
Logic Input High Bias Current
V
2.1
1.7
48
2.5
V
IH
V
1.3
IL
V
V
= 5 V
= 0 V
I
70
2
mA
mA
kW
IN
IN+
Logic Input Low Bias Current
I
IN−
IN
Input Pull−down Resistance
R
80
IN
FAULT SECTION
Fault Output Internally pulled down voltage level
10 kW pull up resistor to
, V > V
DESAT+
V
V
200
mV
V
FLT+
V
DD
DESAT
Fault Output Not Internally pulled down voltage level
10 kW pull up resistor to
, V < V
DESAT+
13.8
FLT−
V
DD
DESAT
Fault Pin Pull−down Resistance
Desaturation High detection threshold (Note 5)
Desaturation Bias Current
R
110
3.0
kW
V
FLT
V
2.3
4
DESAT,TH
I
180
320
430
mA
DESAT
5. The actual desaturation threshold at the Power MOSFET can be adjusted to a value lower than V
Application Note)
with an external resistor (see
DESAT,TH
GATE DRIVER OUTPUT SECTION
High−Level Output Voltage (V − V
)
HO
V
V
= 5 V, No Load
= 0 V, No Load
V
HOH
50
50
mV
mV
A
B
IN
Low−Level Output Voltage (V −V )
V
HOL
HO
S
IN
Source Peak Pulsed Current (Note 6)
V
= 5 V, V = 0 V,
I
O+
2.5
2.5
IN
HO
Pulse Width 10 ms
Sink Peak Pulsed Current (Note 6)
V
= V = 15 V,
I
O−
HO
BS
Pulse Width 10 ms
Allowable Negative V pin voltage, with signal Prop-
V
S
−80
V
S
agation Capability from IN to HO
Driver Output Pull−up Resistance
Driver Output Pull−down Resistance
6. Guaranteed by design
I
I
= 90 mA (DC)
= 90 mA (DC)
R
3
W
W
OUT
OH
R
1.2
OUT
OL
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
ELECTRICAL CHARACTERISTICS
V
BIAS
(V , V ) = 15 V, V = 0 V unless otherwise noted, T = −40C to 125C. Voltage potentials are referenced to COM unless
DD
BS
S
A
otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
CHARGE PUMP SECTION [FAD3171MXA only]
Turn on threshold level, referenced to V
V
> V
R = 100 kW,
CP
7.9
8.3
10.8
15.2
15
V
BS
DD
DDUV+,
S
L
ON
V
= 48 V
Turn off threshold level, referenced to V
CP
CP
11.2
0.4
V
V
V
BS
OFF
Charge Pump V hysteresis
BS
HYS
Delta (CP − V
) (Note 7)
BSUV−
V
> V
R =100 kW,
D
CP,VBSUV−
1
ON
DD
DDUV+,
L
V
S
= 48 V
Charge Pump Supply Voltage
V
S,CP
24
V
Charge Pump Output Current capability (Note 8)
Charge Pump Oscillation Frequency (Note 6)
V
BS
= CP , V > V
I
CP,OUT
150
5.5
mA
ON
S
S,CP
CP
MHz
fs
7. Difference between the charge−pump turn on threshold and V under−voltage negative−going threshold.
BS
8. Net output current, excluding the internal current consumption of the gate driver in steady state.
DYNAMIC SECTION
Input pulse filtering time (Note 9)
Turn−On Propagation Delay
Turn−Off Propagation Delay
Turn−On Rise Time
T
40
50
50
15
10
10
ns
ns
ns
ns
ns
ms
IN_FILT
V
V
= 0 V, C = 1000 pF
t
ON
100
100
25
S
L
= 0 V, C = 1000 pF
t
OFF
S
L
Vs = 0 V, C = 1000 pF
t
R
L
Turn−Off Fall Time
t
F
20
V
DD
and V Under−Voltage filtering time (Note 6)
V
DD
< V
or V
<
t
VDDUV
BS
DDUV−
HO
BS
V
to V falls by 10%
BSUV−
t
VBSUV
External FLT Pulse Width (Note 10)
V
FLT
< V to V falls by
t
3
ms
IL
HO
FLT_Pulse
10%
Desat detection to HO propagation delay
V
> V
to V
L
T
75
110
110
ns
DESAT
DESAT+
HO
DESAT_HO
falls by 10% with R = 0 W
and C = 1 nF
L
Desat detection to FLT propagation delay
FLT Locking Duration
V
DESAT
> V
to V
T
80
ns
ms
W
DESAT,TH
FLT
DESAT_FLT
< V
FLT−
Desaturation or UVLO
detected
t
150
550
170
FLT_LO
Soft shutdown resistance
R
SOFT
9. Shorter input pulses are filtered out and do not cause the output to change state.
10.The pulse width of the external fault signal at which the driver output turns off.
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
20
10
20.0
18.0
16.0
14.0
12.0
10.0
8.0
t
R
−
t
F
6.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 4. Propagation Delay vs. Temperature
Figure 5. Rise Time vs. Temperature
1200
1000
800
600
400
200
0
8.2
8
I
PBS
VBSUV+
7.8
7.6
7.4
7.2
7
VBSUV−
I
PDD
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. Operating Supply Current vs.
Temperature
Figure 7. VBS UVLO vs. Temperature
2.5
2
4.6
4.4
4.2
4
V
IH
VDDUV+
V
IL
1.5
1
VDDUV−
3.8
3.6
3.4
3.2
3
0.5
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. VDD UVLO vs. Temperature
Figure 9. Logic Input Voltage vs. Temperature
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
TYPICAL CHARACTERISTICS
3.5
3.5
SINK
3
3
SINK
2.5
2.5
SOURCE
SOURCE
2
2
1.5
1
1.5
1
0.5
0
0.5
0
T = 25C
A
−40 −20
0
20
40
60
80
100 120
12
13
14
15
16
17
18
TEMPERATURE (C)
V
BS
, SUPPLY VOLTAGE (V)
Figure 10. Peak Pulsed Current vs.
Temperature
Figure 11. Peak Pulsed Current vs. VBS
Voltage
3.7
3.5
3.3
3.1
2.9
2.7
2.5
330
325
320
315
310
305
300
295
290
285
280
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 12. Desat Threshold vs. Temperature
Figure 13. Desat Current vs. Temperature
350
300
250
200
150
100
50
15
14
13
12
11
10
9
CP
OFF
CP
ON
8
7
6
5
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. Charge Pump Turn On/Turn Off
Threshold vs. Temperature
Figure 15. Soft Shutdown Resistance vs.
Temperature
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
GATE DRIVER DESCRIPTION
The gate driver does not take any action and the
Figure 2 shows the block diagram of the FAD3151MXA
and FAD3171MXA (with charge pump). The section below
describes the functional characteristics of 3151/71 gate
drivers.
output follows the input as expected.
After 10 ms of under−voltage condition, the UVLO
circuit triggers a fault for a period equal to FLT locking
duration:
If the under−voltage condition lasts for a duration
shorter than the FLT locking duration, the fault pin is
released after the FLT locking duration is over, upon
which the driver output will begin to follow the
input logic as expected (see Figure 17).
If the under−voltage condition lasts for a duration
longer than the FLT locking duration, the fault pin is
released only after the under−voltage condition has
disappeared. The driver output will begin to follow
the input logic once the fault pin is released (see
Figure 18).
Input and Fault Signal Buffer
The driver includes input and fault signal buffers to avoid
parasitic triggering due to noises at input and fault pins. The
input pin has a 40 ns filter, which means the driver output
will not change its state for an input pulse shorter than 40 ns.
Similarly, the fault pin has a 3 ms filter, which means the
driver output will not change its state for an external fault
pulse shorter than 3 ms.
VDD and VBS Under Voltage Lock Out
The gate driver has UVLO monitoring circuits with a
10 ms filter for both V and V power supplies. If the V
The figures below show examples of driver functionality
DD
BS
DD
or V voltages were to drop below their respective UVLO
during various under−voltage conditions of the V supply;
BS
BS
threshold:
note that the same description applies for an under−voltage
condition of the V supply.
Within the first 10 ms of an under−voltage condition
DD
(see Figure 16):
<10us
VBSUV+
VBSUV−
VBS
IN
HO
FLT
Figure 16. Under−Voltage Condition Shorter than 10 ms
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
10us
VBSUV+
VBSUV−
VBS
Under voltage duration ≤ tFLT_LO
IN
HO enabled
HO
FLT Locking Duration
(typ. 550us)
FLT
Figure 17. Under−Voltage Condition Shorter than FLT Locking Duration
10us
VBSUV+
VBSUV−
VBS
Under voltage duration > tFLT_LO
IN
HO
FLT Locking Duration
(typ. 550us)
FLT
HO disabled
FLT latched
Figure 18. Under−Voltage Condition Longer than FLT Locking Duration
Desaturation Protection with Soft Shutdown
The gate driver has a desaturation detection circuit that
An internal comparator that compares the voltage at the
desat pin (V ) with the defined desat threshold
DESAT
monitors the drain to source V voltage of the power
DS
(V
) of 3 V (typ.). When V
exceeds
DESAT,TH
DESAT
MOSFET through the desaturation detection pin. As shown
in the simplified block diagram in Figure 2, the desaturation
circuit comprises of:
V
, the comparator simultaneously turns off the
DESAT,TH
output ‘slowly’ and triggers a fault condition by pulling
down the fault pin internally.
As shown in application schematic in Figure 1, the desat
An internal current source that provides a continuous
current toward the power stage to monitor the V
DS
diode D , resistor R , blanking capacitor C , and
1 1 BL
voltage. The desat current source (I ) is supplied
DESAT
P−channel JFET P are the minimum external components
1
from the V pin and is continuously active as soon as
required to operate the desaturation protection scheme. The
B
the V is higher than the UVLO
, independent of
driver needs an external pull down transistor P to discharge
DD
VDD+
1
the status of the input logic.
I
and C as soon as the driver output turns off.
DESAT
BL
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NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
Otherwise, the blanking capacitor will continue to charge up
and eventually trigger desat. The presence of a normally on
P1 also enhances noise immunity of desat blanking
capacitor against false triggering during the turn on event of
complementary power switch. The external desat
components can be modified to adjust the blanking time and
the desat detection threshold for a given application. It is
recommended to refer to the Application Note for more
details.
If the power switch is turned−off rapidly during a
heavy−load condition, the high currents may generate a
voltage overshoot across the power switch that could
potentially damage it. In order to protect the devices, the
driver has a soft shutdown feature, which activates upon
desat detection. The output is then driven low through a large
When the voltage at the desaturation pin exceeds the
defined desat threshold, following protection sequence is
performed:
The gate driver initiates a soft shutdown. The driver
will provide a high resistive path through R
for
SOFT
gate capacitance to discharge slowly [see Figure 19].
The fall rate of HO is determined by the time constant
of the RC discharge path.
The driver also triggers an internal fault and pulls down
the fault pin for the period equivalent to Fault Locking
duration (typ. 550 ms).
NOTE: If the desat condition persists even after the fault
locking duration, and if the input signal is still
provided, the driver output will reappear for a
period equivalent to the blanking time, after
which the desat protection will retrigger the soft
shutdown and turn off the output again.
turn−off resistance (R
) which provides a significantly
SOFT
higher resistive path for the gate capacitance to discharge
than during the regular turn−off process. As a result, the
possibility of an abrupt overvoltage spike on the power
switches is reduced.
VDESAT,TH
Desat
IN
Soft shutdown
HO
FLT
FLT Locking Duration
(typ. 550us)
Figure 19. Desaturation Protection and Soft Shutdown
External Fault Triggerring
to logic 1). In this case, the FLT pin performs similar to an
enable pin. The external fault triggering capability allows
the interconnection of fault pins of multiple gate drivers on
both high side and low side driver stages. For example, in a
multi−phase inverter system, the fault pins of all high−side
drivers (or low−side drivers) could be tied together and
controlled with an external controller to achieve Active
short−circuit (ASC) protection. It is recommended to refer
to the Application Note for more details.
The FLT pin is bi−directional in nature and is in a
pulled−up state for normal operation. The gate driver pulls
down the FLT pin internally during desat and under−voltage
lockout condition. As shown in Figure 20, if the FLT pin is
externally pulled down to a logic low for a period longer than
the external FLT pulse width (min. 3 ms), the driver turns off.
It is important to note that the FLT locking duration is not
valid for external fault trigger condition. As a result, the
output is reactivated as soon as the FLT pin is released (set
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
External FLT Pulse Width
(min. 3us)
FLT
(external)
IN
HO
Figure 20. External fault Triggering Condition
Charge Pump for 100% Duty Cycle Operation
It should be ensured that the total leakage current in the
gate path does not exceed the maximum output current
The FAD3171MXA driver contains an internal charge
pump that enables 100% duty−cycle operation of high−side
power switches. When the high−side switch is kept on for a
long duration, the bootstrap capacitor could slowly
discharge and may eventually trigger the under−voltage
lockout protection and turn off the driver output. Therefore,
capability of the charge pump I . For example, in
CP,OUT
Figure 21, when the gate is continuously high, the
pull−down resistance R will continuously sink a current
2
and for this reason, its value should be high enough to
minimize the total leakage current drawn from the charge
pump. Considering a maximum output current of 150 mA at
the purpose of the charge pump is to supply the V
BS
quiescent current necessary for the high−side gate driver to
operate under 100% duty cycle and to compensate for
additional leakage current on the gate path.
V
= CP = 15 V, the value of R should be higher than
BS
ON 2
100 kW to maintain a steady charge pump output.
48V
VDD
RBOOT
DBOOT
D1
R1
1. VDD
2. IN
8. VB
CBOOT
RG
7. HO
3. FLT 6. Desat
4. COM 5. VS
R2
CBL
P1
Figure 21. Leakage Current in the Gate Path
It is important to note that the charge pump is not intended
other times. The necessary conditions for the charge pump
in FAD3171MXA to activate are:
to provide gate charge during switching of power MOSFET;
rather its purpose is to only keep the MOSFET turned on. For
this, it should be ensured at the system level that the
high−side MOSFET is not operated at very high duty cycle
or, if a high duty cycle operation is required, the off time
should be long enough to allow the bootstrap capacitor on
high−side gate driver to completely recharge.
The V voltage is higher than the V under voltage
DD
DD
positive−going threshold (V
)
DDUV+
The V voltage is higher than VS,CP (24 V min.); below
S
this voltage, the efficiency of the charge pump is
reduced.
The V voltage decreases below the charge pump turn
BS
In order to minimize continuous power dissipation, the
charge pump turns on only when needed, and remains off at
on threshold (CP ).
ON
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CONFIDENTIAL AND PROPRIETARY
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FAD3151MXA, FAD3171MXA
The charge pump deactivates as soon as:
turn−on threshold (CP ) is designed to be higher than the
ON
V
threshold. As a result, the driver output is higher
The V voltage rises back to a value higher the charge
BSUV−
BS
than the V
load on the charge pump exceeds I
the V −V pins will slowly decrease and eventually trigger
the under−voltage lockout protection and turn off the driver
threshold during charge pump mode. If the
BSUV−
pump turn off threshold (CP ).
OFF
, the voltage across
CP,OUT
The V is lower than the V under voltage
DD
DD
B
S
negative−going threshold (V
).
DDUV−
In order to ensure that the charge pump and the UVLO
function do not interfere with each other, the charge pump
output.
Switching Time Definitions
VDD=15V
1. VDD
2. IN
8. VB
7. HO
3. FLT 6. Desat
4. COM 5. VS
Figure 22. Switching Time Test Circuit
IN
HO
Figure 23. Input / Output Timing Diagram
50%
50%
IN
tON tr
tOFF
tf
90%
90%
HO
10%
10%
Figure 24. Switching Time Waveform Definitions
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
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CONFIDENTIAL AND PROPRIETARY
NOT FOR PUBLIC RELEASE
FAD3151MXA, FAD3171MXA
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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