FAN5355UC08X [ONSEMI]
1.1A / 1A / 0.8A、3MHz数字可编程调节器;
| 型号： | FAN5355UC08X |
| 厂家： | 
ONSEMI |
| 描述： | 1.1A / 1A / 0.8A、3MHz数字可编程调节器 调节器 |
| 文件： | 总28页 (文件大小：1959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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May 2016
FAN5355
1.1 A / 1 A / 0.8 A, 3 MHz Digitally Programmable Regulator
Features
Description
The FAN5355 device is a high-frequency, ultra-fast transient
response, synchronous step-down DC-DC converter
optimized for low-power applications using small, low-cost
inductors and capacitors. The FAN5355 supports up to
800 mA, 1 A, or 1.1 A load current.
. 93% Efficiency at 3 MHz
. 800 mA, 1 A, or 1.1 A Output Current
. I2C™-Compatible Interface up to 3.4 Mbps
. 6-bit VOUT Programmable from 0.75 V to 1.975 V
. 2.7 V to 5.5 V Input Voltage Range
The device is ideal for mobile phones and similar portable
applications powered by a single-cell Lithium-Ion battery. With
an output-voltage range adjustable via I2C™ interface from
0.75 V to 1.975 V, the device supports low-voltage DSPs and
processors, core power supplies, and memory modules in
smart phones, PDAs, and handheld computers.
. 3 MHz Fixed-Frequency Operation
. Excellent Load and Line Transient Response
. Small Size, 1 μH Inductor Solution
The FAN5355 operates at 3 MHz (nominal) fixed switching
frequency using either its internal oscillator or an external
SYNC frequency.
. ±2% PWM DC Voltage Accuracy
. 35 ns Minimum On-Time
. High-Efficiency, Low-Ripple, Light-Load PFM
. Smooth Transition between PWM and PFM
. 37 μA Operating PFM Quiescent Current
. Pin-Selectable or I2C™ Programmable Output Voltage
. On-the-Fly External Clock Synchronization
. 10-lead MLP (3 x 3 mm) or 12-bump CSP Packages
During light-load conditions, the regulator includes a PFM
mode to enhance light-load efficiency. The regulator
transitions smoothly between PWM and PFM modes with no
glitches on VOUT. In hardware shutdown, the current
consumption is reduced to less than 200 nA.
The serial interface is compatible with Fast/Standard and
High-Speed mode I2C specifications, allowing transfers up to
3.4 Mbps. This interface is used for dynamic voltage scaling
with 12.5 mV voltage steps for reprogramming the mode of
operation (PFM or Forced PWM), or to disable/enable the
output voltage.
Applications
. Cell Phones, Smart Phones
The chip's advanced protection features include short-circuit
protection and current and temperature limits. During a
sustained over-current event, the IC shuts down and restarts
after a delay to reduce average power dissipation into a fault.
. 3G, WiFi®, WiMAX™, and WiBro® Data Cards
. Netbooks®, Ultra-Mobile PCs
. SmartReflex™-Compliant Power Supply
. Split Supply DSPs and μP Solutions OMAP™, XSCALE™
. Mobile Graphic Processors (NVIDIA®, ATI)
. LPDDR2 and Memory Modules
During startup, the IC controls the output slew rate to minimize
input current and output overshoot at the end of soft start. The
IC maintains a consistent soft-start ramp, regardless of output
load during startup.
The FAN5355 is available in 10-lead MLP (3x3 mm) and
12-bump WLCSP packages.
All trademarks are the property of their respective owners.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
www.fairchildsemi.com
Ordering Information
Slave Address Output
LSB Current VOUT Programming
Power-up
Defaults
Order Number(1) Option
A1
0
A0
0
mA
800
Min.
Max.
VSEL0 VSEL1
Package
FAN5355UC00X
FAN5355MP00X
FAN5355UC02X
FAN5355UC03X*
FAN5355UC06X
FAN5355UC08X*
00
00
02
03
06
08
0.7500
0.7500
0.7500
0.7500
1.1875
0.7500
1.5375
1.5375
1.4375(2)
1.5375
1.9750
1.4375(2)
1.05
1.05
1.05
1.00
1.80
1.05
1.35 WLCSP-12, 2.23 x 1.46 mm
1.35 MLP-10, 3 x 3 mm
0
0
800
1
0
800
1.20
WLCSP-12, 2.23 x 1.46 mm
0
0
1000
1000
1100
1.20 WLCSP-12, 2.23 x 1.46 mm
1.80 WLCSP-12, 2.23 x 1.46 mm
0
0
1
0
1.20
WLCSP-12, 2.23 x 1.46 mm
Notes:
1. The “X” designator specifies tape and reel packaging.
2. VOUT is limited to the maximum voltage for all VSEL codes greater than the maximum VOUT listed.
This device is End of Life. Please contact sales for additional information and assistance with replacement devices.
*
Typical Application
AVIN
PVIN
SW
VIN
Q1
Q2
CIN
EN
VSEL
SYNC
VOUT
L OUT
MODULATOR
COUT
SDA
SCL
PGND
VOUT
AGND
Figure 1. Typical Application
Table 1. Recommended External Components
Component
Description
Vendor
Parameter
L(3)
Min.
Typ.
Max.
Units
μH
0.7
1.0
1.2
Murata LQM31P
or FDK MIPSA2520
L1 (LOUT
)
1μH nominal
DCR (series R)
100
mΩ
0603 (1.6x0.8x0.8)
10 μF X5R or better
Murata or equivalent
GRM188R60G106ME47D
COUT
CIN
C(4)
C(4)
5.6
3.0
10.0
4.7
12.0
5.6
μF
μF
0603 (1.6 x 0.8 x 0.8)
4.7 μF X5R or better
Murata or equivalent
GRM188R60J475KE19D
Notes:
3. Minimum L incorporates tolerance, temperature, and partial saturation effects (L decreases with increasing current).
4. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to
frequency, dielectric, and voltage bias effects.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
2
www.fairchildsemi.com
Pin Configuration
Top View
Bottom View
Top View
Figure 2. WLCSP-12, 2.23 x 1.46 mm
Figure 3. MLP10, 3 x 3 mm
Pin Definitions
Pin #
Name(5) Description
WLCSP MLP
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB.
The connection from this pin to the bottom of CIN should be as short as possible.
A1, B1
A2
9
10
1
PGND
SW
Switching Node. Connect to output inductor.
Power Input Voltage. Connect to input power source. The connection from this pin to CIN
should be as short as possible.
A3
PVIN
Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency
on this pin. In PWM mode, when this pin is statically LOW or statically HIGH, or when its
frequency is outside of the specified capture range, the regulator’s frequency is controlled by
its internal 3 MHz clock.
B2
N/A
SYNC
Analog Input Voltage. Connect to input power source as close as possible to the input
bypass capacitor.
B3
C1
2
AVIN
Analog GND. This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin.
8, PAD
AGND
Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is
minimized. This pin should not be left floating.
SDA. I2C interface serial data.
C2
C3
D1
7
3
6
EN
SDA
Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the
control circuit and does not carry DC current.
VOUT
Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This
D2
D3
5
4
VSEL
SCL
behavior can be overridden through I2C register settings. This pin should not be left floating.
SCL. I2C interface serial clock.
Note:
5. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
3
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol Parameter
Min.
-0.3
-0.3
Max.
6.5
AVIN + 0.3(6)
Unit
V
AVIN, SW, PVIN Pins
VCC
Other Pins
V
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
3.5
1.5
KV
KV
°C
°C
°C
Electrostatic Discharge
Protection Level
ESD
TJ
TSTG
TL
Junction Temperature
Storage Temperature
–40
–65
+150
+150
+260
Lead Soldering Temperature, 10 Seconds
Note:
6. Lesser of 6.5V or AVIN+0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to absolute maximum ratings.
Symbol Parameter
Min.
2.7
Max.
5.5
Unit
V
VIN
f
Supply Voltage
Frequency Range
2.7
3.3
MHz
V
VCCIO
TA
SDA and SCL Voltage Swing(7)
Ambient Temperature
Junction Temperature
2.5
–40
–40
+85
+125
°C
TJ
°C
Note:
7. The I2C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5 V. If voltage
swings greater than 2.5 V are required (for example if the I2C bus is pulled up to VIN), the minimum tHD;DAT must be
increased to 80 ns. Most I2C masters change SDA near the midpoint between the falling and rising edges of SCL, which
provides ample tHD;DAT
.
Dissipation Ratings(8)
(9)
Package
θJA
Power Rating at TA ≤ 25°C Derating Factor > TA = 25ºC
Molded Leadless Package (MLP)
Wafer-Level Chip-Scale Package (WLCSP)
Notes:
49ºC/W
2050 mW
900 mW
21 mW/ºC
9 mW/ºC
110ºC/W
8. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any
allowable ambient temperature is PD = [TJ(max) - TA ] / θJA.
9. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard).
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
4
www.fairchildsemi.com
Electrical Specifications
VIN = 3.6 V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1.
Symbol Parameter
Power Supplies
Conditions
Min.
Typ. Max.
Units
VIN
Input Voltage Range
2.7
5.5
V
IO = 0 mA, PFM Mode
IO = 0 mA, 3 MHz PWM Mode
EN = GND
37
4.8
0.1
50
μA
mA
IQ
Quiescent Current
2.0
2.0
ISD
Shutdown Supply Current
μA
EN = VIN, EN_DCDC bit = 0,
SDA = SCL = VIN
0.1
V
IN Rising
2.40
2.15
250
2.60
2.30
300
V
V
VUVLO Under-Voltage Lockout Threshold
VIN Falling
2.00
200
VUVHYST Under-Voltage Lockout Hysteresis
mV
ENABLE, VSEL, SDA, SCL, SYNC
VIH
VIL
IIN
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input Bias Current
1.2
V
V
0.4
Input tied to GND or VIN
0.01
1.00
μA
Power Switch and Protection
V
IN = 3.6 V, CSP Package
145
165
200
P-Channel MOSFET On
Resistance
RDS(ON)P
VIN = 3.6 V, MLP Package
VIN = 2.7 V, MLP Package
VDS = 6 V
mΩ
μA
ILKGP
P-Channel Leakage Current
1
V
IN = 3.6 V, CSP Package
75
95
N-Channel MOSFET On
Resistance
RDS(ON)N
VIN = 3.6 V, MLP Package
VIN = 2.7 V, MLP Package
VDS = 6 V
mΩ
101
ILKGN
RDIS
N-Channel Leakage Current
1
μA
Discharge Resistor for Power-
Down Sequence
Options 03 and 06
60
120
Ω
2.7 V ≤ VIN ≤ 4.2 V, Options 00 and 02
2.7 V ≤ VIN ≤ 5.5 V, Options 00 and 02
2.7 V ≤ VIN ≤ 4.2 V, Options 03 and 06
2.7 V ≤ VIN ≤ 5.5 V, Options 03 and 06
2.7 V ≤ VIN ≤ 4.5 V, Option 08
1150
1050
1350
1250
1400
1350
1350
1550
1550
1650
150
1600
1600
1800
1800
ILIMPK
P-MOS Current Limit
mA
TLIMIT
THYST
Thermal Shutdown
°C
°C
Thermal Shutdown Hysteresis
20
Frequency Control
fSW
Oscillator Frequency
Synchronization Range
2.65
2.7
20
3.00
3.0
3.35
3.3
80
MHz
MHz
%
fSYNC
DSYNC Synchronization Duty Cycle
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
5
www.fairchildsemi.com
Electrical Specifications (Continued)
VIN = 3.6 V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1.
Symbol Parameter
Output Regulation
Conditions
Min.
Typ.
Max.
Units
IOUT(DC) = 0, Forced PWM, VOUT = 1.35 V
–1.5
–2
1.5
2
%
%
%
%
%
%
%
%
%
%
%
%
%
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.5375, IOUT(DC) = 0 to 800 mA, Forced PWM
Option 00
Option 02
Option 03
Option 06
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.5375, IOUT(DC) = 0 to 800 mA, PFM Mode
–1.5
–1.5
–2
3.5
1.5
2
IOUT(DC) = 0, Forced PWM, VOUT = 1.20 V
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.4375, IOUT(DC) = 0 to 800 mA, Forced PWM
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.4375, IOUT(DC) = 0 to 800 mA, PFM Mode
–1.5
–1.5
–2
3.5
1.5
2
IOUT(DC) = 0, Forced PWM, VOUT = 1.20 V
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.5375, IOUT(DC) = 0 to 1 A, Forced PWM
VOUT
VOUT Accuracy
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.5375, IOUT(DC) = 0 to 1 A, PFM Mode
–1.5
–1.5
–2
3.5
1.5
2
IOUT(DC) = 0, Forced PWM, VOUT = 1.800 V
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 1.185 to
1.975, IOUT(DC) = 0 to 1 A, Forced PWM
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 1.185 to
1.975, IOUT(DC) = 0 to 1 A, PFM Mode
–1.5
–1.5
3.5
1.5
I
OUT(DC) = 0, Forced PWM, VOUT = 1.20 V
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
Option 08 1.4375, IOUT(DC) = 0 to 1100 mA, Forced
PWM
–2
2
%
2.7 V ≤ VIN ≤ 5.5 V, VOUT from 0.75 to
1.4375, IOUT(DC) = 0 to 1100 mA, PFM Mode
–1.5
3.5
%
ΔVOUT
ΔILOAD
Load Regulation
Line Regulation
IOUT(DC) = 0 to 800 mA, Forced PWM
–0.5
0
%/A
ΔVOUT
ΔVIN
2.7 V ≤ VIN ≤ 5.5 V, IOUT(DC) = 300 mA
%/V
PWM Mode, VOUT = 1.35 V
2.2
20
mVPP
mVPP
VRIPPLE Output Ripple Voltage
PFM Mode, IOUT(DC) = 10 mA
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
6
www.fairchildsemi.com
Electrical Specifications (Continued)
VIN = 3.6 V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1.
Symbol Parameter
6-Bit DAC
Conditions
Min.
Typ.
Max.
Units
Differential Nonlinearity
Monotonicity Assured by Design
0.8
LSB
Timing
I2CEN
EN HIGH to I2C Start
250
μs
μs
R
LOAD = 75 Ω, Transition from 1.0 to
tV(L-H)
VOUT LOW to HIGH Settling
7
1.5375 V,
VOUT Settled to within 2% of Set Point
Soft Start
Option 06
Regulator
170
140
210
180
R
LOAD > 5 Ω, to VOUT = 1.8000 V
μs
μs
tSS
Enable to
All Other
RLOAD > 5 Ω, to VOUT = Power-up Default
Regulated VOUT
Options
VSLEW
Soft-start VOUT Slew Rate(10)
18.75
V/ms
Note:
10. Option 03 and 06 slew rates are 35.5 V/ms during the first 16 μs of soft start.
AVIN
PVIN
VIN
Q1
Q2
CIN
7-bit
DAC
REF
EN
VSEL
SYNC
SDA
VOUT
SW
I2C
SOFT START
FPWM
L OUT
INTERFACE
AND LOGIC
COUT
MODULATOR
EN_REG
CLK
SCL
PGND
VOUT
AGND
3 MHz Osc
Figure 4. Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
7
www.fairchildsemi.com
I2C Timing Specifications
Guaranteed by design.
Symbol Parameter
Conditions
Min.
Typ.
Max.
100
Units
kHz
Standard Mode
Fast Mode
400
kHz
fSCL
SCL Clock Frequency
3400
1700
kHz
High-Speed Mode, CB < 100 pF
kHz
High-Speed Mode, CB < 400 pF
Standard Mode
4.7
1.3
4
μs
μs
μs
ns
ns
μs
μs
ns
ns
μs
ns
ns
ns
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
pF
Bus-Free Time between STOP and
START Conditions
tBUF
Fast Mode
Standard Mode
START or Repeated-START Hold
Time
tHD;STA
Fast Mode
600
160
4.7
1.3
160
320
4
High-Speed Mode
Standard Mode
Fast Mode
tLOW
SCL LOW Period
SCL HIGH Period
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
Fast Mode
600
60
tHIGH
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
120
4.7
600
160
250
100
10
tSU;STA
Repeated-START Setup Time
Data Setup Time
Fast Mode
High-Speed Mode
Standard Mode
tSU;DAT
Fast Mode
High-Speed Mode
Standard Mode
0
0
0
0
3.45
900
70
Fast Mode
tHD;DAT
Data Hold Time(7)
SCL Rise Time
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
150
1000
300
80
20+0.1CB
Fast Mode
20+0.1CB
tRCL
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
10
20
160
300
300
40
20+0.1CB
20+0.1CB
Fast Mode
tFCL
SCL Fall Time
SDA Rise Time
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
10
20
80
20+0.1CB
20+0.1CB
1000
300
80
tRDA
Fast Mode
Rise Time of SCL After a Repeated
START Condition and After ACK Bit
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
10
20
tRCL1
160
300
300
80
20+0.1CB
20+0.1CB
Fast Mode
tFDA
SDA Fall Time
High-Speed Mode, CB < 100 pF
High-Speed Mode, CB < 400 pF
Standard Mode
10
20
4
160
tSU;STO
CB
Stop Condition Setup Time
Fast Mode
600
160
High-Speed Mode
Capacitive Load for SDA and SCL
400
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
SCL
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 5. I2C Interface Timing for Fast and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
9
www.fairchildsemi.com
Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/PFM, VIN = 3.6 V, TA = 25°C, and recommended components as specified in Table 1.
Efficiency
100 %
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100 %
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Auto PWM/PFM
Forced PWM
Auto PWM/PFM
Forced PWM
VIN = 3.6V
OUT = 1.35V
VIN = 3.6V
VOUT = 1.05V
V
1
10
100
100 0
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 7. Efficiency vs. Load at VOUT = 1.05 V
Figure 8. Efficiency vs. Load at VOUT = 1.35 V
100 %
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Auto PWM/PFM
Forced PWM
Auto PWM/PFM
Forced PWM
VIN = 3.6V
OUT = 1.5V
VIN = 3.6V
OUT = 1.8V
V
V
1
10
100
100 0
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 9. Efficiency vs. Load at VOUT = 1.50 V
Figure 10. Efficiency vs. Load at VOUT = 1.80 V
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/PFM, VIN = 3.6 V, TA = 25°C, and recommended components as specified in Table 1.
1.064
1.062
1.060
1.058
1.056
1.054
1.052
1.050
1.048
1.364
1.362
1.360
1.358
1.356
1.354
1.352
1.350
1.348
Auto PWM/PFM
Forced PWM
Auto PWM/PFM
Forced PWM
1
10
100
1000
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 11. Load Regulation at VOUT = 1.05 V
Figure 12. Load Regulation at VOUT = 1.35 V
1.816
0.10%
1.814
1.812
1.810
1.808
1.806
1.804
1.802
1.800
1.798
0.05%
0.00%
-0.05%
-0.10%
-0.15%
-0.20%
-0.25%
-0.30%
Auto PWM/PFM
Forced PWM
VIN = 2.7V
VIN = 3.6V
VIN = 5.5V
1
10
100
1000
-40
-20
0
20
40
60
80
I LOAD OutputCurrent (mA)
Temperature (C)
Figure 13. Load Regulation at VOUT = 1.80 V
Figure 14. % VOUT Shift vs. Temperature (Normalized)
70
65
60
55
50
45
40
35
30
6.0
5.0
VSEL = 1.8V
4.0
3.0
2.0
1.0
VSEL = 0V
VSEL = 1.8V
VSEL = 0V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN Input Voltage (V)
VIN Input Voltage (V)
Figure 15. Quiescent Current, ILOAD = 0, EN = 1.8 V
Figure 16. Shutdown Current, ILOAD = 0, EN = 0
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.35 V, and load step tR = tF < 100 ns.
Load Transient Response
Figure 17. 50 mA to 400 mA to 50 mA, Forced PWM
Figure 18. 50 mA to 400 mA to 50 mA, Auto PWM/PFM
Figure 19. 400 mA to 750 mA to 400 mA, Auto PWM/PFM
Figure 20. 0 mA to 125 mA to 0 mA, Auto PWM/PFM
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6 V.
VSEL Transitions
Figure 21. Single-Step, RLOAD = 6.2 Ω
Figure 22. Single-Step, RLOAD = 6.2 Ω
Figure 23. Single-Step, RLOAD = 50 Ω
Figure 24. Single-Step, RLOAD = 50 Ω
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6 V.
VSEL Transitions
Figure 25. Single-Step from Forced PWM (MODE1=0),
RLOAD = 50 Ω
Figure 26. Single-Step, RLOAD = 6.2 Ω
IL
VOUT
VSEL
Figure 27. Single–Step from Auto PWM/PFM (MODE1=1),
Figure 28. Multi-Step, Controlled DAC Step (9.6 mV/µs)
DEF_Slew 6 (110), 800 mA Load
RLOAD = 50 Ω
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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Typical Performance Characteristics (Continued)
RLOAD is switched with N-channel MOSFET from VOUT to GND. VIN = 3.6 V, initial VOUT = 1.35 V, initial ILOAD = 0 mA.
Short Circuit and Over-Current Fault Response
Figure 29. Metallic Short Applied at VOUT
Figure 30. Metallic Short Applied at VOUT
Figure 31. RLOAD = 660 mΩ
Figure 32. RLOAD = 660 mΩ
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6 V.
Figure 33. SW-Node Jitter (Infinite Persistence),
ILOAD = 200 mA
Figure 34. SW-Node Jitter, External Synchronization
(Infinite Persistence), ILOAD = 200 mA
70
60
IOUT=500mA
50
IOUT=150mA
IOUT=20mA
40
30
20
10
-
(10)
0.1
1.0
10.0
100.0
1,000.0
Frequency (KHz)
Figure 36. VIN Ripple Rejection (PSRR)
Figure 35. Soft Start, RLOAD = 50 Ω
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Circuit Description
Overview
Power-Up, EN, and Soft-Start
The FAN5355 is a synchronous buck regulator that typically
operates at 3 MHz with moderate to heavy load currents. At
light load currents, the converter operates in power-saving
PFM mode. The regulator automatically transitions between
fixed-frequency PWM and variable-frequency PFM mode to
maintain the highest possible efficiency over the full range of
load current.
All internal circuits remain de-biased and the IC is in a very
low quiescent-current state until the following are true:
1. VIN is above its rising UVLO threshold, and
2. EN is HIGH.
At that point, the IC begins a soft-start cycle, its I2C interface is
enabled, and its registers are loaded with their default values.
The FAN5355 uses a very fast non-linear control architecture
to achieve excellent transient response with minimum-sized
external components.
The FAN5355 integrates an I2C-compatible interface, allowing
transfers up to 3.4 Mbps. This communication interface can be
used to:
During the initial soft start, VOUT ramps linearly to the set point
programmed in the VSEL register selected by the VSEL pin.
The soft start features a fixed output-voltage slew rate of
18.75V/ms and achieves regulation approximately 90μs after
EN rises. PFM mode is enabled during soft start until the
output is in regulation, regardless of the MODE bit settings.
This allows the regulator to start into a partially charged output
without discharging it; in other words, the regulator does not
allow current to flow from the load back to the battery.
1. Dynamically re-program the output voltage in 12.5 mV
increments.
2. Reprogram the mode of operation to enable or disable
PFM mode.
As soon as the output has reached its set point, the control
forces PWM mode for about 85μs to allow all internal control
circuits to calibrate.
3. Control voltage transition slew rate.
4. Control the frequency of operation by synchronizing to an
external clock.
Table 2. Soft-Start Timing (see Figure 37)
5. Enable / disable the regulator.
For more details, refer to the I2C Interface and Register
Description sections.
Symbol
Description
Value (μs)
Time from EN to start of
soft-start ramp
tSSDLY
75
Opt 03, 06 16 +(VSEL–0.7) X 53
VOUT ramp
Output Voltage Programming
tREG
start to
regulation
Opt 00,
(VSEL–0.1) X 53
02, 08
Option(11)
00, 02, 03, 08
06
VOUT Equation
PWROK (CONTROL2[5])
rising from end of tREG and
regulator stays in PWM
mode during this time
VOUT = 0.75 + NVSEL •12.5mV
(1)
(2)
tPOK
10
VOUT = 1.1875 + NVSEL •12.5mV
where NVSEL is the decimal value of the setting of the VSEL
register that controls VOUT
.
Note:
11. Option 02 and 08 maximum voltage is 1.4375 V (see
Table 3).
Figure 37. Soft-Start Timing
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
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www.fairchildsemi.com
Table 3. VSEL vs. VOUT
Software Enable
VSEL Value
VOUT
02, 08
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
The EN_DCDC bit, VSELx[7] can enable the regulator in
conjunction with the EN pin. Setting EN_DCDC with EN HIGH
begins the soft-start sequence described above.
Dec Binary Hex 00, 03
06
0
1
2
3
4
5
6
7
8
9
000000 00
000001 01
000010 02
000011 03
000100 04
000101 05
000110 06
000111 07
001000 08
001001 09
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1.6125
1.6250
1.6375
1.6500
1.6625
1.6750
1.6875
1.7000
1.7125
1.7250
1.7375
1.7500
1.7625
1.7750
1.7875
1.8000
1.8125
1.8250
1.8375
1.8500
1.8625
1.8750
1.8875
1.9000
1.9125
1.9250
1.9375
1.9500
1.9625
1.9750
Table 4. EN_DCDC Behavior
EN_DCDC Bit
EN Pin
I2C
OFF
ON
REGULATOR
0
1
1
0
0
1
0
1
OFF
ON
OFF
ON
OFF
OFF
10 001010 0A 0.8750
11 001011 0B 0.8875
12 001100 0C 0.9000
13 001101 0D 0.9125
14 001110 0E 0.9250
Light-Load (PFM) Operation
15 001111 0F
16 010000 10
17 010001 11
18 010010 12
19 010011 13
20 010100 14
21 010101 15
22 010110 16
23 010111 17
24 011000 18
25 011001 19
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
The FAN5355 offers a low-ripple, single-pulse PFM mode to
save power and improve efficiency when the load current is
very low. PFM operation features:
. Smooth transitions between PFM and PWM modes
. Single-pulse operation for low ripple
. Predictable PFM entry and exit currents.
PFM begins after the inductor current has become
discontinuous, crossing zero during the PWM cycle in 32
consecutive cycles. PFM exit occurs when discontinuous
current mode (DCM) operation cannot supply sufficient current
to maintain regulation. During PFM mode, the inductor current
ripple is about 40% higher than in PWM mode. The load
current required to exit PFM mode is thereby about 20%
higher than the load current required to enter PFM mode,
providing sufficient hysteresis to prevent “mode chatter.”
26 011010 1A 1.0750
27 011011 1B 1.0875
28 011100 1C 1.1000
29 011101 1D 1.1125
30 011110 1E 1.1250
31 011111 1F
32 100000 20
33 100001 21
34 100010 22
35 100011 23
36 100100 24
37 100101 25
38 100110 26
39 100111 27
40 101000 28
41 101001 29
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
While PWM ripple voltage is typically less than 4mVPP, PFM
ripple voltage can be up to 30 mVPP during very light load. To
prevent significant undershoot when a load transient occurs,
the initial DC set point for the regulator in PFM mode is set
10 mV higher than in PWM mode. This offset decays to about
5 mV after the regulator has been in PFM mode for ~100 μs.
The maximum instantaneous voltage in PFM is 30 mV above
the set point.
42 101010 2A 1.2750
43 101011 2B 1.2875
44 101100 2C 1.3000
45 101101 2D 1.3125
46 101110 2E 1.3250
PFM mode can be disabled by writing to the mode control bits:
CONTROL1[3:0] (see Table 1 for details).
47 101111 2F
48 110000 30
49 110001 31
50 110010 32
51 110011 33
52 110100 34
53 110101 35
54 110110 36
55 110111 37
56 111000 38
57 111001 39
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
Some vendors provide both “Light PFM” (LPFM) and “Fast
PFM” (FPFM) modes, while the FAN5355 provides only one
PFM mode. The FAN5355’s single PFM mode features the
fast transient recovery of FPFM, but does this with the low
quiescent current consumption similar to LPFM mode.
58 111010 3A 1.4750
59 111011 3B 1.4875
60 111100 3C 1.5000
61 111101 3D 1.5125
62 111110 3E 1.5250
63 111111 3F
1.5375
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
18
www.fairchildsemi.com
Multi-Step Mode:
Switching-Frequency Control and
Applies to Options 03 and 06 only.
Synchronization
The nominal internal oscillator frequency is 3 MHz. The
regulator runs at its internal clock frequency until these
conditions are met:
The internal DAC is stepped at a rate defined by DEFSLEW,
CONTROL2[2:0], ranging from 000 to 110. This mode
minimizes the current required to charge COUT and thereby
minimizes the current drain from the battery when
transitioning. The PWROK bit, CONTROL2[5], remains LOW
until about 1.5 μs after the DAC completes its ramp.
1. EN_SYNC bit, CONTROL1[5], is set; and
2. A valid frequency appears on the SYNC pin.
Table 5. SYNC
Frequency
Validation
for
VHIGH
fOSC(INTERNAL)=3.0 MHz
CONTROL2
fSYNC Valid
PLL_MULT fSYNC Divider
Min.
1.80
0.90
0.60
0.45
Typ.
3.00
1.50
1.00
0.75
Max.
4.00
2.00
1.33
1.00
VOUT
00
01
10
11
1
2
3
4
VLOW
VSEL
tPOK(L-H)
PWROK
If the EN_SYNC is set and SYNC fails validation, the regulator
continues to run at its internal oscillator frequency. The
regulator is functional if fSYNC is valid, as defined in Table 5,
but its performance is compromised if fSYNC is outside the fSYNC
window in the Electrical Specifications.
Figure 38. Multi-Step VOUT Transition
Single-Step Mode:
Used if DEFSLEW, CONTROL2[2:0] = 111. The internal DAC
is immediately set to the higher voltage and the regulator
performs the transition as quickly as its current-limit circuit
allows, while avoiding excessive overshoot.
When CONTROL1[3:2] = 00 and the VSEL line is LOW, the
converter operates according to the MODE0 bit,
CONTROL1[0], with synchronization disabled regardless of
the state of the EN_SYNC and HW_nSW bits.
Figure 39 shows single-step transition timing. tV(L-H) is the time
it takes the regulator to settle to within 2% of the new set point
and is typically 7 μs for a full-range transition (from 000000 to
111111). The PWROK bit, CONTROL2[5], goes LOW until the
transition is complete and VOUT settled. This typically occurs
Output Voltage Transitions
The IC regulates VOUT to one of two set point voltages, as
determined by the VSEL pin and the HW_nSW bit.
~2 μs after tV(L-H)
.
Table 6. VOUT Set Point and Mode Control MODE_CTRL,
CONTROL1[3:2] = 00
It is good practice to reduce the load current before making
positive VSEL transitions. This reduces the time required to
make positive load transitions and avoids current-limit-induced
overshoot.
VSEL Pin HW_nSW Bit
VOUT Set Point
PFM
0
1
x
1
1
0
VSEL0
VSEL1
VSEL1
Allowed
Per MODE1
Per MODE1
tV(L-H)
VHIGH
98% VHIGH
If HW_nSW = 0, VOUT transitions are initiated through the
following sequence:
1. Write the new setpoint in VSEL1.
VOUT
2. Write desired transition rate in DEFSLEW,
VLOW
CONTROL2[2:0], and set the GO bit in CONTROL2[7].
VSEL
If HW_nSW = 1, VOUT transitions are initiated either by
changing the state of the VSEL pin or by writing to the VSEL
register selected by the VSEL pin.
tPOK(L-H)
PWROK
Figure 39. Single-Step VOUT Transition
Positive Transitions
When transitioning to a higher VOUT, the regulator can perform
the transition using multi-step or single-step mode.
All positive VOUT transitions inhibit PFM until the transition is
complete, which occurs at the end of tPOK(L-H)
.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.1.7
19
www.fairchildsemi.com
I2C Interface
Negative Transitions
When moving from VSEL=1 to VSEL=0, the regulator enters
PFM mode, regardless of the condition of the SYNC pin or
MODE bits, and remains in PFM until the transition is
completed. Reverse current through the inductor is blocked,
and the PFM minimum frequency control inhibited, until the
new set point is reached, at which time the regulator resumes
control using the mode established by MODE_CTRL. The
transition time from VHIGH to VLOW is controlled by the load
current and output capacitance as:
The FAN5355’s serial interface is compatible with standard,
fast, and HS mode I2C bus specifications. The FAN5355’s
SCL line is an input and its SDA line is a bi-directional open-
drain output; it can only pull down the bus when active. The
SDA line only pulls LOW during data reads and when
signaling ACK. All data is shifted in MSB (bit 7) first.
SDA and SCL are normally pulled up to a system I/O power
supply (VCCIO), as shown in Figure 1. If the I2C interface is
not used, SDA and SCL should be tied to AVIN to minimize
quiescent current consumption.
VHIGH − VLOW
tV(H−L) = COUT
•
(3)
ILOAD
Addressing
VHIGH
FAN5355 has four user-accessible registers:
Table 7. I2C Register Addresses
Address
VOUT
VSEL
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
VLOW
tV(L-H)
VSEL0
VSEL1
tPOK(L-H)
CONTROL1
CONTROL2
PWROK
Figure 40. Negative VOUT Transition
Slave Address
Protection Features
In Table 8, A1 and A0 are according to the Ordering
Information table on page 2.
Current Limit / Auto-Restart
Table 8. I2C Slave Address
The regulator includes cycle-by-cycle current limiting, which
prevents the instantaneous inductor current from exceeding
the current-limit threshold.
7
6
5
4
3
2
1
0
1
0
0
1
0
A1
A0
R/W
The IC enters “fault” mode after sustained over-current. If
current limit is asserted for more than 32 consecutive cycles
(about 20 μs), the IC returns to shut-down state and remains
in that condition for ~80 μs. After that time, the regulator
attempts to restart with a normal soft-start cycle. If the fault
has not cleared, it shuts down ~10 μs later.
Bus Timing
As shown in Figure 41, data is normally transferred when SCL
is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge of
SCL to allow ample time for the data to set up before the next
SCL rising edge.
If the fault is a short circuit, the initial current limit is ~30% of
the normal current limit, which produces a very small drain on
the system power source.
Data change allowed
Thermal Protection
SDA
When the junction temperature of the IC exceeds 150°C, the
device turns off all output MOSFETs and remains in a low
quiescent-current state until the die cools to 130°C before
commencing a normal soft-start cycle.
TH
TSU
SCL
Under-Voltage Lockout (UVLO)
Figure 41. Data Transfer Timing
The IC turns off all MOSFETs and remains in a very low
quiescent-current state until VIN rises above the UVLO
threshold.
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a “START” condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 42.
© 2008 Fairchild Semiconductor Corporation
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The master then generates a repeated-start condition (Figure
44) that causes all slaves on the bus to switch to HS mode.
The master then sends I2C packets, as described above,
using the HS-mode clock rate and timing.
THD;STA
Slave Address
MS Bit
SDA
SCL
The bus remains in HS mode until a stop bit (Figure 43) is
sent by the master. While in HS mode, packets are separated
by repeated-start conditions (Figure 44).
Figure 42. Start Bit
Slave Releases
tSU;STA
tHD;STA
A transaction ends with a “STOP” condition, which is defined
as SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 43.
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
Slave Releases
Master Drives
tHD;STO
ACK(0) or
NACK(1)
SDA
SCL
Figure 44. Repeated-Start Timing
Read and Write Transactions
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Figure 43. Stop Bit
Master Drives Bus
Slave Drives Bus
defined as
and
.
During a read from the FAN5355 (Figure 46), the master
issues a “Repeated Start” after sending the register address
and before resending the slave address. The “Repeated Start”
is a 1 to 0 transition on SDA while SCL is HIGH, as shown in
Figure 44.
All addresses and data are MSB first.
Table 9. I2C Bit Definitions for Figure 45 - Figure 46
Symbol Definition
S
START, see Figure 42.
High-Speed (HS) Mode
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4 MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in FS mode (less than
400 KHz clock) and slaves do not ACK this transmission.
NACK. The slave sends a 1 to NACK the
preceding packet.
A
R
P
Repeated START, see Figure 44.
STOP, see Figure 43.
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 45. Write Transaction
0
0
0
1
7 bits
Slave Address
8 bits
7 bits
8 bits
Data
S
0
A
Reg Addr
A
R
Slave Address
1
A
A
P
Figure 46. Read Transaction
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Register Descriptions
Default Values
Each option of the FAN5355 (see Ordering Information on page 2) has different default values for the some of the register bits.
Table 10 defines both the default values and the bit’s type (as defined in Table 11) for each available option.
Table 10. Default Values and Bit Types for VSEL and CONTROL Registers
VSEL0
VSEL1
Option
00
7
1
1
1
1
1
6
1
1
1
1
1
5
0
0
0
1
0
4
1
1
1
1
1
3
1
1
0
0
1
2
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
VOUT
1.05
1.05
1.00
1.80
1.05
Option
00
7
1
1
1
1
1
6
1
1
1
1
1
5
1
1
1
1
1
4
1
0
0
1
0
3
2
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
VOUT
1.35
1.20
1.20
1.80
1.20
0
0
0
0
0
02
02
03
03
06
06
08
08
CONTROL1
CONTROL2
Option
00, 02, 08
03, 06
7
1
1
6
0
0
5
0
0
4
1
1
3
0
0
2
0
0
1
0
0
0
0
0
Option
00, 02, 08
03, 06
7
0
0
6
0
0
5
1
1
4
0
0
3
0
0
2
1
1
1
1
1
0
1
1
Table 11. Bit-Type Definitions for Table 10
#
#
#
Active bit. Changing this bit changes the behavior of the converter, as described below.
Disabled. Converter logic ignores changes made to this bit. Bit can be written to and read-back.
Read-only. Writing to this bit through I2C does not change the read-back value, nor does it change converter behavior.
© 2008 Fairchild Semiconductor Corporation
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Bit Definitions
The following table defines the operation of each register bit. Superscript characters define the default state for each option.
Superscripts 0,2,3,6,8 signify the default values for options 00, 02, 03, 06, and 08 respectively. A signifies the default for all options.
Bit Name
Value
Description
VSEL0
Register Address: 00
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in
either register establishes the EN_DCDC value.
0
EN_DCDC
7
1A
1
Device enabled when EN pin is HIGH, disabled when EN is LOW.
Reserved
DAC[5:0]
6
Table 10
6-bit DAC value to set VOUT.
5:0
VSEL1
Register Address: 01
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in
either register establishes the EN_DCDC value.
0
EN_DCDC
7
1A
1
Device enabled when EN pin is HIGH, disabled when EN is LOW.
Reserved
DAC[5:0]
6
Table 10
6-bit DAC value to set VOUT.
5:0
CONTROL1
Register Address: 02
Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to
distinguish between vendors via I2C.
7:6
5
Reserved
10 A
0A
Disables external signal on SYNC from affecting the regulator.
EN_SYNC
HW_nSW
When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except
when MODE = 00, VSEL pin = LOW, and HW_nSW = 1.
1
0
1A
00A
01
10
11
0A
1
VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit.
4
VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW.
Operation follows MODE0, MODE1.
PFM with automatic transitions to PWM, regardless of VSEL.
PFM disabled (forced PWM), regardless of VSEL.
3:2 MODE_CTRL
Unused.
PFM disabled (forced PWM) when regulator output is controlled by VSEL1.
PFM with automatic transitions to PWM when regulator output is controlled by VSEL1.
1
0
MODE1
MODE0
0A
1
PFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the
operation of the regulator.
CONTROL2
Register Address: 03
0A
1
This bit has no effect when HW_nSW = 1.
7
GO
Starts a VOUT transition if HW_nSW = 0. This bit must be written by the external master to 1 for the next
VOUT transition to start, even if its value might have already been 1 from the last VOUT transition.
0A
1
When the regulator is disabled, VOUT is not discharged.
When the regulator is disabled, VOUT discharges through an internal pull down.
VOUT is not in regulation or is in current limit.
OUTPUT_
DISCHARGE
6
5
0
PWROK
(read only)
1
VOUT is in regulation.
00A
01
fSW = fSYNC when synchronization is enabled.
fSW = 2 X fSYNC when synchronization is enabled.
4:3 PLL_MULT
10
fSW = 3 X fSYNC when synchronization is enabled.
11
fSW = 4 X fSYNC when synchronization is enabled.
000
001
010
011
100
101
110
111A
VOUT slews at 0.15 mV/μs during positive VOUT transitions.
VOUT slews at 0.30 mV/μs during positive VOUT transitions.
VOUT slews at 0.60 mV/μs during positive VOUT transitions.
VOUT slews at 1.20 mV/μs during positive VOUT transitions.
VOUT slews at 2.40 mV/μs during positive VOUT transitions.
VOUT slews at 4.80 mV/μs during positive VOUT transitions.
VOUT slews at 9.60 mV/μs during positive VOUT transitions.
Positive VOUT transitions use single-step mode (see Figure 39).
2:0
DEFSLEW
© 2008 Fairchild Semiconductor Corporation
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The table below pertains to the Marketing outline drawing on the following page.
Product-Specific Dimensions
Product
D
E
X
Y
FAN5355UC
2.200 ±0.030
1.430 ±0.030
0.220
0.355
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